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Merge branch 'fix/fix_csi_bridge_clock_enable_issue' into 'master'

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csi: bridge clock enable shared control issue

See merge request espressif/esp-idf!33498
This commit is contained in:
Armando (Dou Yiwen) 2024-09-14 10:01:27 +08:00
commit c7415fc78d
5 changed files with 24 additions and 42 deletions
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7
components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
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@ -24,7 +24,6 @@
#include "esp_private/esp_cache_private.h" #include "esp_private/esp_cache_private.h"
#include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_clk_tree_common.h"
#include "esp_cache.h" #include "esp_cache.h"
#include "soc/soc_caps.h"
#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE #if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE
#define CSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #define CSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
@ -65,11 +64,7 @@ static esp_err_t s_csi_claim_controller(csi_controller_t *controller)
controller->csi_id = i; controller->csi_id = i;
PERIPH_RCC_ATOMIC() { PERIPH_RCC_ATOMIC() {
mipi_csi_ll_enable_host_bus_clock(i, 0); mipi_csi_ll_enable_host_bus_clock(i, 0);
mipi_csi_ll_enable_host_clock(i, 0);
mipi_csi_ll_enable_host_config_clock(i, 0);
mipi_csi_ll_enable_host_bus_clock(i, 1); mipi_csi_ll_enable_host_bus_clock(i, 1);
mipi_csi_ll_enable_host_clock(i, 1);
mipi_csi_ll_enable_host_config_clock(i, 1);
mipi_csi_ll_reset_host_clock(i); mipi_csi_ll_reset_host_clock(i);
} }
break; break;
@ -91,8 +86,6 @@ static esp_err_t s_csi_declaim_controller(csi_controller_t *controller)
s_platform.controllers[controller->csi_id] = NULL; s_platform.controllers[controller->csi_id] = NULL;
PERIPH_RCC_ATOMIC() { PERIPH_RCC_ATOMIC() {
mipi_csi_ll_enable_host_bus_clock(controller->csi_id, 0); mipi_csi_ll_enable_host_bus_clock(controller->csi_id, 0);
mipi_csi_ll_enable_host_clock(controller->csi_id, 0);
mipi_csi_ll_enable_host_config_clock(controller->csi_id, 0);
} }
_lock_release(&s_platform.mutex); _lock_release(&s_platform.mutex);

22
components/esp_hw_support/include/esp_private/periph_ctrl.h
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@ -25,10 +25,10 @@ extern "C" {
* @note This macro will increase the reference lock of that peripheral. * @note This macro will increase the reference lock of that peripheral.
* You can get the value before the increment from the `rc_name` local variable * You can get the value before the increment from the `rc_name` local variable
*/ */
#define PERIPH_RCC_ACQUIRE_ATOMIC(periph, rc_name) \ #define PERIPH_RCC_ACQUIRE_ATOMIC(rc_periph, rc_name) \
for (uint8_t rc_name, i = 1, __DECLARE_RCC_RC_ATOMIC_ENV; \ for (uint8_t rc_name, _rc_cnt = 1, __DECLARE_RCC_RC_ATOMIC_ENV; \
i ? (rc_name = periph_rcc_acquire_enter(periph), 1) : 0; \ _rc_cnt ? (rc_name = periph_rcc_acquire_enter(rc_periph), 1) : 0; \
periph_rcc_acquire_exit(periph, rc_name), i--) periph_rcc_acquire_exit(rc_periph, rc_name), _rc_cnt--)
/** /**
* @brief Release the RCC lock for a peripheral module * @brief Release the RCC lock for a peripheral module
@ -37,10 +37,10 @@ extern "C" {
* @note This macro will decrease the reference lock of that peripheral. * @note This macro will decrease the reference lock of that peripheral.
* You can get the value after the decrease from the `rc_name` local variable * You can get the value after the decrease from the `rc_name` local variable
*/ */
#define PERIPH_RCC_RELEASE_ATOMIC(periph, rc_name) \ #define PERIPH_RCC_RELEASE_ATOMIC(rc_periph, rc_name) \
for (uint8_t rc_name, i = 1, __DECLARE_RCC_RC_ATOMIC_ENV; \ for (uint8_t rc_name, _rc_cnt = 1, __DECLARE_RCC_RC_ATOMIC_ENV; \
i ? (rc_name = periph_rcc_release_enter(periph), 1) : 0; \ _rc_cnt ? (rc_name = periph_rcc_release_enter(rc_periph), 1) : 0; \
periph_rcc_release_exit(periph, rc_name), i--) periph_rcc_release_exit(rc_periph, rc_name), _rc_cnt--)
/** /**
* @brief A simplified version of `PERIPH_RCC_ACQUIRE/RELEASE_ATOMIC`, without a reference count * @brief A simplified version of `PERIPH_RCC_ACQUIRE/RELEASE_ATOMIC`, without a reference count
@ -48,9 +48,9 @@ extern "C" {
* @note User code protected by this macro should be as short as possible, because it's a critical section * @note User code protected by this macro should be as short as possible, because it's a critical section
*/ */
#define PERIPH_RCC_ATOMIC() \ #define PERIPH_RCC_ATOMIC() \
for (int i = 1, __DECLARE_RCC_ATOMIC_ENV; \ for (int _rc_cnt = 1, __DECLARE_RCC_ATOMIC_ENV; \
i ? (periph_rcc_enter(), 1) : 0; \ _rc_cnt ? (periph_rcc_enter(), 1) : 0; \
periph_rcc_exit(), i--) periph_rcc_exit(), _rc_cnt--)
/** @cond */ /** @cond */
// The following functions are not intended to be used directly by the developers // The following functions are not intended to be used directly by the developers

2
components/esp_hw_support/mipi_csi_share_hw_ctrl.c
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@ -41,6 +41,7 @@ esp_err_t mipi_csi_brg_claim(mipi_csi_brg_user_t user, int *out_id)
PERIPH_RCC_ATOMIC() { PERIPH_RCC_ATOMIC() {
mipi_csi_ll_enable_brg_module_clock(i, true); mipi_csi_ll_enable_brg_module_clock(i, true);
mipi_csi_ll_reset_brg_module_clock(i); mipi_csi_ll_reset_brg_module_clock(i);
mipi_csi_brg_ll_enable_clock(MIPI_CSI_BRG_LL_GET_HW(i), true);
} }
s_ctx.user[i] = user; s_ctx.user[i] = user;
} else { } else {
@ -80,6 +81,7 @@ esp_err_t mipi_csi_brg_declaim(int id)
} else if (s_ctx.ref_cnt[id] == 0) { } else if (s_ctx.ref_cnt[id] == 0) {
PERIPH_RCC_ATOMIC() { PERIPH_RCC_ATOMIC() {
mipi_csi_ll_enable_brg_module_clock(id, false); mipi_csi_ll_enable_brg_module_clock(id, false);
mipi_csi_brg_ll_enable_clock(MIPI_CSI_BRG_LL_GET_HW(id), false);
} }
s_ctx.user[id] = MIPI_CSI_BRG_USER_NO_USER; s_ctx.user[id] = MIPI_CSI_BRG_USER_NO_USER;
} }

11
components/hal/esp32p4/include/hal/mipi_csi_brg_ll.h
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@ -20,6 +20,17 @@ extern "C" {
#define MIPI_CSI_BRG_LL_BRG_NUMS 1 #define MIPI_CSI_BRG_LL_BRG_NUMS 1
#define MIPI_CSI_BRG_LL_GET_HW(id) (((id) == 0) ? &MIPI_CSI_BRIDGE : NULL) #define MIPI_CSI_BRG_LL_GET_HW(id) (((id) == 0) ? &MIPI_CSI_BRIDGE : NULL)
/**
* @brief Enable the clock for MIPI CSI bridge phy
*
* @param dev Pointer to the CSI bridge controller register base address
* @param en true to enable, false to disable
*/
static inline void mipi_csi_brg_ll_enable_clock(csi_brg_dev_t *dev, bool en)
{
dev->host_ctrl.csi_enableclk = en;
}
/** /**
* @brief Enable the CSI bridge * @brief Enable the CSI bridge
* *

24
components/hal/esp32p4/include/hal/mipi_csi_ll.h
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@ -121,30 +121,6 @@ static inline void _mipi_csi_ll_enable_host_bus_clock(int group_id, bool en)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mipi_csi_ll_enable_host_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__) #define mipi_csi_ll_enable_host_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__)
/**
* @brief Enable the clock for MIPI CSI host
*
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_csi_ll_enable_host_clock(int group_id, bool en)
{
(void)group_id;
MIPI_CSI_BRIDGE.host_ctrl.csi_enableclk = en;
}
/**
* @brief Enable the config clock for MIPI CSI host
*
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_csi_ll_enable_host_config_clock(int group_id, bool en)
{
(void)group_id;
MIPI_CSI_BRIDGE.host_ctrl.csi_cfg_clk_en = en;
}
/** /**
* @brief Reset the MIPI CSI host CLK * @brief Reset the MIPI CSI host CLK
* *