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Merge branch 'bugfix/remove_ref_non_ex_options' into 'master'

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config: removed references to non-existing kconfig options

See merge request espressif/esp-idf!17495
This commit is contained in:
Ivan Grokhotkov 2022-03-25 18:02:54 +08:00
commit c70a69b1dd
12 changed files with 18 additions and 36 deletions
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4
components/esp32c2/Kconfig
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@ -118,9 +118,9 @@ menu "ESP32C2-Specific"
config ESP32C2_RTC_CLK_CAL_CYCLES config ESP32C2_RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration" int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if ESP32C2_RTC_CLK_SRC_EXT_CRYS || ESP32C2_RTC_CLK_SRC_EXT_OSC || ESP32C2_RTC_CLK_SRC_INT_8MD256 default 3000 if ESP32C2_RTC_CLK_SRC_EXT_OSC || ESP32C2_RTC_CLK_SRC_INT_8MD256
default 1024 if ESP32C2_RTC_CLK_SRC_INT_RC default 1024 if ESP32C2_RTC_CLK_SRC_INT_RC
range 0 27000 if ESP32C2_RTC_CLK_SRC_EXT_CRYS || ESP32C2_RTC_CLK_SRC_EXT_OSC || ESP32C2_RTC_CLK_SRC_INT_8MD256 range 0 27000 if ESP32C2_RTC_CLK_SRC_EXT_OSC || ESP32C2_RTC_CLK_SRC_INT_8MD256
range 0 32766 if ESP32C2_RTC_CLK_SRC_INT_RC range 0 32766 if ESP32C2_RTC_CLK_SRC_INT_RC
help help
When the startup code initializes RTC_SLOW_CLK, it can perform When the startup code initializes RTC_SLOW_CLK, it can perform

3
components/esp_common/test/test_attr.c
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@ -57,8 +57,7 @@ TEST_CASE("Attributes place variables into correct sections", "[ld]")
#if CONFIG_ESP32_RTCDATA_IN_FAST_MEM || \ #if CONFIG_ESP32_RTCDATA_IN_FAST_MEM || \
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM || \ CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM || \
CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM || \ CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
CONFIG_ESP32C3_RTCDATA_IN_FAST_MEM
TEST_ASSERT(data_in_segment(&s_rtc_data, (int*) SOC_RTC_DRAM_LOW, (int*) SOC_RTC_DRAM_HIGH)); TEST_ASSERT(data_in_segment(&s_rtc_data, (int*) SOC_RTC_DRAM_LOW, (int*) SOC_RTC_DRAM_HIGH));
TEST_ASSERT(data_in_segment(&s_rtc_rodata, (int*) SOC_RTC_DRAM_LOW, (int*) SOC_RTC_DRAM_HIGH)); TEST_ASSERT(data_in_segment(&s_rtc_rodata, (int*) SOC_RTC_DRAM_LOW, (int*) SOC_RTC_DRAM_HIGH));
TEST_ASSERT(data_in_segment(&s_rtc_noinit, (int*) SOC_RTC_DRAM_LOW, (int*) SOC_RTC_DRAM_HIGH)); TEST_ASSERT(data_in_segment(&s_rtc_noinit, (int*) SOC_RTC_DRAM_LOW, (int*) SOC_RTC_DRAM_HIGH));

4
components/esp_hw_support/port/esp32/spiram.c
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@ -31,12 +31,8 @@ we add more types of external RAM memory, this can be made into a more intellige
#if CONFIG_FREERTOS_UNICORE #if CONFIG_FREERTOS_UNICORE
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
#else #else
#if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD
#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
#else
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
#endif #endif
#endif
#if CONFIG_SPIRAM #if CONFIG_SPIRAM

4
components/esp_hw_support/test/test_4mpsram.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -72,7 +72,7 @@ static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host)
#if CONFIG_SPIRAM_OCCUPY_HSPI_HOST || CONFIG_SPIRAM_OCCUPY_VSPI_HOST #if CONFIG_SPIRAM_OCCUPY_HSPI_HOST || CONFIG_SPIRAM_OCCUPY_VSPI_HOST
TEST_CASE("some spi bus occpied by psram", "[psram_4m][test_env=UT_T1_PSRAMV0]") TEST_CASE("some spi bus occpied by psram", "[psram_4m][test_env=UT_T1_PSRAMV0]")
{ {
// NOTE: this unit test rely on the config that PSRAM of 8MB is used only when CONFIG_SPIRAM_BNKSWITCH_ENABLE is set // NOTE: this unit test rely on the config that PSRAM of 8MB is used only when CONFIG_SPIRAM_BANKSWITCH_ENABLE is set
//currently all 8M psram don't need more SPI peripherals //currently all 8M psram don't need more SPI peripherals
#if !CONFIG_SPIRAM || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE #if !CONFIG_SPIRAM || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
#error unexpected test config, only psram 32MBit ver 0 at 80MHz will trigger the workaround #error unexpected test config, only psram 32MBit ver 0 at 80MHz will trigger the workaround

4
components/esp_system/port/soc/esp32c2/clk.c
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@ -93,9 +93,7 @@ static const char *TAG = "clk";
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
#endif #endif
#if defined(CONFIG_ESP32C2_RTC_CLK_SRC_EXT_CRYS) #if defined(CONFIG_ESP32C2_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
#elif defined(CONFIG_ESP32C2_RTC_CLK_SRC_EXT_OSC)
select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC); select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
#elif defined(CONFIG_ESP32C2_RTC_CLK_SRC_INT_8MD256) #elif defined(CONFIG_ESP32C2_RTC_CLK_SRC_INT_8MD256)
select_rtc_slow_clk(SLOW_CLK_8MD256); select_rtc_slow_clk(SLOW_CLK_8MD256);

4
components/esp_system/port/soc/esp32s3/clk.c
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@ -35,11 +35,7 @@ static const char *TAG = "clk";
*/ */
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES #define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES
#ifdef CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY
#define RTC_XTAL_CAL_RETRY CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY
#else
#define RTC_XTAL_CAL_RETRY 1 #define RTC_XTAL_CAL_RETRY 1
#endif
/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. /* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
* The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6.

2
components/esp_system/test/test_ipc.c
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@ -129,6 +129,6 @@ TEST_CASE("Test multiple ipc_calls", "[ipc]")
} }
} }
} }
#endif /* CONFIG_ESP_IPC_USE_CALLERS_PRIORITY */ #endif /* CONFIG_ESP_IPC_USES_CALLERS_PRIORITY */
#endif /* !CONFIG_FREERTOS_UNICORE */ #endif /* !CONFIG_FREERTOS_UNICORE */

2
components/espcoredump/src/core_dump_common.c
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@ -137,7 +137,7 @@ static void* s_exc_frame = NULL;
inline void esp_core_dump_write(panic_info_t *info, core_dump_write_config_t *write_cfg) inline void esp_core_dump_write(panic_info_t *info, core_dump_write_config_t *write_cfg)
{ {
#ifndef CONFIG_ESP_ENABLE_COREDUMP_TO_NONE #ifndef CONFIG_ESP_COREDUMP_ENABLE_TO_NONE
esp_err_t err = ESP_ERR_NOT_SUPPORTED; esp_err_t err = ESP_ERR_NOT_SUPPORTED;
s_exc_frame = (void*) info->frame; s_exc_frame = (void*) info->frame;

7
components/freertos/test/test_preemption.c
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@ -1,3 +1,8 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* /*
Unit tests for FreeRTOS preemption Unit tests for FreeRTOS preemption
*/ */
@ -72,7 +77,7 @@ TEST_CASE("Yield from lower priority task, same CPU", "[freertos]")
} }
#if (portNUM_PROCESSORS == 2) && !CONFIG_FREERTOS_TASK_FUNCTIONS_INTO_FLASH #if (portNUM_PROCESSORS == 2) && !CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH
TEST_CASE("Yield from lower priority task, other CPU", "[freertos]") TEST_CASE("Yield from lower priority task, other CPU", "[freertos]")
{ {
uint32_t trigger_ccount, yield_ccount, now_ccount, delta; uint32_t trigger_ccount, yield_ccount, now_ccount, delta;

2
components/hal/wdt_hal_iram.c
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@ -41,7 +41,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
//Enable or disable level interrupt. Edge interrupt is always disabled. //Enable or disable level interrupt. Edge interrupt is always disabled.
rwdt_ll_set_edge_intr(hal->rwdt_dev, false); rwdt_ll_set_edge_intr(hal->rwdt_dev, false);
rwdt_ll_set_level_intr(hal->rwdt_dev, enable_intr); rwdt_ll_set_level_intr(hal->rwdt_dev, enable_intr);
#else //CONFIG_IDF_TARGET_ESP32S2BETA #else
//Enable or disable chip reset on timeout, and length of chip reset signal //Enable or disable chip reset on timeout, and length of chip reset signal
rwdt_ll_set_chip_reset_width(hal->rwdt_dev, 0); rwdt_ll_set_chip_reset_width(hal->rwdt_dev, 0);
rwdt_ll_set_chip_reset_en(hal->rwdt_dev, false); rwdt_ll_set_chip_reset_en(hal->rwdt_dev, false);

16
components/spi_flash/cache_utils.c
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@ -525,14 +525,14 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
#endif #endif
if (icache_wrap_enable) { if (icache_wrap_enable) {
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32H2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C2_INSTRUCTION_CACHE_LINE_16B #if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
icache_wrap_size = 16; icache_wrap_size = 16;
#else #else
icache_wrap_size = 32; icache_wrap_size = 32;
#endif #endif
} }
if (dcache_wrap_enable) { if (dcache_wrap_enable) {
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32H2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C2_INSTRUCTION_CACHE_LINE_16B #if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B
dcache_wrap_size = 16; dcache_wrap_size = 16;
#else #else
dcache_wrap_size = 32; dcache_wrap_size = 32;
@ -562,18 +562,12 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
spiram_wrap_sizes[1] = dcache_wrap_size; spiram_wrap_sizes[1] = dcache_wrap_size;
flash_wrap_sizes[1] = dcache_wrap_size; flash_wrap_sizes[1] = dcache_wrap_size;
} }
#ifdef CONFIG_EXT_RODATA_SUPPORT
spiram_wrap_sizes[1] = dcache_wrap_size;
#endif
} else { } else {
if (drom0_in_icache) { if (drom0_in_icache) {
flash_wrap_sizes[0] = icache_wrap_size; flash_wrap_sizes[0] = icache_wrap_size;
} else { } else {
flash_wrap_sizes[1] = dcache_wrap_size; flash_wrap_sizes[1] = dcache_wrap_size;
} }
#ifdef CONFIG_EXT_RODATA_SUPPORT
flash_wrap_sizes[1] = dcache_wrap_size;
#endif
} }
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT #ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
spiram_wrap_sizes[1] = dcache_wrap_size; spiram_wrap_sizes[1] = dcache_wrap_size;
@ -817,18 +811,12 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
} else { } else {
spiram_wrap_sizes[1] = dcache_wrap_size; spiram_wrap_sizes[1] = dcache_wrap_size;
} }
#ifdef CONFIG_EXT_RODATA_SUPPORT
spiram_wrap_sizes[1] = dcache_wrap_size;
#endif
} else { } else {
if (drom0_in_icache) { if (drom0_in_icache) {
flash_wrap_sizes[0] = icache_wrap_size; flash_wrap_sizes[0] = icache_wrap_size;
} else { } else {
flash_wrap_sizes[1] = dcache_wrap_size; flash_wrap_sizes[1] = dcache_wrap_size;
} }
#ifdef CONFIG_EXT_RODATA_SUPPORT
flash_wrap_sizes[1] = dcache_wrap_size;
#endif
} }
#ifdef CONFIG_ESP32S3_SPIRAM_SUPPORT #ifdef CONFIG_ESP32S3_SPIRAM_SUPPORT
spiram_wrap_sizes[1] = dcache_wrap_size; spiram_wrap_sizes[1] = dcache_wrap_size;

2
tools/unit-test-app/configs/freertos_flash
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@ -1,2 +1,2 @@
TEST_COMPONENTS=freertos driver spi_flash esp_ringbuf TEST_COMPONENTS=freertos driver spi_flash esp_ringbuf
CONFIG_FREERTOS_TASK_FUNCTIONS_INTO_FLASH=y CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y