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change(driver): reformat driver component with astyle_py

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This commit is contained in:
morris 2024-02-23 17:28:52 +08:00
parent 603bc0536c
commit c65fbbdf71
43 changed files with 704 additions and 749 deletions
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1
components/driver/deprecated/adc1_private.h
View File

@ -12,7 +12,6 @@ extern "C" {
#include "esp_err.h"
/**
* @brief For I2S dma to claim the usage of ADC1.
*

4
components/driver/deprecated/adc_dma_legacy.c
View File

@ -285,7 +285,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
dma_chan = s_adc_digi_ctx->spi_dma_ctx->rx_dma_chan.chan_id;
ret = esp_intr_alloc(spicommon_irqdma_source_for_host(s_adc_digi_ctx->spi_host), 0, adc_dma_intr_handler,
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
if (ret != ESP_OK) {
goto cleanup;
}
@ -300,7 +300,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
s_adc_digi_ctx->i2s_host = I2S_NUM_0;
ret = esp_intr_alloc(i2s_periph_signal[s_adc_digi_ctx->i2s_host].irq, 0, adc_dma_intr_handler,
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
if (ret != ESP_OK) {
goto cleanup;
}

31
components/driver/deprecated/adc_i2s_deprecated.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -50,7 +50,6 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi
esp_pm_lock_handle_t adc_digi_arbiter_lock = NULL;
#endif //CONFIG_PM_ENABLE
#if CONFIG_IDF_TARGET_ESP32
/*---------------------------------------------------------------
ESP32 Depricated ADC APIs and functions
@ -149,20 +148,20 @@ static void adc_digi_controller_reg_set(const adc_digi_config_t *cfg)
{
/* On ESP32, only support ADC1 */
switch (cfg->conv_mode) {
case ADC_CONV_SINGLE_UNIT_1:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC1);
break;
case ADC_CONV_SINGLE_UNIT_2:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC2);
break;
case ADC_CONV_BOTH_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
break;
case ADC_CONV_ALTER_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ALTER_UNIT);
break;
default:
abort();
case ADC_CONV_SINGLE_UNIT_1:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC1);
break;
case ADC_CONV_SINGLE_UNIT_2:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC2);
break;
case ADC_CONV_BOTH_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
break;
case ADC_CONV_ALTER_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ALTER_UNIT);
break;
default:
abort();
}
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {

109
components/driver/deprecated/adc_legacy.c
View File

@ -39,7 +39,6 @@
#include "esp_efuse_rtc_calib.h"
#endif
static const char *ADC_TAG = "ADC";
#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
@ -78,7 +77,6 @@ static _lock_t adc1_dma_lock;
#define SARADC1_RELEASE() _lock_release( &adc1_dma_lock )
#endif
/*
In ADC2, there're two locks used for different cases:
1. lock shared with app and Wi-Fi:
@ -218,21 +216,21 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
} else {
switch(width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
switch (width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
}
}
#elif CONFIG_IDF_TARGET_ESP32S2
@ -307,21 +305,21 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
} else {
switch(width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
switch (width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
}
}
#elif CONFIG_IDF_TARGET_ESP32S2
@ -342,7 +340,7 @@ esp_err_t adc1_dma_mode_acquire(void)
/* Use locks to avoid digtal and RTC controller conflicts.
for adc1, block until acquire the lock. */
SARADC1_ACQUIRE();
ESP_LOGD( ADC_TAG, "dma mode takes adc1 lock." );
ESP_LOGD(ADC_TAG, "dma mode takes adc1 lock.");
sar_periph_ctrl_adc_continuous_power_acquire();
@ -484,19 +482,19 @@ static inline void adc2_init(void)
#endif //CONFIG_IDF_TARGET_ESP32S2
}
static inline void adc2_dac_disable( adc2_channel_t channel)
static inline void adc2_dac_disable(adc2_channel_t channel)
{
#if SOC_DAC_SUPPORTED
#ifdef CONFIG_IDF_TARGET_ESP32
if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 0
if (channel == ADC2_CHANNEL_8) { // the same as DAC channel 0
dac_ll_power_down(DAC_CHAN_0);
} else if ( channel == ADC2_CHANNEL_9 ) {
} else if (channel == ADC2_CHANNEL_9) {
dac_ll_power_down(DAC_CHAN_1);
}
#else
if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 0
if (channel == ADC2_CHANNEL_6) { // the same as DAC channel 0
dac_ll_power_down(DAC_CHAN_0);
} else if ( channel == ADC2_CHANNEL_7 ) {
} else if (channel == ADC2_CHANNEL_7) {
dac_ll_power_down(DAC_CHAN_1);
}
#endif
@ -522,21 +520,21 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
} else {
switch(width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
switch (width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
}
}
#elif CONFIG_IDF_TARGET_ESP32S2
@ -650,7 +648,6 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
#endif //SOC_ADC_RTC_CTRL_SUPPORTED
#endif //#if (SOC_ADC_PERIPH_NUM >= 2)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
/*---------------------------------------------------------------
Legacy ADC Single Read Mode
@ -667,7 +664,6 @@ static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX]; //Array saving attenuat
static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC2, used by single read API
#endif
static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
{
assert(adc_unit < SOC_ADC_PERIPH_NUM);
@ -860,7 +856,6 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#endif //#if (SOC_ADC_PERIPH_NUM >= 2)
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
static void adc_hal_onetime_start(adc_unit_t adc_n, uint32_t clk_src_freq_hz)
{
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@ -876,7 +871,7 @@ static void adc_hal_onetime_start(adc_unit_t adc_n, uint32_t clk_src_freq_hz)
//3 ADC digital controller clock cycle
delay = delay * 3;
//This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
if (digi_clk >= APB_CLK_FREQ/8) {
if (digi_clk >= APB_CLK_FREQ / 8) {
delay = 0;
}

1
components/driver/deprecated/dac_common_legacy.c
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "esp_check.h"
#include "freertos/FreeRTOS.h"

1
components/driver/deprecated/driver/adc.h
View File

@ -278,7 +278,6 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio);
#endif //#if (SOC_ADC_PERIPH_NUM >= 2)
/*---------------------------------------------------------------
ADC DMA Read Setting
---------------------------------------------------------------*/

1
components/driver/deprecated/driver/i2s.h
View File

@ -378,7 +378,6 @@ esp_err_t i2s_adc_disable(i2s_port_t i2s_num);
esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
#endif //SOC_I2S_SUPPORTS_DAC
#ifdef __cplusplus
}
#endif

1
components/driver/deprecated/driver/i2s_types_legacy.h
View File

@ -207,7 +207,6 @@ typedef struct {
} i2s_pdm_tx_upsample_cfg_t;
#endif
/**
* @brief I2S driver configuration parameters
*

2
components/driver/deprecated/driver/mcpwm.h
View File

@ -64,7 +64,7 @@ esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t *mcpwm_conf);
esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t *mcpwm_conf);
/**
* @brief Set resolution of the MCPWM group

2
components/driver/deprecated/driver/rmt_types_legacy.h
View File

@ -15,7 +15,6 @@
extern "C" {
#endif
#define RMT_CHANNEL_FLAGS_AWARE_DFS (1 << 0) /*!< Channel can work during APB clock scaling */
#define RMT_CHANNEL_FLAGS_INVERT_SIG (1 << 1) /*!< Invert RMT signal */
@ -39,7 +38,6 @@ typedef struct {
};
} rmt_item32_t;
#if SOC_RMT_SUPPORTED
/**
* @brief RMT hardware memory layout

1
components/driver/deprecated/driver/temp_sensor_types_legacy.h
View File

@ -23,7 +23,6 @@ typedef enum {
TSENS_DAC_DEFAULT = TSENS_DAC_L2,
} temp_sensor_dac_offset_t;
/**
* @brief Configuration for temperature sensor reading
*/

1
components/driver/deprecated/driver/timer.h
View File

@ -359,7 +359,6 @@ void timer_group_set_alarm_value_in_isr(timer_group_t group_num, timer_idx_t tim
*/
void timer_group_set_counter_enable_in_isr(timer_group_t group_num, timer_idx_t timer_num, timer_start_t counter_en);
/** @brief Get interrupt status, just used in ISR
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1

1
components/driver/deprecated/esp32/dac_legacy.c
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "freertos/FreeRTOS.h"
#include "hal/dac_ll.h"
#include "esp_err.h"

1
components/driver/deprecated/esp32s2/dac_legacy.c
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"

43
components/driver/deprecated/i2s_legacy.c
View File

@ -202,7 +202,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -210,7 +210,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -234,7 +234,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_Q_OVF;
i2s_event.size = p_i2s->tx->buf_size;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -249,7 +249,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -279,7 +279,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
xQueueReceiveFromISR(p_i2s->i2s_queue, &dummy, &tmp);
need_awoke |= tmp;
}
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -293,7 +293,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -307,7 +307,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -321,7 +321,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -329,7 +329,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@ -360,7 +360,7 @@ static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
/* Set GDMA config */
gdma_channel_alloc_config_t dma_cfg = {};
if ( p_i2s[i2s_num]->dir & I2S_DIR_TX) {
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_TX;
/* Register a new GDMA tx channel */
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error");
@ -369,7 +369,7 @@ static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
/* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
gdma_register_tx_event_callbacks(p_i2s[i2s_num]->tx_dma_chan, &cb, p_i2s[i2s_num]);
}
if ( p_i2s[i2s_num]->dir & I2S_DIR_RX) {
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_RX;
/* Register a new GDMA rx channel */
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error");
@ -693,7 +693,7 @@ err:
/*-------------------------------------------------------------
I2S clock operation
-------------------------------------------------------------*/
// [clk_tree] TODO: replace the following switch table by clk_tree API
// [clk_tree] TODO: replace the following switch table by clk_tree API
static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
{
#if SOC_I2S_SUPPORTS_APLL
@ -844,7 +844,6 @@ static esp_err_t i2s_calculate_common_clock(int i2s_num, i2s_hal_clock_info_t *c
return ESP_OK;
}
static esp_err_t i2s_calculate_clock(i2s_port_t i2s_num, i2s_hal_clock_info_t *clk_info)
{
/* Calculate clock for ADC/DAC mode */
@ -996,7 +995,6 @@ static esp_err_t i2s_check_cfg_validity(i2s_port_t i2s_num, const i2s_config_t *
ESP_RETURN_ON_FALSE((cfg->dma_desc_num >= 2 && cfg->dma_desc_num <= 128), ESP_ERR_INVALID_ARG, TAG, "I2S buffer count less than 128 and more than 2");
ESP_RETURN_ON_FALSE((cfg->dma_frame_num >= 8 && cfg->dma_frame_num <= 1024), ESP_ERR_INVALID_ARG, TAG, "I2S buffer length at most 1024 and more than 8");
#if SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
/* Check PDM mode */
if (cfg->mode & I2S_MODE_PDM) {
@ -1041,22 +1039,22 @@ static void i2s_set_slot_legacy(i2s_port_t i2s_num)
}
if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) {
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
i2s_hal_std_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_std_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
i2s_hal_std_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_std_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
}
#if SOC_I2S_SUPPORTS_PDM
else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
#if SOC_I2S_SUPPORTS_PDM_TX
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
i2s_hal_pdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_pdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
#endif
#if SOC_I2S_SUPPORTS_PDM_RX
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
i2s_hal_pdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_pdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
#endif
}
@ -1064,10 +1062,10 @@ static void i2s_set_slot_legacy(i2s_port_t i2s_num)
#if SOC_I2S_SUPPORTS_TDM
else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
i2s_hal_tdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_tdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
i2s_hal_tdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_tdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
}
#endif
@ -1324,7 +1322,7 @@ static void i2s_mode_identify(i2s_port_t i2s_num, const i2s_config_t *i2s_config
#if SOC_I2S_SUPPORTS_ADC_DAC
if ((i2s_config->mode & I2S_MODE_DAC_BUILT_IN) ||
(i2s_config->mode & I2S_MODE_ADC_BUILT_IN)) {
(i2s_config->mode & I2S_MODE_ADC_BUILT_IN)) {
p_i2s[i2s_num]->mode = (i2s_comm_mode_t)I2S_COMM_MODE_ADC_DAC;
}
#endif // SOC_I2S_SUPPORTS_ADC_DAC
@ -1337,7 +1335,7 @@ static esp_err_t i2s_config_transfer(i2s_port_t i2s_num, const i2s_config_t *i2s
/* Convert legacy configuration into general part of slot and clock configuration */
p_i2s[i2s_num]->slot_cfg.data_bit_width = i2s_config->bits_per_sample;
p_i2s[i2s_num]->slot_cfg.slot_bit_width = (int)i2s_config->bits_per_chan < (int)i2s_config->bits_per_sample ?
i2s_config->bits_per_sample : i2s_config->bits_per_chan;
i2s_config->bits_per_sample : i2s_config->bits_per_chan;
p_i2s[i2s_num]->slot_cfg.slot_mode = i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ?
I2S_SLOT_MODE_STEREO : I2S_SLOT_MODE_MONO;
@ -1637,7 +1635,6 @@ esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num)
return ESP_OK;
}
esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void *i2s_queue)
{
#if CONFIG_I2S_ENABLE_DEBUG_LOG

1
components/driver/deprecated/pcnt_legacy.c
View File

@ -37,7 +37,6 @@
#define PCNT_RCC_ATOMIC()
#endif
static const char *TAG = "pcnt(legacy)";
#define PCNT_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, TAG, "%s", str)

2
components/driver/deprecated/rmt_legacy.c
View File

@ -1011,7 +1011,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr
}
#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH
if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
if (intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt");
return ESP_ERR_INVALID_ARG;
}

2
components/driver/deprecated/timer_legacy.c
View File

@ -85,7 +85,7 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
// get clock source frequency
uint32_t counter_src_hz = 0;
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
TIMER_TAG, "get clock source frequency failed");
*time = (double)timer_val * div / counter_src_hz;
return ESP_OK;

96
components/driver/i2c/i2c.c
View File

@ -32,7 +32,6 @@
#include "esp_private/sleep_retention.h"
#endif
#if SOC_I2C_SUPPORT_APB || SOC_I2C_SUPPORT_XTAL
#include "esp_private/esp_clk.h"
#endif
@ -57,8 +56,8 @@ static const char *I2C_TAG = "i2c";
#define I2C_ADDR_ERROR_STR "i2c null address error"
#define I2C_DRIVER_NOT_INSTALL_ERR_STR "i2c driver not installed"
#if SOC_I2C_SUPPORT_SLAVE
#define I2C_SLAVE_BUFFER_LEN_ERR_STR "i2c buffer size too small for slave mode"
#define I2C_MODE_SLAVE_ERR_STR "Only allowed in slave mode"
#define I2C_SLAVE_BUFFER_LEN_ERR_STR "i2c buffer size too small for slave mode"
#define I2C_MODE_SLAVE_ERR_STR "Only allowed in slave mode"
#endif
#define I2C_EVT_QUEUE_ERR_STR "i2c evt queue error"
#define I2C_SEM_ERR_STR "i2c semaphore error"
@ -86,9 +85,9 @@ static const char *I2C_TAG = "i2c";
#define I2C_CMD_EVT_DONE (1)
#define I2C_EVT_QUEUE_LEN (1)
#if SOC_I2C_SUPPORT_SLAVE
#define I2C_SLAVE_TIMEOUT_DEFAULT (32000) /* I2C slave timeout value, APB clock cycle number */
#define I2C_SLAVE_SDA_SAMPLE_DEFAULT (10) /* I2C slave sample time after scl positive edge default value */
#define I2C_SLAVE_SDA_HOLD_DEFAULT (10) /* I2C slave hold time after scl negative edge default value */
#define I2C_SLAVE_TIMEOUT_DEFAULT (32000) /* I2C slave timeout value, APB clock cycle number */
#define I2C_SLAVE_SDA_SAMPLE_DEFAULT (10) /* I2C slave sample time after scl positive edge default value */
#define I2C_SLAVE_SDA_HOLD_DEFAULT (10) /* I2C slave hold time after scl negative edge default value */
#endif
#define I2C_MASTER_TOUT_CNUM_DEFAULT (8) /* I2C master timeout cycle number of I2C clock, after which the timeout interrupt will be triggered */
#define I2C_ACKERR_CNT_MAX (10)
@ -164,7 +163,7 @@ typedef struct {
/* INTERNAL_STRUCT_SIZE must be at least sizeof(i2c_cmd_link_t) */
_Static_assert(I2C_INTERNAL_STRUCT_SIZE >= sizeof(i2c_cmd_link_t),
"I2C_INTERNAL_STRUCT_SIZE must be at least sizeof(i2c_cmd_link_t), please adjust this value.");
"I2C_INTERNAL_STRUCT_SIZE must be at least sizeof(i2c_cmd_link_t), please adjust this value.");
typedef enum {
I2C_STATUS_READ, /*!< read status for current master command */
@ -217,15 +216,14 @@ typedef struct {
#endif
} i2c_context_t;
typedef struct
{
typedef struct {
uint8_t character; /*!< I2C source clock characteristic */
} i2c_clk_alloc_t;
static i2c_context_t i2c_context[I2C_NUM_MAX] = {
I2C_CONTEX_INIT_DEF(I2C_NUM_0),
/* Now that I2C_NUM_MAX is part of an enum (i2c_port_t), we cannot use
* it anomore in the preprocessor! */
/* Now that I2C_NUM_MAX is part of an enum (i2c_port_t), we cannot use
* it anomore in the preprocessor! */
#if SOC_I2C_NUM > 1
I2C_CONTEX_INIT_DEF(I2C_NUM_1),
#endif
@ -293,8 +291,8 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
ESP_RETURN_ON_FALSE(i2c_num != LP_I2C_NUM_0, ESP_ERR_INVALID_ARG, I2C_TAG, "LP_I2C is not supported via i2c_driver_intall()");
#endif // SOC_LP_I2C_SUPPORTED
#if SOC_I2C_SUPPORT_SLAVE
ESP_RETURN_ON_FALSE(mode == I2C_MODE_MASTER || ( slv_rx_buf_len > 100 || slv_tx_buf_len > 100 ),
ESP_ERR_INVALID_ARG, I2C_TAG, I2C_SLAVE_BUFFER_LEN_ERR_STR);
ESP_RETURN_ON_FALSE(mode == I2C_MODE_MASTER || (slv_rx_buf_len > 100 || slv_tx_buf_len > 100),
ESP_ERR_INVALID_ARG, I2C_TAG, I2C_SLAVE_BUFFER_LEN_ERR_STR);
#endif // SOC_I2C_SUPPORT_SLAVE
esp_err_t ret = ESP_OK;
@ -325,7 +323,7 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
if (mode == I2C_MODE_SLAVE) {
#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH
if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
if (intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
ESP_LOGE(I2C_TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt");
goto err;
}
@ -405,8 +403,8 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK);
//hook isr handler
ret = esp_intr_alloc(i2c_periph_signal[i2c_num].irq, intr_alloc_flags,
i2c_isr_handler_default, p_i2c_obj[i2c_num],
&p_i2c_obj[i2c_num]->intr_handle);
i2c_isr_handler_default, p_i2c_obj[i2c_num],
&p_i2c_obj[i2c_num]->intr_handle);
ESP_GOTO_ON_ERROR(ret, err, I2C_TAG, I2C_INTR_ALLOC_ERR_STR);
#if SOC_I2C_SUPPORT_SLAVE
//Enable I2C slave rx interrupt
@ -416,8 +414,8 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
#endif // SOC_I2C_SUPPORT_SLAVE
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_7, I2C_SLEEP_RETENTION_MODULE(i2c_num));
ESP_GOTO_ON_ERROR(ret, err, I2C_TAG, "failed to allocate mem for sleep retention");
ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_7, I2C_SLEEP_RETENTION_MODULE(i2c_num));
ESP_GOTO_ON_ERROR(ret, err, I2C_TAG, "failed to allocate mem for sleep retention");
#endif
return ESP_OK;
@ -741,9 +739,9 @@ static uint32_t s_get_src_clk_freq(i2c_clock_source_t clk_src)
static i2c_clock_source_t s_get_clk_src(const uint32_t clk_flags, const uint32_t clk_speed)
{
i2c_clock_source_t clk_srcs[] = SOC_I2C_CLKS;
for (size_t i = 0; i < sizeof(clk_srcs)/ sizeof(clk_srcs[0]); i++) {
if ( ((clk_flags & i2c_clk_alloc[i].character) == clk_flags) &&
(clk_speed <= (s_get_src_clk_freq(clk_srcs[i]) / 20))) { // I2C SCL clock frequency should not larger than clock source frequency/20
for (size_t i = 0; i < sizeof(clk_srcs) / sizeof(clk_srcs[0]); i++) {
if (((clk_flags & i2c_clk_alloc[i].character) == clk_flags) &&
(clk_speed <= (s_get_src_clk_freq(clk_srcs[i]) / 20))) { // I2C SCL clock frequency should not larger than clock source frequency/20
return clk_srcs[i];
}
}
@ -763,14 +761,14 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
}
#if SOC_I2C_SUPPORT_SLAVE
else {
#if SOC_I2C_SUPPORT_REF_TICK
#if SOC_I2C_SUPPORT_REF_TICK
/* On ESP32-S2, APB clock shall always be used in slave mode as the
* other one, I2C_CLK_SRC_REF_TICK, is too slow, even for sampling a
* 100KHz SCL. */
src_clk = I2C_CLK_SRC_APB;
#else
#else
src_clk = s_get_clk_src(i2c_conf->clk_flags, i2c_conf->slave.maximum_speed);
#endif // CONFIG_IDF_TARGET_ESP32S2
#endif // CONFIG_IDF_TARGET_ESP32S2
}
#endif // SOC_I2C_SUPPORT_SLAVE
ESP_RETURN_ON_FALSE(src_clk != I2C_CLOCK_INVALID, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_CLK_FLAG_ERR_STR);
@ -945,21 +943,21 @@ esp_err_t i2c_get_timeout(i2c_port_t i2c_num, int *timeout)
esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool sda_pullup_en, bool scl_pullup_en, i2c_mode_t mode)
{
ESP_RETURN_ON_FALSE(( i2c_num < I2C_NUM_MAX ), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE((i2c_num < I2C_NUM_MAX), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE(((sda_io_num < 0) || ((GPIO_IS_VALID_OUTPUT_GPIO(sda_io_num)))), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_SDA_IO_ERR_STR);
ESP_RETURN_ON_FALSE(scl_io_num < 0 ||
#if SOC_I2C_SUPPORT_SLAVE
(GPIO_IS_VALID_GPIO(scl_io_num) && mode == I2C_MODE_SLAVE) ||
(GPIO_IS_VALID_GPIO(scl_io_num) && mode == I2C_MODE_SLAVE) ||
#endif // SOC_I2C_SUPPORT_SLAVE
(GPIO_IS_VALID_OUTPUT_GPIO(scl_io_num)),
ESP_ERR_INVALID_ARG, I2C_TAG,
I2C_SCL_IO_ERR_STR);
(GPIO_IS_VALID_OUTPUT_GPIO(scl_io_num)),
ESP_ERR_INVALID_ARG, I2C_TAG,
I2C_SCL_IO_ERR_STR);
ESP_RETURN_ON_FALSE(sda_io_num < 0 ||
(sda_pullup_en == GPIO_PULLUP_ENABLE && GPIO_IS_VALID_OUTPUT_GPIO(sda_io_num)) ||
sda_pullup_en == GPIO_PULLUP_DISABLE, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_GPIO_PULLUP_ERR_STR);
(sda_pullup_en == GPIO_PULLUP_ENABLE && GPIO_IS_VALID_OUTPUT_GPIO(sda_io_num)) ||
sda_pullup_en == GPIO_PULLUP_DISABLE, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_GPIO_PULLUP_ERR_STR);
ESP_RETURN_ON_FALSE(scl_io_num < 0 ||
(scl_pullup_en == GPIO_PULLUP_ENABLE && GPIO_IS_VALID_OUTPUT_GPIO(scl_io_num)) ||
scl_pullup_en == GPIO_PULLUP_DISABLE, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_GPIO_PULLUP_ERR_STR);
(scl_pullup_en == GPIO_PULLUP_ENABLE && GPIO_IS_VALID_OUTPUT_GPIO(scl_io_num)) ||
scl_pullup_en == GPIO_PULLUP_DISABLE, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_GPIO_PULLUP_ERR_STR);
ESP_RETURN_ON_FALSE((sda_io_num != scl_io_num), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_SCL_SDA_EQUAL_ERR_STR);
int sda_in_sig, sda_out_sig, scl_in_sig, scl_out_sig;
@ -1012,7 +1010,7 @@ esp_err_t i2c_master_write_to_device(i2c_port_t i2c_num, uint8_t device_address,
uint8_t buffer[I2C_TRANS_BUF_MINIMUM_SIZE] = { 0 };
i2c_cmd_handle_t handle = i2c_cmd_link_create_static(buffer, sizeof(buffer));
assert (handle != NULL);
assert(handle != NULL);
err = i2c_master_start(handle);
if (err != ESP_OK) {
@ -1037,7 +1035,6 @@ end:
return err;
}
esp_err_t i2c_master_read_from_device(i2c_port_t i2c_num, uint8_t device_address,
uint8_t* read_buffer, size_t read_size,
TickType_t ticks_to_wait)
@ -1046,7 +1043,7 @@ esp_err_t i2c_master_read_from_device(i2c_port_t i2c_num, uint8_t device_address
uint8_t buffer[I2C_TRANS_BUF_MINIMUM_SIZE] = { 0 };
i2c_cmd_handle_t handle = i2c_cmd_link_create_static(buffer, sizeof(buffer));
assert (handle != NULL);
assert(handle != NULL);
err = i2c_master_start(handle);
if (err != ESP_OK) {
@ -1071,7 +1068,6 @@ end:
return err;
}
esp_err_t i2c_master_write_read_device(i2c_port_t i2c_num, uint8_t device_address,
const uint8_t* write_buffer, size_t write_size,
uint8_t* read_buffer, size_t read_size,
@ -1081,7 +1077,7 @@ esp_err_t i2c_master_write_read_device(i2c_port_t i2c_num, uint8_t device_addres
uint8_t buffer[I2C_TRANS_BUF_MINIMUM_SIZE] = { 0 };
i2c_cmd_handle_t handle = i2c_cmd_link_create_static(buffer, sizeof(buffer));
assert (handle != NULL);
assert(handle != NULL);
err = i2c_master_start(handle);
if (err != ESP_OK) {
@ -1379,7 +1375,8 @@ esp_err_t i2c_master_read(i2c_cmd_handle_t cmd_handle, uint8_t *data, size_t dat
}
__attribute__((always_inline))
static inline bool i2c_cmd_is_single_byte(const i2c_cmd_t *cmd) {
static inline bool i2c_cmd_is_single_byte(const i2c_cmd_t *cmd)
{
return cmd->total_bytes == 1;
}
@ -1458,7 +1455,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
p_i2c->cmd_idx = 0;
if (i2c_cmd_is_single_byte(cmd) || cmd->total_bytes == cmd->bytes_used) {
p_i2c->cmd_link.head = p_i2c->cmd_link.head->next;
if(p_i2c->cmd_link.head) {
if (p_i2c->cmd_link.head) {
p_i2c->cmd_link.head->cmd.bytes_used = 0;
}
}
@ -1479,7 +1476,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
}
p_i2c->cmd_idx++;
p_i2c->cmd_link.head = p_i2c->cmd_link.head->next;
if (p_i2c->cmd_link.head == NULL || p_i2c->cmd_idx >= (SOC_I2C_CMD_REG_NUM-1)) {
if (p_i2c->cmd_link.head == NULL || p_i2c->cmd_idx >= (SOC_I2C_CMD_REG_NUM - 1)) {
p_i2c->cmd_idx = 0;
break;
}
@ -1495,12 +1492,11 @@ static bool is_cmd_link_buffer_internal(const i2c_cmd_link_t *link)
{
bool is_internal = true;
for (const i2c_cmd_link_t *cmd_link = link;
cmd_link != NULL && is_internal;
cmd_link = cmd_link->next)
{
cmd_link != NULL && is_internal;
cmd_link = cmd_link->next) {
/* A command node has a valid pointer if it is a read command or a write command with more than one byte. */
const bool data_pointer = (cmd_link->cmd.hw_cmd.op_code == I2C_LL_CMD_WRITE && !i2c_cmd_is_single_byte(&cmd_link->cmd))
|| cmd_link->cmd.hw_cmd.op_code == I2C_LL_CMD_READ;
|| cmd_link->cmd.hw_cmd.op_code == I2C_LL_CMD_READ;
/* Check if the (non-NULL) pointer points to internal memory. */
is_internal &= !data_pointer || cmd_link->cmd.data == NULL || esp_ptr_internal(cmd_link->cmd.data);
}
@ -1512,7 +1508,7 @@ static uint8_t clear_bus_cnt[I2C_NUM_MAX] = { 0 };
esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle, TickType_t ticks_to_wait)
{
ESP_RETURN_ON_FALSE(( i2c_num < I2C_NUM_MAX ), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE((i2c_num < I2C_NUM_MAX), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num] != NULL, ESP_ERR_INVALID_STATE, I2C_TAG, I2C_DRIVER_NOT_INSTALL_ERR_STR);
ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num]->mode == I2C_MODE_MASTER, ESP_ERR_INVALID_STATE, I2C_TAG, I2C_MASTER_MODE_ERR_STR);
ESP_RETURN_ON_FALSE(cmd_handle != NULL, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_CMD_LINK_INIT_ERR_STR);
@ -1520,8 +1516,8 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
#if CONFIG_SPIRAM_USE_MALLOC
//If the i2c read or write buffer is not in internal RAM, we will return ESP_FAIL
//to avoid the ISR handler function crashing when the cache is disabled.
if ( (p_i2c_obj[i2c_num]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) &&
!is_cmd_link_buffer_internal(((const i2c_cmd_desc_t *)cmd_handle)->head) ) {
if ((p_i2c_obj[i2c_num]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) &&
!is_cmd_link_buffer_internal(((const i2c_cmd_desc_t *)cmd_handle)->head)) {
ESP_LOGE(I2C_TAG, I2C_PSRAM_BUFFER_WARN_STR);
return ESP_ERR_INVALID_ARG;
}
@ -1622,7 +1618,7 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
#if SOC_I2C_SUPPORT_SLAVE
int i2c_slave_write_buffer(i2c_port_t i2c_num, const uint8_t *data, int size, TickType_t ticks_to_wait)
{
ESP_RETURN_ON_FALSE(( i2c_num < I2C_NUM_MAX ), ESP_FAIL, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE((i2c_num < I2C_NUM_MAX), ESP_FAIL, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num] != NULL, ESP_FAIL, I2C_TAG, I2C_DRIVER_ERR_STR);
ESP_RETURN_ON_FALSE((data != NULL), ESP_FAIL, I2C_TAG, I2C_ADDR_ERROR_STR);
ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num]->mode == I2C_MODE_SLAVE, ESP_FAIL, I2C_TAG, I2C_MODE_SLAVE_ERR_STR);
@ -1652,7 +1648,7 @@ int i2c_slave_write_buffer(i2c_port_t i2c_num, const uint8_t *data, int size, Ti
int i2c_slave_read_buffer(i2c_port_t i2c_num, uint8_t *data, size_t max_size, TickType_t ticks_to_wait)
{
ESP_RETURN_ON_FALSE(( i2c_num < I2C_NUM_MAX ), ESP_FAIL, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE((i2c_num < I2C_NUM_MAX), ESP_FAIL, I2C_TAG, I2C_NUM_ERROR_STR);
ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num] != NULL, ESP_FAIL, I2C_TAG, I2C_DRIVER_ERR_STR);
ESP_RETURN_ON_FALSE((data != NULL), ESP_FAIL, I2C_TAG, I2C_ADDR_ERROR_STR);
ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num]->mode == I2C_MODE_SLAVE, ESP_FAIL, I2C_TAG, I2C_MODE_SLAVE_ERR_STR);

4
components/driver/i2c/include/driver/i2c.h
View File

@ -60,7 +60,7 @@ extern "C" {
/**
* @brief I2C initialization parameters
*/
typedef struct{
typedef struct {
i2c_mode_t mode; /*!< I2C mode */
int sda_io_num; /*!< GPIO number for I2C sda signal */
int scl_io_num; /*!< GPIO number for I2C scl signal */
@ -82,7 +82,6 @@ typedef struct{
uint32_t clk_flags; /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
} i2c_config_t;
typedef void *i2c_cmd_handle_t; /*!< I2C command handle */
/**
@ -243,7 +242,6 @@ esp_err_t i2c_master_write_read_device(i2c_port_t i2c_num, uint8_t device_addres
uint8_t* read_buffer, size_t read_size,
TickType_t ticks_to_wait);
/**
* @brief Create and initialize an I2C commands list with a given buffer.
* All the allocations for data or signals (START, STOP, ACK, ...) will be

2
components/driver/test_apps/components/esp_serial_slave_link/essl.c
View File

@ -25,7 +25,6 @@
#define TIME_REMAIN(start, end, timeout) TIME_REMAIN_CORE(start, end, timeout, UINT32_MAX)
#define ESSL_MIN(a, b) ((a) < (b) ? (a) : (b))
__attribute__((unused)) static const char TAG[] = "esp_serial_slave_link";
@ -43,7 +42,6 @@ __attribute__((unused)) static const char TAG[] = "esp_serial_slave_link";
#define CHECK_EXECUTE_CMD(DEV, CMD, ...) _CHECK_EXECUTE_CMD(DEV, CMD, #CMD" not supported for the current device.",##__VA_ARGS__)
esp_err_t essl_init(essl_handle_t handle, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, init, wait_ms);

7
components/driver/test_apps/components/esp_serial_slave_link/essl_sdio.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,7 +28,6 @@ static const char TAG[] = "essl_sdio";
#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4)
#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC)
#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
#define ESSL_CMD53_END_ADDR 0x1f800
@ -79,7 +78,6 @@ typedef struct {
///< Block size of the SDIO function 1. After the initialization this will hold the value the slave really do. Valid value is 1-2048.
} essl_sdio_context_t;
esp_err_t essl_sdio_update_tx_buffer_num(void *arg, uint32_t wait_ms);
esp_err_t essl_sdio_update_rx_data_size(void *arg, uint32_t wait_ms);
@ -139,7 +137,7 @@ cleanup:
esp_err_t essl_sdio_deinit_dev(essl_handle_t handle)
{
if (handle) {
free (handle->args);
free(handle->args);
}
free(handle);
return ESP_OK;
@ -412,7 +410,6 @@ esp_err_t essl_sdio_update_rx_data_size(void *arg, uint32_t wait_ms)
return ESP_OK;
}
esp_err_t essl_sdio_write_reg(void *arg, uint8_t addr, uint8_t value, uint8_t *value_o, uint32_t wait_ms)
{
ESP_LOGV(TAG, "write_reg: 0x%02"PRIX8, value);

1
components/driver/test_apps/components/esp_serial_slave_link/essl_sdio_defs.c
View File

@ -6,7 +6,6 @@
// Definitions of Espressif SDIO Slave hardware
#include "essl_sdio.h"
essl_sdio_def_t ESSL_SDIO_DEF_ESP32 = {

2
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h
View File

@ -6,7 +6,6 @@
#pragma once
#include "esp_err.h"
#ifdef __cplusplus
@ -67,7 +66,6 @@ esp_err_t essl_get_tx_buffer_num(essl_handle_t handle, uint32_t *out_tx_num, uin
*/
esp_err_t essl_get_rx_data_size(essl_handle_t handle, uint32_t *out_rx_size, uint32_t wait_ms);
/** Reset the counters of this component. Usually you don't need to do this unless you know the slave is reset.
*
* @param handle Handle of an ESSL device.

1
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio_defs.h
View File

@ -25,7 +25,6 @@ extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32;
/// Definitions of ESP32C6 SDIO Slave hardware
extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32C6;
#ifdef __cplusplus
}
#endif

1
components/driver/test_apps/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// NOTE: From the view of master

2
components/driver/test_apps/components/test_driver_utils/include/test_dualboard_utils.h
View File

@ -23,7 +23,6 @@
*/
void test_fill_random_to_buffers_dualboard(uint32_t seed, uint8_t *dut0_buffer, uint8_t *dut1_buffer, size_t buffer_size);
/**
* Fill tx buffer with random numbers
*
@ -33,7 +32,6 @@ void test_fill_random_to_buffers_dualboard(uint32_t seed, uint8_t *dut0_buffer,
*/
void test_fill_random_to_buffer(uint32_t seed, uint8_t *buffer, size_t buffer_size);
/**
* Calloc a pool, filled with random numbers
*

9
components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -29,7 +29,6 @@
#define TEST_SPI_PERIPH_NUM (SOC_SPI_PERIPH_NUM - 1)
#if CONFIG_IDF_TARGET_ESP32C6 // cs_pin conflict with uart pin
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
@ -46,7 +45,6 @@
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#endif
#if (TEST_SPI_PERIPH_NUM >= 2) // esp32, s2, s3
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI3_HOST
@ -62,7 +60,6 @@
#define TEST_SLAVE_HOST SPI2_HOST
#endif
#if CONFIG_IDF_TARGET_ESP32 // spi3 have iomux pin only on esp32
#define SLAVE_IOMUX_PIN_MISO SPI3_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI SPI3_IOMUX_PIN_NUM_MOSI
@ -97,13 +94,11 @@
#define WIRE_DELAY 12.5
#endif //CONFIG_IDF_TARGET_ESP32
#define GET_DMA_CHAN(HOST) (HOST)
#define TEST_DMA_CHAN_MASTER GET_DMA_CHAN(TEST_SPI_HOST)
#define TEST_DMA_CHAN_SLAVE GET_DMA_CHAN(TEST_SLAVE_HOST)
#define FUNC_SPI 1
#define FUNC_GPIO PIN_FUNC_GPIO
@ -274,7 +269,7 @@ esp_err_t spitest_check_data(int len, spi_transaction_t *master_t, slave_rxdata_
static inline int get_trans_len(spi_dup_t dup, spi_transaction_t *master_t)
{
if (dup!=HALF_DUPLEX_MISO) {
if (dup != HALF_DUPLEX_MISO) {
return master_t->length;
} else {
return master_t->rxlength;

10
components/driver/test_apps/components/test_driver_utils/param_test.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,10 +16,12 @@ void test_serializer(const param_group_t *param_group, const ptest_func_t* test_
test_func->pre_test(&context);
void *pset = param_group->param_group;
for (int i = param_group->pset_num; i >0; i--) {
if (test_func->def_param) test_func->def_param(pset);
for (int i = param_group->pset_num; i > 0; i--) {
if (test_func->def_param) {
test_func->def_param(pset);
}
test_func->loop(pset, context);
pset+=param_group->pset_size;
pset += param_group->pset_size;
}
test_func->post_test(context);

1
components/driver/test_apps/components/test_driver_utils/test_dualboard_utils.c
View File

@ -29,7 +29,6 @@ void test_fill_random_to_buffer(uint32_t seed, uint8_t *buffer, size_t buffer_si
}
}
/*---------------------------------------------------------------
Create a pool with random numbers, get buffer from pool
---------------------------------------------------------------*/

100
components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,8 +10,7 @@
#include "hal/gpio_hal.h"
#include "esp_rom_gpio.h"
int test_freq_default[]=TEST_FREQ_DEFAULT();
int test_freq_default[] = TEST_FREQ_DEFAULT();
const char MASTER_TAG[] = "test_master";
const char SLAVE_TAG[] = "test_slave";
@ -23,7 +22,7 @@ DRAM_ATTR uint8_t spitest_master_send[] = {
0x74,
0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43,
0x74,
};
};
DRAM_ATTR uint8_t spitest_slave_send[] = {
0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0,
0xda,
@ -31,13 +30,15 @@ DRAM_ATTR uint8_t spitest_slave_send[] = {
0xda,
0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0,
0xda,
};
};
void spitest_def_param(void* arg)
{
spitest_param_set_t *param_set=(spitest_param_set_t*)arg;
spitest_param_set_t *param_set = (spitest_param_set_t*)arg;
param_set->test_size = 8;
if (param_set->freq_list==NULL) param_set->freq_list = test_freq_default;
if (param_set->freq_list == NULL) {
param_set->freq_list = test_freq_default;
}
}
/**********************************************************************************
@ -45,25 +46,25 @@ void spitest_def_param(void* arg)
*********************************************************************************/
esp_err_t init_slave_context(spi_slave_task_context_t *context, spi_host_device_t host)
{
context->data_to_send = xQueueCreate( 16, sizeof( slave_txdata_t ));
if ( context->data_to_send == NULL ) {
context->data_to_send = xQueueCreate(16, sizeof(slave_txdata_t));
if (context->data_to_send == NULL) {
return ESP_ERR_NO_MEM;
}
context->data_received = xRingbufferCreate( 1024, RINGBUF_TYPE_NOSPLIT );
if ( context->data_received == NULL ) {
context->data_received = xRingbufferCreate(1024, RINGBUF_TYPE_NOSPLIT);
if (context->data_received == NULL) {
return ESP_ERR_NO_MEM;
}
context->spi=host;
context->spi = host;
return ESP_OK;
}
void deinit_slave_context(spi_slave_task_context_t *context)
{
TEST_ASSERT( context->data_to_send != NULL );
vQueueDelete( context->data_to_send );
TEST_ASSERT(context->data_to_send != NULL);
vQueueDelete(context->data_to_send);
context->data_to_send = NULL;
TEST_ASSERT( context->data_received != NULL );
vRingbufferDelete( context->data_received );
TEST_ASSERT(context->data_received != NULL);
vRingbufferDelete(context->data_received);
context->data_received = NULL;
}
@ -76,27 +77,27 @@ void spitest_slave_task(void* arg)
spi_slave_task_context_t* context = (spi_slave_task_context_t*) arg;
QueueHandle_t queue = context->data_to_send;
RingbufHandle_t ringbuf = context->data_received;
uint8_t recvbuf[320+8];
uint8_t recvbuf[320 + 8];
slave_txdata_t txdata;
ESP_LOGI( SLAVE_TAG, "slave up" );
ESP_LOGI(SLAVE_TAG, "slave up");
//never quit, but blocked by the queue, waiting to be killed, when no more send from main task.
while( 1 ) {
BaseType_t ret = xQueueReceive( queue, &txdata, portMAX_DELAY );
while (1) {
BaseType_t ret = xQueueReceive(queue, &txdata, portMAX_DELAY);
assert(ret);
spi_slave_transaction_t t = {};
t.length = txdata.len;
t.tx_buffer = txdata.start;
t.rx_buffer = recvbuf+8;
t.rx_buffer = recvbuf + 8;
//loop until trans_len != 0 to skip glitches
do {
TEST_ESP_OK( spi_slave_transmit( context->spi, &t, portMAX_DELAY ) );
} while ( t.trans_len <= 2 );
TEST_ESP_OK(spi_slave_transmit(context->spi, &t, portMAX_DELAY));
} while (t.trans_len <= 2);
memcpy(recvbuf, &t.trans_len, sizeof(uint32_t));
*(uint8_t**)(recvbuf+4) = (uint8_t*)txdata.start;
ESP_LOGD( SLAVE_TAG, "received: %" PRIu32, (uint32_t)t.trans_len );
xRingbufferSend( ringbuf, recvbuf, 8+(t.trans_len+7)/8, portMAX_DELAY );
*(uint8_t**)(recvbuf + 4) = (uint8_t*)txdata.start;
ESP_LOGD(SLAVE_TAG, "received: %" PRIu32, (uint32_t)t.trans_len);
xRingbufferSend(ringbuf, recvbuf, 8 + (t.trans_len + 7) / 8, portMAX_DELAY);
}
}
@ -120,9 +121,11 @@ void spitest_init_transactions(const spitest_param_set_t *cfg, spitest_context_t
const spi_dup_t dup = cfg->dup;
for (int i = 0; i < cfg->test_size; i++) {
const void* tx_buffer = spitest_master_send + i%8;
int length = 8*test_len[i];
if (cfg->length_aligned) length = (length+31)&(~31);
const void* tx_buffer = spitest_master_send + i % 8;
int length = 8 * test_len[i];
if (cfg->length_aligned) {
length = (length + 31) & (~31);
}
if (dup == HALF_DUPLEX_MISO) {
trans[i] = (spi_transaction_t) {
@ -141,30 +144,38 @@ void spitest_init_transactions(const spitest_param_set_t *cfg, spitest_context_t
.rx_buffer = rx_buf_ptr,
};
}
rx_buf_ptr = (uint8_t*)( (uint32_t)(rx_buf_ptr + (length+7)/8 + 3) & (~3));
rx_buf_ptr = (uint8_t*)((uint32_t)(rx_buf_ptr + (length + 7) / 8 + 3) & (~3));
const void* slave_tx = spitest_slave_send + (cfg->slave_unaligned_addr? i%3: (i%3)*4);
const void* slave_tx = spitest_slave_send + (cfg->slave_unaligned_addr ? i % 3 : (i % 3) * 4);
//prepare slave tx data
context->slave_trans[i] = (slave_txdata_t) {
.start = slave_tx,
.len = 512,
};
if (cfg->slave_dma_chan != 0) context->slave_trans[i].len = 1024;
if (cfg->slave_dma_chan != 0) {
context->slave_trans[i].len = 1024;
}
}
}
void spitest_master_print_data(spi_transaction_t *t, int rxlength)
{
if (t->tx_buffer) ESP_LOG_BUFFER_HEX( "master tx", t->tx_buffer, t->length/8 );
if (t->rx_buffer) ESP_LOG_BUFFER_HEX( "master rx", t->rx_buffer, rxlength/8 );
if (t->tx_buffer) {
ESP_LOG_BUFFER_HEX("master tx", t->tx_buffer, t->length / 8);
}
if (t->rx_buffer) {
ESP_LOG_BUFFER_HEX("master rx", t->rx_buffer, rxlength / 8);
}
}
void spitest_slave_print_data(slave_rxdata_t *t, bool print_rxdata)
{
int rcv_len = (t->len+7)/8;
int rcv_len = (t->len + 7) / 8;
ESP_LOGI(SLAVE_TAG, "trans_len: %" PRIu32, t->len);
ESP_LOG_BUFFER_HEX("slave tx", t->tx_start, rcv_len);
if (print_rxdata) ESP_LOG_BUFFER_HEX("slave rx", t->data, rcv_len);
if (print_rxdata) {
ESP_LOG_BUFFER_HEX("slave rx", t->data, rcv_len);
}
}
esp_err_t spitest_check_data(int len, spi_transaction_t *master_t, slave_rxdata_t *slave_t, bool check_master_data, bool check_slave_len, bool check_slave_data)
@ -173,18 +184,18 @@ esp_err_t spitest_check_data(int len, spi_transaction_t *master_t, slave_rxdata_
uint32_t rcv_len = slave_t->len;
//currently the rcv_len can be in range of [t->length-1, t->length+3]
if (check_slave_len &&
(rcv_len < len - 1 || rcv_len > len + 4)) {
ret = ESP_FAIL;
(rcv_len < len - 1 || rcv_len > len + 4)) {
ret = ESP_FAIL;
}
if (check_master_data &&
memcmp(slave_t->tx_start, master_t->rx_buffer, (len + 7) / 8) != 0 ) {
ret = ESP_FAIL;
memcmp(slave_t->tx_start, master_t->rx_buffer, (len + 7) / 8) != 0) {
ret = ESP_FAIL;
}
if (check_slave_data &&
memcmp(master_t->tx_buffer, slave_t->data, (len + 7) / 8) != 0 ) {
ret = ESP_FAIL;
memcmp(master_t->tx_buffer, slave_t->data, (len + 7) / 8) != 0) {
ret = ESP_FAIL;
}
if (ret != ESP_OK) {
ESP_LOGI(SLAVE_TAG, "slave_recv_len: %" PRIu32, rcv_len);
@ -201,11 +212,10 @@ esp_err_t spitest_check_data(int len, spi_transaction_t *master_t, slave_rxdata_
return ESP_OK;
}
void master_free_device_bus(spi_device_handle_t spi)
{
TEST_ESP_OK( spi_bus_remove_device(spi) );
TEST_ESP_OK( spi_bus_free(TEST_SPI_HOST) );
TEST_ESP_OK(spi_bus_remove_device(spi));
TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
}
void spitest_gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx)

48
components/driver/test_apps/dac_test_apps/legacy_dac_driver/main/test_legacy_dac.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -48,17 +48,17 @@ TEST_CASE("DAC_output(RTC)_check_by_adc", "[dac_legacy]")
{
gpio_num_t adc_gpio_num, dac_gpio_num;
TEST_ESP_OK( adc2_pad_get_io_num( ADC_TEST_CHANNEL_NUM, &adc_gpio_num ) );
TEST_ESP_OK( dac_pad_get_io_num( DAC_TEST_CHANNEL_NUM, &dac_gpio_num ) );
TEST_ESP_OK(adc2_pad_get_io_num(ADC_TEST_CHANNEL_NUM, &adc_gpio_num));
TEST_ESP_OK(dac_pad_get_io_num(DAC_TEST_CHANNEL_NUM, &dac_gpio_num));
printf("Please connect ADC2 CH%d-GPIO%d <--> DAC CH%d-GPIO%d.\n", ADC_TEST_CHANNEL_NUM, adc_gpio_num,
DAC_TEST_CHANNEL_NUM + 1, dac_gpio_num );
DAC_TEST_CHANNEL_NUM + 1, dac_gpio_num);
TEST_ESP_OK( dac_output_enable( DAC_TEST_CHANNEL_NUM ) );
TEST_ESP_OK(dac_output_enable(DAC_TEST_CHANNEL_NUM));
//be sure to do the init before using adc2.
printf("adc2_init...\n");
TEST_ESP_OK( adc2_config_channel_atten( ADC_TEST_CHANNEL_NUM, ADC_TEST_ATTEN ) );
TEST_ESP_OK(adc2_config_channel_atten(ADC_TEST_CHANNEL_NUM, ADC_TEST_ATTEN));
vTaskDelay(2 * portTICK_PERIOD_MS);
@ -66,28 +66,28 @@ TEST_CASE("DAC_output(RTC)_check_by_adc", "[dac_legacy]")
int output_data = 0;
int read_raw = 0, read_old = 0;
for (int i = 0; i < DAC_OUT_TIMES; i++) {
TEST_ESP_OK( dac_output_voltage( DAC_TEST_CHANNEL_NUM, output_data ) );
TEST_ESP_OK(dac_output_voltage(DAC_TEST_CHANNEL_NUM, output_data));
output_data += DAC_OUT_STEP;
vTaskDelay(2 * portTICK_PERIOD_MS);
TEST_ESP_OK( adc2_get_raw( ADC_TEST_CHANNEL_NUM, ADC_TEST_WIDTH, &read_raw) );
TEST_ESP_OK(adc2_get_raw(ADC_TEST_CHANNEL_NUM, ADC_TEST_WIDTH, &read_raw));
ESP_LOGI(TAG, "DAC: %d - ADC: %d", output_data, read_raw);
if (read_old != 0) {
TEST_ASSERT_GREATER_THAN(read_old, read_raw);
}
read_old = read_raw;
}
TEST_ESP_OK( dac_output_disable( DAC_TEST_CHANNEL_NUM ) );
TEST_ESP_OK(dac_output_disable(DAC_TEST_CHANNEL_NUM));
}
TEST_CASE("DAC_cw_generator_output(RTC)_check_by_adc", "[dac_legacy]")
{
gpio_num_t adc_gpio_num, dac_gpio_num;
TEST_ESP_OK( adc2_pad_get_io_num( ADC_TEST_CHANNEL_NUM, &adc_gpio_num ) );
TEST_ESP_OK( dac_pad_get_io_num( DAC_TEST_CHANNEL_NUM, &dac_gpio_num ) );
TEST_ESP_OK(adc2_pad_get_io_num(ADC_TEST_CHANNEL_NUM, &adc_gpio_num));
TEST_ESP_OK(dac_pad_get_io_num(DAC_TEST_CHANNEL_NUM, &dac_gpio_num));
printf("Please connect ADC2 CH%d-GPIO%d <--> DAC CH%d-GPIO%d.\n", ADC_TEST_CHANNEL_NUM, adc_gpio_num,
DAC_TEST_CHANNEL_NUM + 1, dac_gpio_num );
DAC_TEST_CHANNEL_NUM + 1, dac_gpio_num);
dac_cw_config_t cw = {
.en_ch = DAC_TEST_CHANNEL_NUM,
@ -100,13 +100,13 @@ TEST_CASE("DAC_cw_generator_output(RTC)_check_by_adc", "[dac_legacy]")
.offset = 16,
#endif
};
TEST_ESP_OK( dac_cw_generator_config(&cw) );
TEST_ESP_OK( dac_cw_generator_enable() );
TEST_ESP_OK( dac_output_enable( DAC_TEST_CHANNEL_NUM ) );
TEST_ESP_OK(dac_cw_generator_config(&cw));
TEST_ESP_OK(dac_cw_generator_enable());
TEST_ESP_OK(dac_output_enable(DAC_TEST_CHANNEL_NUM));
//be sure to do the init before using adc2.
printf("adc2_init...\n");
TEST_ESP_OK( adc2_config_channel_atten( ADC_TEST_CHANNEL_NUM, ADC_TEST_ATTEN ) );
TEST_ESP_OK(adc2_config_channel_atten(ADC_TEST_CHANNEL_NUM, ADC_TEST_ATTEN));
vTaskDelay(2 * portTICK_PERIOD_MS);
@ -114,14 +114,14 @@ TEST_CASE("DAC_cw_generator_output(RTC)_check_by_adc", "[dac_legacy]")
int read_raw[3] = {0};
for (int i = 0; i < DAC_TEST_TIMES; i++) {
vTaskDelay(10 * portTICK_PERIOD_MS);
TEST_ESP_OK( adc2_get_raw( ADC_TEST_CHANNEL_NUM, ADC_TEST_WIDTH, &read_raw[0]) );
TEST_ESP_OK(adc2_get_raw(ADC_TEST_CHANNEL_NUM, ADC_TEST_WIDTH, &read_raw[0]));
ESP_LOGI(TAG, "ADC: %d", read_raw[0]);
read_raw[2] = read_raw[1];
read_raw[1] = read_raw[0];
}
TEST_ESP_OK( dac_cw_generator_disable() );
TEST_ESP_OK( dac_output_disable( DAC_TEST_CHANNEL_NUM ) );
TEST_ESP_OK(dac_cw_generator_disable());
TEST_ESP_OK(dac_output_disable(DAC_TEST_CHANNEL_NUM));
}
#if CONFIG_IDF_TARGET_ESP32S2
@ -136,7 +136,7 @@ static bool subtest_adc_dac(int mV_ref, esp_adc_cal_characteristics_t * chars)
int raw;
adc2_get_raw((adc2_channel_t)ADC_TEST_CHANNEL_NUM, ADC_WIDTH_BIT_13, &raw);
uint32_t voltage = esp_adc_cal_raw_to_voltage(raw, chars);
TEST_ASSERT_INT_WITHIN( 200, mV_ref, voltage ); // 200 mV error allowance, because both DAC and ADC have error
TEST_ASSERT_INT_WITHIN(200, mV_ref, voltage); // 200 mV error allowance, because both DAC and ADC have error
return true;
}
@ -146,11 +146,11 @@ TEST_CASE("esp32s2_adc2-dac_with_adc2_calibration", "[dac_legacy]")
if (esp_adc_cal_check_efuse(ESP_ADC_CAL_VAL_EFUSE_TP) != ESP_OK) {
TEST_IGNORE_MESSAGE("Warning: This esp32s2 board does not support calibration. This test will be skipped.\n");
}
TEST_ESP_OK( adc2_pad_get_io_num( ADC_TEST_CHANNEL_NUM, &adc_gpio_num ) );
TEST_ESP_OK( dac_pad_get_io_num( DAC_TEST_CHANNEL_NUM, &dac_gpio_num ) );
TEST_ESP_OK(adc2_pad_get_io_num(ADC_TEST_CHANNEL_NUM, &adc_gpio_num));
TEST_ESP_OK(dac_pad_get_io_num(DAC_TEST_CHANNEL_NUM, &dac_gpio_num));
printf("Please connect ADC2 CH%d-GPIO%d <--> DAC CH%d-GPIO%d.\n", ADC_TEST_CHANNEL_NUM, adc_gpio_num,
DAC_TEST_CHANNEL_NUM + 1, dac_gpio_num );
TEST_ESP_OK( dac_output_enable( DAC_TEST_CHANNEL_NUM ) );
DAC_TEST_CHANNEL_NUM + 1, dac_gpio_num);
TEST_ESP_OK(dac_output_enable(DAC_TEST_CHANNEL_NUM));
esp_adc_cal_characteristics_t chars;

3
components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
View File

@ -85,14 +85,13 @@
const __attribute__((unused)) static char *TAG = "TEST_ADC_LEGACY";
void test_adc_set_io_level(adc_unit_t unit, adc_channel_t channel, bool level)
{
TEST_ASSERT(channel < SOC_ADC_CHANNEL_NUM(unit) && "invalid channel");
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
uint32_t io_num = ADC_GET_IO_NUM(unit, channel);
TEST_ESP_OK(gpio_set_pull_mode(io_num, (level ? GPIO_PULLUP_ONLY: GPIO_PULLDOWN_ONLY)));
TEST_ESP_OK(gpio_set_pull_mode(io_num, (level ? GPIO_PULLUP_ONLY : GPIO_PULLDOWN_ONLY)));
#else
gpio_num_t io_num = ADC_GET_IO_NUM(unit, channel);
if (level) {

68
components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
View File

@ -50,17 +50,16 @@ static DRAM_ATTR i2c_dev_t *const I2C[SOC_I2C_NUM] = { &I2C0,
#if SOC_I2C_NUM > 1
&I2C1,
#endif
};
};
#define ACK_VAL 0
#define NACK_VAL 1
static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, size_t size)
{
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
TEST_ESP_OK(i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | WRITE_BIT, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_write_byte(cmd, (ESP_SLAVE_ADDR << 1) | WRITE_BIT, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_write(cmd, data_wr, size, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_stop(cmd));
esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 5000 / portTICK_PERIOD_MS);
@ -82,7 +81,6 @@ static i2c_config_t i2c_master_init(void)
return conf_master;
}
#if SOC_I2C_SUPPORT_SLAVE // i2c test can't work without slave
static i2c_config_t i2c_slave_init(void)
@ -103,7 +101,7 @@ static i2c_config_t i2c_slave_init(void)
TEST_CASE("I2C i2c_set_pin() fails if sda and scl gpios are same", "[i2c]")
{
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, i2c_set_pin(0, 0, 0, true, true , I2C_MODE_MASTER));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, i2c_set_pin(0, 0, 0, true, true, I2C_MODE_MASTER));
}
TEST_CASE("I2C config test", "[i2c]")
@ -137,7 +135,7 @@ TEST_CASE("I2C config test", "[i2c]")
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ASSERT_EQUAL_INT32(I2C[I2C_SLAVE_NUM] -> ctr.ms_mode, 0);
TEST_ESP_OK(i2c_driver_delete(I2C_SLAVE_NUM));
}
@ -169,16 +167,15 @@ TEST_CASE("I2C set and get period test", "[i2c]")
TEST_ESP_OK(i2c_driver_delete(I2C_MASTER_NUM));
}
#if SOC_I2C_SUPPORT_SLAVE // i2c test can't work without slave
TEST_CASE("I2C config FIFO test", "[i2c]")
{
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ASSERT_BIT_LOW(1, I2C[I2C_SLAVE_NUM]->fifo_conf.tx_fifo_rst);
TEST_ESP_OK(i2c_reset_tx_fifo(I2C_SLAVE_NUM));
TEST_ASSERT_BIT_LOW(0, I2C[I2C_SLAVE_NUM]->fifo_conf.tx_fifo_rst);
@ -245,7 +242,7 @@ static void disp_buf(uint8_t *buf, int len)
int i;
for (i = 0; i < len; i++) {
printf("%02x ", buf[i]);
if (( i + 1 ) % 16 == 0) {
if ((i + 1) % 16 == 0) {
printf("\n");
}
}
@ -283,7 +280,7 @@ static void i2c_slave_read_test(void)
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@ -291,7 +288,7 @@ static void i2c_slave_read_test(void)
unity_wait_for_signal("master write");
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
len = i2c_slave_read_buffer(I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
if (len == 0) {
break;
}
@ -321,19 +318,19 @@ static void master_read_slave_test(void)
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
i2c_master_write_byte(cmd, (ESP_SLAVE_ADDR << 1) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH-1, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH-1, NACK_VAL);
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH - 1, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH - 1, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_PERIOD_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_PERIOD_MS);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("%d\n", data_rd[i]);
TEST_ASSERT(data_rd[i]==i);
TEST_ASSERT(data_rd[i] == i);
}
free(data_rd);
unity_send_signal("ready to delete");
@ -346,7 +343,7 @@ static void slave_write_buffer_test(void)
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@ -364,10 +361,8 @@ static void slave_write_buffer_test(void)
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=generic_multi_device][timeout=150]", master_read_slave_test, slave_write_buffer_test);
static void i2c_master_write_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
@ -382,7 +377,7 @@ static void i2c_master_write_read_test(void)
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
i2c_master_write_byte(cmd, (ESP_SLAVE_ADDR << 1) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read and write");
@ -394,7 +389,7 @@ static void i2c_master_write_read_test(void)
vTaskDelay(100 / portTICK_PERIOD_MS);
disp_buf(data_rd, RW_TEST_LENGTH);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i/2);
TEST_ASSERT(data_rd[i] == i / 2);
}
for (int i = 0; i < DATA_LENGTH; i++) {
@ -418,7 +413,7 @@ static void i2c_slave_read_write_test(void)
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@ -426,13 +421,13 @@ static void i2c_slave_read_write_test(void)
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i/2;
data_wr[i] = i / 2;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_PERIOD_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read and write");
unity_wait_for_signal("slave read");
size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_PERIOD_MS);
size_rd = i2c_slave_read_buffer(I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_PERIOD_MS);
printf("slave read data is:\n");
disp_buf(data_rd, size_rd);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
@ -446,7 +441,6 @@ static void i2c_slave_read_write_test(void)
TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=generic_multi_device][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test);
static void i2c_master_repeat_write(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
@ -480,7 +474,7 @@ static void i2c_slave_repeat_read(void)
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH * 3);
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@ -488,7 +482,7 @@ static void i2c_slave_repeat_read(void)
unity_wait_for_signal("master write");
while (1) {
int len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_PERIOD_MS);
int len = i2c_slave_read_buffer(I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_PERIOD_MS);
if (len == 0) {
break;
}
@ -541,7 +535,7 @@ static void i2c_slave_read_test_more_ports(void)
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_NUM_1, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_NUM_1, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_NUM_1, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@ -549,7 +543,7 @@ static void i2c_slave_read_test_more_ports(void)
unity_wait_for_signal("master write");
while (1) {
len = i2c_slave_read_buffer( I2C_NUM_1, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
len = i2c_slave_read_buffer(I2C_NUM_1, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
if (len == 0) {
break;
}
@ -580,14 +574,14 @@ static void test_task(void *pvParameters)
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
while (exit_flag == false) {
if (test_read_func) {
i2c_slave_read_buffer(I2C_SLAVE_NUM, data, DATA_LENGTH, 0);
} else {
i2c_slave_write_buffer(I2C_SLAVE_NUM, data, DATA_LENGTH, 0);
}
vTaskDelay(10/portTICK_PERIOD_MS);
vTaskDelay(10 / portTICK_PERIOD_MS);
}
free(data);
@ -651,9 +645,9 @@ TEST_CASE("I2C general API test", "[i2c]")
.sda_io_num = I2C_MASTER_SDA_IO,
.scl_io_num = I2C_MASTER_SCL_IO,
};
TEST_ESP_OK(i2c_param_config( i2c_num, &conf_master));
TEST_ESP_OK(i2c_param_config(i2c_num, &conf_master));
int time_get0, time_get1;
for(int i = 10; i < I2C_TEST_TIME; i++) {
for (int i = 10; i < I2C_TEST_TIME; i++) {
//set period test
TEST_ESP_OK(i2c_set_period(i2c_num, i, i));
TEST_ESP_OK(i2c_get_period(i2c_num, &time_get0, &time_get1));
@ -708,11 +702,11 @@ static void i2c_scl_freq_cal(void)
int negpulse_cnt = uart_ll_get_neg_pulse_cnt(&UART1);
int high_period_cnt = uart_ll_get_high_pulse_cnt(&UART1);
int low_period_cnt = uart_ll_get_low_pulse_cnt(&UART1);
if(edg_cnt != expt_cnt) {
if (edg_cnt != expt_cnt) {
printf("\nedg_cnt != %d, test fail\n", expt_cnt);
return;
}
printf("\nDetected SCL frequency: %d Hz\n", i2c_source_clk_freq / ((pospulse_cnt + negpulse_cnt) / 2) );
printf("\nDetected SCL frequency: %d Hz\n", i2c_source_clk_freq / ((pospulse_cnt + negpulse_cnt) / 2));
printf("\nSCL high period %.3f (us), SCL low_period %.3f (us)\n\n", (float)(i2c_cource_clk_period * high_period_cnt), (float)(i2c_cource_clk_period * low_period_cnt));
uart_ll_set_autobaud_en(&UART1, false);
@ -733,7 +727,7 @@ TEST_CASE("I2C SCL freq test (local test)", "[i2c][ignore]")
.scl_io_num = I2C_MASTER_SCL_IO,
};
uint8_t *data = (uint8_t *)malloc(30);
TEST_ESP_OK(i2c_param_config( i2c_num, &conf_master));
TEST_ESP_OK(i2c_param_config(i2c_num, &conf_master));
TEST_ESP_OK(i2c_driver_install(i2c_num, I2C_MODE_MASTER, 0, 0, 0));
memset(data, 0, 0);
uart_aut_baud_det_init(uart1_rxd_io);

11
components/driver/test_apps/legacy_i2c_driver/main/test_legacy_i2c_sleep_retention.c
View File

@ -40,12 +40,11 @@
#define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, size_t size)
{
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
TEST_ESP_OK(i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | WRITE_BIT, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_write_byte(cmd, (ESP_SLAVE_ADDR << 1) | WRITE_BIT, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_write(cmd, data_wr, size, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_stop(cmd));
esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 5000 / portTICK_PERIOD_MS);
@ -87,7 +86,7 @@ static void disp_buf(uint8_t *buf, int len)
int i;
for (i = 0; i < len; i++) {
printf("%02x ", buf[i]);
if (( i + 1 ) % 16 == 0) {
if ((i + 1) % 16 == 0) {
printf("\n");
}
}
@ -143,7 +142,7 @@ static void i2c_slave_read_sleep_test(void)
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@ -151,7 +150,7 @@ static void i2c_slave_read_sleep_test(void)
unity_wait_for_signal("master write and sleep");
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
len = i2c_slave_read_buffer(I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
if (len == 0) {
break;
}
@ -173,7 +172,7 @@ static void i2c_slave_read_sleep_test(void)
memset(data_rd, 0, DATA_LENGTH);
size_rd = 0;
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
len = i2c_slave_read_buffer(I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_PERIOD_MS);
if (len == 0) {
break;
}

88
components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -89,11 +89,11 @@ static esp_err_t test_touch_sw_read_test_runner(void)
ESP_LOGI(TAG, "%s", __func__);
uint16_t touch_value;
TEST_ESP_OK( touch_pad_init() );
TEST_ESP_OK( touch_pad_set_fsm_mode(TOUCH_FSM_MODE_SW) );
TEST_ESP_OK(touch_pad_init());
TEST_ESP_OK(touch_pad_set_fsm_mode(TOUCH_FSM_MODE_SW));
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL) );
TEST_ESP_OK(touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL));
}
// Start task to read values sensed by pads
@ -104,7 +104,7 @@ static esp_err_t test_touch_sw_read_test_runner(void)
}
printf("\n");
TEST_ESP_OK( touch_pad_deinit() );
TEST_ESP_OK(touch_pad_deinit());
return ESP_OK;
}
@ -114,23 +114,23 @@ static esp_err_t test_touch_sw_read(void)
ESP_LOGI(TAG, "%s", __func__);
uint16_t touch_value;
TEST_ESP_OK( touch_pad_init() );
TEST_ESP_OK( touch_pad_set_fsm_mode(TOUCH_FSM_MODE_SW) );
TEST_ESP_OK(touch_pad_init());
TEST_ESP_OK(touch_pad_set_fsm_mode(TOUCH_FSM_MODE_SW));
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL) );
TEST_ESP_OK(touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL));
}
// Start task to read values sensed by pads
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
printf("test T%d\n", touch_list[i]);
TEST_ESP_OK( touch_pad_read(touch_list[i], &touch_value) );
TEST_ESP_OK(touch_pad_read(touch_list[i], &touch_value));
printf("T%d:[%4d] ", touch_list[i], touch_value);
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value);
}
printf("\n");
TEST_ESP_OK( touch_pad_deinit() );
TEST_ESP_OK(touch_pad_deinit());
return ESP_OK;
}
@ -141,29 +141,29 @@ static esp_err_t test_touch_timer_read(void)
uint16_t touch_value[TEST_TOUCH_CHANNEL], touch_temp[TEST_TOUCH_CHANNEL];
int t_cnt = TEST_TOUCH_COUNT_NUM;
TEST_ESP_OK( touch_pad_init() );
TEST_ESP_OK( touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER) );
TEST_ESP_OK(touch_pad_init());
TEST_ESP_OK(touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER));
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL) );
TEST_ESP_OK(touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL));
}
// Start task to read values sensed by pads
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_read(touch_list[i], &touch_value[i]) );
TEST_ESP_OK(touch_pad_read(touch_list[i], &touch_value[i]));
printf("T%d:[%4d] ", touch_list[i], touch_value[i]);
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value[i]);
}
while (t_cnt--) {
// Start task to read values sensed by pads
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_read(touch_list[i], &touch_temp[i]) );
TEST_ESP_OK(touch_pad_read(touch_list[i], &touch_temp[i]));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_temp[i]);
TEST_ASSERT_UINT32_WITHIN((uint32_t)((float)touch_temp[i]*TOUCH_READ_ERROR_THRESH), touch_temp[i], touch_value[i]);
}
vTaskDelay(50 / portTICK_PERIOD_MS);
}
TEST_ESP_OK( touch_pad_deinit() );
TEST_ESP_OK(touch_pad_deinit());
return ESP_OK;
}
@ -174,11 +174,11 @@ static esp_err_t test_touch_filtered_read(void)
uint16_t touch_value, touch_temp;
int t_cnt = TEST_TOUCH_COUNT_NUM;
TEST_ESP_OK( touch_pad_init() );
TEST_ESP_OK( touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER) );
TEST_ESP_OK(touch_pad_init());
TEST_ESP_OK(touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER));
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL) );
TEST_ESP_OK(touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL));
}
// Initialize and start a software filter to detect slight change of capacitance.
touch_pad_filter_start(TOUCHPAD_FILTER_TOUCH_PERIOD);
@ -186,20 +186,20 @@ static esp_err_t test_touch_filtered_read(void)
while (t_cnt--) {
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_read(touch_list[i], &touch_value) );
TEST_ESP_OK(touch_pad_read(touch_list[i], &touch_value));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value);
TEST_ESP_OK( touch_pad_read_raw_data(touch_list[i], &touch_value) );
TEST_ESP_OK(touch_pad_read_raw_data(touch_list[i], &touch_value));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value);
TEST_ESP_OK( touch_pad_read_filtered(touch_list[i], &touch_temp) );
TEST_ESP_OK(touch_pad_read_filtered(touch_list[i], &touch_temp));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_temp);
TEST_ASSERT_UINT32_WITHIN((uint32_t)((float)touch_temp*TOUCH_READ_ERROR_THRESH), touch_temp, touch_value);
TEST_ASSERT_UINT32_WITHIN((uint32_t)((float)touch_temp * TOUCH_READ_ERROR_THRESH), touch_temp, touch_value);
printf("T%d:[%4d] ", touch_list[i], touch_value);
}
vTaskDelay(50 / portTICK_PERIOD_MS);
}
printf("\n");
TEST_ESP_OK( touch_pad_deinit() );
TEST_ESP_OK(touch_pad_deinit());
return ESP_OK;
}
@ -214,9 +214,9 @@ TEST_CASE("Touch Sensor all channel read test", "[touch]")
#endif
TOUCH_REG_BASE_TEST();
test_touch_sw_read_test_runner();
TEST_ESP_OK( test_touch_sw_read() );
TEST_ESP_OK( test_touch_timer_read() );
TEST_ESP_OK( test_touch_filtered_read() );
TEST_ESP_OK(test_touch_sw_read());
TEST_ESP_OK(test_touch_timer_read());
TEST_ESP_OK(test_touch_filtered_read());
#if CONFIG_PM_ENABLE
TEST_ESP_OK(esp_pm_lock_release(pm_lock));
TEST_ESP_OK(esp_pm_lock_delete(pm_lock));
@ -227,9 +227,9 @@ static int test_touch_parameter(touch_pad_t pad_num, int meas_time, int slp_time
{
ESP_LOGI(TAG, "%s", __func__);
uint16_t touch_value;
TEST_ESP_OK( touch_pad_init() );
TEST_ESP_OK( touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER) );
TEST_ESP_OK( touch_pad_config(pad_num, TOUCH_READ_INVALID_VAL) );
TEST_ESP_OK(touch_pad_init());
TEST_ESP_OK(touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER));
TEST_ESP_OK(touch_pad_config(pad_num, TOUCH_READ_INVALID_VAL));
touch_pad_set_measurement_interval(slp_time);
touch_pad_set_measurement_clock_cycles(meas_time);
@ -241,17 +241,17 @@ static int test_touch_parameter(touch_pad_t pad_num, int meas_time, int slp_time
vTaskDelay(500 / portTICK_PERIOD_MS);
// Start task to read values sensed by pads
TEST_ESP_OK( touch_pad_read(pad_num, &touch_value) );
TEST_ESP_OK(touch_pad_read(pad_num, &touch_value));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value);
printf("T%d:[%4d] ", pad_num, touch_value);
TEST_ESP_OK( touch_pad_read_raw_data(pad_num, &touch_value) );
TEST_ESP_OK(touch_pad_read_raw_data(pad_num, &touch_value));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value);
printf("T%d:[%4d] ", pad_num, touch_value);
TEST_ESP_OK( touch_pad_read_filtered(pad_num, &touch_value) );
TEST_ESP_OK(touch_pad_read_filtered(pad_num, &touch_value));
TEST_ASSERT_NOT_EQUAL(TOUCH_READ_INVALID_VAL, touch_value);
printf("T%d:[%4d] \n", pad_num, touch_value);
TEST_ESP_OK( touch_pad_deinit() );
TEST_ESP_OK(touch_pad_deinit());
return touch_value;
}
@ -316,12 +316,12 @@ static esp_err_t test_touch_interrupt(void)
ESP_LOGI(TAG, "%s", __func__);
uint16_t touch_value;
TEST_ESP_OK( touch_pad_init() );
TEST_ESP_OK( touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER) );
TEST_ESP_OK(touch_pad_init());
TEST_ESP_OK(touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER));
touch_pad_set_voltage(TOUCH_HVOLT_2V7, TOUCH_LVOLT_0V5, TOUCH_HVOLT_ATTEN_1V);
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
TEST_ESP_OK( touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL) );
TEST_ESP_OK(touch_pad_config(touch_list[i], TOUCH_READ_INVALID_VAL));
}
// Initialize and start a software filter to detect slight change of capacitance.
touch_pad_filter_start(TOUCHPAD_FILTER_TOUCH_PERIOD);
@ -329,16 +329,16 @@ static esp_err_t test_touch_interrupt(void)
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
//read filtered value
TEST_ESP_OK( touch_pad_read_filtered(touch_list[i], &touch_value) );
TEST_ESP_OK(touch_pad_read_filtered(touch_list[i], &touch_value));
ESP_LOGI(TAG, "test init: touch pad [%d] val is %d", touch_list[i], touch_value);
//set interrupt threshold.
TEST_ESP_OK( touch_pad_set_thresh(touch_list[i], touch_value * 2 / 3) );
TEST_ESP_OK(touch_pad_set_thresh(touch_list[i], touch_value * 2 / 3));
}
// Register touch interrupt ISR
TEST_ESP_OK( touch_pad_isr_register(test_touch_intr_cb, NULL) );
TEST_ESP_OK( touch_pad_clear_status() );
TEST_ESP_OK( touch_pad_intr_enable() );
TEST_ESP_OK(touch_pad_isr_register(test_touch_intr_cb, NULL));
TEST_ESP_OK(touch_pad_clear_status());
TEST_ESP_OK(touch_pad_intr_enable());
int test_cnt = TEST_TOUCH_COUNT_NUM;
while (test_cnt--) {
@ -366,12 +366,12 @@ static esp_err_t test_touch_interrupt(void)
printf_touch_hw_read("release");
}
TEST_ESP_OK( touch_pad_deinit() );
TEST_ESP_OK(touch_pad_deinit());
return ESP_OK;
}
TEST_CASE("Touch Sensor interrupt test", "[touch]")
{
TEST_ESP_OK( test_touch_interrupt() );
TEST_ESP_OK(test_touch_interrupt());
}

716
components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c
View File

File diff suppressed because it is too large Load Diff

62
components/driver/test_apps/touch_sensor_v2/main/touch_scope.c
View File

@ -45,20 +45,20 @@ static void float_to_byte(float *target, unsigned char *buf, unsigned char offse
*/
static void datascope_get_channel_data(float data, unsigned char channel)
{
if ( (channel > 10) || (channel == 0) ) {
if ((channel > 10) || (channel == 0)) {
return;
} else {
switch (channel) {
case 1: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 2: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 3: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 4: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 5: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 6: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 7: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 8: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 9: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 10: float_to_byte(&data,datascope_output_buffer, channel*4-3); break;
case 1: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 2: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 3: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 4: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 5: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 6: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 7: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 8: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 9: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
case 10: float_to_byte(&data, datascope_output_buffer, channel * 4 - 3); break;
}
}
}
@ -71,21 +71,21 @@ static void datascope_get_channel_data(float data, unsigned char channel)
*/
static unsigned char datascope_data_generate(unsigned char channel_num)
{
if ( (channel_num > 10) || (channel_num == 0) ) {
if ((channel_num > 10) || (channel_num == 0)) {
return 0;
} else {
datascope_output_buffer[0] = '$'; //frame header
switch(channel_num) {
case 1: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 2: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 3: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 4: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 5: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 6: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 7: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 8: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 9: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
case 10: datascope_output_buffer[channel_num*4+1] = channel_num*4+1; return channel_num*4+2; break;
switch (channel_num) {
case 1: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 2: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 3: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 4: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 5: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 6: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 7: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 8: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 9: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
case 10: datascope_output_buffer[channel_num * 4 + 1] = channel_num * 4 + 1; return channel_num * 4 + 2; break;
}
}
return 0;
@ -107,21 +107,21 @@ int test_tp_print_to_scope(float *data, unsigned char channel_num)
if (uart_num >= UART_NUM_MAX) {
return ESP_FAIL;
}
if ( (channel_num > 10) || (channel_num == 0) || (NULL == data) ) {
if ((channel_num > 10) || (channel_num == 0) || (NULL == data)) {
return ESP_FAIL;
}
for(uint8_t i = 0 ; i < channel_num; i++) {
datascope_get_channel_data(data[i] , i+1); // write data x into channel 1~10.
for (uint8_t i = 0 ; i < channel_num; i++) {
datascope_get_channel_data(data[i], i + 1); // write data x into channel 1~10.
}
unsigned char out_len = datascope_data_generate(channel_num); // Generate n number data.
unsigned char *out_data = datascope_output_buffer;
// Init uart.
if(uart_num != uart_used) {
if (uart_num != uart_used) {
return 0;
} else {
#if ROM_UART_DRIVER_ENABLE
esp_rom_output_tx_wait_idle(uart_num); // Default print uart mumber is 0.
for(int i=0; i<out_len; i++) {
for (int i = 0; i < out_len; i++) {
esp_rom_output_tx_one_char(out_data[i]);
}
return out_len;
@ -155,11 +155,11 @@ esp_err_t test_tp_scope_debug_init(uint8_t uart_num, int tx_io_num, int rx_io_nu
{
#if ROM_UART_DRIVER_ENABLE
esp_rom_output_tx_wait_idle(0); // Default print uart mumber is 0.
if(uart_num != 0) {
if (uart_num != 0) {
esp_rom_output_set_as_console(uart_num);
}
#else
if(uart_used == uart_num) {
if (uart_used == uart_num) {
return ESP_FAIL;
}
if (uart_num >= UART_NUM_MAX) {
@ -179,7 +179,7 @@ esp_err_t test_tp_scope_debug_init(uint8_t uart_num, int tx_io_num, int rx_io_nu
uart_param_config(uart_num, &uart_config);
// Set UART pins using UART0 default pins i.e. no changes
uart_set_pin(uart_num, scope_tx_io_num, scope_rx_io_num,
UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
uart_driver_install(uart_num, 1024, 2048, 0, NULL, 0);
uart_used = uart_num;
#endif

4
components/driver/touch_sensor/esp32/touch_sensor.c
View File

@ -108,9 +108,9 @@ static void touch_pad_filter_cb(void *arg)
_touch_pad_read(i, &val, mode);
s_touch_pad_filter->raw_val[i] = val;
s_touch_pad_filter->filter_last_val[i] = s_touch_pad_filter->filter_last_val[i] == 0 ?
((uint32_t)val << TOUCH_PAD_SHIFT_DEFAULT) : s_touch_pad_filter->filter_last_val[i];
((uint32_t)val << TOUCH_PAD_SHIFT_DEFAULT) : s_touch_pad_filter->filter_last_val[i];
s_touch_pad_filter->filter_last_val[i] = _touch_filter_iir((val << TOUCH_PAD_SHIFT_DEFAULT),
s_touch_pad_filter->filter_last_val[i], TOUCH_PAD_FILTER_FACTOR_DEFAULT);
s_touch_pad_filter->filter_last_val[i], TOUCH_PAD_FILTER_FACTOR_DEFAULT);
s_touch_pad_filter->filtered_val[i] =
(s_touch_pad_filter->filter_last_val[i] + TOUCH_PAD_SHIFT_ROUND_DEFAULT) >> TOUCH_PAD_SHIFT_DEFAULT;
}

2
components/driver/touch_sensor/esp32s2/touch_sensor.c
View File

@ -107,7 +107,7 @@ esp_err_t touch_pad_isr_register(intr_handler_t fn, void *arg, touch_pad_intr_ma
#endif
esp_err_t ret = rtc_isr_register(fn, arg, en_msk, 0);
/* Must ensure: After being registered, it is executed first. */
if ( (ret == ESP_OK) && (reg_flag == false) && (intr_mask & (TOUCH_PAD_INTR_MASK_SCAN_DONE | TOUCH_PAD_INTR_MASK_TIMEOUT)) ) {
if ((ret == ESP_OK) && (reg_flag == false) && (intr_mask & (TOUCH_PAD_INTR_MASK_SCAN_DONE | TOUCH_PAD_INTR_MASK_TIMEOUT))) {
rtc_isr_register(touch_pad_workaround_isr_internal, NULL, RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M | RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M, 0);
reg_flag = true;
}

1
components/driver/touch_sensor/include/driver/touch_sensor_common.h
View File

@ -130,7 +130,6 @@ esp_err_t touch_pad_set_fsm_mode(touch_fsm_mode_t mode);
*/
esp_err_t touch_pad_get_fsm_mode(touch_fsm_mode_t *mode);
/**
* @brief To clear the touch sensor channel active status.
*

8
components/driver/touch_sensor/touch_sensor_common.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -55,11 +55,11 @@ esp_err_t touch_pad_isr_deregister(intr_handler_t fn, void *arg)
esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, touch_volt_atten_t atten)
{
TOUCH_CHECK(((refh < TOUCH_HVOLT_MAX) && (refh >= (int )TOUCH_HVOLT_KEEP)), "touch refh error",
TOUCH_CHECK(((refh < TOUCH_HVOLT_MAX) && (refh >= (int)TOUCH_HVOLT_KEEP)), "touch refh error",
ESP_ERR_INVALID_ARG);
TOUCH_CHECK(((refl < TOUCH_LVOLT_MAX) && (refh >= (int )TOUCH_LVOLT_KEEP)), "touch refl error",
TOUCH_CHECK(((refl < TOUCH_LVOLT_MAX) && (refh >= (int)TOUCH_LVOLT_KEEP)), "touch refl error",
ESP_ERR_INVALID_ARG);
TOUCH_CHECK(((atten < TOUCH_HVOLT_ATTEN_MAX) && (refh >= (int )TOUCH_HVOLT_ATTEN_KEEP)), "touch atten error",
TOUCH_CHECK(((atten < TOUCH_HVOLT_ATTEN_MAX) && (refh >= (int)TOUCH_HVOLT_ATTEN_KEEP)), "touch atten error",
ESP_ERR_INVALID_ARG);
const touch_hal_volt_t volt = {

1
tools/ci/astyle-rules.yml
View File

@ -51,7 +51,6 @@ components_not_formatted_temporary:
- "/components/cmock/"
- "/components/console/"
- "/components/cxx/"
- "/components/driver/"
- "/components/efuse/"
- "/components/esp_coex/"
- "/components/esp_eth/"