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https://github.com/espressif/esp-idf.git
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Merge branch 'fix/xts_aes_register_prefix_discrepancy_c6_h2' into 'master'
fix: xts aes register prefix discrepancy for ESP32H2 and ESP32C6 Closes DOC-5171 and DOC-5179 See merge request espressif/esp-idf!23944
This commit is contained in:
Mahavir Jain
commit
c606127315
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -15,7 +15,7 @@
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#include <stdbool.h>
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#include <string.h>
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#include "soc/hp_system_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/xts_aes_reg.h"
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#include "soc/soc.h"
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#include "hal/assert.h"
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@ -60,7 +60,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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{
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// Our hardware only support flash encryption
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HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
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REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type);
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REG_SET_FIELD(XTS_AES_DESTINATION_REG(0), XTS_AES_DESTINATION, type);
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}
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/**
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@ -71,7 +71,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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{
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// Desired block should not be larger than the block size.
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REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5);
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REG_SET_FIELD(XTS_AES_LINESIZE_REG(0), XTS_AES_LINESIZE, size >> 5);
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}
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/**
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@ -85,7 +85,7 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
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{
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uint32_t plaintext_offs = (address % 64);
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memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
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memcpy((void *)(XTS_AES_PLAIN_MEM(0) + plaintext_offs), buffer, size);
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}
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/**
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@ -95,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
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*/
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static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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{
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REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr);
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REG_SET_FIELD(XTS_AES_PHYSICAL_ADDRESS_REG(0), XTS_AES_PHYSICAL_ADDRESS, flash_addr);
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}
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/**
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@ -103,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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*/
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static inline void spi_flash_encrypt_ll_calculate_start(void)
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{
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REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1);
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REG_SET_FIELD(XTS_AES_TRIGGER_REG(0), XTS_AES_TRIGGER, 1);
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}
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/**
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@ -111,7 +111,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
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*/
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static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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{
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while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) {
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while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
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}
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}
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@ -120,8 +120,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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*/
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static inline void spi_flash_encrypt_ll_done(void)
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{
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REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE);
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while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) {
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REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE);
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while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
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}
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}
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@ -130,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
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*/
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static inline void spi_flash_encrypt_ll_destroy(void)
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{
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REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY);
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REG_SET_BIT(XTS_AES_DESTROY_REG(0), XTS_AES_DESTROY);
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}
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/**
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@ -15,7 +15,7 @@
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#include <stdbool.h>
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#include <string.h>
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#include "soc/hp_system_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/xts_aes_reg.h"
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#include "soc/soc.h"
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#include "hal/assert.h"
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@ -60,7 +60,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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{
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// Our hardware only support flash encryption
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HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
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REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type);
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REG_SET_FIELD(XTS_AES_DESTINATION_REG(0), XTS_AES_DESTINATION, type);
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}
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/**
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@ -71,7 +71,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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{
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// Desired block should not be larger than the block size.
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REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5);
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REG_SET_FIELD(XTS_AES_LINESIZE_REG(0), XTS_AES_LINESIZE, size >> 5);
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}
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/**
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@ -85,7 +85,7 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
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{
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uint32_t plaintext_offs = (address % 64);
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memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
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memcpy((void *)(XTS_AES_PLAIN_MEM(0) + plaintext_offs), buffer, size);
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}
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/**
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@ -95,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
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*/
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static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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{
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REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr);
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REG_SET_FIELD(XTS_AES_PHYSICAL_ADDRESS_REG(0), XTS_AES_PHYSICAL_ADDRESS, flash_addr);
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}
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/**
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@ -103,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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*/
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static inline void spi_flash_encrypt_ll_calculate_start(void)
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{
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REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1);
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REG_SET_FIELD(XTS_AES_TRIGGER_REG(0), XTS_AES_TRIGGER, 1);
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}
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/**
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@ -111,7 +111,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
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*/
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static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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{
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while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) {
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while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
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}
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}
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@ -120,8 +120,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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*/
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static inline void spi_flash_encrypt_ll_done(void)
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{
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REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE);
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while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) {
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REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE);
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while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
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}
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}
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@ -130,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
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*/
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static inline void spi_flash_encrypt_ll_destroy(void)
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{
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REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY);
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REG_SET_BIT(XTS_AES_DESTROY_REG(0), XTS_AES_DESTROY);
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}
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/**
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,6 +7,7 @@
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -2998,94 +2999,6 @@ isable..*/
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#define SPI_MEM_CLK_EN_V 0x1
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#define SPI_MEM_CLK_EN_S 0
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#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300)
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/* SPI_MEM_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: This field is only used to generate include file in c case. This field is useles
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s. Please do not use this field..*/
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#define SPI_MEM_XTS_PLAIN 0xFFFFFFFF
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#define SPI_MEM_XTS_PLAIN_M ((SPI_MEM_XTS_PLAIN_V)<<(SPI_MEM_XTS_PLAIN_S))
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#define SPI_MEM_XTS_PLAIN_V 0xFFFFFFFF
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#define SPI_MEM_XTS_PLAIN_S 0
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#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
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/* SPI_MEM_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
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/*description: This bits stores the line-size parameter which will be used in manual encryption
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calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
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1: 32-bytes, 2: 64-bytes, 3:reserved..*/
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#define SPI_MEM_XTS_LINESIZE 0x00000003
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#define SPI_MEM_XTS_LINESIZE_M ((SPI_MEM_XTS_LINESIZE_V)<<(SPI_MEM_XTS_LINESIZE_S))
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#define SPI_MEM_XTS_LINESIZE_V 0x3
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#define SPI_MEM_XTS_LINESIZE_S 0
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#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
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/* SPI_MEM_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: This bit stores the destination parameter which will be used in manual encryptio
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n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
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used..*/
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#define SPI_MEM_XTS_DESTINATION (BIT(0))
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#define SPI_MEM_XTS_DESTINATION_M (BIT(0))
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#define SPI_MEM_XTS_DESTINATION_V 0x1
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#define SPI_MEM_XTS_DESTINATION_S 0
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#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
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/* SPI_MEM_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
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/*description: This bits stores the physical-address parameter which will be used in manual enc
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ryption calculation. This value should aligned with byte number decided by line-
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size parameter..*/
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#define SPI_MEM_XTS_PHYSICAL_ADDRESS 0x03FFFFFF
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#define SPI_MEM_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_XTS_PHYSICAL_ADDRESS_S))
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#define SPI_MEM_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF
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#define SPI_MEM_XTS_PHYSICAL_ADDRESS_S 0
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#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
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/* SPI_MEM_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
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/*description: Set this bit to trigger the process of manual encryption calculation. This actio
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n should only be asserted when manual encryption status is 0. After this action,
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manual encryption status becomes 1. After calculation is done, manual encryptio
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n status becomes 2..*/
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#define SPI_MEM_XTS_TRIGGER (BIT(0))
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#define SPI_MEM_XTS_TRIGGER_M (BIT(0))
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#define SPI_MEM_XTS_TRIGGER_V 0x1
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#define SPI_MEM_XTS_TRIGGER_S 0
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#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
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/* SPI_MEM_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
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/*description: Set this bit to release encrypted result to mspi. This action should only be ass
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erted when manual encryption status is 2. After this action, manual encryption s
|
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tatus will become 3..*/
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#define SPI_MEM_XTS_RELEASE (BIT(0))
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#define SPI_MEM_XTS_RELEASE_M (BIT(0))
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#define SPI_MEM_XTS_RELEASE_V 0x1
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#define SPI_MEM_XTS_RELEASE_S 0
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#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
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/* SPI_MEM_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
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/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
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en manual encryption status is 3. After this action, manual encryption status wi
|
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ll become 0..*/
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#define SPI_MEM_XTS_DESTROY (BIT(0))
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#define SPI_MEM_XTS_DESTROY_M (BIT(0))
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#define SPI_MEM_XTS_DESTROY_V 0x1
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#define SPI_MEM_XTS_DESTROY_S 0
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#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
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/* SPI_MEM_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
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/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
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calculation, 2: encryption calculation is done but the encrypted result is invi
|
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sible to mspi, 3: the encrypted result is visible to mspi..*/
|
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#define SPI_MEM_XTS_STATE 0x00000003
|
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#define SPI_MEM_XTS_STATE_M ((SPI_MEM_XTS_STATE_V)<<(SPI_MEM_XTS_STATE_S))
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#define SPI_MEM_XTS_STATE_V 0x3
|
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#define SPI_MEM_XTS_STATE_S 0
|
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|
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#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
|
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/* SPI_MEM_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
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/*description: This bits stores the last modified-time of manual encryption feature..*/
|
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#define SPI_MEM_XTS_DATE 0x3FFFFFFF
|
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#define SPI_MEM_XTS_DATE_M ((SPI_MEM_XTS_DATE_V)<<(SPI_MEM_XTS_DATE_S))
|
||||
#define SPI_MEM_XTS_DATE_V 0x3FFFFFFF
|
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#define SPI_MEM_XTS_DATE_S 0
|
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|
||||
#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C)
|
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/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
|
||||
/*description: MSPI-MMU item content.*/
|
||||
@ -3147,31 +3060,6 @@ sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define SPI_MEM_MMU_MEM_FORCE_ON_V 0x1
|
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#define SPI_MEM_MMU_MEM_FORCE_ON_S 0
|
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|
||||
#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
|
||||
/* SPI_MEM_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
||||
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_S 4
|
||||
/* SPI_MEM_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
||||
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
||||
ing key 1..*/
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN (BIT(3))
|
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#define SPI_MEM_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN_V 0x1
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN_S 3
|
||||
/* SPI_MEM_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
|
||||
7: The bigger the number is, the more secure the cryption is. (Note that the per
|
||||
formance of cryption will decrease together with this number increasing).*/
|
||||
#define SPI_MEM_CRYPT_SECURITY_LEVEL 0x00000007
|
||||
#define SPI_MEM_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_CRYPT_SECURITY_LEVEL_S))
|
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#define SPI_MEM_CRYPT_SECURITY_LEVEL_V 0x7
|
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#define SPI_MEM_CRYPT_SECURITY_LEVEL_S 0
|
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|
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#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0)
|
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/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
|
||||
/*description: ECO high register.*/
|
||||
|
||||
128
components/soc/esp32c6/include/soc/xts_aes_reg.h
Normal file
128
components/soc/esp32c6/include/soc/xts_aes_reg.h
Normal file
@ -0,0 +1,128 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
|
||||
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: This field is only used to generate include file in c case. This field is useles
|
||||
s. Please do not use this field..*/
|
||||
#define XTS_AES_PLAIN 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
|
||||
#define XTS_AES_PLAIN_V 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_S 0
|
||||
|
||||
#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
|
||||
/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the line-size parameter which will be used in manual encryption
|
||||
calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
|
||||
1: 32-bytes, 2: 64-bytes, 3:reserved..*/
|
||||
#define XTS_AES_LINESIZE 0x00000003
|
||||
#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
|
||||
#define XTS_AES_LINESIZE_V 0x3
|
||||
#define XTS_AES_LINESIZE_S 0
|
||||
|
||||
#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
|
||||
/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: This bit stores the destination parameter which will be used in manual encryptio
|
||||
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
|
||||
used..*/
|
||||
#define XTS_AES_DESTINATION (BIT(0))
|
||||
#define XTS_AES_DESTINATION_M (BIT(0))
|
||||
#define XTS_AES_DESTINATION_V 0x1
|
||||
#define XTS_AES_DESTINATION_S 0
|
||||
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
|
||||
/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: This bits stores the physical-address parameter which will be used in manual enc
|
||||
ryption calculation. This value should aligned with byte number decided by line-
|
||||
size parameter..*/
|
||||
#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_S 0
|
||||
|
||||
#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
|
||||
/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
|
||||
n should only be asserted when manual encryption status is 0. After this action,
|
||||
manual encryption status becomes 1. After calculation is done, manual encryptio
|
||||
n status becomes 2..*/
|
||||
#define XTS_AES_TRIGGER (BIT(0))
|
||||
#define XTS_AES_TRIGGER_M (BIT(0))
|
||||
#define XTS_AES_TRIGGER_V 0x1
|
||||
#define XTS_AES_TRIGGER_S 0
|
||||
|
||||
#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
|
||||
/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to release encrypted result to mspi. This action should only be ass
|
||||
erted when manual encryption status is 2. After this action, manual encryption s
|
||||
tatus will become 3..*/
|
||||
#define XTS_AES_RELEASE (BIT(0))
|
||||
#define XTS_AES_RELEASE_M (BIT(0))
|
||||
#define XTS_AES_RELEASE_V 0x1
|
||||
#define XTS_AES_RELEASE_S 0
|
||||
|
||||
#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
|
||||
/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
||||
en manual encryption status is 3. After this action, manual encryption status wi
|
||||
ll become 0..*/
|
||||
#define XTS_AES_DESTROY (BIT(0))
|
||||
#define XTS_AES_DESTROY_M (BIT(0))
|
||||
#define XTS_AES_DESTROY_V 0x1
|
||||
#define XTS_AES_DESTROY_S 0
|
||||
|
||||
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
|
||||
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
||||
calculation, 2: encryption calculation is done but the encrypted result is invi
|
||||
sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define XTS_AES_STATE 0x00000003
|
||||
#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
|
||||
#define XTS_AES_STATE_V 0x3
|
||||
#define XTS_AES_STATE_S 0
|
||||
|
||||
#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
|
||||
/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
||||
/*description: This bits stores the last modified-time of manual encryption feature..*/
|
||||
#define XTS_AES_DATE 0x3FFFFFFF
|
||||
#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
|
||||
#define XTS_AES_DATE_V 0x3FFFFFFF
|
||||
|
||||
#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
|
||||
/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
||||
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
|
||||
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
||||
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
||||
ing key 1..*/
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3
|
||||
/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
|
||||
7: The bigger the number is, the more secure the cryption is. (Note that the per
|
||||
formance of cryption will decrease together with this number increasing).*/
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,15 +1,15 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
|
||||
/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
|
||||
@ -2994,94 +2994,6 @@ isable..*/
|
||||
#define SPI_MEM_CLK_EN_V 0x1
|
||||
#define SPI_MEM_CLK_EN_S 0
|
||||
|
||||
#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300)
|
||||
/* SPI_MEM_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: This field is only used to generate include file in c case. This field is useles
|
||||
s. Please do not use this field..*/
|
||||
#define SPI_MEM_XTS_PLAIN 0xFFFFFFFF
|
||||
#define SPI_MEM_XTS_PLAIN_M ((SPI_MEM_XTS_PLAIN_V)<<(SPI_MEM_XTS_PLAIN_S))
|
||||
#define SPI_MEM_XTS_PLAIN_V 0xFFFFFFFF
|
||||
#define SPI_MEM_XTS_PLAIN_S 0
|
||||
|
||||
#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
|
||||
/* SPI_MEM_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the line-size parameter which will be used in manual encryption
|
||||
calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
|
||||
1: 32-bytes, 2: 64-bytes, 3:reserved..*/
|
||||
#define SPI_MEM_XTS_LINESIZE 0x00000003
|
||||
#define SPI_MEM_XTS_LINESIZE_M ((SPI_MEM_XTS_LINESIZE_V)<<(SPI_MEM_XTS_LINESIZE_S))
|
||||
#define SPI_MEM_XTS_LINESIZE_V 0x3
|
||||
#define SPI_MEM_XTS_LINESIZE_S 0
|
||||
|
||||
#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
|
||||
/* SPI_MEM_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: This bit stores the destination parameter which will be used in manual encryptio
|
||||
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
|
||||
used..*/
|
||||
#define SPI_MEM_XTS_DESTINATION (BIT(0))
|
||||
#define SPI_MEM_XTS_DESTINATION_M (BIT(0))
|
||||
#define SPI_MEM_XTS_DESTINATION_V 0x1
|
||||
#define SPI_MEM_XTS_DESTINATION_S 0
|
||||
|
||||
#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
|
||||
/* SPI_MEM_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: This bits stores the physical-address parameter which will be used in manual enc
|
||||
ryption calculation. This value should aligned with byte number decided by line-
|
||||
size parameter..*/
|
||||
#define SPI_MEM_XTS_PHYSICAL_ADDRESS 0x03FFFFFF
|
||||
#define SPI_MEM_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_XTS_PHYSICAL_ADDRESS_S))
|
||||
#define SPI_MEM_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF
|
||||
#define SPI_MEM_XTS_PHYSICAL_ADDRESS_S 0
|
||||
|
||||
#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
|
||||
/* SPI_MEM_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
|
||||
n should only be asserted when manual encryption status is 0. After this action,
|
||||
manual encryption status becomes 1. After calculation is done, manual encryptio
|
||||
n status becomes 2..*/
|
||||
#define SPI_MEM_XTS_TRIGGER (BIT(0))
|
||||
#define SPI_MEM_XTS_TRIGGER_M (BIT(0))
|
||||
#define SPI_MEM_XTS_TRIGGER_V 0x1
|
||||
#define SPI_MEM_XTS_TRIGGER_S 0
|
||||
|
||||
#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
|
||||
/* SPI_MEM_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to release encrypted result to mspi. This action should only be ass
|
||||
erted when manual encryption status is 2. After this action, manual encryption s
|
||||
tatus will become 3..*/
|
||||
#define SPI_MEM_XTS_RELEASE (BIT(0))
|
||||
#define SPI_MEM_XTS_RELEASE_M (BIT(0))
|
||||
#define SPI_MEM_XTS_RELEASE_V 0x1
|
||||
#define SPI_MEM_XTS_RELEASE_S 0
|
||||
|
||||
#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
|
||||
/* SPI_MEM_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
||||
en manual encryption status is 3. After this action, manual encryption status wi
|
||||
ll become 0..*/
|
||||
#define SPI_MEM_XTS_DESTROY (BIT(0))
|
||||
#define SPI_MEM_XTS_DESTROY_M (BIT(0))
|
||||
#define SPI_MEM_XTS_DESTROY_V 0x1
|
||||
#define SPI_MEM_XTS_DESTROY_S 0
|
||||
|
||||
#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
|
||||
/* SPI_MEM_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
||||
calculation, 2: encryption calculation is done but the encrypted result is invi
|
||||
sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define SPI_MEM_XTS_STATE 0x00000003
|
||||
#define SPI_MEM_XTS_STATE_M ((SPI_MEM_XTS_STATE_V)<<(SPI_MEM_XTS_STATE_S))
|
||||
#define SPI_MEM_XTS_STATE_V 0x3
|
||||
#define SPI_MEM_XTS_STATE_S 0
|
||||
|
||||
#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
|
||||
/* SPI_MEM_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
||||
/*description: This bits stores the last modified-time of manual encryption feature..*/
|
||||
#define SPI_MEM_XTS_DATE 0x3FFFFFFF
|
||||
#define SPI_MEM_XTS_DATE_M ((SPI_MEM_XTS_DATE_V)<<(SPI_MEM_XTS_DATE_S))
|
||||
#define SPI_MEM_XTS_DATE_V 0x3FFFFFFF
|
||||
#define SPI_MEM_XTS_DATE_S 0
|
||||
|
||||
#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C)
|
||||
/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
|
||||
/*description: MSPI-MMU item content.*/
|
||||
@ -3143,31 +3055,6 @@ sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define SPI_MEM_MMU_MEM_FORCE_ON_V 0x1
|
||||
#define SPI_MEM_MMU_MEM_FORCE_ON_S 0
|
||||
|
||||
#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
|
||||
/* SPI_MEM_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
||||
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
||||
#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_S 4
|
||||
/* SPI_MEM_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
||||
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
||||
ing key 1..*/
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN (BIT(3))
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN_V 0x1
|
||||
#define SPI_MEM_CRYPT_CALC_D_DPA_EN_S 3
|
||||
/* SPI_MEM_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
|
||||
7: The bigger the number is, the more secure the cryption is. (Note that the per
|
||||
formance of cryption will decrease together with this number increasing).*/
|
||||
#define SPI_MEM_CRYPT_SECURITY_LEVEL 0x00000007
|
||||
#define SPI_MEM_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_CRYPT_SECURITY_LEVEL_S))
|
||||
#define SPI_MEM_CRYPT_SECURITY_LEVEL_V 0x7
|
||||
#define SPI_MEM_CRYPT_SECURITY_LEVEL_S 0
|
||||
|
||||
#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0)
|
||||
/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
|
||||
/*description: ECO high register.*/
|
||||
|
||||
129
components/soc/esp32h2/include/soc/xts_aes_reg.h
Normal file
129
components/soc/esp32h2/include/soc/xts_aes_reg.h
Normal file
@ -0,0 +1,129 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
|
||||
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: This field is only used to generate include file in c case. This field is useles
|
||||
s. Please do not use this field..*/
|
||||
#define XTS_AES_PLAIN 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
|
||||
#define XTS_AES_PLAIN_V 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_S 0
|
||||
|
||||
#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
|
||||
/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the line-size parameter which will be used in manual encryption
|
||||
calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
|
||||
1: 32-bytes, 2: 64-bytes, 3:reserved..*/
|
||||
#define XTS_AES_LINESIZE 0x00000003
|
||||
#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
|
||||
#define XTS_AES_LINESIZE_V 0x3
|
||||
#define XTS_AES_LINESIZE_S 0
|
||||
|
||||
#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
|
||||
/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: This bit stores the destination parameter which will be used in manual encryptio
|
||||
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
|
||||
used..*/
|
||||
#define XTS_AES_DESTINATION (BIT(0))
|
||||
#define XTS_AES_DESTINATION_M (BIT(0))
|
||||
#define XTS_AES_DESTINATION_V 0x1
|
||||
#define XTS_AES_DESTINATION_S 0
|
||||
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
|
||||
/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: This bits stores the physical-address parameter which will be used in manual enc
|
||||
ryption calculation. This value should aligned with byte number decided by line-
|
||||
size parameter..*/
|
||||
#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_S 0
|
||||
|
||||
#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
|
||||
/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
|
||||
n should only be asserted when manual encryption status is 0. After this action,
|
||||
manual encryption status becomes 1. After calculation is done, manual encryptio
|
||||
n status becomes 2..*/
|
||||
#define XTS_AES_TRIGGER (BIT(0))
|
||||
#define XTS_AES_TRIGGER_M (BIT(0))
|
||||
#define XTS_AES_TRIGGER_V 0x1
|
||||
#define XTS_AES_TRIGGER_S 0
|
||||
|
||||
#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
|
||||
/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to release encrypted result to mspi. This action should only be ass
|
||||
erted when manual encryption status is 2. After this action, manual encryption s
|
||||
tatus will become 3..*/
|
||||
#define XTS_AES_RELEASE (BIT(0))
|
||||
#define XTS_AES_RELEASE_M (BIT(0))
|
||||
#define XTS_AES_RELEASE_V 0x1
|
||||
#define XTS_AES_RELEASE_S 0
|
||||
|
||||
#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
|
||||
/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
||||
en manual encryption status is 3. After this action, manual encryption status wi
|
||||
ll become 0..*/
|
||||
#define XTS_AES_DESTROY (BIT(0))
|
||||
#define XTS_AES_DESTROY_M (BIT(0))
|
||||
#define XTS_AES_DESTROY_V 0x1
|
||||
#define XTS_AES_DESTROY_S 0
|
||||
|
||||
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
|
||||
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
||||
calculation, 2: encryption calculation is done but the encrypted result is invi
|
||||
sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define XTS_AES_STATE 0x00000003
|
||||
#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
|
||||
#define XTS_AES_STATE_V 0x3
|
||||
#define XTS_AES_STATE_S 0
|
||||
|
||||
#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
|
||||
/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
||||
/*description: This bits stores the last modified-time of manual encryption feature..*/
|
||||
#define XTS_AES_DATE 0x3FFFFFFF
|
||||
#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
|
||||
#define XTS_AES_DATE_V 0x3FFFFFFF
|
||||
#define XTS_AES_DATE_S 0
|
||||
|
||||
#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
|
||||
/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
||||
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
|
||||
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
||||
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
||||
ing key 1..*/
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3
|
||||
/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
|
||||
7: The bigger the number is, the more secure the cryption is. (Note that the per
|
||||
formance of cryption will decrease together with this number increasing).*/
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user