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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ethernet: set DMA owner after all descriptors have configured
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parent
d918e7ad8a
commit
c54d599d0d
@ -451,44 +451,55 @@ uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
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if (lastlen) {
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bufcount++;
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}
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if (bufcount > CONFIG_ETH_DMA_TX_BUFFER_NUM) {
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goto err;
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}
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eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc;
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/* A frame is transmitted in multiple descriptor */
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for (uint32_t i = 0; i < bufcount; i++) {
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for (int i = 0; i < bufcount; i++) {
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/* Check if the descriptor is owned by the Ethernet DMA (when 1) or CPU (when 0) */
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if (hal->tx_desc->TDES0.Own != EMAC_DMADESC_OWNER_CPU) {
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if (desc_iter->TDES0.Own != EMAC_DMADESC_OWNER_CPU) {
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goto err;
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}
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/* Clear FIRST and LAST segment bits */
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hal->tx_desc->TDES0.FirstSegment = 0;
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hal->tx_desc->TDES0.LastSegment = 0;
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desc_iter->TDES0.FirstSegment = 0;
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desc_iter->TDES0.LastSegment = 0;
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desc_iter->TDES0.InterruptOnComplete = 0;
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if (i == 0) {
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/* Setting the first segment bit */
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hal->tx_desc->TDES0.FirstSegment = 1;
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desc_iter->TDES0.FirstSegment = 1;
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}
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if (i == (bufcount - 1)) {
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/* Setting the last segment bit */
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hal->tx_desc->TDES0.LastSegment = 1;
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desc_iter->TDES0.LastSegment = 1;
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/* Enable transmit interrupt */
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hal->tx_desc->TDES0.InterruptOnComplete = 1;
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desc_iter->TDES0.InterruptOnComplete = 1;
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/* Program size */
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hal->tx_desc->TDES1.TransmitBuffer1Size = lastlen;
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desc_iter->TDES1.TransmitBuffer1Size = lastlen;
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/* copy data from uplayer stack buffer */
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memcpy((void *)(hal->tx_desc->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, lastlen);
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memcpy((void *)(desc_iter->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, lastlen);
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sentout += lastlen;
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} else {
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/* Program size */
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hal->tx_desc->TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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desc_iter->TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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/* copy data from uplayer stack buffer */
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memcpy((void *)(hal->tx_desc->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, CONFIG_ETH_DMA_BUFFER_SIZE);
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memcpy((void *)(desc_iter->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, CONFIG_ETH_DMA_BUFFER_SIZE);
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sentout += CONFIG_ETH_DMA_BUFFER_SIZE;
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}
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/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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hal->tx_desc->TDES0.Own = EMAC_DMADESC_OWNER_DMA;
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/* Point to next descriptor */
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desc_iter = (eth_dma_tx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
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}
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/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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for (int i = 0; i < bufcount; i++) {
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hal->tx_desc->TDES0.Own = EMAC_DMADESC_OWNER_DMA;
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hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);
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}
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err:
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hal->dma_regs->dmatxpolldemand = 0;
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return sentout;
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err:
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return 0;
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}
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uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain)
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