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feat(spiram): refactor for spiram device driver for s3/c5
This commit is contained in:
C.S.M
parent
d1571c144b
commit
c431e9b830
@ -36,7 +36,12 @@ if(CONFIG_SPIRAM)
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endif()
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if(CONFIG_SPIRAM_MODE_QUAD)
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if(${target} STREQUAL "esp32" OR ${target} STREQUAL "esp32s2")
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list(APPEND srcs "${target}/esp_psram_impl_quad.c")
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else()
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list(APPEND srcs "device/esp_psram_impl_ap_quad.c")
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endif()
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elseif(CONFIG_SPIRAM_MODE_OCT)
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list(APPEND srcs "${target}/esp_psram_impl_octal.c")
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endif()
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320
components/esp_psram/device/esp_psram_impl_ap_quad.c
Normal file
320
components/esp_psram/device/esp_psram_impl_ap_quad.c
Normal file
@ -0,0 +1,320 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "../esp_psram_impl.h"
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#include "rom/spi_flash.h"
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#include "rom/opi_flash.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "hal/gpio_hal.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/esp_gpio_reserve.h"
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#include "hal/psram_ctrlr_ll.h"
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#include "esp_quad_psram_defs.h"
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#include "soc/soc_caps.h"
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static const char* TAG = "quad_psram";
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static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
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static void config_psram_spi_phases(void);
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static uint8_t s_psram_cs_io = (uint8_t) -1;
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uint8_t esp_psram_impl_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation)
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{
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esp_rom_spiflash_read_mode_t rd_mode = (mode == PSRAM_HAL_CMD_QPI) ? ESP_ROM_SPIFLASH_QIO_MODE : ESP_ROM_SPIFLASH_SLOWRD_MODE;
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esp_rom_spi_set_op_mode(spi_num, rd_mode);
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if (mode == PSRAM_HAL_CMD_QPI) {
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psram_ctrlr_ll_enable_quad_command(PSRAM_CTRLR_LL_MSPI_ID_1, true);
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}
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psram_ctrlr_ll_common_transaction_base(spi_num, rd_mode,
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cmd, cmd_bit_len,
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addr, addr_bit_len,
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dummy_bits,
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mosi_data, mosi_bit_len,
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miso_data, miso_bit_len,
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cs_mask,
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is_write_erase_operation);
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}
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//exit QPI mode(set back to SPI mode)
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static void psram_disable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_QPI,
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PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//TODO IDF-4307
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//switch psram burst length(32 bytes or 1024 bytes)
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//datasheet says it should be 1024 bytes by default
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static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode)
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{
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psram_exec_cmd(spi_num, mode,
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PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//send reset command to psram, in spi mode
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static void psram_reset_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_RESET_EN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_RESET, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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esp_err_t psram_enable_wrap(uint32_t wrap_size)
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{
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//TODO: IDF-4307
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static uint32_t current_wrap_size = 0;
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if (current_wrap_size == wrap_size) {
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return ESP_OK;
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}
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switch (wrap_size) {
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case 32:
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case 0:
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psram_set_wrap_burst_length(1, PSRAM_HAL_CMD_QPI);
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current_wrap_size = wrap_size;
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return ESP_OK;
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case 16:
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case 64:
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default:
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return ESP_FAIL;
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}
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}
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bool psram_support_wrap_size(uint32_t wrap_size)
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{
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switch (wrap_size) {
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case 0:
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case 32:
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return true;
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case 16:
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case 64:
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default:
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return false;
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}
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}
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//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
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static void psram_read_id(int spi_num, uint32_t* dev_id)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_DEVICE_ID, 8, /* command and command bit len*/
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0, 24, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//enter QPI mode
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static void psram_enable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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static void psram_set_cs_timing(void)
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{
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psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_HOLD_VAL);
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psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_SETUP_VAL);
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}
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static void psram_gpio_config(void)
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{
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//CS1
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uint8_t cs1_io = PSRAM_CS_IO;
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if (cs1_io == SPI_CS1_GPIO_NUM) {
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gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1);
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} else {
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esp_rom_gpio_connect_out_signal(cs1_io, FSPICS1_OUT_IDX, 0, 0);
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gpio_ll_func_sel(&GPIO, cs1_io, PIN_FUNC_GPIO);
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}
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s_psram_cs_io = cs1_io;
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//WP HD
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uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
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#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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// MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader.
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} else {
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// MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader.
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wp_io = esp_rom_efuse_get_flash_wp_gpio();
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}
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esp_rom_spiflash_select_qio_pins(wp_io, spiconfig);
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#else
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//This ROM function will init both WP and HD pins.
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esp_rom_spiflash_select_qio_pins(wp_io, 0);
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#endif
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// Reserve psram pins
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esp_gpio_reserve(BIT64(cs1_io) | BIT64(wp_io));
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}
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#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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static void s_config_psram_clock(void)
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{
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// This function can be extended if we have other psram frequency
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uint32_t clock_conf = 0;
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#if (CONFIG_SPIRAM_SPEED == 80)
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clock_conf = psram_ctrlr_ll_calculate_clock_reg(1);
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#elif (CONFIG_SPIRAM_SPEED == 40)
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clock_conf = psram_ctrlr_ll_calculate_clock_reg(2);
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#endif
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psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_0, clock_conf);
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}
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#endif
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esp_err_t esp_psram_impl_enable(void)
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{
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psram_gpio_config();
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psram_set_cs_timing();
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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//enter MSPI slow mode to init PSRAM device registers
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mspi_timing_enter_low_speed_mode(true);
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#endif // SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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uint32_t psram_id = 0;
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//We use SPI1 to init PSRAM
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psram_disable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
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psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, &psram_id);
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if (!PSRAM_IS_VALID(psram_id)) {
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/* 16Mbit psram ID read error workaround:
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* treat the first read id as a dummy one as the pre-condition,
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* Send Read ID command again
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*/
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psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, &psram_id);
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if (!PSRAM_IS_VALID(psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)psram_id);
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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if (PSRAM_IS_64MBIT_TRIAL(psram_id)) {
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s_psram_size = PSRAM_SIZE_8MB;
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} else if (PSRAM_IS_2T_APS3204(psram_id)) {
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s_psram_size = PSRAM_SIZE_4MB;
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} else {
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uint8_t density = PSRAM_SIZE_ID(psram_id);
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s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
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density == 0x1 ? PSRAM_SIZE_4MB :
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density == 0x2 ? PSRAM_SIZE_8MB : 0;
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}
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//SPI1: send psram reset command
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psram_reset_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
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//SPI1: send QPI enable command
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psram_enable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
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mspi_timing_psram_tuning();
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//Configure SPI0 PSRAM related SPI Phases
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config_psram_spi_phases();
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//Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
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mspi_timing_enter_high_speed_mode(true);
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#else
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s_config_psram_clock();
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//Configure SPI0 PSRAM related SPI Phases
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config_psram_spi_phases();
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#endif
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return ESP_OK;
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}
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//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
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static void config_psram_spi_phases(void)
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{
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psram_ctrlr_ll_set_read_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_HAL_CMD_QPI);
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psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_QUAD_WRITE);
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psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_FAST_READ_QUAD);
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psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_ADDR_LENGTH);
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psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_FAST_READ_QUAD_DUMMY);
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psram_ctrlr_ll_set_cs_pin(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_CS_ID_1);
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}
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/*---------------------------------------------------------------------------------
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* Following APIs are not required to be IRAM-Safe
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*
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* Consider moving these to another file if this kind of APIs grows dramatically
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*-------------------------------------------------------------------------------*/
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esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
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{
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if (!out_size_bytes) {
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return ESP_ERR_INVALID_ARG;
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}
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*out_size_bytes = s_psram_size;
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return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
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}
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/**
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* This function is to get the available physical psram size in bytes.
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*
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* When ECC is enabled, the available size will be reduced.
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* On S3 Quad PSRAM, ECC is not enabled for now.
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*/
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esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
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{
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if (!out_size_bytes) {
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return ESP_ERR_INVALID_ARG;
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}
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*out_size_bytes = s_psram_size;
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return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
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}
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74
components/esp_psram/device/esp_quad_psram_defs.h
Normal file
74
components/esp_psram/device/esp_quad_psram_defs.h
Normal file
@ -0,0 +1,74 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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//Commands for PSRAM chip
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#pragma once
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#include "soc/io_mux_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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#define PSRAM_ENTER_QMODE 0x35
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#define PSRAM_EXIT_QMODE 0xF5
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#define PSRAM_RESET_EN 0x66
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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#define PSRAM_FAST_READ_DUMMY 4
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#define PSRAM_FAST_READ_QUAD_DUMMY 6
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// ID
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#define PSRAM_ID_KGD_M 0xff
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#define PSRAM_ID_KGD_S 8
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#define PSRAM_ID_KGD 0x5d
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#define PSRAM_ID_EID_M 0xff
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#define PSRAM_ID_EID_S 16
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// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
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//
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// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
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// -------------------------------------
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// 0 | 0 | 0 | 16
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// 0 | 0 | 1 | 32
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// 0 | 1 | 0 | 64
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#define PSRAM_EID_SIZE_M 0x07
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#define PSRAM_EID_SIZE_S 5
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#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
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#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
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#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
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#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
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#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
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#define PSRAM_IS_2T_APS3204(id) ((((id) >> 21) && 0xfffff) == 1)
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// IO-pins for PSRAM.
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// PSRAM clock and cs IO should be configured based on hardware design.
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#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
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#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
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#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
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#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
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#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
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||||
#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
|
||||
|
||||
#define PSRAM_CMD_LENGTH 8
|
||||
#define PSRAM_ADDR_LENGTH 24
|
||||
|
||||
#define PSRAM_CS_HOLD_VAL 1
|
||||
#define PSRAM_CS_SETUP_VAL 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,411 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2013-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "string.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_types.h"
|
||||
#include "esp_bit_defs.h"
|
||||
#include "esp_log.h"
|
||||
#include "../esp_psram_impl.h"
|
||||
#include "esp32c5/rom/spi_flash.h"
|
||||
#include "esp32c5/rom/opi_flash.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "hal/gpio_hal.h"
|
||||
#include "esp_private/esp_gpio_reserve.h"
|
||||
#include "soc/spi1_mem_reg.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
|
||||
static const char* TAG = "quad_psram";
|
||||
|
||||
//Commands for PSRAM chip
|
||||
#define PSRAM_READ 0x03
|
||||
#define PSRAM_FAST_READ 0x0B
|
||||
#define PSRAM_FAST_READ_QUAD 0xEB
|
||||
#define PSRAM_WRITE 0x02
|
||||
#define PSRAM_QUAD_WRITE 0x38
|
||||
#define PSRAM_ENTER_QMODE 0x35
|
||||
#define PSRAM_EXIT_QMODE 0xF5
|
||||
#define PSRAM_RESET_EN 0x66
|
||||
#define PSRAM_RESET 0x99
|
||||
#define PSRAM_SET_BURST_LEN 0xC0
|
||||
#define PSRAM_DEVICE_ID 0x9F
|
||||
|
||||
#define PSRAM_FAST_READ_DUMMY 4
|
||||
#define PSRAM_FAST_READ_QUAD_DUMMY 6
|
||||
|
||||
// ID
|
||||
#define PSRAM_ID_KGD_M 0xff
|
||||
#define PSRAM_ID_KGD_S 8
|
||||
#define PSRAM_ID_KGD 0x5d
|
||||
#define PSRAM_ID_EID_M 0xff
|
||||
#define PSRAM_ID_EID_S 16
|
||||
|
||||
// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
|
||||
//
|
||||
// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
|
||||
// -------------------------------------
|
||||
// 0 | 0 | 0 | 16
|
||||
// 0 | 0 | 1 | 32
|
||||
// 0 | 1 | 0 | 64
|
||||
#define PSRAM_EID_SIZE_M 0x07
|
||||
#define PSRAM_EID_SIZE_S 5
|
||||
|
||||
#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
|
||||
#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
|
||||
#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
|
||||
#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
|
||||
|
||||
#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
|
||||
#define PSRAM_IS_2T_APS3204(id) ((((id) >> 21) && 0xfffff) == 1)
|
||||
|
||||
// IO-pins for PSRAM.
|
||||
// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
|
||||
// hardcode the flash pins as well, making this code incompatible with either a setup
|
||||
// that has the flash on non-standard pins or ESP32s with built-in flash.
|
||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
||||
// PSRAM clock and cs IO should be configured based on hardware design.
|
||||
#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
|
||||
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
|
||||
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
|
||||
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
|
||||
#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
|
||||
|
||||
#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
|
||||
#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
|
||||
|
||||
#define SPI1_NUM 1
|
||||
#define SPI0_NUM 0
|
||||
|
||||
typedef enum {
|
||||
PSRAM_CMD_QPI,
|
||||
PSRAM_CMD_SPI,
|
||||
} psram_cmd_mode_t;
|
||||
|
||||
typedef esp_rom_spi_cmd_t psram_cmd_t;
|
||||
|
||||
static uint32_t s_psram_id = 0;
|
||||
static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
|
||||
static void config_psram_spi_phases(void);
|
||||
extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
static uint8_t s_psram_cs_io = (uint8_t) -1;
|
||||
|
||||
uint8_t esp_psram_impl_get_cs_io(void)
|
||||
{
|
||||
return s_psram_cs_io;
|
||||
}
|
||||
|
||||
static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
|
||||
{
|
||||
if (mode == PSRAM_CMD_QPI) {
|
||||
esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
|
||||
SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
|
||||
} else if (mode == PSRAM_CMD_SPI) {
|
||||
esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
|
||||
}
|
||||
}
|
||||
static void _psram_exec_cmd(int spi_num,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t* mosi_data, int mosi_bit_len,
|
||||
uint8_t* miso_data, int miso_bit_len)
|
||||
{
|
||||
esp_rom_spi_cmd_t conf;
|
||||
uint32_t _addr = addr;
|
||||
conf.addr = &_addr;
|
||||
conf.addrBitLen = addr_bit_len;
|
||||
conf.cmd = cmd;
|
||||
conf.cmdBitLen = cmd_bit_len;
|
||||
conf.dummyBitLen = dummy_bits;
|
||||
conf.txData = (uint32_t*) mosi_data;
|
||||
conf.txDataBitLen = mosi_bit_len;
|
||||
conf.rxData = (uint32_t*) miso_data;
|
||||
conf.rxDataBitLen = miso_bit_len;
|
||||
esp_rom_spi_cmd_config(spi_num, &conf);
|
||||
}
|
||||
|
||||
void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t* mosi_data, int mosi_bit_len,
|
||||
uint8_t* miso_data, int miso_bit_len,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation)
|
||||
{
|
||||
uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
|
||||
uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
|
||||
uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
|
||||
uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
|
||||
psram_set_op_mode(spi_num, mode);
|
||||
_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
|
||||
dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
|
||||
esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
|
||||
|
||||
WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
|
||||
WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
|
||||
WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
|
||||
WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
|
||||
}
|
||||
|
||||
//exit QPI mode(set back to SPI mode)
|
||||
static void psram_disable_qio_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
|
||||
PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//TODO IDF-4307
|
||||
//switch psram burst length(32 bytes or 1024 bytes)
|
||||
//datasheet says it should be 1024 bytes by default
|
||||
static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
|
||||
{
|
||||
psram_exec_cmd(spi_num, mode,
|
||||
PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//send reset command to psram, in spi mode
|
||||
static void psram_reset_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_RESET_EN, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_RESET, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
esp_err_t psram_enable_wrap(uint32_t wrap_size)
|
||||
{
|
||||
//TODO: IDF-4307
|
||||
static uint32_t current_wrap_size = 0;
|
||||
if (current_wrap_size == wrap_size) {
|
||||
return ESP_OK;
|
||||
}
|
||||
switch (wrap_size) {
|
||||
case 32:
|
||||
case 0:
|
||||
psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
|
||||
current_wrap_size = wrap_size;
|
||||
return ESP_OK;
|
||||
case 16:
|
||||
case 64:
|
||||
default:
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
bool psram_support_wrap_size(uint32_t wrap_size)
|
||||
{
|
||||
switch (wrap_size) {
|
||||
case 0:
|
||||
case 32:
|
||||
return true;
|
||||
case 16:
|
||||
case 64:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
|
||||
static void psram_read_id(int spi_num, uint32_t* dev_id)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
|
||||
0, 24, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//enter QPI mode
|
||||
static void psram_enable_qio_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
static void psram_set_cs_timing(void)
|
||||
{
|
||||
//SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
|
||||
SET_PERI_REG_BITS(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_HOLD_TIME_V, 3, SPI_SMEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_SETUP_TIME_V, 3, SPI_SMEM_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_HOLD_M | SPI_SMEM_CS_SETUP_M);
|
||||
|
||||
SET_PERI_REG_BITS(SPI_SMEM_AC_REG(0), SPI_SMEM_CS_HOLD_DELAY_V, 3, SPI_SMEM_CS_HOLD_DELAY_S);
|
||||
}
|
||||
|
||||
static void psram_gpio_config(void)
|
||||
{
|
||||
//CS1
|
||||
uint8_t cs1_io = PSRAM_CS_IO;
|
||||
if (cs1_io == SPI_CS1_GPIO_NUM) {
|
||||
gpio_hal_iomux_func_sel(IO_MUX_GPIO15_REG, FUNC_SPICS1_SPICS1);
|
||||
} else {
|
||||
esp_rom_gpio_connect_out_signal(cs1_io, FSPICS1_OUT_IDX, 0, 0);
|
||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
|
||||
}
|
||||
s_psram_cs_io = cs1_io;
|
||||
|
||||
//WP HD
|
||||
uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
|
||||
//This ROM function will init both WP and HD pins.
|
||||
esp_rom_spiflash_select_qio_pins(wp_io, 0);
|
||||
|
||||
// Reserve psram pins
|
||||
esp_gpio_reserve(BIT64(cs1_io) | BIT64(wp_io));
|
||||
}
|
||||
|
||||
esp_err_t esp_psram_impl_enable(void) //psram init
|
||||
{
|
||||
psram_gpio_config();
|
||||
psram_set_cs_timing();
|
||||
|
||||
//We use SPI1 to init PSRAM
|
||||
psram_disable_qio_mode(SPI1_NUM);
|
||||
psram_read_id(SPI1_NUM, &s_psram_id);
|
||||
if (!PSRAM_IS_VALID(s_psram_id)) {
|
||||
/* 16Mbit psram ID read error workaround:
|
||||
* treat the first read id as a dummy one as the pre-condition,
|
||||
* Send Read ID command again
|
||||
*/
|
||||
psram_read_id(SPI1_NUM, &s_psram_id);
|
||||
if (!PSRAM_IS_VALID(s_psram_id)) {
|
||||
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
|
||||
return ESP_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
if (PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
|
||||
s_psram_size = PSRAM_SIZE_8MB;
|
||||
} else if (PSRAM_IS_2T_APS3204(s_psram_id)) {
|
||||
s_psram_size = PSRAM_SIZE_4MB;
|
||||
} else {
|
||||
uint8_t density = PSRAM_SIZE_ID(s_psram_id);
|
||||
s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
|
||||
density == 0x1 ? PSRAM_SIZE_4MB :
|
||||
density == 0x2 ? PSRAM_SIZE_8MB : 0;
|
||||
}
|
||||
|
||||
//SPI1: send psram reset command
|
||||
psram_reset_mode(SPI1_NUM);
|
||||
//SPI1: send QPI enable command
|
||||
psram_enable_qio_mode(SPI1_NUM);
|
||||
|
||||
//Configure SPI0 PSRAM related SPI Phases
|
||||
config_psram_spi_phases();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv)
|
||||
{
|
||||
uint32_t freqbits = 0;
|
||||
if (1 >= freqdiv) {
|
||||
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
|
||||
} else {
|
||||
freqbits = (((freqdiv - 1) << SPI_MEM_SCLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_SCLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_SCLKCNT_L_S);
|
||||
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
|
||||
}
|
||||
}
|
||||
|
||||
//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
|
||||
static void config_psram_spi_phases(void)
|
||||
{
|
||||
#if (CONFIG_SPIRAM_SPEED == 80)
|
||||
psram_clock_set(0, 1);
|
||||
#elif (CONFIG_SPIRAM_SPEED == 40)
|
||||
psram_clock_set(0, 2);
|
||||
#endif
|
||||
|
||||
//Config CMD phase
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
|
||||
|
||||
//Config ADDR phase
|
||||
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
|
||||
|
||||
//Dummy
|
||||
/**
|
||||
* We set the PSRAM chip required dummy here. If timing tuning is needed,
|
||||
* the dummy length will be updated in `mspi_timing_enter_high_speed_mode()`
|
||||
*/
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy
|
||||
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------
|
||||
* Following APIs are not required to be IRAM-Safe
|
||||
*
|
||||
* Consider moving these to another file if this kind of APIs grows dramatically
|
||||
*-------------------------------------------------------------------------------*/
|
||||
esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
|
||||
{
|
||||
if (!out_size_bytes) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*out_size_bytes = s_psram_size;
|
||||
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
|
||||
esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
|
||||
{
|
||||
if (!out_size_bytes) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*out_size_bytes = s_psram_size;
|
||||
|
||||
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
@ -1,412 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2013-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "string.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_types.h"
|
||||
#include "esp_bit_defs.h"
|
||||
#include "esp_log.h"
|
||||
#include "../esp_psram_impl.h"
|
||||
#include "esp32s3/rom/spi_flash.h"
|
||||
#include "esp32s3/rom/opi_flash.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "hal/gpio_hal.h"
|
||||
#include "esp_private/spi_flash_os.h"
|
||||
#include "esp_private/mspi_timing_tuning.h"
|
||||
#include "esp_private/esp_gpio_reserve.h"
|
||||
|
||||
static const char* TAG = "quad_psram";
|
||||
|
||||
//Commands for PSRAM chip
|
||||
#define PSRAM_READ 0x03
|
||||
#define PSRAM_FAST_READ 0x0B
|
||||
#define PSRAM_FAST_READ_QUAD 0xEB
|
||||
#define PSRAM_WRITE 0x02
|
||||
#define PSRAM_QUAD_WRITE 0x38
|
||||
#define PSRAM_ENTER_QMODE 0x35
|
||||
#define PSRAM_EXIT_QMODE 0xF5
|
||||
#define PSRAM_RESET_EN 0x66
|
||||
#define PSRAM_RESET 0x99
|
||||
#define PSRAM_SET_BURST_LEN 0xC0
|
||||
#define PSRAM_DEVICE_ID 0x9F
|
||||
|
||||
#define PSRAM_FAST_READ_DUMMY 4
|
||||
#define PSRAM_FAST_READ_QUAD_DUMMY 6
|
||||
|
||||
// ID
|
||||
#define PSRAM_ID_KGD_M 0xff
|
||||
#define PSRAM_ID_KGD_S 8
|
||||
#define PSRAM_ID_KGD 0x5d
|
||||
#define PSRAM_ID_EID_M 0xff
|
||||
#define PSRAM_ID_EID_S 16
|
||||
|
||||
// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
|
||||
//
|
||||
// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
|
||||
// -------------------------------------
|
||||
// 0 | 0 | 0 | 16
|
||||
// 0 | 0 | 1 | 32
|
||||
// 0 | 1 | 0 | 64
|
||||
#define PSRAM_EID_SIZE_M 0x07
|
||||
#define PSRAM_EID_SIZE_S 5
|
||||
|
||||
#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
|
||||
#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
|
||||
#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
|
||||
#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
|
||||
|
||||
#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
|
||||
#define PSRAM_IS_2T_APS3204(id) ((((id) >> 21) && 0xfffff) == 1)
|
||||
|
||||
// IO-pins for PSRAM.
|
||||
// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
|
||||
// hardcode the flash pins as well, making this code incompatible with either a setup
|
||||
// that has the flash on non-standard pins or ESP32s with built-in flash.
|
||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
||||
// PSRAM clock and cs IO should be configured based on hardware design.
|
||||
#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
|
||||
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
|
||||
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
|
||||
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
|
||||
#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
|
||||
|
||||
#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
|
||||
#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
|
||||
|
||||
#define SPI1_NUM 1
|
||||
#define SPI0_NUM 0
|
||||
|
||||
typedef enum {
|
||||
PSRAM_CMD_QPI,
|
||||
PSRAM_CMD_SPI,
|
||||
} psram_cmd_mode_t;
|
||||
|
||||
typedef esp_rom_spi_cmd_t psram_cmd_t;
|
||||
|
||||
static uint32_t s_psram_id = 0;
|
||||
static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
|
||||
static void config_psram_spi_phases(void);
|
||||
extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
static uint8_t s_psram_cs_io = (uint8_t) -1;
|
||||
|
||||
uint8_t esp_psram_impl_get_cs_io(void)
|
||||
{
|
||||
return s_psram_cs_io;
|
||||
}
|
||||
|
||||
static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
|
||||
{
|
||||
if (mode == PSRAM_CMD_QPI) {
|
||||
esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
|
||||
SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
|
||||
} else if (mode == PSRAM_CMD_SPI) {
|
||||
esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
|
||||
}
|
||||
}
|
||||
static void _psram_exec_cmd(int spi_num,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t* mosi_data, int mosi_bit_len,
|
||||
uint8_t* miso_data, int miso_bit_len)
|
||||
{
|
||||
esp_rom_spi_cmd_t conf;
|
||||
uint32_t _addr = addr;
|
||||
conf.addr = &_addr;
|
||||
conf.addrBitLen = addr_bit_len;
|
||||
conf.cmd = cmd;
|
||||
conf.cmdBitLen = cmd_bit_len;
|
||||
conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723
|
||||
conf.txData = (uint32_t*) mosi_data;
|
||||
conf.txDataBitLen = mosi_bit_len;
|
||||
conf.rxData = (uint32_t*) miso_data;
|
||||
conf.rxDataBitLen = miso_bit_len;
|
||||
esp_rom_spi_cmd_config(spi_num, &conf);
|
||||
}
|
||||
|
||||
void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t* mosi_data, int mosi_bit_len,
|
||||
uint8_t* miso_data, int miso_bit_len,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation)
|
||||
{
|
||||
uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
|
||||
uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
|
||||
uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
|
||||
uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
|
||||
psram_set_op_mode(spi_num, mode);
|
||||
_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
|
||||
dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
|
||||
esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
|
||||
|
||||
WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
|
||||
WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
|
||||
WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
|
||||
WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
|
||||
}
|
||||
|
||||
//exit QPI mode(set back to SPI mode)
|
||||
static void psram_disable_qio_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
|
||||
PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//TODO IDF-4307
|
||||
//switch psram burst length(32 bytes or 1024 bytes)
|
||||
//datasheet says it should be 1024 bytes by default
|
||||
static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
|
||||
{
|
||||
psram_exec_cmd(spi_num, mode,
|
||||
PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//send reset command to psram, in spi mode
|
||||
static void psram_reset_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_RESET_EN, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_RESET, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
esp_err_t psram_enable_wrap(uint32_t wrap_size)
|
||||
{
|
||||
//TODO: IDF-4307
|
||||
static uint32_t current_wrap_size = 0;
|
||||
if (current_wrap_size == wrap_size) {
|
||||
return ESP_OK;
|
||||
}
|
||||
switch (wrap_size) {
|
||||
case 32:
|
||||
case 0:
|
||||
psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
|
||||
current_wrap_size = wrap_size;
|
||||
return ESP_OK;
|
||||
case 16:
|
||||
case 64:
|
||||
default:
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
bool psram_support_wrap_size(uint32_t wrap_size)
|
||||
{
|
||||
switch (wrap_size) {
|
||||
case 0:
|
||||
case 32:
|
||||
return true;
|
||||
case 16:
|
||||
case 64:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
|
||||
static void psram_read_id(int spi_num, uint32_t* dev_id)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_DEVICE_ID, 8, /* command and command bit len*/
|
||||
0, 24, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
//enter QPI mode
|
||||
static void psram_enable_qio_mode(int spi_num)
|
||||
{
|
||||
psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
|
||||
PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
|
||||
0, 0, /* address and address bit len*/
|
||||
0, /* dummy bit len */
|
||||
NULL, 0, /* tx data and tx bit len*/
|
||||
NULL, 0, /* rx data and rx bit len*/
|
||||
CS_PSRAM_SEL, /* cs bit mask*/
|
||||
false); /* whether is program/erase operation */
|
||||
}
|
||||
|
||||
static void psram_set_cs_timing(void)
|
||||
{
|
||||
//SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
|
||||
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
|
||||
}
|
||||
|
||||
static void psram_gpio_config(void)
|
||||
{
|
||||
//CS1
|
||||
uint8_t cs1_io = PSRAM_CS_IO;
|
||||
if (cs1_io == SPI_CS1_GPIO_NUM) {
|
||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], FUNC_SPICS1_SPICS1);
|
||||
} else {
|
||||
esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, 0, 0);
|
||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
|
||||
}
|
||||
s_psram_cs_io = cs1_io;
|
||||
|
||||
//WP HD
|
||||
uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
|
||||
// MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader.
|
||||
} else {
|
||||
// MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader.
|
||||
wp_io = esp_rom_efuse_get_flash_wp_gpio();
|
||||
}
|
||||
//This ROM function will init both WP and HD pins.
|
||||
esp_rom_spiflash_select_qio_pins(wp_io, spiconfig);
|
||||
|
||||
// Reserve psram pins
|
||||
esp_gpio_reserve(BIT64(cs1_io) | BIT64(wp_io));
|
||||
}
|
||||
|
||||
esp_err_t esp_psram_impl_enable(void) //psram init
|
||||
{
|
||||
psram_gpio_config();
|
||||
psram_set_cs_timing();
|
||||
|
||||
//enter MSPI slow mode to init PSRAM device registers
|
||||
mspi_timing_enter_low_speed_mode(true);
|
||||
|
||||
//We use SPI1 to init PSRAM
|
||||
psram_disable_qio_mode(SPI1_NUM);
|
||||
psram_read_id(SPI1_NUM, &s_psram_id);
|
||||
if (!PSRAM_IS_VALID(s_psram_id)) {
|
||||
/* 16Mbit psram ID read error workaround:
|
||||
* treat the first read id as a dummy one as the pre-condition,
|
||||
* Send Read ID command again
|
||||
*/
|
||||
psram_read_id(SPI1_NUM, &s_psram_id);
|
||||
if (!PSRAM_IS_VALID(s_psram_id)) {
|
||||
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08" PRIx32 ", PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
|
||||
return ESP_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
if (PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
|
||||
s_psram_size = PSRAM_SIZE_8MB;
|
||||
} else if (PSRAM_IS_2T_APS3204(s_psram_id)) {
|
||||
s_psram_size = PSRAM_SIZE_4MB;
|
||||
} else {
|
||||
uint8_t density = PSRAM_SIZE_ID(s_psram_id);
|
||||
s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
|
||||
density == 0x1 ? PSRAM_SIZE_4MB :
|
||||
density == 0x2 ? PSRAM_SIZE_8MB : 0;
|
||||
}
|
||||
|
||||
//SPI1: send psram reset command
|
||||
psram_reset_mode(SPI1_NUM);
|
||||
//SPI1: send QPI enable command
|
||||
psram_enable_qio_mode(SPI1_NUM);
|
||||
|
||||
//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
|
||||
mspi_timing_psram_tuning();
|
||||
|
||||
//Configure SPI0 PSRAM related SPI Phases
|
||||
config_psram_spi_phases();
|
||||
//Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
|
||||
mspi_timing_enter_high_speed_mode(true);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
|
||||
static void config_psram_spi_phases(void)
|
||||
{
|
||||
//Config CMD phase
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
|
||||
|
||||
//Config ADDR phase
|
||||
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
|
||||
|
||||
//Dummy
|
||||
/**
|
||||
* We set the PSRAM chip required dummy here. If timing tuning is needed,
|
||||
* the dummy length will be updated in `mspi_timing_enter_high_speed_mode()`
|
||||
*/
|
||||
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy
|
||||
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------
|
||||
* Following APIs are not required to be IRAM-Safe
|
||||
*
|
||||
* Consider moving these to another file if this kind of APIs grows dramatically
|
||||
*-------------------------------------------------------------------------------*/
|
||||
esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
|
||||
{
|
||||
if (!out_size_bytes) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*out_size_bytes = s_psram_size;
|
||||
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function is to get the available physical psram size in bytes.
|
||||
*
|
||||
* When ECC is enabled, the available size will be reduced.
|
||||
* On S3 Quad PSRAM, ECC is not enabled for now.
|
||||
*/
|
||||
esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
|
||||
{
|
||||
if (!out_size_bytes) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*out_size_bytes = s_psram_size;
|
||||
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
||||
}
|
||||
@ -4,8 +4,8 @@ entries:
|
||||
|
||||
if SPIRAM = y:
|
||||
if SPIRAM_MODE_QUAD = y:
|
||||
if IDF_TARGET_ESP32S3 = y:
|
||||
esp_psram_impl_quad (noflash)
|
||||
if IDF_TARGET_ESP32 = n && IDF_TARGET_ESP32S2 = n:
|
||||
esp_psram_impl_ap_quad (noflash)
|
||||
|
||||
if IDF_TARGET_ESP32S3 = y:
|
||||
if SPIRAM_MODE_OCT = y:
|
||||
|
||||
264
components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
Normal file
264
components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
Normal file
@ -0,0 +1,264 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The ll is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <sys/param.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "soc/spi_mem_struct.h"
|
||||
#include "soc/spi1_mem_reg.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "rom/opi_flash.h"
|
||||
#include "hal/psram_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PSRAM_CTRLR_LL_MSPI_ID_0 0
|
||||
#define PSRAM_CTRLR_LL_MSPI_ID_1 1
|
||||
|
||||
#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M
|
||||
|
||||
/**
|
||||
* @brief PSRAM enum for cs id.
|
||||
*/
|
||||
typedef enum {
|
||||
PSRAM_LL_CS_ID_0 = 0,
|
||||
PSRAM_LL_CS_ID_1 = 1,
|
||||
} psram_ll_cs_id_t;
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM write cmd
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param cmd_bitlen command bitlen
|
||||
* @param cmd_val command value
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitlen, uint32_t cmd_val)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(cmd_bitlen > 0);
|
||||
SPIMEM0.cache_sctrl.sram_usr_wcmd = 1;
|
||||
SPIMEM0.sram_dwr_cmd.sram_usr_wr_cmd_bitlen = cmd_bitlen - 1;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_dwr_cmd, sram_usr_wr_cmd_value, cmd_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM read cmd
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param cmd_bitlen command bitlen
|
||||
* @param cmd_val command value
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitlen, uint32_t cmd_val)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(cmd_bitlen > 0);
|
||||
SPIMEM0.cache_sctrl.sram_usr_rcmd = 1;
|
||||
SPIMEM0.sram_drd_cmd.sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_drd_cmd, sram_usr_rd_cmd_value, cmd_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM addr bitlen
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param addr_bitlen address bitlen
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_addr_bitlen(uint32_t mspi_id, uint32_t addr_bitlen)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(addr_bitlen > 0);
|
||||
SPIMEM0.cache_sctrl.sram_addr_bitlen = addr_bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM read dummy
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param dummy_n dummy number
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(dummy_n > 0);
|
||||
SPIMEM0.cache_sctrl.usr_rd_sram_dummy = 1;
|
||||
SPIMEM0.cache_sctrl.sram_rdummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM bus clock
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param clock_conf Configuration value for psram clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock_conf)
|
||||
{
|
||||
SPIMEM0.sram_clk.val = clock_conf;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate spi_flash clock frequency division parameters for register.
|
||||
*
|
||||
* @param clkdiv frequency division factor
|
||||
*
|
||||
* @return Register setting for the given clock division factor.
|
||||
*/
|
||||
static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
|
||||
{
|
||||
uint32_t div_parameter;
|
||||
// See comments of `clock` in `spi_mem_struct.h`
|
||||
if (clkdiv == 1) {
|
||||
div_parameter = (1 << 31);
|
||||
} else {
|
||||
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
|
||||
}
|
||||
return div_parameter;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure the psram read mode
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param read_mode read mode
|
||||
*/
|
||||
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode)
|
||||
{
|
||||
typeof (SPIMEM0.cache_sctrl) cache_sctrl;
|
||||
cache_sctrl.val = SPIMEM0.cache_sctrl.val;
|
||||
|
||||
cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
|
||||
switch (read_mode) {
|
||||
case PSRAM_HAL_CMD_SPI:
|
||||
cache_sctrl.usr_sram_dio = 1;
|
||||
break;
|
||||
case PSRAM_HAL_CMD_QPI:
|
||||
cache_sctrl.usr_sram_qio = 1;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
SPIMEM0.cache_sctrl.val = cache_sctrl.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CS setup
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param setup_n cs setup time
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_setup(uint32_t mspi_id, uint32_t setup_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(setup_n > 0);
|
||||
SPIMEM0.spi_smem_ac.reg_smem_cs_setup = 1;
|
||||
SPIMEM0.spi_smem_ac.reg_smem_cs_setup_time = setup_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CS hold
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param hold_n cs hold time
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_hold(uint32_t mspi_id, uint32_t hold_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(hold_n > 0);
|
||||
SPIMEM0.spi_smem_ac.reg_smem_cs_hold = 1;
|
||||
SPIMEM0.spi_smem_ac.reg_smem_cs_hold_time = hold_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CS hold delay
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param hold_delay_n cs hold delay time
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_hold_delay(uint32_t mspi_id, uint32_t hold_delay_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(hold_delay_n > 0);
|
||||
SPIMEM0.spi_smem_ac.reg_smem_cs_hold_delay = hold_delay_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PSRAM common transaction
|
||||
*
|
||||
* See `opi_flash.h` for parameters
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_common_transaction_base(uint32_t mspi_id, esp_rom_spiflash_read_mode_t mode,
|
||||
uint32_t cmd, uint32_t cmd_bitlen,
|
||||
uint32_t addr, uint32_t addr_bitlen,
|
||||
uint32_t dummy_bits,
|
||||
uint8_t* mosi_data, uint32_t mosi_bitlen,
|
||||
uint8_t* miso_data, uint32_t miso_bitlen,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation)
|
||||
{
|
||||
esp_rom_spi_cmd_t conf = {
|
||||
.cmd = cmd,
|
||||
.cmdBitLen = cmd_bitlen,
|
||||
.addr = &addr,
|
||||
.addrBitLen = addr_bitlen,
|
||||
.txData = (uint32_t *)mosi_data,
|
||||
.txDataBitLen = mosi_bitlen,
|
||||
.rxData = (uint32_t *)miso_data,
|
||||
.rxDataBitLen = miso_bitlen,
|
||||
.dummyBitLen = dummy_bits,
|
||||
};
|
||||
esp_rom_spi_cmd_config(mspi_id, &conf);
|
||||
esp_rom_spi_cmd_start(mspi_id, miso_data, miso_bitlen / 8, cs_mask, is_write_erase_operation);
|
||||
}
|
||||
|
||||
/**
|
||||
* Select which pin to use for the psram
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param cs_id cs_id for psram to use.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_pin(uint32_t mspi_id, psram_ll_cs_id_t cs_id)
|
||||
{
|
||||
SPIMEM0.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
|
||||
SPIMEM0.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the psram quad command
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param ena true if enable, otherwise false
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena)
|
||||
{
|
||||
SPIMEM1.ctrl.fcmd_quad = ena;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
231
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
Normal file
231
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
Normal file
@ -0,0 +1,231 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The ll is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <sys/param.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "soc/spi_mem_struct.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "rom/opi_flash.h"
|
||||
#include "hal/psram_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PSRAM_CTRLR_LL_MSPI_ID_0 0
|
||||
#define PSRAM_CTRLR_LL_MSPI_ID_1 1
|
||||
|
||||
#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M
|
||||
|
||||
/**
|
||||
* @brief PSRAM enum for cs id.
|
||||
*/
|
||||
typedef enum {
|
||||
PSRAM_LL_CS_ID_0 = 0,
|
||||
PSRAM_LL_CS_ID_1 = 1,
|
||||
} psram_ll_cs_id_t;
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM write cmd
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param cmd_bitlen command bitlen
|
||||
* @param cmd_val command value
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitlen, uint32_t cmd_val)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(cmd_bitlen > 0);
|
||||
SPIMEM0.cache_sctrl.usr_wcmd = 1;
|
||||
SPIMEM0.sram_dwr_cmd.usr_wr_cmd_bitlen = cmd_bitlen - 1;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_dwr_cmd, usr_wr_cmd_value, cmd_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM read cmd
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param cmd_bitlen command bitlen
|
||||
* @param cmd_val command value
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitlen, uint32_t cmd_val)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(cmd_bitlen > 0);
|
||||
SPIMEM0.cache_sctrl.usr_rcmd = 1;
|
||||
SPIMEM0.sram_drd_cmd.usr_rd_cmd_bitlen = cmd_bitlen - 1;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_drd_cmd, usr_rd_cmd_value, cmd_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM addr bitlen
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param addr_bitlen address bitlen
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_addr_bitlen(uint32_t mspi_id, uint32_t addr_bitlen)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(addr_bitlen > 0);
|
||||
SPIMEM0.cache_sctrl.sram_addr_bitlen = addr_bitlen - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PSRAM read dummy
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param dummy_n dummy number
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(dummy_n > 0);
|
||||
SPIMEM0.cache_sctrl.usr_rd_sram_dummy = 1;
|
||||
SPIMEM0.cache_sctrl.sram_rdummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Configure the psram read mode
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param read_mode read mode
|
||||
*/
|
||||
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode)
|
||||
{
|
||||
typeof (SPIMEM0.cache_sctrl) cache_sctrl;
|
||||
cache_sctrl.val = SPIMEM0.cache_sctrl.val;
|
||||
|
||||
cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
|
||||
switch (read_mode) {
|
||||
case PSRAM_HAL_CMD_SPI:
|
||||
cache_sctrl.usr_sram_dio = 1;
|
||||
break;
|
||||
case PSRAM_HAL_CMD_QPI:
|
||||
cache_sctrl.usr_sram_qio = 1;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
SPIMEM0.cache_sctrl.val = cache_sctrl.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CS setup
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param setup_n cs setup time
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_setup(uint32_t mspi_id, uint32_t setup_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(setup_n > 0);
|
||||
SPIMEM0.spi_smem_ac.smem_cs_setup = 1;
|
||||
SPIMEM0.spi_smem_ac.smem_cs_setup_time = setup_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CS hold
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param hold_n cs hold time
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_hold(uint32_t mspi_id, uint32_t hold_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(hold_n > 0);
|
||||
SPIMEM0.spi_smem_ac.smem_cs_hold = 1;
|
||||
SPIMEM0.spi_smem_ac.smem_cs_hold_time = hold_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CS hold delay
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param hold_delay_n cs hold delay time
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_set_cs_hold_delay(uint32_t mspi_id, uint32_t hold_delay_n)
|
||||
{
|
||||
(void)mspi_id;
|
||||
HAL_ASSERT(hold_delay_n > 0);
|
||||
SPIMEM0.spi_smem_ac.smem_cs_hold_delay = hold_delay_n - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PSRAM common transaction
|
||||
*
|
||||
* See `opi_flash.h` for parameters
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_common_transaction_base(uint32_t mspi_id, esp_rom_spiflash_read_mode_t mode,
|
||||
uint32_t cmd, uint32_t cmd_bitlen,
|
||||
uint32_t addr, uint32_t addr_bitlen,
|
||||
uint32_t dummy_bits,
|
||||
uint8_t* mosi_data, uint32_t mosi_bitlen,
|
||||
uint8_t* miso_data, uint32_t miso_bitlen,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation)
|
||||
{
|
||||
esp_rom_spi_cmd_t conf = {
|
||||
.cmd = cmd,
|
||||
.cmdBitLen = cmd_bitlen,
|
||||
.addr = &addr,
|
||||
.addrBitLen = addr_bitlen,
|
||||
.txData = (uint32_t *)mosi_data,
|
||||
.txDataBitLen = mosi_bitlen,
|
||||
.rxData = (uint32_t *)miso_data,
|
||||
.rxDataBitLen = miso_bitlen,
|
||||
.dummyBitLen = dummy_bits,
|
||||
};
|
||||
esp_rom_spi_cmd_config(mspi_id, &conf);
|
||||
esp_rom_spi_cmd_start(mspi_id, miso_data, miso_bitlen / 8, cs_mask, is_write_erase_operation);
|
||||
}
|
||||
|
||||
/**
|
||||
* Select which pin to use for the psram
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param cs_id cs_id for psram to use.
|
||||
*/
|
||||
static inline void psram_ctrlr_ll_set_cs_pin(uint32_t mspi_id, psram_ll_cs_id_t cs_id)
|
||||
{
|
||||
SPIMEM0.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
|
||||
SPIMEM0.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the psram quad command
|
||||
*
|
||||
* @param mspi_id mspi_id
|
||||
* @param ena true if enable, otherwise false
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena)
|
||||
{
|
||||
SPIMEM1.ctrl.fcmd_quad = ena;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
25
components/hal/include/hal/psram_types.h
Normal file
25
components/hal/include/hal/psram_types.h
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enumeration of PSRAM command types
|
||||
*/
|
||||
typedef enum {
|
||||
PSRAM_HAL_CMD_QPI, /*!< Quad command for psram command */
|
||||
PSRAM_HAL_CMD_SPI, /*!< SPI command for psram command */
|
||||
} psram_hal_cmd_mode_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user