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Merge branch 'feature/add_h2_beta2_target_support' into 'master'

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esp32h2: Add support for esp32h2 beta2 version

Closes IDF-4230

See merge request espressif/esp-idf!15630
This commit is contained in:
Michael (XIAO Xufeng) 2021-11-26 03:56:01 +00:00
commit c4310fb0db
94 changed files with 33901 additions and 672 deletions
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21
Kconfig
View File

@ -11,6 +11,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_ENV_FPGA
# This option is for internal use only
bool
default "y" if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3378
option env="IDF_ENV_FPGA"
config IDF_TARGET_ARCH_RISCV
@ -57,6 +58,23 @@ mainmenu "Espressif IoT Development Framework Configuration"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
choice IDF_TARGET_ESP32H2_BETA_VERSION
prompt "ESP32-H2 beta version"
depends on IDF_TARGET_ESP32H2
default IDF_TARGET_ESP32H2_BETA_VERSION_1
help
Currently ESP32-H2 has several beta versions for internal use only.
Select the one that matches your chip model.
config IDF_TARGET_ESP32H2_BETA_VERSION_1
bool
prompt "ESP32-H2 beta1"
config IDF_TARGET_ESP32H2_BETA_VERSION_2
bool
prompt "ESP32-H2 beta2"
select ESPTOOLPY_NO_STUB # TODO: IDF-4288
endchoice
config IDF_TARGET_ESP8684
bool
default "y" if IDF_TARGET="esp8684"
@ -75,8 +93,9 @@ mainmenu "Espressif IoT Development Framework Configuration"
default 0x0002 if IDF_TARGET_ESP32S2
default 0x0005 if IDF_TARGET_ESP32C3
default 0x0009 if IDF_TARGET_ESP32S3
default 0x000A if IDF_TARGET_ESP32H2 # ESP32H2-TODO: IDF-3475
default 0x000C if IDF_TARGET_ESP8684
default 0x000A if IDF_TARGET_ESP32H2_BETA_VERSION_1
default 0x000E if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3475
default 0xFFFF
menu "SDK tool configuration"

6
components/bootloader_support/include/esp_app_format.h
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@ -16,8 +16,12 @@ typedef enum {
ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 */ // ESP32H2-TODO: IDF-3475
ESP_CHIP_ID_ESP8684 = 0x000C, /*!< chip ID: ESP32-8684 */
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
ESP_CHIP_ID_ESP32H2 = 0x000E, /*!< chip ID: ESP32-H2 Beta2*/ // ESP32H2-TODO: IDF-3475
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */
#endif
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;

8
components/bootloader_support/src/bootloader_efuse_esp32h2.c
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@ -9,12 +9,20 @@
uint8_t bootloader_common_get_chip_revision(void)
{
#if IDF_TARGET_ESP32H2_BETA_VERSION_1 // TODO: IDF-4337
// should return the same value as esp_efuse_get_chip_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
#else
return 0;
#endif
}
uint32_t bootloader_common_get_chip_ver_pkg(void)
{
#if IDF_TARGET_ESP32H2_BETA_VERSION_1 // TODO: IDF-4337
// should return the same value as esp_efuse_get_pkg_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
#else
return 0;
#endif
}

14
components/efuse/esp32h2/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 6aaac59bd3f6d31bea4aef43b1f0d78a
// md5_digest_table 8d520559b0ed30f0cef34704317f2815
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -24,7 +24,7 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
};
static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
{EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
{EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
};
static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
@ -179,8 +179,8 @@ static const esp_efuse_desc_t DIS_USB[] = {
{EFUSE_BLK0, 45, 1}, // Disable USB function,
};
static const esp_efuse_desc_t DIS_CAN[] = {
{EFUSE_BLK0, 46, 1}, // Disable CAN function,
static const esp_efuse_desc_t DIS_TWAI[] = {
{EFUSE_BLK0, 46, 1}, // Disable TWAI function,
};
static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
@ -508,7 +508,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
&WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
&WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
NULL
};
@ -702,8 +702,8 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
&DIS_CAN[0], // Disable CAN function
const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
&DIS_TWAI[0], // Disable TWAI function
NULL
};

4
components/efuse/esp32h2/esp_efuse_table.csv
View File

@ -16,7 +16,7 @@
# EFUSE_RD_WR_DIS_REG #
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
@ -57,7 +57,7 @@
DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.

Can't render this file because it contains an unexpected character in line 7 and column 87.

4
components/efuse/esp32h2/include/esp_efuse_table.h
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@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 6aaac59bd3f6d31bea4aef43b1f0d78a
// md5_digest_table 8d520559b0ed30f0cef34704317f2815
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -57,7 +57,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];

4
components/esp_hw_support/port/esp32h2/rtc_clk_init.c
View File

@ -43,7 +43,11 @@ void rtc_clk_init(rtc_clk_config_t cfg)
* - CK8M_DFREQ value controls tuning of 8M clock.
* CLK_8M_DFREQ constant gives the best temperature characteristics.
*/
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
#endif
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
/* enable modem clk */

5
components/esp_hw_support/port/esp32h2/rtc_init.c
View File

@ -80,8 +80,13 @@ void rtc_init(rtc_config_t cfg)
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
}
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
#endif
// clear i2c_reset_protect pd force, need tested in low temperature.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);

67
components/esp_hw_support/port/esp32h2/rtc_sleep.c
View File

@ -24,6 +24,18 @@
#include "soc_log.h"
#include "esp_rom_uart.h"
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG
#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG
#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG RTC_CNTL_DIGULATOR0_DBIAS_REG
#define RTC_CNTL_REGULATOR1_DBIAS_REG RTC_CNTL_RTCULATOR1_DBIAS_REG
#define RTC_CNTL_REGULATOR0_DBIAS_REG RTC_CNTL_RTCULATOR0_DBIAS_REG
#endif
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
@ -77,27 +89,27 @@ void regulator_set(regulator_cfg_t cfg)
{
// DIG REGULATOR0
if (cfg.dig_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
}
// DIG REGULATOR1
if (cfg.dig_regul1_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
}
// RTC REGULATOR0
if (cfg.rtc_regul0_en) {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 1);
}
}
@ -105,27 +117,27 @@ void regulator_slt(regulator_config_t regula_cfg)
{
// dig regulator
if (regula_cfg.dig_source == 1) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
}
// rtc regulator
if (regula_cfg.rtc_source == 1) {
REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
}
}
void dbias_switch_set(dbias_swt_cfg_t cfg)
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
}
void left_up_trx_fpu(bool fpu)
@ -186,19 +198,20 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
// ESP32-H2 TO-DO: IDF-3693
if (cfg.deep_slp) {
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}

14
components/esp_rom/CMakeLists.txt
View File

@ -28,10 +28,20 @@ idf_component_register(SRCS ${sources}
INCLUDE_DIRS ${include_dirs}
PRIV_REQUIRES ${private_required_comp})
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
set(ld_folder "ld/rev1")
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
set(ld_folder "ld/rev2")
endif()
else()
set(ld_folder "ld")
endif()
# Append a target linker script at the target-specific path,
# only the 'name' part is different for each script
function(rom_linker_script name)
target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/ld/${target}.rom.${name}.ld")
target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.${name}.ld")
endfunction()
if(target STREQUAL "linux")
@ -40,7 +50,7 @@ if(target STREQUAL "linux")
target_compile_options(${COMPONENT_LIB} PUBLIC -Wimplicit-fallthrough=0 -Wno-shift-count-overflow)
endif()
else()
target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/ld/${target}.rom.ld")
target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.ld")
rom_linker_script("api")
rom_linker_script("libgcc")
endif()

6
components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld → components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 );

6
components/esp_rom/esp32h2/ld/esp32h2.rom.ld → components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/esp32h2.rom.libgcc.ld → components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.libgcc.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/esp32h2.rom.newlib-nano.ld → components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib-nano.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld → components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/esp32h2.rom.version.ld → components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.version.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32b1z
*
* These addresses should be compatible with any ROM version for this chip.

45
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld Normal file
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@ -0,0 +1,45 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 );
PROVIDE ( esp_rom_tjpgd_prepare = 0x40000100 );
PROVIDE ( esp_rom_crc32_le = crc32_le );
PROVIDE ( esp_rom_crc16_le = crc16_le );
PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_crc32_be = crc32_be );
PROVIDE ( esp_rom_crc16_be = crc16_be );
PROVIDE ( esp_rom_crc8_be = crc8_be );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1958
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld Normal file
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File diff suppressed because it is too large Load Diff

113
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld Normal file
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@ -0,0 +1,113 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h2.rom.libgcc.ld for esp32h2
*
*
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group libgcc
***************************************/
/* Functions */
__absvdi2 = 0x4000098c;
__absvsi2 = 0x40000990;
__adddf3 = 0x40000994;
__addsf3 = 0x40000998;
__addvdi3 = 0x4000099c;
__addvsi3 = 0x400009a0;
__ashldi3 = 0x400009a4;
__ashrdi3 = 0x400009a8;
__bswapdi2 = 0x400009ac;
__bswapsi2 = 0x400009b0;
__clear_cache = 0x400009b4;
__clrsbdi2 = 0x400009b8;
__clrsbsi2 = 0x400009bc;
__clzdi2 = 0x400009c0;
__clzsi2 = 0x400009c4;
__cmpdi2 = 0x400009c8;
__ctzdi2 = 0x400009cc;
__ctzsi2 = 0x400009d0;
__divdc3 = 0x400009d4;
__divdf3 = 0x400009d8;
__divdi3 = 0x400009dc;
__divsc3 = 0x400009e0;
__divsf3 = 0x400009e4;
__divsi3 = 0x400009e8;
__eqdf2 = 0x400009ec;
__eqsf2 = 0x400009f0;
__extendsfdf2 = 0x400009f4;
__ffsdi2 = 0x400009f8;
__ffssi2 = 0x400009fc;
__fixdfdi = 0x40000a00;
__fixdfsi = 0x40000a04;
__fixsfdi = 0x40000a08;
__fixsfsi = 0x40000a0c;
__fixunsdfsi = 0x40000a10;
__fixunssfdi = 0x40000a14;
__fixunssfsi = 0x40000a18;
__floatdidf = 0x40000a1c;
__floatdisf = 0x40000a20;
__floatsidf = 0x40000a24;
__floatsisf = 0x40000a28;
__floatundidf = 0x40000a2c;
__floatundisf = 0x40000a30;
__floatunsidf = 0x40000a34;
__floatunsisf = 0x40000a38;
__gcc_bcmp = 0x40000a3c;
__gedf2 = 0x40000a40;
__gesf2 = 0x40000a44;
__gtdf2 = 0x40000a48;
__gtsf2 = 0x40000a4c;
__ledf2 = 0x40000a50;
__lesf2 = 0x40000a54;
__lshrdi3 = 0x40000a58;
__ltdf2 = 0x40000a5c;
__ltsf2 = 0x40000a60;
__moddi3 = 0x40000a64;
__modsi3 = 0x40000a68;
__muldc3 = 0x40000a6c;
__muldf3 = 0x40000a70;
__muldi3 = 0x40000a74;
__mulsc3 = 0x40000a78;
__mulsf3 = 0x40000a7c;
__mulsi3 = 0x40000a80;
__mulvdi3 = 0x40000a84;
__mulvsi3 = 0x40000a88;
__nedf2 = 0x40000a8c;
__negdf2 = 0x40000a90;
__negdi2 = 0x40000a94;
__negsf2 = 0x40000a98;
__negvdi2 = 0x40000a9c;
__negvsi2 = 0x40000aa0;
__nesf2 = 0x40000aa4;
__paritysi2 = 0x40000aa8;
__popcountdi2 = 0x40000aac;
__popcountsi2 = 0x40000ab0;
__powidf2 = 0x40000ab4;
__powisf2 = 0x40000ab8;
__subdf3 = 0x40000abc;
__subsf3 = 0x40000ac0;
__subvdi3 = 0x40000ac4;
__subvsi3 = 0x40000ac8;
__truncdfsf2 = 0x40000acc;
__ucmpdi2 = 0x40000ad0;
__udivdi3 = 0x40000ad4;
__udivmoddi4 = 0x40000ad8;
__udivsi3 = 0x40000adc;
__udiv_w_sdiv = 0x40000ae0;
__umoddi3 = 0x40000ae4;
__umodsi3 = 0x40000ae8;
__unorddf2 = 0x40000aec;
__unordsf2 = 0x40000af0;
__extenddftf2 = 0x40000af4;
__trunctfdf2 = 0x40000af8;

48
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld Normal file
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@ -0,0 +1,48 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2
*
*
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib_nano_format
***************************************/
/* Functions */
__sprint_r = 0x40000674;
_fiprintf_r = 0x40000678;
_fprintf_r = 0x4000067c;
_printf_common = 0x40000680;
_printf_i = 0x40000684;
_vfiprintf_r = 0x40000688;
_vfprintf_r = 0x4000068c;
fiprintf = 0x40000690;
fprintf = 0x40000694;
printf = 0x40000698;
vfiprintf = 0x4000069c;
vfprintf = 0x400006a0;
asprintf = 0x400006a4;
sprintf = 0x400006a8;
snprintf = 0x400006ac;
siprintf = 0x400006b0;
sniprintf = 0x400006b4;
vprintf = 0x400006b8;
viprintf = 0x400006bc;
vsnprintf = 0x400006c0;
vsniprintf = 0x400006c4;
__rom_printf_float = 0x400006c8;
__rom_scanf_float = 0x400006cc;
_scanf_i = 0x400006d0;
_scanf_chars = 0x400006d4;
sscanf = 0x400006d8;
siscanf = 0x400006dc;

148
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld Normal file
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@ -0,0 +1,148 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h2.rom.newlib.ld for esp32h2
*
*
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x40000484;
memset = 0x40000488;
memcpy = 0x4000048c;
memmove = 0x40000490;
memcmp = 0x40000494;
strcpy = 0x40000498;
strncpy = 0x4000049c;
strcmp = 0x400004a0;
strncmp = 0x400004a4;
strlen = 0x400004a8;
strstr = 0x400004ac;
bzero = 0x400004b0;
_isatty_r = 0x400004b4;
sbrk = 0x400004b8;
isalnum = 0x400004bc;
isalpha = 0x400004c0;
isascii = 0x400004c4;
isblank = 0x400004c8;
iscntrl = 0x400004cc;
isdigit = 0x400004d0;
islower = 0x400004d4;
isgraph = 0x400004d8;
isprint = 0x400004dc;
ispunct = 0x400004e0;
isspace = 0x400004e4;
isupper = 0x400004e8;
toupper = 0x400004ec;
tolower = 0x400004f0;
toascii = 0x400004f4;
memccpy = 0x400004f8;
memchr = 0x400004fc;
memrchr = 0x40000500;
strcasecmp = 0x40000504;
strcasestr = 0x40000508;
strcat = 0x4000050c;
strdup = 0x40000510;
strchr = 0x40000514;
strcspn = 0x40000518;
strcoll = 0x4000051c;
strlcat = 0x40000520;
strlcpy = 0x40000524;
strlwr = 0x40000528;
strncasecmp = 0x4000052c;
strncat = 0x40000530;
strndup = 0x40000534;
strnlen = 0x40000538;
strrchr = 0x4000053c;
strsep = 0x40000540;
strspn = 0x40000544;
strtok_r = 0x40000548;
strupr = 0x4000054c;
longjmp = 0x40000550;
setjmp = 0x40000554;
abs = 0x40000558;
div = 0x4000055c;
labs = 0x40000560;
ldiv = 0x40000564;
qsort = 0x40000568;
rand_r = 0x4000056c;
rand = 0x40000570;
srand = 0x40000574;
utoa = 0x40000578;
itoa = 0x4000057c;
atoi = 0x40000580;
atol = 0x40000584;
strtol = 0x40000588;
strtoul = 0x4000058c;
fflush = 0x40000590;
_fflush_r = 0x40000594;
_fwalk = 0x40000598;
_fwalk_reent = 0x4000059c;
__smakebuf_r = 0x400005a0;
__swhatbuf_r = 0x400005a4;
__swbuf_r = 0x400005a8;
__swbuf = 0x400005ac;
__swsetup_r = 0x400005b0;
_strtod_l = 0x400005b4;
_strtod_r = 0x400005b8;
strtod_l = 0x400005bc;
strtod = 0x400005c0;
strtof_l = 0x400005c4;
strtof = 0x400005c8;
_strtol_r = 0x400005cc;
strtol_l = 0x400005d0;
_strtoul_r = 0x400005d4;
strtoul_l = 0x400005d8;
__match = 0x400005dc;
__hexnan = 0x400005e0;
__hexdig_fun = 0x400005e4;
__gethex = 0x400005e8;
_Balloc = 0x400005ec;
_Bfree = 0x400005f0;
__multadd = 0x400005f4;
__s2b = 0x400005f8;
__hi0bits = 0x400005fc;
__lo0bits = 0x40000600;
__i2b = 0x40000604;
__multiply = 0x40000608;
__pow5mult = 0x4000060c;
__lshift = 0x40000610;
__mcmp = 0x40000614;
__mdiff = 0x40000618;
__ulp = 0x4000061c;
__b2d = 0x40000620;
__d2b = 0x40000624;
__ratio = 0x40000628;
_mprec_log10 = 0x4000062c;
__copybits = 0x40000630;
__any_on = 0x40000634;
asctime = 0x40000638;
asctime_r = 0x4000063c;
atof = 0x40000640;
atoff = 0x40000644;
_dtoa_r = 0x40000648;
_wctomb_r = 0x4000064c;
__ascii_wctomb = 0x40000650;
_mbtowc_r = 0x40000654;
__ascii_mbtowc = 0x40000658;
puts = 0x4000065c;
putc = 0x40000660;
putchar = 0x40000664;
nan = 0x40000668;
nanf = 0x4000066c;
__errno = 0x40000670;
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffd8;
_global_impure_ptr = 0x3fcdffd4;

14
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld Normal file
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@ -0,0 +1,14 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32h2
*
* These addresses should be compatible with any ROM version for this chip.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_rom_chip_id = 0x40000010;
_rom_eco_version = 0x40000014;

26
components/esp_system/port/soc/esp32h2/system_internal.c
View File

@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "sdkconfig.h"
@ -95,7 +87,15 @@ void IRAM_ATTR esp_restart_noos(void)
// Reset timer/spi/uart
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG,
SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST |
SYSTEM_BT_RST | SYSTEM_BTMAC_RST |
SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST
);
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0);
// Reset dma
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);

2
components/esptool_py/Kconfig.projbuild
View File

@ -2,7 +2,9 @@ menu "Serial flasher config"
config ESPTOOLPY_NO_STUB
bool "Disable download stub"
default "y" if IDF_TARGET_ESP32H2 && IDF_ENV_FPGA # TODO: IDF-4288
default "n"
help
The flasher tool sends a precompiled download stub first by default. That stub allows things
like compressed downloads and more. Usually you should not need to disable that feature

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit 2b3221f9f24bacd982e025dc67f25dea956366bf
Subproject commit 6b582c2b92d3c079098e0e296df03ff6cffeecf5

8
components/esptool_py/project_include.cmake
View File

@ -6,6 +6,14 @@ idf_build_get_property(python PYTHON)
idf_build_get_property(idf_path IDF_PATH)
set(chip_model ${target})
# TODO: remove this if block when esp32h2 beta1 is no longer supported
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
set(chip_model esp32h2beta1)
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
set(chip_model esp32h2beta2)
endif()
endif()
set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model})
set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py")

18
components/hal/esp32h2/include/hal/i2c_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for I2C register operations

21
components/hal/esp32h2/include/hal/rwdt_ll.h
View File

@ -1,19 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

18
components/hal/esp32h2/include/hal/systimer_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>

18
components/hal/esp32h2/include/hal/uart_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.

13
components/soc/esp32h2/CMakeLists.txt
View File

@ -16,4 +16,15 @@ set(srcs
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
set(inc_path "." "include")
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
list(APPEND inc_path "include/rev1")
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
list(APPEND inc_path "include/rev2")
endif()
endif()
target_include_directories(${COMPONENT_LIB} PUBLIC ${inc_path})

18
components/soc/esp32h2/gpio_periph.c
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"

20
components/soc/esp32h2/include/soc/assist_debug_reg.h → components/soc/esp32h2/include/rev1/soc/assist_debug_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ASSIST_DEBUG_REG_H_
#define _SOC_ASSIST_DEBUG_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */

30
components/soc/esp32h2/include/soc/clkrst_reg.h → components/soc/esp32h2/include/rev1/soc/clkrst_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_CLKRST_REG_H_
#define _SOC_CLKRST_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0000)
/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h3 ; */
/*description: */
@ -417,12 +409,12 @@ extern "C" {
#define SYSTEM_MSPI_DIV_NUM_M ((SYSTEM_MSPI_DIV_NUM_V)<<(SYSTEM_MSPI_DIV_NUM_S))
#define SYSTEM_MSPI_DIV_NUM_V 0xFF
#define SYSTEM_MSPI_DIV_NUM_S 24
/* SYSTEM_CAN_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
/* SYSTEM_TWAI_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
/*description: */
#define SYSTEM_CAN_DIV_NUM 0x000000FF
#define SYSTEM_CAN_DIV_NUM_M ((SYSTEM_CAN_DIV_NUM_V)<<(SYSTEM_CAN_DIV_NUM_S))
#define SYSTEM_CAN_DIV_NUM_V 0xFF
#define SYSTEM_CAN_DIV_NUM_S 16
#define SYSTEM_TWAI_DIV_NUM 0x000000FF
#define SYSTEM_TWAI_DIV_NUM_M ((SYSTEM_TWAI_DIV_NUM_V)<<(SYSTEM_TWAI_DIV_NUM_S))
#define SYSTEM_TWAI_DIV_NUM_V 0xFF
#define SYSTEM_TWAI_DIV_NUM_S 16
/* SYSTEM_USB_DEVICE_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
/*description: */
#define SYSTEM_USB_DEVICE_DIV_NUM 0x000000FF

20
components/soc/esp32h2/include/soc/efuse_reg.h → components/soc/esp32h2/include/rev1/soc/efuse_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_REG_H_
#define _SOC_EFUSE_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000)
/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Disable programming of individual eFuses.*/

24
components/soc/esp32h2/include/soc/efuse_struct.h → components/soc/esp32h2/include/rev1/soc/efuse_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#ifdef __cplusplus
@ -29,7 +21,7 @@ typedef volatile struct efuse_dev_s {
uint32_t dis_usb_device: 1; /*Set this bit to disable usb device.*/
uint32_t dis_force_download: 1; /*Set this bit to disable the function that forces chip into download mode.*/
uint32_t dis_usb: 1; /*Set this bit to disable USB function.*/
uint32_t dis_can: 1; /*Set this bit to disable CAN function.*/
uint32_t dis_twai: 1; /*Set this bit to disable TWAI function.*/
uint32_t jtag_sel_enable: 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
uint32_t soft_dis_jtag: 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/
uint32_t dis_pad_jtag: 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
@ -113,7 +105,7 @@ typedef volatile struct efuse_dev_s {
uint32_t dis_usb_device: 1; /*The value of DIS_USB_DEVICE.*/
uint32_t dis_force_download: 1; /*The value of DIS_FORCE_DOWNLOAD.*/
uint32_t dis_usb: 1; /*The value of DIS_USB.*/
uint32_t dis_can: 1; /*The value of DIS_CAN.*/
uint32_t dis_twai: 1; /*The value of DIS_TWAI.*/
uint32_t jtag_sel_enable: 1; /*The value of JTAG_SEL_ENABLE.*/
uint32_t soft_dis_jtag: 3; /*The value of SOFT_DIS_JTAG.*/
uint32_t dis_pad_jtag: 1; /*The value of DIS_PAD_JTAG.*/
@ -281,7 +273,7 @@ typedef volatile struct efuse_dev_s {
uint32_t dis_usb_device_err: 1; /*If DIS_USB_DEVICE is 1 then it indicates a programming error.*/
uint32_t dis_force_download_err: 1; /*If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/
uint32_t dis_usb_err: 1; /*If DIS_USB is 1 then it indicates a programming error.*/
uint32_t dis_can_err: 1; /*If DIS_CAN is 1 then it indicates a programming error.*/
uint32_t dis_twai_err: 1; /*If DIS_TWAI is 1 then it indicates a programming error.*/
uint32_t jtag_sel_enable_err: 1; /*If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/
uint32_t soft_dis_jtag_err: 3; /*If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/
uint32_t dis_pad_jtag_err: 1; /*If DIS_PAD_JTAG is 1 then it indicates a programming error.*/

20
components/soc/esp32h2/include/soc/gpio_reg.h → components/soc/esp32h2/include/rev1/soc/gpio_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_REG_H_
#define _SOC_GPIO_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_PIN_CONFIG_MSB 12
#define GPIO_PIN_CONFIG_LSB 11
#define GPIO_PIN_CONFIG_MASK 0x00001800

20
components/soc/esp32h2/include/soc/gpio_sd_reg.h → components/soc/esp32h2/include/rev1/soc/gpio_sd_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */

18
components/soc/esp32h2/include/soc/gpio_sig_map.h → components/soc/esp32h2/include/rev1/soc/gpio_sig_map.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_

32
components/soc/esp32h2/include/soc/interrupt_core0_reg.h → components/soc/esp32h2/include/rev1/soc/interrupt_core0_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
@ -222,13 +214,13 @@ extern "C" {
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CAN_INT_MAP_S 0
#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TWAI_INT_MAP_M ((INTERRUPT_CORE0_TWAI_INT_MAP_V)<<(INTERRUPT_CORE0_TWAI_INT_MAP_S))
#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */

20
components/soc/esp32h2/include/soc/io_mux_reg.h → components/soc/esp32h2/include/rev1/soc/io_mux_reg.h
View File

@ -1,20 +1,12 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#include "soc.h"
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */

20
components/soc/esp32h2/include/soc/rtc_cntl_reg.h → components/soc/esp32h2/include/rev1/soc/rtc_cntl_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_CNTL_REG_H_
#define _SOC_RTC_CNTL_REG_H_
@ -29,11 +21,11 @@
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG

18
components/soc/esp32h2/include/soc/rtc_cntl_struct.h → components/soc/esp32h2/include/rev1/soc/rtc_cntl_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus

50
components/soc/esp32h2/include/soc/sensitive_reg.h → components/soc/esp32h2/include/rev1/soc/sensitive_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENSITIVE_REG_H_
#define _SOC_SENSITIVE_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000)
/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
@ -1472,12 +1464,12 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003
@ -1752,12 +1744,12 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003
@ -2344,12 +2336,12 @@ extern "C" {
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S 10
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S 10
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003

26
components/soc/esp32h2/include/soc/sensitive_struct.h → components/soc/esp32h2/include/rev1/soc/sensitive_struct.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENSITIVE_STRUCT_H_
#define _SOC_SENSITIVE_STRUCT_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct sensitive_dev_s {
union {
@ -659,7 +651,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved2 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl: 2; /*core_0_pif_pms_constrain_world_0_apb_ctrl*/
uint32_t reserved6 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_0_can: 2; /*core_0_pif_pms_constrain_world_0_can*/
uint32_t reg_core_0_pif_pms_constrain_world_0_twai: 2; /*core_0_pif_pms_constrain_world_0_twai*/
uint32_t reserved12 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1: 2; /*core_0_pif_pms_constrain_world_0_i2s1*/
uint32_t reserved16 : 6;
@ -753,7 +745,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved2: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2;
uint32_t reserved6: 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_twai: 2;
uint32_t reserved12: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2;
uint32_t reserved16: 6;
@ -1006,7 +998,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved2 : 2;
uint32_t reg_backup_bus_pms_constrain_apb_ctrl: 2; /*backup_bus_pms_constrain_apb_ctrl*/
uint32_t reserved6 : 4;
uint32_t reg_backup_bus_pms_constrain_can: 2; /*backup_bus_pms_constrain_can*/
uint32_t reg_backup_bus_pms_constrain_twai: 2; /*backup_bus_pms_constrain_twai*/
uint32_t reserved12 : 2;
uint32_t reg_backup_bus_pms_constrain_i2s1: 2; /*backup_bus_pms_constrain_i2s1*/
uint32_t reserved16 : 6;

5
components/soc/esp32h2/include/soc/soc_caps.h → components/soc/esp32h2/include/rev1/soc/soc_caps.h
View File

@ -1,3 +1,8 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and

20
components/soc/esp32h2/include/soc/syscon_reg.h → components/soc/esp32h2/include/rev1/soc/syscon_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */

18
components/soc/esp32h2/include/soc/syscon_struct.h → components/soc/esp32h2/include/rev1/soc/syscon_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
#ifdef __cplusplus

22
components/soc/esp32h2/include/soc/system_reg.h → components/soc/esp32h2/include/rev1/soc/system_reg.h
View File

@ -1,25 +1,17 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSTEM_REG_H_
#define _SOC_SYSTEM_REG_H_
#include "soc/soc.h"
#include "soc/clkrst_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#include "clkrst_reg.h"
#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000)
/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */

20
components/soc/esp32h2/include/soc/system_struct.h → components/soc/esp32h2/include/rev1/soc/system_struct.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSTEM_STRUCT_H_
#define _SOC_SYSTEM_STRUCT_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct system_dev_s {
union {

7
components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h → components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h
View File

@ -1,6 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
* SPDX-License-Identifier: Apache-2.0
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

20
components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h → components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_struct.h
View File

@ -1,24 +1,16 @@
// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct usb_serial_jtag_dev_s {
union {

896
components/soc/esp32h2/include/rev2/soc/assist_debug_reg.h Normal file
View File

@ -0,0 +1,896 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W; bitpos: [2]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W; bitpos: [4]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W; bitpos: [5]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W; bitpos: [6]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W; bitpos: [7]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W; bitpos: [8]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W; bitpos: [9]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [10]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [11]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : RW; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW; bitpos: [0]; default: 0;
* enable recording function, if enable, assist_debug will update PdebugPC, so you can
* read it
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW; bitpos: [1]; default: 0;
* enable CPU Pdebug function, if enable, CPU will update PdebugPC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
/** ASSIST_DEBUG_LOG_SETTING_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/** ASSIST_DEBUG_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_ENA 0x00000007U
#define ASSIST_DEBUG_LOG_ENA_M (ASSIST_DEBUG_LOG_ENA_V << ASSIST_DEBUG_LOG_ENA_S)
#define ASSIST_DEBUG_LOG_ENA_V 0x00000007U
#define ASSIST_DEBUG_LOG_ENA_S 0
/** ASSIST_DEBUG_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MODE 0x0000000FU
#define ASSIST_DEBUG_LOG_MODE_M (ASSIST_DEBUG_LOG_MODE_V << ASSIST_DEBUG_LOG_MODE_S)
#define ASSIST_DEBUG_LOG_MODE_V 0x0000000FU
#define ASSIST_DEBUG_LOG_MODE_S 3
/** ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7))
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V << ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S)
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7
/** ASSIST_DEBUG_LOG_DATA_0_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/** ASSIST_DEBUG_LOG_DATA_0 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_DATA_0_M (ASSIST_DEBUG_LOG_DATA_0_V << ASSIST_DEBUG_LOG_DATA_0_S)
#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_DATA_0_S 0
/** ASSIST_DEBUG_LOG_DATA_MASK_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
/** ASSIST_DEBUG_LOG_DATA_SIZE : R/W; bitpos: [15:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFFU
#define ASSIST_DEBUG_LOG_DATA_SIZE_M (ASSIST_DEBUG_LOG_DATA_SIZE_V << ASSIST_DEBUG_LOG_DATA_SIZE_S)
#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0x0000FFFFU
#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0
/** ASSIST_DEBUG_LOG_MIN_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c)
/** ASSIST_DEBUG_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MIN_M (ASSIST_DEBUG_LOG_MIN_V << ASSIST_DEBUG_LOG_MIN_S)
#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MIN_S 0
/** ASSIST_DEBUG_LOG_MAX_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
/** ASSIST_DEBUG_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MAX_M (ASSIST_DEBUG_LOG_MAX_V << ASSIST_DEBUG_LOG_MAX_S)
#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MAX_S 0
/** ASSIST_DEBUG_LOG_MEM_START_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
/** ASSIST_DEBUG_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MEM_START_M (ASSIST_DEBUG_LOG_MEM_START_V << ASSIST_DEBUG_LOG_MEM_START_S)
#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MEM_START_S 0
/** ASSIST_DEBUG_LOG_MEM_END_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
/** ASSIST_DEBUG_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MEM_END_M (ASSIST_DEBUG_LOG_MEM_END_V << ASSIST_DEBUG_LOG_MEM_END_S)
#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MEM_END_S 0
/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M (ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V << ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFFU
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0
/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG register
* register description
*/
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0))
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S)
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x00000001U
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
/** ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S)
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* register description
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* Need add description
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_DATE_REG register
* register description
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 33587216;
* Need add description
*/
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* Add later.
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* Add later.
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* Add later.
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* Add later.
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* Add later.
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Add later.
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* Add later.
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Add later.
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* Add later.
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Add later.
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Add later.
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* Add later.
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
* Add later.
*/
#define ECC_MULT_SECURITY_MODE (BIT(3))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 3
/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
* Add later.
*/
#define ECC_MULT_CLK_EN (BIT(4))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [6:5]; default: 0;
* Add later.
*/
#define ECC_MULT_WORK_MODE 0x00000003U
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x00000003U
#define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [7]; default: 0;
* Add later.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(7))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 7
/** ECC_MULT_DATE_REG register
* Add later.
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 33628720;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt registers */
/** Type of int_raw register
* Add later.
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* Add later.
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* Add later.
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* Add later.
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* Add later.
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Add later.
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* Add later.
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Add later.
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* Add later.
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Add later.
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Add later.
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0;
* Add later.
*/
uint32_t key_length:1;
/** security_mode : R/W; bitpos: [3]; default: 0;
* Add later.
*/
uint32_t security_mode:1;
/** clk_en : R/W; bitpos: [4]; default: 0;
* Add later.
*/
uint32_t clk_en:1;
/** work_mode : R/W; bitpos: [6:5]; default: 0;
* Add later.
*/
uint32_t work_mode:2;
/** verification_result : RO/SS; bitpos: [7]; default: 0;
* Add later.
*/
uint32_t verification_result:1;
uint32_t reserved_8:24;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of date register
* Add later.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 33628720;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
} ecc_mult_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x100, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** GPIO_SD_SIGMADELTA0_REG register
* Duty Cycle Configure Register of SDM0
*/
#define GPIO_SD_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD_SD0_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD_SD0_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA1_REG register
* Duty Cycle Configure Register of SDM1
*/
#define GPIO_SD_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD_SD0_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD_SD0_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA2_REG register
* Duty Cycle Configure Register of SDM2
*/
#define GPIO_SD_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD_SD0_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD_SD0_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA3_REG register
* Duty Cycle Configure Register of SDM3
*/
#define GPIO_SD_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xc)
/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
#define GPIO_SD_SD0_IN 0x000000FFU
#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
#define GPIO_SD_SD0_IN_V 0x000000FFU
#define GPIO_SD_SD0_IN_S 0
/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
#define GPIO_SD_SD0_PRESCALE 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU
#define GPIO_SD_SD0_PRESCALE_S 8
/** GPIO_SD_SIGMADELTA_CG_REG register
* Clock Gating Configure Register
*/
#define GPIO_SD_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
/** GPIO_SD_CLK_EN : R/W; bitpos: [31]; default: 0;
* Clock enable bit of configuration registers for sigma delta modulation.
*/
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (GPIO_SD_CLK_EN_V << GPIO_SD_CLK_EN_S)
#define GPIO_SD_CLK_EN_V 0x00000001U
#define GPIO_SD_CLK_EN_S 31
/** GPIO_SD_SIGMADELTA_MISC_REG register
* MISC Register
*/
#define GPIO_SD_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
/** GPIO_SD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
#define GPIO_SD_FUNCTION_CLK_EN (BIT(30))
#define GPIO_SD_FUNCTION_CLK_EN_M (GPIO_SD_FUNCTION_CLK_EN_V << GPIO_SD_FUNCTION_CLK_EN_S)
#define GPIO_SD_FUNCTION_CLK_EN_V 0x00000001U
#define GPIO_SD_FUNCTION_CLK_EN_S 30
/** GPIO_SD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
#define GPIO_SD_SPI_SWAP (BIT(31))
#define GPIO_SD_SPI_SWAP_M (GPIO_SD_SPI_SWAP_V << GPIO_SD_SPI_SWAP_S)
#define GPIO_SD_SPI_SWAP_V 0x00000001U
#define GPIO_SD_SPI_SWAP_S 31
/** GPIO_SD_PAD_COMP_CONFIG_REG register
* PAD Compare configure Register
*/
#define GPIO_SD_PAD_COMP_CONFIG_REG (DR_REG_GPIO_SD_BASE + 0x28)
/** GPIO_SD_XPD_COMP : R/W; bitpos: [0]; default: 0;
* Pad compare enable bit.
*/
#define GPIO_SD_XPD_COMP (BIT(0))
#define GPIO_SD_XPD_COMP_M (GPIO_SD_XPD_COMP_V << GPIO_SD_XPD_COMP_S)
#define GPIO_SD_XPD_COMP_V 0x00000001U
#define GPIO_SD_XPD_COMP_S 0
/** GPIO_SD_MODE_COMP : R/W; bitpos: [1]; default: 0;
* 1 to enable external reference from PAD[0]. 0 to enable internal reference,
* meanwhile PAD[0] can be used as a regular GPIO.
*/
#define GPIO_SD_MODE_COMP (BIT(1))
#define GPIO_SD_MODE_COMP_M (GPIO_SD_MODE_COMP_V << GPIO_SD_MODE_COMP_S)
#define GPIO_SD_MODE_COMP_V 0x00000001U
#define GPIO_SD_MODE_COMP_S 1
/** GPIO_SD_DREF_COMP : R/W; bitpos: [4:2]; default: 0;
* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
*/
#define GPIO_SD_DREF_COMP 0x00000007U
#define GPIO_SD_DREF_COMP_M (GPIO_SD_DREF_COMP_V << GPIO_SD_DREF_COMP_S)
#define GPIO_SD_DREF_COMP_V 0x00000007U
#define GPIO_SD_DREF_COMP_S 2
/** GPIO_SD_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0;
* Zero Detect mode select.
*/
#define GPIO_SD_ZERO_DET_MODE 0x00000003U
#define GPIO_SD_ZERO_DET_MODE_M (GPIO_SD_ZERO_DET_MODE_V << GPIO_SD_ZERO_DET_MODE_S)
#define GPIO_SD_ZERO_DET_MODE_V 0x00000003U
#define GPIO_SD_ZERO_DET_MODE_S 5
/** GPIO_SD_PAD_COMP_FILTER_REG register
* Zero Detect filter Register
*/
#define GPIO_SD_PAD_COMP_FILTER_REG (DR_REG_GPIO_SD_BASE + 0x2c)
/** GPIO_SD_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0;
* Zero Detect filter cycle length
*/
#define GPIO_SD_ZERO_DET_FILTER_CNT 0xFFFFFFFFU
#define GPIO_SD_ZERO_DET_FILTER_CNT_M (GPIO_SD_ZERO_DET_FILTER_CNT_V << GPIO_SD_ZERO_DET_FILTER_CNT_S)
#define GPIO_SD_ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU
#define GPIO_SD_ZERO_DET_FILTER_CNT_S 0
/** GPIO_SD_INT_RAW_REG register
* GPIO_SD interrupt raw register
*/
#define GPIO_SD_INT_RAW_REG (DR_REG_GPIO_SD_BASE + 0x80)
/** GPIO_SD_PAD_COMP_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* Pad compare raw interrupt
*/
#define GPIO_SD_PAD_COMP_INT_RAW (BIT(0))
#define GPIO_SD_PAD_COMP_INT_RAW_M (GPIO_SD_PAD_COMP_INT_RAW_V << GPIO_SD_PAD_COMP_INT_RAW_S)
#define GPIO_SD_PAD_COMP_INT_RAW_V 0x00000001U
#define GPIO_SD_PAD_COMP_INT_RAW_S 0
/** GPIO_SD_INT_ST_REG register
* GPIO_SD interrupt masked register
*/
#define GPIO_SD_INT_ST_REG (DR_REG_GPIO_SD_BASE + 0x84)
/** GPIO_SD_PAD_COMP_INT_ST : RO; bitpos: [0]; default: 0;
* Pad compare masked interrupt
*/
#define GPIO_SD_PAD_COMP_INT_ST (BIT(0))
#define GPIO_SD_PAD_COMP_INT_ST_M (GPIO_SD_PAD_COMP_INT_ST_V << GPIO_SD_PAD_COMP_INT_ST_S)
#define GPIO_SD_PAD_COMP_INT_ST_V 0x00000001U
#define GPIO_SD_PAD_COMP_INT_ST_S 0
/** GPIO_SD_INT_ENA_REG register
* GPIO_SD interrupt enable register
*/
#define GPIO_SD_INT_ENA_REG (DR_REG_GPIO_SD_BASE + 0x88)
/** GPIO_SD_PAD_COMP_INT_ENA : R/W; bitpos: [0]; default: 0;
* Pad compare interrupt enable
*/
#define GPIO_SD_PAD_COMP_INT_ENA (BIT(0))
#define GPIO_SD_PAD_COMP_INT_ENA_M (GPIO_SD_PAD_COMP_INT_ENA_V << GPIO_SD_PAD_COMP_INT_ENA_S)
#define GPIO_SD_PAD_COMP_INT_ENA_V 0x00000001U
#define GPIO_SD_PAD_COMP_INT_ENA_S 0
/** GPIO_SD_INT_CLR_REG register
* GPIO_SD interrupt clear register
*/
#define GPIO_SD_INT_CLR_REG (DR_REG_GPIO_SD_BASE + 0x8c)
/** GPIO_SD_PAD_COMP_INT_CLR : WT; bitpos: [0]; default: 0;
* Pad compare interrupt clear
*/
#define GPIO_SD_PAD_COMP_INT_CLR (BIT(0))
#define GPIO_SD_PAD_COMP_INT_CLR_M (GPIO_SD_PAD_COMP_INT_CLR_V << GPIO_SD_PAD_COMP_INT_CLR_S)
#define GPIO_SD_PAD_COMP_INT_CLR_V 0x00000001U
#define GPIO_SD_PAD_COMP_INT_CLR_S 0
/** GPIO_SD_SIGMADELTA_VERSION_REG register
* Version Control Register
*/
#define GPIO_SD_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0xfc)
/** GPIO_SD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 34668848;
* Version control register.
*/
#define GPIO_SD_GPIO_SD_DATE 0x0FFFFFFFU
#define GPIO_SD_GPIO_SD_DATE_M (GPIO_SD_GPIO_SD_DATE_V << GPIO_SD_GPIO_SD_DATE_S)
#define GPIO_SD_GPIO_SD_DATE_V 0x0FFFFFFFU
#define GPIO_SD_GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_IDX 4
#define SPICS0_OUT_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define I2S_MCLK_IN_IDX 12
#define I2S_MCLK_OUT_IDX 12
#define I2SO_BCK_IN_IDX 13
#define I2SO_BCK_OUT_IDX 13
#define I2SO_WS_IN_IDX 14
#define I2SO_WS_OUT_IDX 14
#define I2SI_SD_IN_IDX 15
#define I2SO_SD_OUT_IDX 15
#define I2SI_BCK_IN_IDX 16
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define I2SO_SD1_OUT_IDX 18
#define CPU_TESTBUS0_IDX 20
#define CPU_TESTBUS1_IDX 21
#define CPU_TESTBUS2_IDX 22
#define CPU_TESTBUS3_IDX 23
#define CPU_TESTBUS4_IDX 24
#define CPU_TESTBUS5_IDX 25
#define CPU_TESTBUS6_IDX 26
#define CPU_TESTBUS7_IDX 27
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_IDX 36
#define USB_JTAG_TMS_IDX 37
#define USB_JTAG_TDI_IDX 38
#define USB_JTAG_TDO_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
#define USB_EXTPHY_SPEED_IDX 41
#define USB_EXTPHY_RCV_IDX 42
#define USB_EXTPHY_VPO_IDX 42
#define USB_EXTPHY_VMO_IDX 43
#define USB_EXTPHY_SUSPND_IDX 44
#define EXT_ADC_START_IDX 45
#define LEDC_LS_SIG_OUT0_IDX 45
#define LEDC_LS_SIG_OUT1_IDX 46
#define LEDC_LS_SIG_OUT2_IDX 47
#define LEDC_LS_SIG_OUT3_IDX 48
#define LEDC_LS_SIG_OUT4_IDX 49
#define LEDC_LS_SIG_OUT5_IDX 50
#define RMT_SIG_IN0_IDX 51
#define RMT_SIG_OUT0_IDX 51
#define RMT_SIG_IN1_IDX 52
#define RMT_SIG_OUT1_IDX 52
#define I2CEXT0_SCL_IN_IDX 53
#define I2CEXT0_SCL_OUT_IDX 53
#define I2CEXT0_SDA_IN_IDX 54
#define I2CEXT0_SDA_OUT_IDX 54
#define GPIO_SD0_OUT_IDX 55
#define GPIO_SD1_OUT_IDX 56
#define GPIO_SD2_OUT_IDX 57
#define GPIO_SD3_OUT_IDX 58
#define EVENT_MATRIX_IN0_IDX 59
#define TASK_MATRIX_OUT0_IDX 59
#define EVENT_MATRIX_IN1_IDX 60
#define TASK_MATRIX_OUT1_IDX 60
#define EVENT_MATRIX_IN2_IDX 61
#define TASK_MATRIX_OUT2_IDX 61
#define EVENT_MATRIX_IN3_IDX 62
#define TASK_MATRIX_OUT3_IDX 62
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_IDX 63
#define FSPIQ_IN_IDX 64
#define FSPIQ_OUT_IDX 64
#define FSPID_IN_IDX 65
#define FSPID_OUT_IDX 65
#define FSPIHD_IN_IDX 66
#define FSPIHD_OUT_IDX 66
#define FSPIWP_IN_IDX 67
#define FSPIWP_OUT_IDX 67
#define FSPICS0_IN_IDX 68
#define FSPICS0_OUT_IDX 68
#define FSPICS1_OUT_IDX 69
#define FSPICS2_OUT_IDX 70
#define FSPICS3_OUT_IDX 71
#define FSPICS4_OUT_IDX 72
#define FSPICS5_OUT_IDX 73
#define TWAI_RX_IDX 74
#define TWAI_TX_IDX 74
#define TWAI_BUS_OFF_ON_IDX 75
#define TWAI_CLKOUT_IDX 76
#define PCMFSYNC_IN_IDX 77
#define PCMFSYNC_OUT_IDX 77
#define PCMCLK_IN_IDX 78
#define PCMCLK_OUT_IDX 78
#define PCMDIN_IDX 79
#define PCMDOUT_IDX 79
#define CO_EXT_PRIORITY_IN_IDX 80
#define CO_EXT_PRIORITY_OUT_IDX 80
#define CO_EXT_ACTIVE_IN_IDX 81
#define CO_EXT_ACTIVE_OUT_IDX 81
#define MODEM_COEX_GRANT1_IDX 87
#define MODEM_COEX_GRANT2_IDX 88
#define ANT_SEL0_IDX 89
#define ANT_SEL1_IDX 90
#define ANT_SEL2_IDX 91
#define ANT_SEL3_IDX 92
#define ANT_SEL4_IDX 93
#define ANT_SEL5_IDX 94
#define ANT_SEL6_IDX 95
#define ANT_SEL7_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define SYNCERR_IDX 101
#define SYNC_FOUND_IDX 102
#define CH_IDX_IDX 103
#define SYNC_WINDOW_IDX 104
#define DATA_EN_IDX 105
#define DATA_IDX 106
#define PKT_TX_ON_IDX 107
#define PKT_RX_ON_IDX 108
#define TXRU_ON_IDX 109
#define RXRU_ON_IDX 110
#define LELC_ST3_IDX 111
#define LELC_ST2_IDX 112
#define LELC_ST1_IDX 113
#define LELC_ST0_IDX 114
#define CRCOK_IDX 115
#define CLK_GPIO_IDX 116
#define RADIO_START_IDX 117
#define SEQUENCE_ON_IDX 118
#define PUMP_CLK_IDX 119
#define PUMP_XPD_IDX 120
#define PUMP_DRV1_IDX 121
#define PUMP_DRV0_IDX 122
#define CLK_OUT_OUT1_IDX 123
#define CLK_OUT_OUT2_IDX 124
#define CLK_OUT_OUT3_IDX 125
#define SPICS1_OUT_IDX 126
#define USB_JTAG_TRST_IDX 127
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2109090
#endif /* _SOC_GPIO_SIG_MAP_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_VDD_SPI_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define SPI_HD_GPIO_NUM 16
#define SPI_WP_GPIO_NUM 15
#define SPI_CS0_GPIO_NUM 13
#define SPI_CLK_GPIO_NUM 17
#define SPI_D_GPIO_NUM 18
#define SPI_Q_GPIO_NUM 14
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 20
#define MAX_GPIO_NUM 24
#define DIG_IO_HOLD_BIT_SHIFT 0
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4)
#define FUNC_GPIO0_FSPIQ 2
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x8)
#define FUNC_GPIO1_FSPICS0 2
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xC)
#define FUNC_MTMS_FSPIWP 2
#define FUNC_MTMS_GPIO2 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x10)
#define FUNC_MTDO_FSPIHD 2
#define FUNC_MTDO_GPIO3 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14)
#define FUNC_MTCK_FSPICLK 2
#define FUNC_MTCK_GPIO4 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
#define FUNC_MTDI_FSPID 2
#define FUNC_MTDI_GPIO5 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x2C)
#define FUNC_XTAL_32K_P_GPIO10 1
#define FUNC_XTAL_32K_P_GPIO10_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x30)
#define FUNC_XTAL_32K_N_GPIO11 1
#define FUNC_XTAL_32K_N_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x38)
#define FUNC_SPICS0_GPIO13 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x3C)
#define FUNC_SPIQ_GPIO14 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x40)
#define FUNC_SPIWP_GPIO15 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x44)
#define FUNC_SPIHD_GPIO16 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x48)
#define FUNC_SPICLK_GPIO17 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x4C)
#define FUNC_SPID_GPIO18 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x50)
#define FUNC_VDD_SPI_GPIO19 1
#define FUNC_VDD_SPI_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE + 0x54)
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x58)
#define FUNC_U0RXD_GPIO21 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x5C)
#define FUNC_U0TXD_GPIO22 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x64)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE + 0x68)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
/** IO_MUX_DATE_REG register
* IO MUX Version Control Register
*/
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 0x2109090;
* Version control register
*/
#define IO_MUX_DATE 0x0FFFFFFF
#define IO_MUX_DATE_M (IO_MUX_DATE_V << IO_MUX_DATE_S)
#define IO_MUX_DATE_V 0x0FFFFFFFU
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x2109090

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CPU_CORES_NUM 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_AES_GDMA (1)
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- ADC CAPS -------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (26)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_AUTO_ENABLE (1) /*!< The dedicated GPIO peripheral is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_CODEC (1)
#define SOC_I2S_SUPPORTS_TDM (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
/*-------------------------- MPU CAPS ----------------------------------------*/
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
/*-------------------------- RTC CAPS --------------------------------------*/
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-H2 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_BT_PD (1)

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SYSCON_WIFI_BB_CFG_REG register
* register description
*/
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xc)
/** SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFFU
#define SYSCON_WIFI_BB_CFG_M (SYSCON_WIFI_BB_CFG_V << SYSCON_WIFI_BB_CFG_S)
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU
#define SYSCON_WIFI_BB_CFG_S 0
/** SYSCON_WIFI_BB_CFG_2_REG register
* register description
*/
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
/** SYSCON_WIFI_BB_CFG_2 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFFU
#define SYSCON_WIFI_BB_CFG_2_M (SYSCON_WIFI_BB_CFG_2_V << SYSCON_WIFI_BB_CFG_2_S)
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFFU
#define SYSCON_WIFI_BB_CFG_2_S 0
/** SYSCON_HOST_INF_SEL_REG register
* register description
*/
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1c)
/** SYSCON_PERI_IO_SWAP : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_IO_SWAP 0x000000FFU
#define SYSCON_PERI_IO_SWAP_M (SYSCON_PERI_IO_SWAP_V << SYSCON_PERI_IO_SWAP_S)
#define SYSCON_PERI_IO_SWAP_V 0x000000FFU
#define SYSCON_PERI_IO_SWAP_S 0
/** SYSCON_EXT_MEM_PMS_LOCK_REG register
* register description
*/
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
/** SYSCON_EXT_MEM_PMS_LOCK : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_M (SYSCON_EXT_MEM_PMS_LOCK_V << SYSCON_EXT_MEM_PMS_LOCK_S)
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x00000001U
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
/** SYSCON_FLASH_ACE0_ATTR_REG register
* register description
*/
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
/** SYSCON_FLASH_ACE0_ATTR : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
#define SYSCON_FLASH_ACE0_ATTR 0x00000003U
#define SYSCON_FLASH_ACE0_ATTR_M (SYSCON_FLASH_ACE0_ATTR_V << SYSCON_FLASH_ACE0_ATTR_S)
#define SYSCON_FLASH_ACE0_ATTR_V 0x00000003U
#define SYSCON_FLASH_ACE0_ATTR_S 0
/** SYSCON_FLASH_ACE1_ATTR_REG register
* register description
*/
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2c)
/** SYSCON_FLASH_ACE1_ATTR : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
#define SYSCON_FLASH_ACE1_ATTR 0x00000003U
#define SYSCON_FLASH_ACE1_ATTR_M (SYSCON_FLASH_ACE1_ATTR_V << SYSCON_FLASH_ACE1_ATTR_S)
#define SYSCON_FLASH_ACE1_ATTR_V 0x00000003U
#define SYSCON_FLASH_ACE1_ATTR_S 0
/** SYSCON_FLASH_ACE2_ATTR_REG register
* register description
*/
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
/** SYSCON_FLASH_ACE2_ATTR : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
#define SYSCON_FLASH_ACE2_ATTR 0x00000003U
#define SYSCON_FLASH_ACE2_ATTR_M (SYSCON_FLASH_ACE2_ATTR_V << SYSCON_FLASH_ACE2_ATTR_S)
#define SYSCON_FLASH_ACE2_ATTR_V 0x00000003U
#define SYSCON_FLASH_ACE2_ATTR_S 0
/** SYSCON_FLASH_ACE3_ATTR_REG register
* register description
*/
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
/** SYSCON_FLASH_ACE3_ATTR : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
#define SYSCON_FLASH_ACE3_ATTR 0x00000003U
#define SYSCON_FLASH_ACE3_ATTR_M (SYSCON_FLASH_ACE3_ATTR_V << SYSCON_FLASH_ACE3_ATTR_S)
#define SYSCON_FLASH_ACE3_ATTR_V 0x00000003U
#define SYSCON_FLASH_ACE3_ATTR_S 0
/** SYSCON_FLASH_ACE0_ADDR_REG register
* register description
*/
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
/** SYSCON_FLASH_ACE0_ADDR_S : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFFU
#define SYSCON_FLASH_ACE0_ADDR_S_M (SYSCON_FLASH_ACE0_ADDR_S_V << SYSCON_FLASH_ACE0_ADDR_S_S)
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFFU
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
/** SYSCON_FLASH_ACE1_ADDR_REG register
* register description
*/
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3c)
/** SYSCON_FLASH_ACE1_ADDR_S : R/W; bitpos: [31:0]; default: 4194304;
* Need add description
*/
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFFU
#define SYSCON_FLASH_ACE1_ADDR_S_M (SYSCON_FLASH_ACE1_ADDR_S_V << SYSCON_FLASH_ACE1_ADDR_S_S)
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFFU
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
/** SYSCON_FLASH_ACE2_ADDR_REG register
* register description
*/
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
/** SYSCON_FLASH_ACE2_ADDR_S : R/W; bitpos: [31:0]; default: 8388608;
* Need add description
*/
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFFU
#define SYSCON_FLASH_ACE2_ADDR_S_M (SYSCON_FLASH_ACE2_ADDR_S_V << SYSCON_FLASH_ACE2_ADDR_S_S)
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFFU
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
/** SYSCON_FLASH_ACE3_ADDR_REG register
* register description
*/
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
/** SYSCON_FLASH_ACE3_ADDR_S : R/W; bitpos: [31:0]; default: 12582912;
* Need add description
*/
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFFU
#define SYSCON_FLASH_ACE3_ADDR_S_M (SYSCON_FLASH_ACE3_ADDR_S_V << SYSCON_FLASH_ACE3_ADDR_S_S)
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFFU
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
/** SYSCON_FLASH_ACE0_SIZE_REG register
* register description
*/
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
/** SYSCON_FLASH_ACE0_SIZE : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
#define SYSCON_FLASH_ACE0_SIZE 0x00001FFFU
#define SYSCON_FLASH_ACE0_SIZE_M (SYSCON_FLASH_ACE0_SIZE_V << SYSCON_FLASH_ACE0_SIZE_S)
#define SYSCON_FLASH_ACE0_SIZE_V 0x00001FFFU
#define SYSCON_FLASH_ACE0_SIZE_S 0
/** SYSCON_FLASH_ACE1_SIZE_REG register
* register description
*/
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4c)
/** SYSCON_FLASH_ACE1_SIZE : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
#define SYSCON_FLASH_ACE1_SIZE 0x00001FFFU
#define SYSCON_FLASH_ACE1_SIZE_M (SYSCON_FLASH_ACE1_SIZE_V << SYSCON_FLASH_ACE1_SIZE_S)
#define SYSCON_FLASH_ACE1_SIZE_V 0x00001FFFU
#define SYSCON_FLASH_ACE1_SIZE_S 0
/** SYSCON_FLASH_ACE2_SIZE_REG register
* register description
*/
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
/** SYSCON_FLASH_ACE2_SIZE : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
#define SYSCON_FLASH_ACE2_SIZE 0x00001FFFU
#define SYSCON_FLASH_ACE2_SIZE_M (SYSCON_FLASH_ACE2_SIZE_V << SYSCON_FLASH_ACE2_SIZE_S)
#define SYSCON_FLASH_ACE2_SIZE_V 0x00001FFFU
#define SYSCON_FLASH_ACE2_SIZE_S 0
/** SYSCON_FLASH_ACE3_SIZE_REG register
* register description
*/
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
/** SYSCON_FLASH_ACE3_SIZE : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
#define SYSCON_FLASH_ACE3_SIZE 0x00001FFFU
#define SYSCON_FLASH_ACE3_SIZE_M (SYSCON_FLASH_ACE3_SIZE_V << SYSCON_FLASH_ACE3_SIZE_S)
#define SYSCON_FLASH_ACE3_SIZE_V 0x00001FFFU
#define SYSCON_FLASH_ACE3_SIZE_S 0
/** SYSCON_SPI_MEM_PMS_CTRL_REG register
* register description
*/
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
/** SYSCON_SPI_MEM_REJECT_INT : RO; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_M (SYSCON_SPI_MEM_REJECT_INT_V << SYSCON_SPI_MEM_REJECT_INT_S)
#define SYSCON_SPI_MEM_REJECT_INT_V 0x00000001U
#define SYSCON_SPI_MEM_REJECT_INT_S 0
/** SYSCON_SPI_MEM_REJECT_CLR : WOD; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_M (SYSCON_SPI_MEM_REJECT_CLR_V << SYSCON_SPI_MEM_REJECT_CLR_S)
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x00000001U
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
/** SYSCON_SPI_MEM_REJECT_CDE : RO; bitpos: [6:2]; default: 0;
* Need add description
*/
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001FU
#define SYSCON_SPI_MEM_REJECT_CDE_M (SYSCON_SPI_MEM_REJECT_CDE_V << SYSCON_SPI_MEM_REJECT_CDE_S)
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x0000001FU
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
/** SYSCON_SPI_MEM_REJECT_ADDR_REG register
* register description
*/
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8c)
/** SYSCON_SPI_MEM_REJECT_ADDR : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFFU
#define SYSCON_SPI_MEM_REJECT_ADDR_M (SYSCON_SPI_MEM_REJECT_ADDR_V << SYSCON_SPI_MEM_REJECT_ADDR_S)
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFFU
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
/** SYSCON_SYSCON_SDIO_CTRL_REG register
* register description
*/
#define SYSCON_SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
/** SYSCON_SDIO_WIN_ACCESS_EN : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (SYSCON_SDIO_WIN_ACCESS_EN_V << SYSCON_SDIO_WIN_ACCESS_EN_S)
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
/** SYSCON_REDCY_SIG0_REG register
* register description
*/
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
/** SYSCON_REDCY_SIG0 : R/W; bitpos: [30:0]; default: 0;
* Need add description
*/
#define SYSCON_REDCY_SIG0 0x7FFFFFFFU
#define SYSCON_REDCY_SIG0_M (SYSCON_REDCY_SIG0_V << SYSCON_REDCY_SIG0_S)
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFFU
#define SYSCON_REDCY_SIG0_S 0
/** SYSCON_REDCY_ANDOR : RO; bitpos: [31]; default: 0;
* Need add description
*/
#define SYSCON_REDCY_ANDOR (BIT(31))
#define SYSCON_REDCY_ANDOR_M (SYSCON_REDCY_ANDOR_V << SYSCON_REDCY_ANDOR_S)
#define SYSCON_REDCY_ANDOR_V 0x00000001U
#define SYSCON_REDCY_ANDOR_S 31
/** SYSCON_REDCY_SIG1_REG register
* register description
*/
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
/** SYSCON_REDCY_SIG1 : R/W; bitpos: [30:0]; default: 0;
* Need add description
*/
#define SYSCON_REDCY_SIG1 0x7FFFFFFFU
#define SYSCON_REDCY_SIG1_M (SYSCON_REDCY_SIG1_V << SYSCON_REDCY_SIG1_S)
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFFU
#define SYSCON_REDCY_SIG1_S 0
/** SYSCON_REDCY_NANDOR : RO; bitpos: [31]; default: 0;
* Need add description
*/
#define SYSCON_REDCY_NANDOR (BIT(31))
#define SYSCON_REDCY_NANDOR_M (SYSCON_REDCY_NANDOR_V << SYSCON_REDCY_NANDOR_S)
#define SYSCON_REDCY_NANDOR_V 0x00000001U
#define SYSCON_REDCY_NANDOR_S 31
/** SYSCON_FRONT_END_MEM_PD_REG register
* register description
*/
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9c)
/** SYSCON_AGC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_M (SYSCON_AGC_MEM_FORCE_PU_V << SYSCON_AGC_MEM_FORCE_PU_S)
#define SYSCON_AGC_MEM_FORCE_PU_V 0x00000001U
#define SYSCON_AGC_MEM_FORCE_PU_S 0
/** SYSCON_AGC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_M (SYSCON_AGC_MEM_FORCE_PD_V << SYSCON_AGC_MEM_FORCE_PD_S)
#define SYSCON_AGC_MEM_FORCE_PD_V 0x00000001U
#define SYSCON_AGC_MEM_FORCE_PD_S 1
/** SYSCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
* Need add description
*/
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_M (SYSCON_PBUS_MEM_FORCE_PU_V << SYSCON_PBUS_MEM_FORCE_PU_S)
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x00000001U
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
/** SYSCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_M (SYSCON_PBUS_MEM_FORCE_PD_V << SYSCON_PBUS_MEM_FORCE_PD_S)
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x00000001U
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
/** SYSCON_DC_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1;
* Need add description
*/
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (SYSCON_DC_MEM_FORCE_PU_V << SYSCON_DC_MEM_FORCE_PU_S)
#define SYSCON_DC_MEM_FORCE_PU_V 0x00000001U
#define SYSCON_DC_MEM_FORCE_PU_S 4
/** SYSCON_DC_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
* Need add description
*/
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_M (SYSCON_DC_MEM_FORCE_PD_V << SYSCON_DC_MEM_FORCE_PD_S)
#define SYSCON_DC_MEM_FORCE_PD_V 0x00000001U
#define SYSCON_DC_MEM_FORCE_PD_S 5
/** SYSCON_RETENTION_CTRL_REG register
* register description
*/
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xa0)
/** SYSCON_NOBYPASS_CPU_ISO_RST : R/W; bitpos: [27]; default: 0;
* Need add description
*/
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (SYSCON_NOBYPASS_CPU_ISO_RST_V << SYSCON_NOBYPASS_CPU_ISO_RST_S)
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x00000001U
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
/** SYSCON_CLKGATE_FORCE_ON_REG register
* register description
*/
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xa4)
/** SYSCON_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003U
#define SYSCON_ROM_CLKGATE_FORCE_ON_M (SYSCON_ROM_CLKGATE_FORCE_ON_V << SYSCON_ROM_CLKGATE_FORCE_ON_S)
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x00000003U
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
/** SYSCON_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [5:2]; default: 15;
* Need add description
*/
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000FU
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M (SYSCON_SRAM_CLKGATE_FORCE_ON_V << SYSCON_SRAM_CLKGATE_FORCE_ON_S)
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2
/** SYSCON_MEM_POWER_DOWN_REG register
* register description
*/
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xa8)
/** SYSCON_ROM_POWER_DOWN : R/W; bitpos: [1:0]; default: 0;
* Need add description
*/
#define SYSCON_ROM_POWER_DOWN 0x00000003U
#define SYSCON_ROM_POWER_DOWN_M (SYSCON_ROM_POWER_DOWN_V << SYSCON_ROM_POWER_DOWN_S)
#define SYSCON_ROM_POWER_DOWN_V 0x00000003U
#define SYSCON_ROM_POWER_DOWN_S 0
/** SYSCON_SRAM_POWER_DOWN : R/W; bitpos: [5:2]; default: 0;
* Need add description
*/
#define SYSCON_SRAM_POWER_DOWN 0x0000000FU
#define SYSCON_SRAM_POWER_DOWN_M (SYSCON_SRAM_POWER_DOWN_V << SYSCON_SRAM_POWER_DOWN_S)
#define SYSCON_SRAM_POWER_DOWN_V 0x0000000FU
#define SYSCON_SRAM_POWER_DOWN_S 2
/** SYSCON_MEM_POWER_UP_REG register
* register description
*/
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xac)
/** SYSCON_ROM_POWER_UP : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
#define SYSCON_ROM_POWER_UP 0x00000003U
#define SYSCON_ROM_POWER_UP_M (SYSCON_ROM_POWER_UP_V << SYSCON_ROM_POWER_UP_S)
#define SYSCON_ROM_POWER_UP_V 0x00000003U
#define SYSCON_ROM_POWER_UP_S 0
/** SYSCON_SRAM_POWER_UP : R/W; bitpos: [5:2]; default: 15;
* Need add description
*/
#define SYSCON_SRAM_POWER_UP 0x0000000FU
#define SYSCON_SRAM_POWER_UP_M (SYSCON_SRAM_POWER_UP_V << SYSCON_SRAM_POWER_UP_S)
#define SYSCON_SRAM_POWER_UP_V 0x0000000FU
#define SYSCON_SRAM_POWER_UP_S 2
/** SYSCON_RND_DATA_REG register
* register description
*/
#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xb0)
/** SYSCON_RND_DATA : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_RND_DATA 0xFFFFFFFFU
#define SYSCON_RND_DATA_M (SYSCON_RND_DATA_V << SYSCON_RND_DATA_S)
#define SYSCON_RND_DATA_V 0xFFFFFFFFU
#define SYSCON_RND_DATA_S 0
/** SYSCON_PERI_BACKUP_CONFIG_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xb4)
/** SYSCON_PERI_BACKUP_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000007U
#define SYSCON_PERI_BACKUP_FLOW_ERR_M (SYSCON_PERI_BACKUP_FLOW_ERR_V << SYSCON_PERI_BACKUP_FLOW_ERR_S)
#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x00000007U
#define SYSCON_PERI_BACKUP_FLOW_ERR_S 0
/** SYSCON_PERI_BACKUP_ADDR_MAP_MODE : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_M (SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V << SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S)
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V 0x00000001U
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S 3
/** SYSCON_PERI_BACKUP_BURST_LIMIT : R/W; bitpos: [8:4]; default: 8;
* Need add description
*/
#define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001FU
#define SYSCON_PERI_BACKUP_BURST_LIMIT_M (SYSCON_PERI_BACKUP_BURST_LIMIT_V << SYSCON_PERI_BACKUP_BURST_LIMIT_S)
#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x0000001FU
#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4
/** SYSCON_PERI_BACKUP_TOUT_THRES : R/W; bitpos: [18:9]; default: 50;
* Need add description
*/
#define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FFU
#define SYSCON_PERI_BACKUP_TOUT_THRES_M (SYSCON_PERI_BACKUP_TOUT_THRES_V << SYSCON_PERI_BACKUP_TOUT_THRES_S)
#define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x000003FFU
#define SYSCON_PERI_BACKUP_TOUT_THRES_S 9
/** SYSCON_PERI_BACKUP_SIZE : R/W; bitpos: [28:19]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_SIZE 0x000003FFU
#define SYSCON_PERI_BACKUP_SIZE_M (SYSCON_PERI_BACKUP_SIZE_V << SYSCON_PERI_BACKUP_SIZE_S)
#define SYSCON_PERI_BACKUP_SIZE_V 0x000003FFU
#define SYSCON_PERI_BACKUP_SIZE_S 19
/** SYSCON_PERI_BACKUP_START : WO; bitpos: [29]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_START (BIT(29))
#define SYSCON_PERI_BACKUP_START_M (SYSCON_PERI_BACKUP_START_V << SYSCON_PERI_BACKUP_START_S)
#define SYSCON_PERI_BACKUP_START_V 0x00000001U
#define SYSCON_PERI_BACKUP_START_S 29
/** SYSCON_PERI_BACKUP_TO_MEM : R/W; bitpos: [30]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_TO_MEM (BIT(30))
#define SYSCON_PERI_BACKUP_TO_MEM_M (SYSCON_PERI_BACKUP_TO_MEM_V << SYSCON_PERI_BACKUP_TO_MEM_S)
#define SYSCON_PERI_BACKUP_TO_MEM_V 0x00000001U
#define SYSCON_PERI_BACKUP_TO_MEM_S 30
/** SYSCON_PERI_BACKUP_ENA : R/W; bitpos: [31]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_ENA (BIT(31))
#define SYSCON_PERI_BACKUP_ENA_M (SYSCON_PERI_BACKUP_ENA_V << SYSCON_PERI_BACKUP_ENA_S)
#define SYSCON_PERI_BACKUP_ENA_V 0x00000001U
#define SYSCON_PERI_BACKUP_ENA_S 31
/** SYSCON_PERI_BACKUP_APB_ADDR_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xb8)
/** SYSCON_PERI_BACKUP_APB_START_ADDR : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_APB_START_ADDR_M (SYSCON_PERI_BACKUP_APB_START_ADDR_V << SYSCON_PERI_BACKUP_APB_START_ADDR_S)
#define SYSCON_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_APB_START_ADDR_S 0
/** SYSCON_PERI_BACKUP_MEM_ADDR_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xbc)
/** SYSCON_PERI_BACKUP_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_MEM_START_ADDR_M (SYSCON_PERI_BACKUP_MEM_START_ADDR_V << SYSCON_PERI_BACKUP_MEM_START_ADDR_S)
#define SYSCON_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_MEM_START_ADDR_S 0
/** SYSCON_PERI_BACKUP_REG_MAP0_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_REG_MAP0_REG (DR_REG_SYSCON_BASE + 0xc0)
/** SYSCON_PERI_BACKUP_REG_MAP0 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_REG_MAP0 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP0_M (SYSCON_PERI_BACKUP_REG_MAP0_V << SYSCON_PERI_BACKUP_REG_MAP0_S)
#define SYSCON_PERI_BACKUP_REG_MAP0_V 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP0_S 0
/** SYSCON_PERI_BACKUP_REG_MAP1_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_REG_MAP1_REG (DR_REG_SYSCON_BASE + 0xc4)
/** SYSCON_PERI_BACKUP_REG_MAP1 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_REG_MAP1 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP1_M (SYSCON_PERI_BACKUP_REG_MAP1_V << SYSCON_PERI_BACKUP_REG_MAP1_S)
#define SYSCON_PERI_BACKUP_REG_MAP1_V 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP1_S 0
/** SYSCON_PERI_BACKUP_REG_MAP2_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_REG_MAP2_REG (DR_REG_SYSCON_BASE + 0xc8)
/** SYSCON_PERI_BACKUP_REG_MAP2 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_REG_MAP2 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP2_M (SYSCON_PERI_BACKUP_REG_MAP2_V << SYSCON_PERI_BACKUP_REG_MAP2_S)
#define SYSCON_PERI_BACKUP_REG_MAP2_V 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP2_S 0
/** SYSCON_PERI_BACKUP_REG_MAP3_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_REG_MAP3_REG (DR_REG_SYSCON_BASE + 0xcc)
/** SYSCON_PERI_BACKUP_REG_MAP3 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_REG_MAP3 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP3_M (SYSCON_PERI_BACKUP_REG_MAP3_V << SYSCON_PERI_BACKUP_REG_MAP3_S)
#define SYSCON_PERI_BACKUP_REG_MAP3_V 0xFFFFFFFFU
#define SYSCON_PERI_BACKUP_REG_MAP3_S 0
/** SYSCON_PERI_BACKUP_INT_RAW_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xd0)
/** SYSCON_PERI_BACKUP_DONE_INT_RAW : RO; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (SYSCON_PERI_BACKUP_DONE_INT_RAW_V << SYSCON_PERI_BACKUP_DONE_INT_RAW_S)
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x00000001U
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0
/** SYSCON_PERI_BACKUP_ERR_INT_RAW : RO; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (SYSCON_PERI_BACKUP_ERR_INT_RAW_V << SYSCON_PERI_BACKUP_ERR_INT_RAW_S)
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x00000001U
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1
/** SYSCON_PERI_BACKUP_INT_ST_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xd4)
/** SYSCON_PERI_BACKUP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (SYSCON_PERI_BACKUP_DONE_INT_ST_V << SYSCON_PERI_BACKUP_DONE_INT_ST_S)
#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x00000001U
#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0
/** SYSCON_PERI_BACKUP_ERR_INT_ST : RO; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_ST_M (SYSCON_PERI_BACKUP_ERR_INT_ST_V << SYSCON_PERI_BACKUP_ERR_INT_ST_S)
#define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x00000001U
#define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1
/** SYSCON_PERI_BACKUP_INT_ENA_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xd8)
/** SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (SYSCON_PERI_BACKUP_DONE_INT_ENA_V << SYSCON_PERI_BACKUP_DONE_INT_ENA_S)
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x00000001U
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0
/** SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (SYSCON_PERI_BACKUP_ERR_INT_ENA_V << SYSCON_PERI_BACKUP_ERR_INT_ENA_S)
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x00000001U
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1
/** SYSCON_PERI_BACKUP_INT_CLR_REG register
* register description
*/
#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xdc)
/** SYSCON_PERI_BACKUP_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (SYSCON_PERI_BACKUP_DONE_INT_CLR_V << SYSCON_PERI_BACKUP_DONE_INT_CLR_S)
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x00000001U
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0
/** SYSCON_PERI_BACKUP_ERR_INT_CLR : WO; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (SYSCON_PERI_BACKUP_ERR_INT_CLR_V << SYSCON_PERI_BACKUP_ERR_INT_CLR_S)
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x00000001U
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1
/** SYSCON_SYSCON_REGCLK_CONF_REG register
* register description
*/
#define SYSCON_SYSCON_REGCLK_CONF_REG (DR_REG_SYSCON_BASE + 0xe0)
/** SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSCON_CLK_EN (BIT(0))
#define SYSCON_CLK_EN_M (SYSCON_CLK_EN_V << SYSCON_CLK_EN_S)
#define SYSCON_CLK_EN_V 0x00000001U
#define SYSCON_CLK_EN_S 0
/** SYSCON_SYSCON_DATE_REG register
* register description
*/
#define SYSCON_SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3fc)
/** SYSCON_SYSCON_DATE : R/W; bitpos: [31:0]; default: 34607184;
* Version control
*/
#define SYSCON_SYSCON_DATE 0xFFFFFFFFU
#define SYSCON_SYSCON_DATE_M (SYSCON_SYSCON_DATE_V << SYSCON_SYSCON_DATE_S)
#define SYSCON_SYSCON_DATE_V 0xFFFFFFFFU
#define SYSCON_SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of wifi_bb_cfg register
* register description
*/
typedef union {
struct {
/** wifi_bb_cfg : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t wifi_bb_cfg:32;
};
uint32_t val;
} syscon_wifi_bb_cfg_reg_t;
/** Type of wifi_bb_cfg_2 register
* register description
*/
typedef union {
struct {
/** wifi_bb_cfg_2 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t wifi_bb_cfg_2:32;
};
uint32_t val;
} syscon_wifi_bb_cfg_2_reg_t;
/** Type of host_inf_sel register
* register description
*/
typedef union {
struct {
/** peri_io_swap : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
uint32_t peri_io_swap:8;
uint32_t reserved_8:24;
};
uint32_t val;
} syscon_host_inf_sel_reg_t;
/** Type of ext_mem_pms_lock register
* register description
*/
typedef union {
struct {
/** ext_mem_pms_lock : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t ext_mem_pms_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} syscon_ext_mem_pms_lock_reg_t;
/** Type of flash_ace0_attr register
* register description
*/
typedef union {
struct {
/** flash_ace0_attr : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
uint32_t flash_ace0_attr:2;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_flash_ace0_attr_reg_t;
/** Type of flash_ace1_attr register
* register description
*/
typedef union {
struct {
/** flash_ace1_attr : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
uint32_t flash_ace1_attr:2;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_flash_ace1_attr_reg_t;
/** Type of flash_ace2_attr register
* register description
*/
typedef union {
struct {
/** flash_ace2_attr : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
uint32_t flash_ace2_attr:2;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_flash_ace2_attr_reg_t;
/** Type of flash_ace3_attr register
* register description
*/
typedef union {
struct {
/** flash_ace3_attr : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
uint32_t flash_ace3_attr:2;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_flash_ace3_attr_reg_t;
/** Type of flash_ace0_addr register
* register description
*/
typedef union {
struct {
/** flash_ace0_addr_s : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t flash_ace0_addr_s:32;
};
uint32_t val;
} syscon_flash_ace0_addr_reg_t;
/** Type of flash_ace1_addr register
* register description
*/
typedef union {
struct {
/** flash_ace1_addr_s : R/W; bitpos: [31:0]; default: 4194304;
* Need add description
*/
uint32_t flash_ace1_addr_s:32;
};
uint32_t val;
} syscon_flash_ace1_addr_reg_t;
/** Type of flash_ace2_addr register
* register description
*/
typedef union {
struct {
/** flash_ace2_addr_s : R/W; bitpos: [31:0]; default: 8388608;
* Need add description
*/
uint32_t flash_ace2_addr_s:32;
};
uint32_t val;
} syscon_flash_ace2_addr_reg_t;
/** Type of flash_ace3_addr register
* register description
*/
typedef union {
struct {
/** flash_ace3_addr_s : R/W; bitpos: [31:0]; default: 12582912;
* Need add description
*/
uint32_t flash_ace3_addr_s:32;
};
uint32_t val;
} syscon_flash_ace3_addr_reg_t;
/** Type of flash_ace0_size register
* register description
*/
typedef union {
struct {
/** flash_ace0_size : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
uint32_t flash_ace0_size:13;
uint32_t reserved_13:19;
};
uint32_t val;
} syscon_flash_ace0_size_reg_t;
/** Type of flash_ace1_size register
* register description
*/
typedef union {
struct {
/** flash_ace1_size : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
uint32_t flash_ace1_size:13;
uint32_t reserved_13:19;
};
uint32_t val;
} syscon_flash_ace1_size_reg_t;
/** Type of flash_ace2_size register
* register description
*/
typedef union {
struct {
/** flash_ace2_size : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
uint32_t flash_ace2_size:13;
uint32_t reserved_13:19;
};
uint32_t val;
} syscon_flash_ace2_size_reg_t;
/** Type of flash_ace3_size register
* register description
*/
typedef union {
struct {
/** flash_ace3_size : R/W; bitpos: [12:0]; default: 1024;
* Need add description
*/
uint32_t flash_ace3_size:13;
uint32_t reserved_13:19;
};
uint32_t val;
} syscon_flash_ace3_size_reg_t;
/** Type of spi_mem_pms_ctrl register
* register description
*/
typedef union {
struct {
/** spi_mem_reject_int : RO; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t spi_mem_reject_int:1;
/** spi_mem_reject_clr : WOD; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t spi_mem_reject_clr:1;
/** spi_mem_reject_cde : RO; bitpos: [6:2]; default: 0;
* Need add description
*/
uint32_t spi_mem_reject_cde:5;
uint32_t reserved_7:25;
};
uint32_t val;
} syscon_spi_mem_pms_ctrl_reg_t;
/** Type of spi_mem_reject_addr register
* register description
*/
typedef union {
struct {
/** spi_mem_reject_addr : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t spi_mem_reject_addr:32;
};
uint32_t val;
} syscon_spi_mem_reject_addr_reg_t;
/** Type of syscon_sdio_ctrl register
* register description
*/
typedef union {
struct {
/** sdio_win_access_en : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t sdio_win_access_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} syscon_syscon_sdio_ctrl_reg_t;
/** Type of redcy_sig0 register
* register description
*/
typedef union {
struct {
/** redcy_sig0 : R/W; bitpos: [30:0]; default: 0;
* Need add description
*/
uint32_t redcy_sig0:31;
/** redcy_andor : RO; bitpos: [31]; default: 0;
* Need add description
*/
uint32_t redcy_andor:1;
};
uint32_t val;
} syscon_redcy_sig0_reg_t;
/** Type of redcy_sig1 register
* register description
*/
typedef union {
struct {
/** redcy_sig1 : R/W; bitpos: [30:0]; default: 0;
* Need add description
*/
uint32_t redcy_sig1:31;
/** redcy_nandor : RO; bitpos: [31]; default: 0;
* Need add description
*/
uint32_t redcy_nandor:1;
};
uint32_t val;
} syscon_redcy_sig1_reg_t;
/** Type of front_end_mem_pd register
* register description
*/
typedef union {
struct {
/** agc_mem_force_pu : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t agc_mem_force_pu:1;
/** agc_mem_force_pd : R/W; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t agc_mem_force_pd:1;
/** pbus_mem_force_pu : R/W; bitpos: [2]; default: 1;
* Need add description
*/
uint32_t pbus_mem_force_pu:1;
/** pbus_mem_force_pd : R/W; bitpos: [3]; default: 0;
* Need add description
*/
uint32_t pbus_mem_force_pd:1;
/** dc_mem_force_pu : R/W; bitpos: [4]; default: 1;
* Need add description
*/
uint32_t dc_mem_force_pu:1;
/** dc_mem_force_pd : R/W; bitpos: [5]; default: 0;
* Need add description
*/
uint32_t dc_mem_force_pd:1;
uint32_t reserved_6:26;
};
uint32_t val;
} syscon_front_end_mem_pd_reg_t;
/** Type of retention_ctrl register
* register description
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** nobypass_cpu_iso_rst : R/W; bitpos: [27]; default: 0;
* Need add description
*/
uint32_t nobypass_cpu_iso_rst:1;
uint32_t reserved_28:4;
};
uint32_t val;
} syscon_retention_ctrl_reg_t;
/** Type of clkgate_force_on register
* register description
*/
typedef union {
struct {
/** rom_clkgate_force_on : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
uint32_t rom_clkgate_force_on:2;
/** sram_clkgate_force_on : R/W; bitpos: [5:2]; default: 15;
* Need add description
*/
uint32_t sram_clkgate_force_on:4;
uint32_t reserved_6:26;
};
uint32_t val;
} syscon_clkgate_force_on_reg_t;
/** Type of mem_power_down register
* register description
*/
typedef union {
struct {
/** rom_power_down : R/W; bitpos: [1:0]; default: 0;
* Need add description
*/
uint32_t rom_power_down:2;
/** sram_power_down : R/W; bitpos: [5:2]; default: 0;
* Need add description
*/
uint32_t sram_power_down:4;
uint32_t reserved_6:26;
};
uint32_t val;
} syscon_mem_power_down_reg_t;
/** Type of mem_power_up register
* register description
*/
typedef union {
struct {
/** rom_power_up : R/W; bitpos: [1:0]; default: 3;
* Need add description
*/
uint32_t rom_power_up:2;
/** sram_power_up : R/W; bitpos: [5:2]; default: 15;
* Need add description
*/
uint32_t sram_power_up:4;
uint32_t reserved_6:26;
};
uint32_t val;
} syscon_mem_power_up_reg_t;
/** Type of rnd_data register
* register description
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t rnd_data:32;
};
uint32_t val;
} syscon_rnd_data_reg_t;
/** Type of peri_backup_config register
* register description
*/
typedef union {
struct {
/** peri_backup_flow_err : RO; bitpos: [2:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_flow_err:3;
/** peri_backup_addr_map_mode : R/W; bitpos: [3]; default: 0;
* Need add description
*/
uint32_t peri_backup_addr_map_mode:1;
/** peri_backup_burst_limit : R/W; bitpos: [8:4]; default: 8;
* Need add description
*/
uint32_t peri_backup_burst_limit:5;
/** peri_backup_tout_thres : R/W; bitpos: [18:9]; default: 50;
* Need add description
*/
uint32_t peri_backup_tout_thres:10;
/** peri_backup_size : R/W; bitpos: [28:19]; default: 0;
* Need add description
*/
uint32_t peri_backup_size:10;
/** peri_backup_start : WO; bitpos: [29]; default: 0;
* Need add description
*/
uint32_t peri_backup_start:1;
/** peri_backup_to_mem : R/W; bitpos: [30]; default: 0;
* Need add description
*/
uint32_t peri_backup_to_mem:1;
/** peri_backup_ena : R/W; bitpos: [31]; default: 0;
* Need add description
*/
uint32_t peri_backup_ena:1;
};
uint32_t val;
} syscon_peri_backup_config_reg_t;
/** Type of peri_backup_apb_addr register
* register description
*/
typedef union {
struct {
/** peri_backup_apb_start_addr : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_apb_start_addr:32;
};
uint32_t val;
} syscon_peri_backup_apb_addr_reg_t;
/** Type of peri_backup_mem_addr register
* register description
*/
typedef union {
struct {
/** peri_backup_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_mem_start_addr:32;
};
uint32_t val;
} syscon_peri_backup_mem_addr_reg_t;
/** Type of peri_backup_reg_map0 register
* register description
*/
typedef union {
struct {
/** peri_backup_reg_map0 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_reg_map0:32;
};
uint32_t val;
} syscon_peri_backup_reg_map0_reg_t;
/** Type of peri_backup_reg_map1 register
* register description
*/
typedef union {
struct {
/** peri_backup_reg_map1 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_reg_map1:32;
};
uint32_t val;
} syscon_peri_backup_reg_map1_reg_t;
/** Type of peri_backup_reg_map2 register
* register description
*/
typedef union {
struct {
/** peri_backup_reg_map2 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_reg_map2:32;
};
uint32_t val;
} syscon_peri_backup_reg_map2_reg_t;
/** Type of peri_backup_reg_map3 register
* register description
*/
typedef union {
struct {
/** peri_backup_reg_map3 : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t peri_backup_reg_map3:32;
};
uint32_t val;
} syscon_peri_backup_reg_map3_reg_t;
/** Type of peri_backup_int_raw register
* register description
*/
typedef union {
struct {
/** peri_backup_done_int_raw : RO; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t peri_backup_done_int_raw:1;
/** peri_backup_err_int_raw : RO; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t peri_backup_err_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_peri_backup_int_raw_reg_t;
/** Type of peri_backup_int_st register
* register description
*/
typedef union {
struct {
/** peri_backup_done_int_st : RO; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t peri_backup_done_int_st:1;
/** peri_backup_err_int_st : RO; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t peri_backup_err_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_peri_backup_int_st_reg_t;
/** Type of peri_backup_int_ena register
* register description
*/
typedef union {
struct {
/** peri_backup_done_int_ena : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t peri_backup_done_int_ena:1;
/** peri_backup_err_int_ena : R/W; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t peri_backup_err_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_peri_backup_int_ena_reg_t;
/** Type of peri_backup_int_clr register
* register description
*/
typedef union {
struct {
/** peri_backup_done_int_clr : WO; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t peri_backup_done_int_clr:1;
/** peri_backup_err_int_clr : WO; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t peri_backup_err_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} syscon_peri_backup_int_clr_reg_t;
/** Type of syscon_regclk_conf register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} syscon_syscon_regclk_conf_reg_t;
/** Type of syscon_date register
* register description
*/
typedef union {
struct {
/** syscon_date : R/W; bitpos: [31:0]; default: 34607184;
* Version control
*/
uint32_t syscon_date:32;
};
uint32_t val;
} syscon_syscon_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
volatile syscon_wifi_bb_cfg_2_reg_t wifi_bb_cfg_2;
uint32_t reserved_014[2];
volatile syscon_host_inf_sel_reg_t host_inf_sel;
volatile syscon_ext_mem_pms_lock_reg_t ext_mem_pms_lock;
uint32_t reserved_024;
volatile syscon_flash_ace0_attr_reg_t flash_ace0_attr;
volatile syscon_flash_ace1_attr_reg_t flash_ace1_attr;
volatile syscon_flash_ace2_attr_reg_t flash_ace2_attr;
volatile syscon_flash_ace3_attr_reg_t flash_ace3_attr;
volatile syscon_flash_ace0_addr_reg_t flash_ace0_addr;
volatile syscon_flash_ace1_addr_reg_t flash_ace1_addr;
volatile syscon_flash_ace2_addr_reg_t flash_ace2_addr;
volatile syscon_flash_ace3_addr_reg_t flash_ace3_addr;
volatile syscon_flash_ace0_size_reg_t flash_ace0_size;
volatile syscon_flash_ace1_size_reg_t flash_ace1_size;
volatile syscon_flash_ace2_size_reg_t flash_ace2_size;
volatile syscon_flash_ace3_size_reg_t flash_ace3_size;
uint32_t reserved_058[12];
volatile syscon_spi_mem_pms_ctrl_reg_t spi_mem_pms_ctrl;
volatile syscon_spi_mem_reject_addr_reg_t spi_mem_reject_addr;
volatile syscon_syscon_sdio_ctrl_reg_t syscon_sdio_ctrl;
volatile syscon_redcy_sig0_reg_t redcy_sig0;
volatile syscon_redcy_sig1_reg_t redcy_sig1;
volatile syscon_front_end_mem_pd_reg_t front_end_mem_pd;
volatile syscon_retention_ctrl_reg_t retention_ctrl;
volatile syscon_clkgate_force_on_reg_t clkgate_force_on;
volatile syscon_mem_power_down_reg_t mem_power_down;
volatile syscon_mem_power_up_reg_t mem_power_up;
volatile syscon_rnd_data_reg_t rnd_data;
volatile syscon_peri_backup_config_reg_t peri_backup_config;
volatile syscon_peri_backup_apb_addr_reg_t peri_backup_apb_addr;
volatile syscon_peri_backup_mem_addr_reg_t peri_backup_mem_addr;
volatile syscon_peri_backup_reg_map0_reg_t peri_backup_reg_map0;
volatile syscon_peri_backup_reg_map1_reg_t peri_backup_reg_map1;
volatile syscon_peri_backup_reg_map2_reg_t peri_backup_reg_map2;
volatile syscon_peri_backup_reg_map3_reg_t peri_backup_reg_map3;
volatile syscon_peri_backup_int_raw_reg_t peri_backup_int_raw;
volatile syscon_peri_backup_int_st_reg_t peri_backup_int_st;
volatile syscon_peri_backup_int_ena_reg_t peri_backup_int_ena;
volatile syscon_peri_backup_int_clr_reg_t peri_backup_int_clr;
volatile syscon_syscon_regclk_conf_reg_t syscon_regclk_conf;
uint32_t reserved_0e4[198];
volatile syscon_syscon_date_reg_t syscon_date;
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifndef __cplusplus
_Static_assert(sizeof(syscon_dev_t) == 0x400, "Invalid size of syscon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clkrst_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SYSTEM_CPU_PERI_CLK_EN_REG register
* register description
*/
#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0)
/** SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0;
* Need add description
*/
#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))
#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S)
#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x00000001U
#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6
/** SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0;
* Need add description
*/
#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))
#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S)
#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001U
#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7
/** SYSTEM_CPU_PERI_RST_EN_REG register
* register description
*/
#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4)
/** SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1;
* Need add description
*/
#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6))
#define SYSTEM_RST_EN_ASSIST_DEBUG_M (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S)
#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x00000001U
#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6
/** SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1;
* Need add description
*/
#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7))
#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S)
#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001U
#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7
/** SYSTEM_CPU_PER_CONF_REG register
* register description
*/
#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8)
/** SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
* Need add description
*/
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3))
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3
/** SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
* Need add description
*/
#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000FU
#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S)
#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000FU
#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4
/** SYSTEM_MEM_PD_MASK_REG register
* register description
*/
#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc)
/** SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0))
#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S)
#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001U
#define SYSTEM_LSLP_MEM_PD_MASK_S 0
/** SYSTEM_CPU_INTR_FROM_CPU_0_REG register
* register description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x10)
/** SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S)
#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0
/** SYSTEM_CPU_INTR_FROM_CPU_1_REG register
* register description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x14)
/** SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S)
#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0
/** SYSTEM_CPU_INTR_FROM_CPU_2_REG register
* register description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x18)
/** SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S)
#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0
/** SYSTEM_CPU_INTR_FROM_CPU_3_REG register
* register description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x1c)
/** SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S)
#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0
/** SYSTEM_RSA_PD_CTRL_REG register
* register description
*/
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x20)
/** SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define SYSTEM_RSA_MEM_PD (BIT(0))
#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S)
#define SYSTEM_RSA_MEM_PD_V 0x00000001U
#define SYSTEM_RSA_MEM_PD_S 0
/** SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1))
#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S)
#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001U
#define SYSTEM_RSA_MEM_FORCE_PU_S 1
/** SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
* Need add description
*/
#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2))
#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S)
#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001U
#define SYSTEM_RSA_MEM_FORCE_PD_S 2
/** SYSTEM_EDMA_CTRL_REG register
* register description
*/
#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x24)
/** SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define SYSTEM_EDMA_CLK_ON (BIT(0))
#define SYSTEM_EDMA_CLK_ON_M (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S)
#define SYSTEM_EDMA_CLK_ON_V 0x00000001U
#define SYSTEM_EDMA_CLK_ON_S 0
/** SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSTEM_EDMA_RESET (BIT(1))
#define SYSTEM_EDMA_RESET_M (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S)
#define SYSTEM_EDMA_RESET_V 0x00000001U
#define SYSTEM_EDMA_RESET_S 1
/** SYSTEM_CACHE_CONTROL_REG register
* register description
*/
#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x28)
/** SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define SYSTEM_ICACHE_CLK_ON (BIT(0))
#define SYSTEM_ICACHE_CLK_ON_M (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S)
#define SYSTEM_ICACHE_CLK_ON_V 0x00000001U
#define SYSTEM_ICACHE_CLK_ON_S 0
/** SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSTEM_ICACHE_RESET (BIT(1))
#define SYSTEM_ICACHE_RESET_M (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S)
#define SYSTEM_ICACHE_RESET_V 0x00000001U
#define SYSTEM_ICACHE_RESET_S 1
/** SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1;
* Need add description
*/
#define SYSTEM_DCACHE_CLK_ON (BIT(2))
#define SYSTEM_DCACHE_CLK_ON_M (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S)
#define SYSTEM_DCACHE_CLK_ON_V 0x00000001U
#define SYSTEM_DCACHE_CLK_ON_S 2
/** SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define SYSTEM_DCACHE_RESET (BIT(3))
#define SYSTEM_DCACHE_RESET_M (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S)
#define SYSTEM_DCACHE_RESET_V 0x00000001U
#define SYSTEM_DCACHE_RESET_S 3
/** SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* register description
*/
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x2c)
/** SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Need add description
*/
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Need add description
*/
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** SYSTEM_RTC_FASTMEM_CONFIG_REG register
* register description
*/
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x30)
/** SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0;
* Need add description
*/
#define SYSTEM_RTC_MEM_CRC_START (BIT(8))
#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S)
#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001U
#define SYSTEM_RTC_MEM_CRC_START_S 8
/** SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0;
* Need add description
*/
#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FFU
#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S)
#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FFU
#define SYSTEM_RTC_MEM_CRC_ADDR_S 9
/** SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047;
* Need add description
*/
#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FFU
#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S)
#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FFU
#define SYSTEM_RTC_MEM_CRC_LEN_S 20
/** SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0;
* Need add description
*/
#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31))
#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S)
#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001U
#define SYSTEM_RTC_MEM_CRC_FINISH_S 31
/** SYSTEM_RTC_FASTMEM_CRC_REG register
* register description
*/
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x34)
/** SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFFU
#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S)
#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFFU
#define SYSTEM_RTC_MEM_CRC_RES_S 0
/** SYSTEM_REDUNDANT_ECO_CTRL_REG register
* register description
*/
#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38)
/** SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0))
#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S)
#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001U
#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0
/** SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0;
* Need add description
*/
#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1))
#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S)
#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001U
#define SYSTEM_REDUNDANT_ECO_RESULT_S 1
/** SYSTEM_CLOCK_GATE_REG register
* register description
*/
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x3c)
/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define SYSTEM_CLK_EN (BIT(0))
#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S)
#define SYSTEM_CLK_EN_V 0x00000001U
#define SYSTEM_CLK_EN_S 0
/** SYSTEM_MEM_PVT_REG register
* register description
*/
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x40)
/** SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3;
* Need add description
*/
#define SYSTEM_MEM_PATH_LEN 0x0000000FU
#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S)
#define SYSTEM_MEM_PATH_LEN_V 0x0000000FU
#define SYSTEM_MEM_PATH_LEN_S 0
/** SYSTEM_MEM_ERR_CNT_CLR : WO; bitpos: [4]; default: 0;
* Need add description
*/
#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4))
#define SYSTEM_MEM_ERR_CNT_CLR_M (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S)
#define SYSTEM_MEM_ERR_CNT_CLR_V 0x00000001U
#define SYSTEM_MEM_ERR_CNT_CLR_S 4
/** SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0;
* Need add description
*/
#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5))
#define SYSTEM_MEM_PVT_MONITOR_EN_M (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S)
#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x00000001U
#define SYSTEM_MEM_PVT_MONITOR_EN_S 5
/** SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0;
* Need add description
*/
#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFFU
#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S)
#define SYSTEM_MEM_TIMING_ERR_CNT_V 0x0000FFFFU
#define SYSTEM_MEM_TIMING_ERR_CNT_S 6
/** SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0;
* Need add description
*/
#define SYSTEM_MEM_VT_SEL 0x00000003U
#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S)
#define SYSTEM_MEM_VT_SEL_V 0x00000003U
#define SYSTEM_MEM_VT_SEL_S 22
/** SYSTEM_SYSTEM_REG_DATE_REG register
* register description
*/
#define SYSTEM_SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
/** SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872;
* Need add description
*/
#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFFU
#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S)
#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFFU
#define SYSTEM_SYSTEM_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of cpu_peri_clk_en register
* register description
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** clk_en_assist_debug : R/W; bitpos: [6]; default: 0;
* Need add description
*/
uint32_t clk_en_assist_debug:1;
/** clk_en_dedicated_gpio : R/W; bitpos: [7]; default: 0;
* Need add description
*/
uint32_t clk_en_dedicated_gpio:1;
uint32_t reserved_8:24;
};
uint32_t val;
} system_cpu_peri_clk_en_reg_t;
/** Type of cpu_peri_rst_en register
* register description
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** rst_en_assist_debug : R/W; bitpos: [6]; default: 1;
* Need add description
*/
uint32_t rst_en_assist_debug:1;
/** rst_en_dedicated_gpio : R/W; bitpos: [7]; default: 1;
* Need add description
*/
uint32_t rst_en_dedicated_gpio:1;
uint32_t reserved_8:24;
};
uint32_t val;
} system_cpu_peri_rst_en_reg_t;
/** Type of cpu_per_conf register
* register description
*/
typedef union {
struct {
uint32_t reserved_0:3;
/** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
* Need add description
*/
uint32_t cpu_wait_mode_force_on:1;
/** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
* Need add description
*/
uint32_t cpu_waiti_delay_num:4;
uint32_t reserved_8:24;
};
uint32_t val;
} system_cpu_per_conf_reg_t;
/** Type of mem_pd_mask register
* register description
*/
typedef union {
struct {
/** lslp_mem_pd_mask : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t lslp_mem_pd_mask:1;
uint32_t reserved_1:31;
};
uint32_t val;
} system_mem_pd_mask_reg_t;
/** Type of cpu_intr_from_cpu_0 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_0:1;
uint32_t reserved_1:31;
};
uint32_t val;
} system_cpu_intr_from_cpu_0_reg_t;
/** Type of cpu_intr_from_cpu_1 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_1:1;
uint32_t reserved_1:31;
};
uint32_t val;
} system_cpu_intr_from_cpu_1_reg_t;
/** Type of cpu_intr_from_cpu_2 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_2:1;
uint32_t reserved_1:31;
};
uint32_t val;
} system_cpu_intr_from_cpu_2_reg_t;
/** Type of cpu_intr_from_cpu_3 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_3:1;
uint32_t reserved_1:31;
};
uint32_t val;
} system_cpu_intr_from_cpu_3_reg_t;
/** Type of rsa_pd_ctrl register
* register description
*/
typedef union {
struct {
/** rsa_mem_pd : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t rsa_mem_pd:1;
/** rsa_mem_force_pu : R/W; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t rsa_mem_force_pu:1;
/** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
* Need add description
*/
uint32_t rsa_mem_force_pd:1;
uint32_t reserved_3:29;
};
uint32_t val;
} system_rsa_pd_ctrl_reg_t;
/** Type of edma_ctrl register
* register description
*/
typedef union {
struct {
/** edma_clk_on : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t edma_clk_on:1;
/** edma_reset : R/W; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t edma_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} system_edma_ctrl_reg_t;
/** Type of cache_control register
* register description
*/
typedef union {
struct {
/** icache_clk_on : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t icache_clk_on:1;
/** icache_reset : R/W; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t icache_reset:1;
/** dcache_clk_on : R/W; bitpos: [2]; default: 1;
* Need add description
*/
uint32_t dcache_clk_on:1;
/** dcache_reset : R/W; bitpos: [3]; default: 0;
* Need add description
*/
uint32_t dcache_reset:1;
uint32_t reserved_4:28;
};
uint32_t val;
} system_cache_control_reg_t;
/** Type of external_device_encrypt_decrypt_control register
* register description
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Need add description
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Need add description
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} system_external_device_encrypt_decrypt_control_reg_t;
/** Type of rtc_fastmem_config register
* register description
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** rtc_mem_crc_start : R/W; bitpos: [8]; default: 0;
* Need add description
*/
uint32_t rtc_mem_crc_start:1;
/** rtc_mem_crc_addr : R/W; bitpos: [19:9]; default: 0;
* Need add description
*/
uint32_t rtc_mem_crc_addr:11;
/** rtc_mem_crc_len : R/W; bitpos: [30:20]; default: 2047;
* Need add description
*/
uint32_t rtc_mem_crc_len:11;
/** rtc_mem_crc_finish : RO; bitpos: [31]; default: 0;
* Need add description
*/
uint32_t rtc_mem_crc_finish:1;
};
uint32_t val;
} system_rtc_fastmem_config_reg_t;
/** Type of rtc_fastmem_crc register
* register description
*/
typedef union {
struct {
/** rtc_mem_crc_res : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t rtc_mem_crc_res:32;
};
uint32_t val;
} system_rtc_fastmem_crc_reg_t;
/** Type of redundant_eco_ctrl register
* register description
*/
typedef union {
struct {
/** redundant_eco_drive : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t redundant_eco_drive:1;
/** redundant_eco_result : RO; bitpos: [1]; default: 0;
* Need add description
*/
uint32_t redundant_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} system_redundant_eco_ctrl_reg_t;
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} system_clock_gate_reg_t;
/** Type of mem_pvt register
* register description
*/
typedef union {
struct {
/** mem_path_len : R/W; bitpos: [3:0]; default: 3;
* Need add description
*/
uint32_t mem_path_len:4;
/** mem_err_cnt_clr : WO; bitpos: [4]; default: 0;
* Need add description
*/
uint32_t mem_err_cnt_clr:1;
/** mem_pvt_monitor_en : R/W; bitpos: [5]; default: 0;
* Need add description
*/
uint32_t mem_pvt_monitor_en:1;
/** mem_timing_err_cnt : RO; bitpos: [21:6]; default: 0;
* Need add description
*/
uint32_t mem_timing_err_cnt:16;
/** mem_vt_sel : R/W; bitpos: [23:22]; default: 0;
* Need add description
*/
uint32_t mem_vt_sel:2;
uint32_t reserved_24:8;
};
uint32_t val;
} system_mem_pvt_reg_t;
/** Type of system_reg_date register
* register description
*/
typedef union {
struct {
/** system_reg_date : R/W; bitpos: [27:0]; default: 34615872;
* Need add description
*/
uint32_t system_reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} system_system_reg_date_reg_t;
typedef struct {
volatile system_cpu_peri_clk_en_reg_t cpu_peri_clk_en;
volatile system_cpu_peri_rst_en_reg_t cpu_peri_rst_en;
volatile system_cpu_per_conf_reg_t cpu_per_conf;
volatile system_mem_pd_mask_reg_t mem_pd_mask;
volatile system_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile system_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
volatile system_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
volatile system_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
volatile system_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
volatile system_edma_ctrl_reg_t edma_ctrl;
volatile system_cache_control_reg_t cache_control;
volatile system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile system_rtc_fastmem_config_reg_t rtc_fastmem_config;
volatile system_rtc_fastmem_crc_reg_t rtc_fastmem_crc;
volatile system_redundant_eco_ctrl_reg_t redundant_eco_ctrl;
volatile system_clock_gate_reg_t clock_gate;
volatile system_mem_pvt_reg_t mem_pvt;
uint32_t reserved_044[1006];
volatile system_system_reg_date_reg_t system_reg_date;
} system_dev_t;
extern system_dev_t SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(system_dev_t) == 0x1000, "Invalid size of system_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_SERIAL_JTAG_EP1_REG register
* FIFO access for the CDC-ACM data IN and OUT endpoints.
*/
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field. When
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
* bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU
#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
/** USB_SERIAL_JTAG_EP1_CONF_REG register
* Configuration and control registers for the CDC-ACM FIFOs.
*/
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
*/
#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U
#define USB_SERIAL_JTAG_WR_DONE_S 0
/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
* USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
* USB Host.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx FIFO.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
/** USB_SERIAL_JTAG_INT_RAW_REG register
* Interrupt raw status register.
*/
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when flush cmd is received for IN
* endpoint 2 of JTAG.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when SOF frame is received.
*/
#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
* one packet.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when pid error is detected.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when CRC5 error is detected.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when CRC16 error is detected.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when stuff error is detected.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
* received.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when usb bus reset is detected.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
* zero palyload.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
* zero palyload.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
/** USB_SERIAL_JTAG_INT_ST_REG register
* Interrupt status register.
*/
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
/** USB_SERIAL_JTAG_INT_ENA_REG register
* Interrupt enable status register.
*/
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
/** USB_SERIAL_JTAG_INT_CLR_REG register
* Interrupt clear status register.
*/
#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
/** USB_SERIAL_JTAG_CONF0_REG register
* PHY hardware configuration.
*/
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY
*/
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U
#define USB_SERIAL_JTAG_PHY_SEL_S 0
/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D- exchange
*/
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
* USB D+ D- exchange
*/
#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U
#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV
*/
#define USB_SERIAL_JTAG_VREFH 0x00000003U
#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
#define USB_SERIAL_JTAG_VREFH_V 0x00000003U
#define USB_SERIAL_JTAG_VREFH_S 3
/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV
*/
#define USB_SERIAL_JTAG_VREFL 0x00000003U
#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
#define USB_SERIAL_JTAG_VREFL_V 0x00000003U
#define USB_SERIAL_JTAG_VREFL_S 5
/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
* Enable software control input threshold
*/
#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U
#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup pulldown
*/
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull up.
*/
#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U
#define USB_SERIAL_JTAG_DP_PULLUP_S 9
/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull down.
*/
#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U
#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
* Control USB D- pull up.
*/
#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U
#define USB_SERIAL_JTAG_DM_PULLUP_S 11
/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
* Control USB D- pull down.
*/
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
* Control pull up value.
*/
#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U
#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
* Enable USB pad function.
*/
#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
/** USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W; bitpos: [15]; default: 0;
* 0: TX output at clock negedge. 1: Tx output at clock posedge.
*/
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL (BIT(15))
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S)
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V 0x00000001U
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S 15
/** USB_SERIAL_JTAG_PLL_DIV2_EN : R/W; bitpos: [16]; default: 1;
* This bit is used to set divider coefficient of PLL. 0: PLL divider coefficient is
* 0. 1: PLL divider coefficient is 1.
*/
#define USB_SERIAL_JTAG_PLL_DIV2_EN (BIT(16))
#define USB_SERIAL_JTAG_PLL_DIV2_EN_M (USB_SERIAL_JTAG_PLL_DIV2_EN_V << USB_SERIAL_JTAG_PLL_DIV2_EN_S)
#define USB_SERIAL_JTAG_PLL_DIV2_EN_V 0x00000001U
#define USB_SERIAL_JTAG_PLL_DIV2_EN_S 16
/** USB_SERIAL_JTAG_TEST_REG register
* Registers used for debugging the PHY.
*/
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
* Enable test of the USB pad
*/
#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
*/
#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test
*/
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test
*/
#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 0;
* USB differential rx value in test
*/
#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4))
#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4
/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 0;
* USB D+ rx value in test
*/
#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5))
#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_RX_DP_S 5
/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
* USB D- rx value in test
*/
#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6))
#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U
#define USB_SERIAL_JTAG_TEST_RX_DM_S 6
/** USB_SERIAL_JTAG_JFIFO_ST_REG register
* JTAG FIFO status and control registers.
*/
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
* JTAT in fifo counter.
*/
#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U
#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U
#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is empty.
*/
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is full.
*/
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
* JTAT out fifo counter.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is empty.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is full.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in fifo.
*/
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out fifo.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
/** USB_SERIAL_JTAG_FRAM_NUM_REG register
* Last received SOF frame index register.
*/
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
* Frame index of received SOF frame.
*/
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
* Control IN endpoint status information.
*/
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U
#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
* CDC-ACM IN endpoint status information.
*/
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U
#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
* CDC-ACM interrupt IN endpoint status information.
*/
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U
#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
* JTAG IN endpoint status information.
*/
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U
#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
* Control OUT endpoint status information.
*/
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
* CDC-ACM OUT endpoint status information.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U
#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is received.
*/
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
* JTAG OUT endpoint status information.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U
#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U
#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
/** USB_SERIAL_JTAG_MISC_CONF_REG register
* Clock enable control
*/
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
* registers.
*/
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U
#define USB_SERIAL_JTAG_CLK_EN_S 0
/** USB_SERIAL_JTAG_MEM_CONF_REG register
* Memory power control
*/
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
* 1: power down usb memory.
*/
#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U
#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb memory.
*/
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
/** USB_SERIAL_JTAG_DATE_REG register
* Date register
*/
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34607505;
* register version.
*/
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU
#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU
#define USB_SERIAL_JTAG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of ep1 register
* FIFO access for the CDC-ACM data IN and OUT endpoints.
*/
typedef union {
struct {
/** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field. When
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
* bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
/** Type of ep1_conf register
* Configuration and control registers for the CDC-ACM FIFOs.
*/
typedef union {
struct {
/** wr_done : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
*/
uint32_t wr_done:1;
/** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
* USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
* USB Host.
*/
uint32_t serial_in_ep_data_free:1;
/** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx FIFO.
*/
uint32_t serial_out_ep_data_avail:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_ep1_conf_reg_t;
/** Type of conf0 register
* PHY hardware configuration.
*/
typedef union {
struct {
/** phy_sel : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY
*/
uint32_t phy_sel:1;
/** exchg_pins_override : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D- exchange
*/
uint32_t exchg_pins_override:1;
/** exchg_pins : R/W; bitpos: [2]; default: 0;
* USB D+ D- exchange
*/
uint32_t exchg_pins:1;
/** vrefh : R/W; bitpos: [4:3]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV
*/
uint32_t vrefh:2;
/** vrefl : R/W; bitpos: [6:5]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV
*/
uint32_t vrefl:2;
/** vref_override : R/W; bitpos: [7]; default: 0;
* Enable software control input threshold
*/
uint32_t vref_override:1;
/** pad_pull_override : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup pulldown
*/
uint32_t pad_pull_override:1;
/** dp_pullup : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull up.
*/
uint32_t dp_pullup:1;
/** dp_pulldown : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull down.
*/
uint32_t dp_pulldown:1;
/** dm_pullup : R/W; bitpos: [11]; default: 0;
* Control USB D- pull up.
*/
uint32_t dm_pullup:1;
/** dm_pulldown : R/W; bitpos: [12]; default: 0;
* Control USB D- pull down.
*/
uint32_t dm_pulldown:1;
/** pullup_value : R/W; bitpos: [13]; default: 0;
* Control pull up value.
*/
uint32_t pullup_value:1;
/** usb_pad_enable : R/W; bitpos: [14]; default: 1;
* Enable USB pad function.
*/
uint32_t usb_pad_enable:1;
/** phy_tx_edge_sel : R/W; bitpos: [15]; default: 0;
* 0: TX output at clock negedge. 1: Tx output at clock posedge.
*/
uint32_t phy_tx_edge_sel:1;
/** pll_div2_en : R/W; bitpos: [16]; default: 1;
* This bit is used to set divider coefficient of PLL. 0: PLL divider coefficient is
* 0. 1: PLL divider coefficient is 1.
*/
uint32_t pll_div2_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} usb_serial_jtag_conf0_reg_t;
/** Type of test register
* Registers used for debugging the PHY.
*/
typedef union {
struct {
/** test_enable : R/W; bitpos: [0]; default: 0;
* Enable test of the USB pad
*/
uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
*/
uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test
*/
uint32_t test_tx_dp:1;
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test
*/
uint32_t test_tx_dm:1;
/** test_rx_rcv : RO; bitpos: [4]; default: 0;
* USB differential rx value in test
*/
uint32_t test_rx_rcv:1;
/** test_rx_dp : RO; bitpos: [5]; default: 0;
* USB D+ rx value in test
*/
uint32_t test_rx_dp:1;
/** test_rx_dm : RO; bitpos: [6]; default: 0;
* USB D- rx value in test
*/
uint32_t test_rx_dm:1;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_serial_jtag_test_reg_t;
/** Type of misc_conf register
* Clock enable control
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
* registers.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_misc_conf_reg_t;
/** Type of mem_conf register
* Memory power control
*/
typedef union {
struct {
/** usb_mem_pd : R/W; bitpos: [0]; default: 0;
* 1: power down usb memory.
*/
uint32_t usb_mem_pd:1;
/** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb memory.
*/
uint32_t usb_mem_clk_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_serial_jtag_mem_conf_reg_t;
/** Group: Interrupt Registers */
/** Type of int_raw register
* Interrupt raw status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when flush cmd is received for IN
* endpoint 2 of JTAG.
*/
uint32_t jtag_in_flush_int_raw:1;
/** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when SOF frame is received.
*/
uint32_t sof_int_raw:1;
/** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
* one packet.
*/
uint32_t serial_out_recv_pkt_int_raw:1;
/** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
*/
uint32_t serial_in_empty_int_raw:1;
/** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when pid error is detected.
*/
uint32_t pid_err_int_raw:1;
/** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when CRC5 error is detected.
*/
uint32_t crc5_err_int_raw:1;
/** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when CRC16 error is detected.
*/
uint32_t crc16_err_int_raw:1;
/** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when stuff error is detected.
*/
uint32_t stuff_err_int_raw:1;
/** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
* received.
*/
uint32_t in_token_rec_in_ep1_int_raw:1;
/** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when usb bus reset is detected.
*/
uint32_t usb_bus_reset_int_raw:1;
/** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
* zero palyload.
*/
uint32_t out_ep1_zero_payload_int_raw:1;
/** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
* zero palyload.
*/
uint32_t out_ep2_zero_payload_int_raw:1;
uint32_t reserved_12:20;
};
uint32_t val;
} usb_serial_jtag_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t jtag_in_flush_int_st:1;
/** sof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t sof_int_st:1;
/** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
uint32_t serial_out_recv_pkt_int_st:1;
/** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_in_empty_int_st:1;
/** pid_err_int_st : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t pid_err_int_st:1;
/** crc5_err_int_st : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t crc5_err_int_st:1;
/** crc16_err_int_st : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t crc16_err_int_st:1;
/** stuff_err_int_st : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t stuff_err_int_st:1;
/** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
uint32_t in_token_rec_in_ep1_int_st:1;
/** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t usb_bus_reset_int_st:1;
/** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t out_ep1_zero_payload_int_st:1;
/** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t out_ep2_zero_payload_int_st:1;
uint32_t reserved_12:20;
};
uint32_t val;
} usb_serial_jtag_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t jtag_in_flush_int_ena:1;
/** sof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t sof_int_ena:1;
/** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_out_recv_pkt_int_ena:1;
/** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_in_empty_int_ena:1;
/** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t pid_err_int_ena:1;
/** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t crc5_err_int_ena:1;
/** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t crc16_err_int_ena:1;
/** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t stuff_err_int_ena:1;
/** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
*/
uint32_t in_token_rec_in_ep1_int_ena:1;
/** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t usb_bus_reset_int_ena:1;
/** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep1_zero_payload_int_ena:1;
/** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep2_zero_payload_int_ena:1;
uint32_t reserved_12:20;
};
uint32_t val;
} usb_serial_jtag_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t jtag_in_flush_int_clr:1;
/** sof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
*/
uint32_t sof_int_clr:1;
/** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_out_recv_pkt_int_clr:1;
/** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_in_empty_int_clr:1;
/** pid_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t pid_err_int_clr:1;
/** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t crc5_err_int_clr:1;
/** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t crc16_err_int_clr:1;
/** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t stuff_err_int_clr:1;
/** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
*/
uint32_t in_token_rec_in_ep1_int_clr:1;
/** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t usb_bus_reset_int_clr:1;
/** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep1_zero_payload_int_clr:1;
/** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep2_zero_payload_int_clr:1;
uint32_t reserved_12:20;
};
uint32_t val;
} usb_serial_jtag_int_clr_reg_t;
/** Group: Status Registers */
/** Type of jfifo_st register
* JTAG FIFO status and control registers.
*/
typedef union {
struct {
/** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
* JTAT in fifo counter.
*/
uint32_t in_fifo_cnt:2;
/** in_fifo_empty : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is empty.
*/
uint32_t in_fifo_empty:1;
/** in_fifo_full : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is full.
*/
uint32_t in_fifo_full:1;
/** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
* JTAT out fifo counter.
*/
uint32_t out_fifo_cnt:2;
/** out_fifo_empty : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is empty.
*/
uint32_t out_fifo_empty:1;
/** out_fifo_full : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is full.
*/
uint32_t out_fifo_full:1;
/** in_fifo_reset : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in fifo.
*/
uint32_t in_fifo_reset:1;
/** out_fifo_reset : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out fifo.
*/
uint32_t out_fifo_reset:1;
uint32_t reserved_10:22;
};
uint32_t val;
} usb_serial_jtag_jfifo_st_reg_t;
/** Type of fram_num register
* Last received SOF frame index register.
*/
typedef union {
struct {
/** sof_frame_index : RO; bitpos: [10:0]; default: 0;
* Frame index of received SOF frame.
*/
uint32_t sof_frame_index:11;
uint32_t reserved_11:21;
};
uint32_t val;
} usb_serial_jtag_fram_num_reg_t;
/** Type of in_ep0_st register
* Control IN endpoint status information.
*/
typedef union {
struct {
/** in_ep0_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 0.
*/
uint32_t in_ep0_state:2;
/** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 0.
*/
uint32_t in_ep0_wr_addr:7;
/** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 0.
*/
uint32_t in_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep0_st_reg_t;
/** Type of in_ep1_st register
* CDC-ACM IN endpoint status information.
*/
typedef union {
struct {
/** in_ep1_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 1.
*/
uint32_t in_ep1_state:2;
/** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 1.
*/
uint32_t in_ep1_wr_addr:7;
/** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 1.
*/
uint32_t in_ep1_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep1_st_reg_t;
/** Type of in_ep2_st register
* CDC-ACM interrupt IN endpoint status information.
*/
typedef union {
struct {
/** in_ep2_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 2.
*/
uint32_t in_ep2_state:2;
/** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 2.
*/
uint32_t in_ep2_wr_addr:7;
/** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 2.
*/
uint32_t in_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep2_st_reg_t;
/** Type of in_ep3_st register
* JTAG IN endpoint status information.
*/
typedef union {
struct {
/** in_ep3_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 3.
*/
uint32_t in_ep3_state:2;
/** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 3.
*/
uint32_t in_ep3_wr_addr:7;
/** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 3.
*/
uint32_t in_ep3_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep3_st_reg_t;
/** Type of out_ep0_st register
* Control OUT endpoint status information.
*/
typedef union {
struct {
/** out_ep0_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 0.
*/
uint32_t out_ep0_state:2;
/** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
*/
uint32_t out_ep0_wr_addr:7;
/** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 0.
*/
uint32_t out_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep0_st_reg_t;
/** Type of out_ep1_st register
* CDC-ACM OUT endpoint status information.
*/
typedef union {
struct {
/** out_ep1_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 1.
*/
uint32_t out_ep1_state:2;
/** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
*/
uint32_t out_ep1_wr_addr:7;
/** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 1.
*/
uint32_t out_ep1_rd_addr:7;
/** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is received.
*/
uint32_t out_ep1_rec_data_cnt:7;
uint32_t reserved_23:9;
};
uint32_t val;
} usb_serial_jtag_out_ep1_st_reg_t;
/** Type of out_ep2_st register
* JTAG OUT endpoint status information.
*/
typedef union {
struct {
/** out_ep2_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 2.
*/
uint32_t out_ep2_state:2;
/** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
*/
uint32_t out_ep2_wr_addr:7;
/** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 2.
*/
uint32_t out_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep2_st_reg_t;
/** Group: Version Registers */
/** Type of date register
* Date register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 34607505;
* register version.
*/
uint32_t date:32;
};
uint32_t val;
} usb_serial_jtag_date_reg_t;
typedef struct {
volatile usb_serial_jtag_ep1_reg_t ep1;
volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
volatile usb_serial_jtag_int_raw_reg_t int_raw;
volatile usb_serial_jtag_int_st_reg_t int_st;
volatile usb_serial_jtag_int_ena_reg_t int_ena;
volatile usb_serial_jtag_int_clr_reg_t int_clr;
volatile usb_serial_jtag_conf0_reg_t conf0;
volatile usb_serial_jtag_test_reg_t test;
volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
volatile usb_serial_jtag_fram_num_reg_t fram_num;
volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
uint32_t reserved_04c[13];
volatile usb_serial_jtag_date_reg_t date;
} usb_serial_jtag_dev_t;
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
#ifndef __cplusplus
_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

20
components/soc/esp32h2/include/soc/dport_access.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
@ -20,7 +12,7 @@
#include "esp_attr.h"
#include "esp32h2/dport_access.h"
#include "soc.h"
#include "uart_reg.h"
#include "soc/uart_reg.h"
#ifdef __cplusplus
extern "C" {

20
components/soc/esp32h2/include/soc/i2c_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2C_REG_H_
#define _SOC_I2C_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */

20
components/soc/esp32h2/include/soc/i2c_struct.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2C_STRUCT_H_
#define _SOC_I2C_STRUCT_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct i2c_dev_s {
union {

20
components/soc/esp32h2/include/soc/i2s_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/

18
components/soc/esp32h2/include/soc/i2s_struct.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_I2S_STRUCT_H_
#define _SOC_I2S_STRUCT_H_
#ifdef __cplusplus

2
components/soc/esp32h2/include/soc/interrupt_reg.h
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@ -1 +1 @@
#include "interrupt_core0_reg.h"
#include "soc/interrupt_core0_reg.h"

20
components/soc/esp32h2/include/soc/periph_defs.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -75,7 +67,7 @@ typedef enum {
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/
ETS_TWAI_INTR_SOURCE, /**< interrupt of twai, level*/
ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/

20
components/soc/esp32h2/include/soc/rmt_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RMT_REG_H_
#define _SOC_RMT_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000)
#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004)

18
components/soc/esp32h2/include/soc/rmt_struct.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_

18
components/soc/esp32h2/include/soc/rtc.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>

20
components/soc/esp32h2/include/soc/soc.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -81,7 +73,7 @@
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define DR_REG_CAN_BASE 0x6002B000
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000

20
components/soc/esp32h2/include/soc/systimer_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYS_TIMER_REG_H_
#define _SOC_SYS_TIMER_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000)
/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating*/

15
components/soc/esp32h2/include/soc/systimer_struct.h
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@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

2
components/soc/esp32h2/include/soc/timer_group_reg.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

20
components/soc/esp32h2/include/soc/uart_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UART_REG_H_
#define _SOC_UART_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: UART $n accesses FIFO via this register.*/

18
components/soc/esp32h2/include/soc/uart_struct.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
#ifdef __cplusplus

20
components/soc/esp32h2/include/soc/uhci_reg.h
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@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UHCI_REG_H_
#define _SOC_UHCI_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: If this bit is set to 1 UHCI will end payload receive process

18
components/soc/esp32h2/include/soc/uhci_struct.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_
#ifdef __cplusplus

20
components/soc/esp32h2/interrupts.c
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
@ -40,7 +32,7 @@ const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
[22] = "UART1",
[23] = "LEDC",
[24] = "EFUSE",
[25] = "CAN",
[25] = "TWAI",
[26] = "USB",
[27] = "RTC_CORE",
[28] = "RMT",

31
tools/ci/check_copyright_ignore.txt
View File

@ -928,7 +928,6 @@ components/esp_system/port/soc/esp32h2/apb_backup_dma.c
components/esp_system/port/soc/esp32h2/cache_err_int.c
components/esp_system/port/soc/esp32h2/cache_err_int.h
components/esp_system/port/soc/esp32h2/reset_reason.c
components/esp_system/port/soc/esp32h2/system_internal.c
components/esp_system/port/soc/esp32s2/cache_err_int.c
components/esp_system/port/soc/esp32s2/cache_err_int.h
components/esp_system/port/soc/esp32s2/reset_reason.c
@ -1193,12 +1192,10 @@ components/hal/esp32h2/include/hal/ds_ll.h
components/hal/esp32h2/include/hal/gpspi_flash_ll.h
components/hal/esp32h2/include/hal/hmac_hal.h
components/hal/esp32h2/include/hal/hmac_ll.h
components/hal/esp32h2/include/hal/i2c_ll.h
components/hal/esp32h2/include/hal/interrupt_controller_ll.h
components/hal/esp32h2/include/hal/memprot_ll.h
components/hal/esp32h2/include/hal/mpu_ll.h
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
components/hal/esp32h2/include/hal/rwdt_ll.h
components/hal/esp32h2/include/hal/sha_ll.h
components/hal/esp32h2/include/hal/sigmadelta_ll.h
components/hal/esp32h2/include/hal/soc_ll.h
@ -1206,9 +1203,7 @@ components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32h2/include/hal/spi_flash_ll.h
components/hal/esp32h2/include/hal/spi_ll.h
components/hal/esp32h2/include/hal/spimem_flash_ll.h
components/hal/esp32h2/include/hal/systimer_ll.h
components/hal/esp32h2/include/hal/twai_ll.h
components/hal/esp32h2/include/hal/uart_ll.h
components/hal/esp32h2/include/hal/uhci_ll.h
components/hal/esp32h2/include/hal/uhci_types.h
components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
@ -1937,7 +1932,7 @@ components/soc/esp32c3/sigmadelta_periph.c
components/soc/esp32c3/spi_periph.c
components/soc/esp32c3/uart_periph.c
components/soc/esp32h2/adc_periph.c
components/soc/esp32h2/gpio_periph.c
components/soc/esp32h2/gdma_periph.c
components/soc/esp32h2/i2c_periph.c
components/soc/esp32h2/i2s_periph.c
components/soc/esp32h2/include/soc/adc_channel.h
@ -1945,47 +1940,30 @@ components/soc/esp32h2/include/soc/apb_ctrl_reg.h
components/soc/esp32h2/include/soc/apb_ctrl_struct.h
components/soc/esp32h2/include/soc/apb_saradc_reg.h
components/soc/esp32h2/include/soc/apb_saradc_struct.h
components/soc/esp32h2/include/soc/assist_debug_reg.h
components/soc/esp32h2/include/soc/bb_reg.h
components/soc/esp32h2/include/soc/boot_mode.h
components/soc/esp32h2/include/soc/clkout_channel.h
components/soc/esp32h2/include/soc/clkrst_reg.h
components/soc/esp32h2/include/soc/dport_access.h
components/soc/esp32h2/include/soc/efuse_reg.h
components/soc/esp32h2/include/soc/efuse_struct.h
components/soc/esp32h2/include/soc/extmem_reg.h
components/soc/esp32h2/include/soc/fe_reg.h
components/soc/esp32h2/include/soc/gpio_pins.h
components/soc/esp32h2/include/soc/gpio_reg.h
components/soc/esp32h2/include/soc/gpio_sd_reg.h
components/soc/esp32h2/include/soc/gpio_sd_struct.h
components/soc/esp32h2/include/soc/gpio_sig_map.h
components/soc/esp32h2/include/soc/gpio_struct.h
components/soc/esp32h2/include/soc/hwcrypto_reg.h
components/soc/esp32h2/include/soc/i2c_reg.h
components/soc/esp32h2/include/soc/i2c_struct.h
components/soc/esp32h2/include/soc/i2s_reg.h
components/soc/esp32h2/include/soc/i2s_struct.h
components/soc/esp32h2/include/soc/interrupt_core0_reg.h
components/soc/esp32h2/include/soc/interrupt_reg.h
components/soc/esp32h2/include/soc/io_mux_reg.h
components/soc/esp32h2/include/soc/ledc_reg.h
components/soc/esp32h2/include/soc/mmu.h
components/soc/esp32h2/include/soc/nrx_reg.h
components/soc/esp32h2/include/soc/periph_defs.h
components/soc/esp32h2/include/soc/reset_reasons.h
components/soc/esp32h2/include/soc/rmt_reg.h
components/soc/esp32h2/include/soc/rmt_struct.h
components/soc/esp32h2/include/soc/rtc.h
components/soc/esp32h2/include/soc/rtc_caps.h
components/soc/esp32h2/include/soc/rtc_cntl_reg.h
components/soc/esp32h2/include/soc/rtc_cntl_struct.h
components/soc/esp32h2/include/soc/rtc_i2c_reg.h
components/soc/esp32h2/include/soc/rtc_i2c_struct.h
components/soc/esp32h2/include/soc/rtc_io_caps.h
components/soc/esp32h2/include/soc/sensitive_reg.h
components/soc/esp32h2/include/soc/sensitive_struct.h
components/soc/esp32h2/include/soc/soc.h
components/soc/esp32h2/include/soc/soc_caps.h
components/soc/esp32h2/include/soc/soc_pins.h
components/soc/esp32h2/include/soc/spi_caps.h
@ -1998,19 +1976,12 @@ components/soc/esp32h2/include/soc/syscon_reg.h
components/soc/esp32h2/include/soc/syscon_struct.h
components/soc/esp32h2/include/soc/system_reg.h
components/soc/esp32h2/include/soc/system_struct.h
components/soc/esp32h2/include/soc/systimer_reg.h
components/soc/esp32h2/include/soc/systimer_struct.h
components/soc/esp32h2/include/soc/twai_struct.h
components/soc/esp32h2/include/soc/uart_channel.h
components/soc/esp32h2/include/soc/uart_pins.h
components/soc/esp32h2/include/soc/uart_reg.h
components/soc/esp32h2/include/soc/uart_struct.h
components/soc/esp32h2/include/soc/uhci_reg.h
components/soc/esp32h2/include/soc/uhci_struct.h
components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h
components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
components/soc/esp32h2/include/soc/wdev_reg.h
components/soc/esp32h2/interrupts.c
components/soc/esp32h2/ld/esp32h2.peripherals.ld
components/soc/esp32h2/ledc_periph.c
components/soc/esp32h2/rmt_periph.c