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Merge branch 'save_isr_ctx_to_coredump_v5.1' into 'release/v5.1'

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feat(coredump): save isr context to coredump elf file (v5.1)

See merge request espressif/esp-idf!27454
This commit is contained in:
Alexey Gerenkov 2023-12-06 18:38:54 +08:00
commit c42c37aff7
4 changed files with 12 additions and 4 deletions
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4
components/espcoredump/include_core_dump/esp_core_dump_port.h
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@ -40,8 +40,10 @@ uint16_t esp_core_dump_get_arch_id(void);
*
* @param info Pointer to the panic information. It contains the execution
* frame.
* @param isr_context A flag indicating whether the crash happened within an ISR context.
* Set to 1 if the crash occurred in an ISR, and 0 otherwise.
*/
void esp_core_dump_port_init(panic_info_t *info);
void esp_core_dump_port_init(panic_info_t *info, bool isr_context);
/**
* @brief Reset fake stacks allocator, if any.

4
components/espcoredump/src/core_dump_common.c
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@ -151,8 +151,10 @@ inline void esp_core_dump_write(panic_info_t *info, core_dump_write_config_t *wr
esp_err_t err = ESP_ERR_NOT_SUPPORTED;
s_exc_frame = (void*) info->frame;
bool isr_context = esp_core_dump_in_isr_context();
esp_core_dump_setup_stack();
esp_core_dump_port_init(info);
esp_core_dump_port_init(info, isr_context);
#if CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN
err = esp_core_dump_write_binary(write_cfg);
#elif CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF

4
components/espcoredump/src/port/riscv/core_dump_port.c
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@ -141,6 +141,7 @@ _Static_assert(sizeof(riscv_prstatus) == PRSTATUS_SIZE,
*/
typedef struct {
uint32_t crashed_task_tcb;
uint32_t isr_context;
} riscv_extra_info_t;
@ -157,9 +158,10 @@ static uint32_t s_fake_stacks_num = 0;
/* Statically initialize the extra information structure. */
static riscv_extra_info_t s_extra_info = { 0 };
inline void esp_core_dump_port_init(panic_info_t *info)
inline void esp_core_dump_port_init(panic_info_t *info, bool isr_context)
{
s_extra_info.crashed_task_tcb = COREDUMP_CURR_TASK_MARKER;
s_extra_info.isr_context = isr_context;
}
/**

4
components/espcoredump/src/port/xtensa/core_dump_port.c
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@ -95,6 +95,7 @@ typedef struct
core_dump_reg_pair_t exccause;
core_dump_reg_pair_t excvaddr;
core_dump_reg_pair_t extra_regs[COREDUMP_EXTRA_REG_NUM];
uint32_t isr_context;
} __attribute__((packed)) xtensa_extra_info_t;
// Xtensa Program Status for GDB
@ -259,7 +260,7 @@ static esp_err_t esp_core_dump_get_regs_from_stack(void* stack_addr,
return ESP_OK;
}
inline void esp_core_dump_port_init(panic_info_t *info)
inline void esp_core_dump_port_init(panic_info_t *info, bool isr_context)
{
s_extra_info.crashed_task_tcb = COREDUMP_CURR_TASK_MARKER;
// Initialize exccause register to default value (required if current task corrupted)
@ -271,6 +272,7 @@ inline void esp_core_dump_port_init(panic_info_t *info)
if (info->pseudo_excause) {
s_exc_frame->exccause += XCHAL_EXCCAUSE_NUM;
}
s_extra_info.isr_context = isr_context;
}
/**