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ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld

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This commit is contained in:
Wu Jian Gang 2016-08-19 18:28:32 +08:00
parent bce356b700
commit c3102e8fb2
3 changed files with 14 additions and 15 deletions
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15
components/esp32/ld/eagle.fpga32.v7.ld → components/esp32/ld/esp32.common.ld
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@ -1,18 +1,3 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x3fffe000;
/* Default entry point: */
ENTRY(call_user_start_cpu0);

14
components/esp32/ld/esp32.ld Normal file
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@ -0,0 +1,14 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x3fffe000;

0
components/esp32/ld/eagle.fpga32.rom.addr.v7.ld → components/esp32/ld/esp32.rom.ld
View File