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HAL: wrapped emac_ll functions to emac_hal

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Closes #9934
This commit is contained in:
Ondrej Kosta 2023-04-05 14:18:44 +02:00 committed by Ondrej
parent d82eb6942c
commit c231c79fc8
6 changed files with 119 additions and 86 deletions
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43
components/esp_eth/src/esp_eth_mac_esp.c
View File

@ -29,7 +29,6 @@
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "hal/emac_ll.h"
static const char *TAG = "esp.emac";
@ -85,15 +84,15 @@ static esp_err_t emac_esp32_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr,
{
esp_err_t ret = ESP_OK;
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
ESP_GOTO_ON_FALSE(!emac_ll_is_mii_busy(emac->hal.mac_regs), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
emac_ll_set_phy_data(emac->hal.mac_regs, reg_value);
ESP_GOTO_ON_FALSE(!emac_hal_is_mii_busy(&emac->hal), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
emac_hal_set_phy_data(&emac->hal, reg_value);
emac_hal_set_phy_cmd(&emac->hal, phy_addr, phy_reg, true);
/* polling the busy flag */
uint32_t to = 0;
bool busy = true;
do {
esp_rom_delay_us(100);
busy = emac_ll_is_mii_busy(emac->hal.mac_regs);
busy = emac_hal_is_mii_busy(&emac->hal);
to += 100;
} while (busy && to < PHY_OPERATION_TIMEOUT_US);
ESP_GOTO_ON_FALSE(!busy, ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
@ -107,19 +106,19 @@ static esp_err_t emac_esp32_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr,
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(reg_value, ESP_ERR_INVALID_ARG, err, TAG, "can't set reg_value to null");
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
ESP_GOTO_ON_FALSE(!emac_ll_is_mii_busy(emac->hal.mac_regs), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
ESP_GOTO_ON_FALSE(!emac_hal_is_mii_busy(&emac->hal), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
emac_hal_set_phy_cmd(&emac->hal, phy_addr, phy_reg, false);
/* polling the busy flag */
uint32_t to = 0;
bool busy = true;
do {
esp_rom_delay_us(100);
busy = emac_ll_is_mii_busy(emac->hal.mac_regs);
busy = emac_hal_is_mii_busy(&emac->hal);
to += 100;
} while (busy && to < PHY_OPERATION_TIMEOUT_US);
ESP_GOTO_ON_FALSE(!busy, ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
/* Store value */
*reg_value = emac_ll_get_phy_data(emac->hal.mac_regs);
*reg_value = emac_hal_get_phy_data(&emac->hal);
return ESP_OK;
err:
return ret;
@ -175,7 +174,7 @@ static esp_err_t emac_esp32_set_speed(esp_eth_mac_t *mac, eth_speed_t speed)
esp_err_t ret = ESP_ERR_INVALID_ARG;
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
if (speed >= ETH_SPEED_10M && speed < ETH_SPEED_MAX) {
emac_ll_set_port_speed(emac->hal.mac_regs, speed);
emac_hal_set_speed(&emac->hal, speed);
ESP_LOGD(TAG, "working in %dMbps", speed == ETH_SPEED_10M ? 10 : 100);
return ESP_OK;
}
@ -187,7 +186,7 @@ static esp_err_t emac_esp32_set_duplex(esp_eth_mac_t *mac, eth_duplex_t duplex)
esp_err_t ret = ESP_ERR_INVALID_ARG;
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
if (duplex == ETH_DUPLEX_HALF || duplex == ETH_DUPLEX_FULL) {
emac_ll_set_duplex(emac->hal.mac_regs, duplex);
emac_hal_set_duplex(&emac->hal, duplex);
ESP_LOGD(TAG, "working in %s duplex", duplex == ETH_DUPLEX_HALF ? "half" : "full");
return ESP_OK;
}
@ -197,7 +196,7 @@ static esp_err_t emac_esp32_set_duplex(esp_eth_mac_t *mac, eth_duplex_t duplex)
static esp_err_t emac_esp32_set_promiscuous(esp_eth_mac_t *mac, bool enable)
{
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
emac_ll_promiscuous_mode_enable(emac->hal.mac_regs, enable);
emac_hal_set_promiscuous(&emac->hal, enable);
return ESP_OK;
}
@ -305,9 +304,9 @@ static void emac_esp32_rx_task(void *arg)
#if CONFIG_ETH_SOFT_FLOW_CONTROL
// we need to do extra checking of remained frames in case there are no unhandled frames left, but pause frame is still undergoing
if ((emac->free_rx_descriptor < emac->flow_control_low_water_mark) && emac->do_flow_ctrl && emac->frames_remain) {
emac_ll_pause_frame_enable(emac->hal.ext_regs, true);
emac_hal_send_pause_frame(&emac->hal, true);
} else if ((emac->free_rx_descriptor > emac->flow_control_high_water_mark) || !emac->frames_remain) {
emac_ll_pause_frame_enable(emac->hal.ext_regs, false);
emac_hal_send_pause_frame(&emac->hal, false);
}
#endif
} while (emac->frames_remain);
@ -358,10 +357,10 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
emac_esp32_init_smi_gpio(emac);
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL), err, TAG, "lowlevel init failed");
/* software reset */
emac_ll_reset(emac->hal.dma_regs);
emac_hal_reset(&emac->hal);
uint32_t to = 0;
for (to = 0; to < emac->sw_reset_timeout_ms / 10; to++) {
if (emac_ll_is_reset_done(emac->hal.dma_regs)) {
if (emac_hal_is_reset_done(&emac->hal)) {
break;
}
vTaskDelay(pdMS_TO_TICKS(10));
@ -427,7 +426,7 @@ static esp_err_t emac_esp32_stop(esp_eth_mac_t *mac)
static esp_err_t emac_esp32_del(esp_eth_mac_t *mac)
{
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
esp_emac_free_driver_obj(emac, emac->hal.descriptors);
esp_emac_free_driver_obj(emac, emac_hal_get_desc_chain(&emac->hal));
periph_module_disable(PERIPH_EMAC_MODULE);
return ESP_OK;
}
@ -436,13 +435,13 @@ static esp_err_t emac_esp32_del(esp_eth_mac_t *mac)
IRAM_ATTR void emac_isr_default_handler(void *args)
{
emac_hal_context_t *hal = (emac_hal_context_t *)args;
emac_esp32_t *emac = __containerof(hal, emac_esp32_t, hal);
BaseType_t high_task_wakeup = pdFALSE;
uint32_t intr_stat = emac_ll_get_intr_status(hal->dma_regs);
emac_ll_clear_corresponding_intr(hal->dma_regs, intr_stat);
uint32_t intr_stat = emac_hal_get_intr_status(hal);
emac_hal_clear_corresponding_intr(hal, intr_stat);
#if EMAC_LL_CONFIG_ENABLE_INTR_MASK & EMAC_LL_INTR_RECEIVE_ENABLE
if (intr_stat & EMAC_LL_DMA_RECEIVE_FINISH_INTR) {
emac_esp32_t *emac = __containerof(hal, emac_esp32_t, hal);
BaseType_t high_task_wakeup = pdFALSE;
/* notify receive task */
vTaskNotifyGiveFromISR(emac->rx_task_hdl, &high_task_wakeup);
if (high_task_wakeup == pdTRUE) {
@ -537,7 +536,7 @@ static esp_err_t esp_emac_config_data_interface(const eth_esp32_emac_config_t *e
/* MII interface GPIO initialization */
emac_hal_iomux_init_mii();
/* Enable MII clock */
emac_ll_clock_enable_mii(emac->hal.ext_regs);
emac_hal_clock_enable_mii(&emac->hal);
break;
case EMAC_DATA_INTERFACE_RMII:
// by default, the clock mode is selected at compile time (by Kconfig)
@ -569,7 +568,7 @@ static esp_err_t esp_emac_config_data_interface(const eth_esp32_emac_config_t *e
ESP_GOTO_ON_FALSE(emac->clock_config.rmii.clock_gpio == EMAC_CLK_IN_GPIO,
ESP_ERR_INVALID_ARG, err, TAG, "ESP32 EMAC only support input RMII clock to GPIO0");
emac_hal_iomux_rmii_clk_input();
emac_ll_clock_enable_rmii_input(emac->hal.ext_regs);
emac_hal_clock_enable_rmii_input(&emac->hal);
} else if (emac->clock_config.rmii.clock_mode == EMAC_CLK_OUT) {
ESP_GOTO_ON_FALSE(emac->clock_config.rmii.clock_gpio == EMAC_APPL_CLK_OUT_GPIO ||
emac->clock_config.rmii.clock_gpio == EMAC_CLK_OUT_GPIO ||
@ -580,7 +579,7 @@ static esp_err_t esp_emac_config_data_interface(const eth_esp32_emac_config_t *e
REG_SET_FIELD(PIN_CTRL, CLK_OUT1, 6);
}
/* Enable RMII clock */
emac_ll_clock_enable_rmii_output(emac->hal.ext_regs);
emac_hal_clock_enable_rmii_output(&emac->hal);
// Power up APLL clock
periph_rtc_apll_acquire();
ESP_GOTO_ON_ERROR(emac_config_apll_clock(), err, TAG, "Configure APLL for RMII failed");

99
components/hal/include/hal/emac_hal.h
View File

@ -15,9 +15,7 @@ extern "C" {
#include "esp_assert.h"
#include "esp_err.h"
#include "hal/eth_types.h"
#include "soc/emac_dma_struct.h"
#include "soc/emac_mac_struct.h"
#include "soc/emac_ext_struct.h"
#include "hal/emac_ll.h"
/**
* @brief Indicate to ::emac_hal_receive_frame that receive frame buffer was allocated by ::emac_hal_alloc_recv_buf
@ -159,10 +157,14 @@ typedef struct {
ESP_STATIC_ASSERT(sizeof(eth_dma_rx_descriptor_t) == 32, "eth_dma_rx_descriptor_t should occupy 32 bytes in memory");
volatile typedef struct emac_mac_dev_t *emac_mac_soc_regs_t;
volatile typedef struct emac_dma_dev_t *emac_dma_soc_regs_t;
volatile typedef struct emac_ext_dev_t *emac_ext_soc_regs_t;
typedef struct {
emac_mac_dev_t *mac_regs;
emac_dma_dev_t *dma_regs;
emac_ext_dev_t *ext_regs;
emac_mac_soc_regs_t mac_regs;
emac_dma_soc_regs_t dma_regs;
emac_ext_soc_regs_t ext_regs;
uint8_t **rx_buf;
uint8_t **tx_buf;
void *descriptors;
@ -193,11 +195,37 @@ void emac_hal_iomux_init_tx_er(void);
void emac_hal_iomux_init_rx_er(void);
static inline void emac_hal_clock_enable_mii(emac_hal_context_t *hal)
{
emac_ll_clock_enable_mii(hal->ext_regs);
}
static inline void emac_hal_clock_enable_rmii_input(emac_hal_context_t *hal)
{
emac_ll_clock_enable_rmii_input(hal->ext_regs);
}
static inline void emac_hal_clock_enable_rmii_output(emac_hal_context_t *hal)
{
emac_ll_clock_enable_rmii_output(hal->ext_regs);
}
void emac_hal_reset_desc_chain(emac_hal_context_t *hal);
void emac_hal_reset(emac_hal_context_t *hal);
static inline void *emac_hal_get_desc_chain(emac_hal_context_t *hal)
{
return hal->descriptors;
}
bool emac_hal_is_reset_done(emac_hal_context_t *hal);
static inline void emac_hal_reset(emac_hal_context_t *hal)
{
emac_ll_reset(hal->dma_regs);
}
static inline bool emac_hal_is_reset_done(emac_hal_context_t *hal)
{
return emac_ll_is_reset_done(hal->dma_regs);
}
void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq);
@ -205,24 +233,45 @@ void emac_hal_init_mac_default(emac_hal_context_t *hal);
void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *hal_config);
void emac_hal_set_speed(emac_hal_context_t *hal, uint32_t speed);
static inline void emac_hal_set_speed(emac_hal_context_t *hal, eth_speed_t speed)
{
emac_ll_set_port_speed(hal->mac_regs, speed);
}
void emac_hal_set_duplex(emac_hal_context_t *hal, eth_duplex_t duplex);
static inline void emac_hal_set_duplex(emac_hal_context_t *hal, eth_duplex_t duplex)
{
emac_ll_set_duplex(hal->mac_regs, duplex);
}
void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable);
static inline void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable)
{
emac_ll_promiscuous_mode_enable(hal->mac_regs, enable);
}
/**
* @brief Send MAC-CTRL frames to peer (EtherType=0x8808, opcode=0x0001, dest_addr=MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01))
*/
void emac_hal_send_pause_frame(emac_hal_context_t *hal, bool enable);
static inline void emac_hal_send_pause_frame(emac_hal_context_t *hal, bool enable)
{
emac_ll_pause_frame_enable(hal->ext_regs, enable);
}
bool emac_hal_is_mii_busy(emac_hal_context_t *hal);
static inline bool emac_hal_is_mii_busy(emac_hal_context_t *hal)
{
return emac_ll_is_mii_busy(hal->mac_regs);
}
void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write);
void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value);
static inline void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value)
{
emac_ll_set_phy_data(hal->mac_regs, reg_value);
}
uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal);
static inline uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal)
{
return emac_ll_get_phy_data(hal->mac_regs);
}
void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
@ -308,13 +357,25 @@ uint32_t emac_hal_flush_recv_frame(emac_hal_context_t *hal, uint32_t *frames_rem
void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable);
uint32_t emac_hal_get_intr_enable_status(emac_hal_context_t *hal);
static inline uint32_t emac_hal_get_intr_enable_status(emac_hal_context_t *hal)
{
return emac_ll_get_intr_enable_status(hal->dma_regs);
}
uint32_t emac_hal_get_intr_status(emac_hal_context_t *hal);
static inline uint32_t emac_hal_get_intr_status(emac_hal_context_t *hal)
{
return emac_ll_get_intr_status(hal->dma_regs);
}
void emac_hal_clear_corresponding_intr(emac_hal_context_t *hal, uint32_t bits);
static inline void emac_hal_clear_corresponding_intr(emac_hal_context_t *hal, uint32_t bits)
{
emac_ll_clear_corresponding_intr(hal->dma_regs, bits);
}
void emac_hal_clear_all_intr(emac_hal_context_t *hal);
static inline void emac_hal_clear_all_intr(emac_hal_context_t *hal)
{
emac_ll_clear_all_pending_intr(hal->dma_regs);
}
#ifdef __cplusplus
}

20
components/soc/esp32/include/soc/emac_dma_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
@ -20,7 +12,7 @@ extern "C"
#include <stdint.h>
typedef volatile struct emac_dma_dev_s {
typedef volatile struct emac_dma_dev_t {
union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/

20
components/soc/esp32/include/soc/emac_ext_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
@ -19,7 +11,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct emac_ext_dev_s {
typedef volatile struct emac_ext_dev_t {
union {
struct {
uint32_t div_num : 4;

20
components/soc/esp32/include/soc/emac_mac_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
@ -19,7 +11,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct emac_mac_dev_s {
volatile typedef struct emac_mac_dev_t {
union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/

3
tools/ci/check_copyright_ignore.txt
View File

@ -768,9 +768,6 @@ components/soc/esp32/include/soc/apb_ctrl_reg.h
components/soc/esp32/include/soc/apb_ctrl_struct.h
components/soc/esp32/include/soc/bb_reg.h
components/soc/esp32/include/soc/boot_mode.h
components/soc/esp32/include/soc/emac_dma_struct.h
components/soc/esp32/include/soc/emac_ext_struct.h
components/soc/esp32/include/soc/emac_mac_struct.h
components/soc/esp32/include/soc/fe_reg.h
components/soc/esp32/include/soc/flash_encryption_reg.h
components/soc/esp32/include/soc/gpio_pins.h