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Merge branch 'bugfix/bootloader_min_revision_c3' into 'master'

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Fix bootloader minimum revision check and print for ESP32-C3

Closes IDFGH-5106

See merge request espressif/esp-idf!13248
This commit is contained in:
Mahavir Jain 2021-04-21 04:41:47 +00:00
commit c22805e94b
4 changed files with 8 additions and 5 deletions
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4
components/bootloader_support/src/bootloader_common_loader.c
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@ -77,7 +77,9 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
} }
uint8_t revision = bootloader_common_get_chip_revision(); uint8_t revision = bootloader_common_get_chip_revision();
if (revision < img_hdr->min_chip_rev) { if (revision < img_hdr->min_chip_rev) {
ESP_LOGE(TAG, "can't run on lower chip revision, expected %d, found %d", revision, img_hdr->min_chip_rev); /* To fix this error, please update mininum supported chip revision from configuration,
* located in TARGET (e.g. ESP32) specific options under "Component config" menu */
ESP_LOGE(TAG, "This chip is revision %d but the application is configured for minimum revision %d. Can't run.", revision, img_hdr->min_chip_rev);
err = ESP_FAIL; err = ESP_FAIL;
} else if (revision != img_hdr->min_chip_rev) { } else if (revision != img_hdr->min_chip_rev) {
#ifdef BOOTLOADER_BUILD #ifdef BOOTLOADER_BUILD

7
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@ -263,15 +263,15 @@ static void bootloader_super_wdt_auto_feed(void)
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0); REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
} }
#if CONFIG_ESP32C3_REV_MIN < 3
static inline void bootloader_hardware_init(void) static inline void bootloader_hardware_init(void)
{ {
// This check is always included in the bootloader so it can
// print the minimum revision error message later in the boot
if (bootloader_common_get_chip_revision() < 3) { if (bootloader_common_get_chip_revision() < 3) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1); REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12); REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
} }
} }
#endif
static inline void bootloader_glitch_reset_disable(void) static inline void bootloader_glitch_reset_disable(void)
{ {
@ -286,9 +286,8 @@ static inline void bootloader_glitch_reset_disable(void)
esp_err_t bootloader_init(void) esp_err_t bootloader_init(void)
{ {
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
#if CONFIG_ESP32C3_REV_MIN < 3
bootloader_hardware_init(); bootloader_hardware_init();
#endif
bootloader_glitch_reset_disable(); bootloader_glitch_reset_disable();
bootloader_super_wdt_auto_feed(); bootloader_super_wdt_auto_feed();
// protect memory region // protect memory region

1
tools/test_apps/system/bootloader_sections/sdkconfig.ci.flash_encryption
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@ -1,2 +1,3 @@
CONFIG_SECURE_FLASH_ENC_ENABLED=y CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y
CONFIG_PARTITION_TABLE_OFFSET=0xA000

1
tools/test_apps/system/build_test/sdkconfig.ci.flash_encryption_release
View File

@ -1,2 +1,3 @@
CONFIG_SECURE_FLASH_ENC_ENABLED=y CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y
CONFIG_PARTITION_TABLE_OFFSET=0xA000