From c1bdd9c6978cef73707a75622a2249169ac35eac Mon Sep 17 00:00:00 2001 From: gaoxu Date: Fri, 16 Sep 2022 14:43:52 +0800 Subject: [PATCH] psram: remove CS/CLK pin settings in kconfig on ESP32S2/S3 --- components/esp_psram/esp32s2/Kconfig.spiram | 21 ++++++------------- .../esp_psram/esp32s2/esp_psram_impl_quad.c | 4 ++-- components/esp_psram/esp32s3/Kconfig.spiram | 21 ++++++------------- .../esp_psram/esp32s3/esp_psram_impl_octal.c | 2 +- .../esp_psram/esp32s3/esp_psram_impl_quad.c | 4 ++-- components/esp_psram/sdkconfig.rename.esp32s2 | 5 +++++ components/esp_psram/sdkconfig.rename.esp32s3 | 5 +++++ 7 files changed, 27 insertions(+), 35 deletions(-) create mode 100644 components/esp_psram/sdkconfig.rename.esp32s2 create mode 100644 components/esp_psram/sdkconfig.rename.esp32s3 diff --git a/components/esp_psram/esp32s2/Kconfig.spiram b/components/esp_psram/esp32s2/Kconfig.spiram index 4f6d701100..4277a21df7 100644 --- a/components/esp_psram/esp32s2/Kconfig.spiram +++ b/components/esp_psram/esp32s2/Kconfig.spiram @@ -40,22 +40,13 @@ menu "SPI RAM config" This should only be used for tasks where the stack is never accessed while the cache is disabled. Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH. - menu "PSRAM clock and cs IO for ESP32S2" - depends on SPIRAM - config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. + config SPIRAM_CLK_IO + int + default 30 - config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - endmenu + config SPIRAM_CS_IO + int + default 26 config SPIRAM_FETCH_INSTRUCTIONS bool "Move Instructions in Flash to PSRAM" diff --git a/components/esp_psram/esp32s2/esp_psram_impl_quad.c b/components/esp_psram/esp32s2/esp_psram_impl_quad.c index 448100acbc..8d039f27f9 100644 --- a/components/esp_psram/esp32s2/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s2/esp_psram_impl_quad.c @@ -72,8 +72,8 @@ static const char* TAG = "quad_psram"; #define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM // PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 -#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 +#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM +#define PSRAM_CS_IO SPI_CS1_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM diff --git a/components/esp_psram/esp32s3/Kconfig.spiram b/components/esp_psram/esp32s3/Kconfig.spiram index 0b37d84f23..ac67b35ce1 100644 --- a/components/esp_psram/esp32s3/Kconfig.spiram +++ b/components/esp_psram/esp32s3/Kconfig.spiram @@ -49,22 +49,13 @@ menu "SPI RAM config" This should only be used for tasks where the stack is never accessed while the cache is disabled. Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH. - menu "PSRAM Clock and CS IO for ESP32S3" - depends on SPIRAM - config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. + config SPIRAM_CLK_IO + int + default 30 - config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. - endmenu + config SPIRAM_CS_IO + int + default 26 config SPIRAM_FETCH_INSTRUCTIONS bool "Move Instructions in Flash to PSRAM" diff --git a/components/esp_psram/esp32s3/esp_psram_impl_octal.c b/components/esp_psram/esp32s3/esp_psram_impl_octal.c index 24f6bc0b3e..b1e50896bc 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_octal.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_octal.c @@ -29,7 +29,7 @@ #define OCT_PSRAM_ADDR_BITLEN 32 #define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) -#define OCT_PSRAM_CS1_IO CONFIG_DEFAULT_PSRAM_CS_IO +#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM #define OCT_PSRAM_CS_SETUP_TIME 3 #define OCT_PSRAM_CS_HOLD_TIME 3 diff --git a/components/esp_psram/esp32s3/esp_psram_impl_quad.c b/components/esp_psram/esp32s3/esp_psram_impl_quad.c index 5b7b677020..3a2cad377b 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_quad.c @@ -68,8 +68,8 @@ static const char* TAG = "quad_psram"; #define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM // PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 -#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 +#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM +#define PSRAM_CS_IO SPI_CS1_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM diff --git a/components/esp_psram/sdkconfig.rename.esp32s2 b/components/esp_psram/sdkconfig.rename.esp32s2 new file mode 100644 index 0000000000..3c7ba13acf --- /dev/null +++ b/components/esp_psram/sdkconfig.rename.esp32s2 @@ -0,0 +1,5 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO +CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO diff --git a/components/esp_psram/sdkconfig.rename.esp32s3 b/components/esp_psram/sdkconfig.rename.esp32s3 new file mode 100644 index 0000000000..3c7ba13acf --- /dev/null +++ b/components/esp_psram/sdkconfig.rename.esp32s3 @@ -0,0 +1,5 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO +CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO