From a633704790c6c382a4c328e3b325cc4a0a5b68e0 Mon Sep 17 00:00:00 2001 From: Wang Fang Date: Sat, 2 Apr 2022 11:01:13 +0800 Subject: [PATCH] docs: update dedicated gpio doc for esp32-c3 --- .../api-reference/peripherals/dedic_gpio.rst | 54 ++++++++++++++----- 1 file changed, 41 insertions(+), 13 deletions(-) diff --git a/docs/en/api-reference/peripherals/dedic_gpio.rst b/docs/en/api-reference/peripherals/dedic_gpio.rst index 89b83e948b..8be795c283 100644 --- a/docs/en/api-reference/peripherals/dedic_gpio.rst +++ b/docs/en/api-reference/peripherals/dedic_gpio.rst @@ -72,8 +72,20 @@ GPIO Bundle Operations * - Read the value that output from bundle - :cpp:func:`dedic_gpio_bundle_read_in` -.. note:: - The functions above just wrap the customized instructions defined for {IDF_TARGET_NAME}, for the details of those instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. +.. only:: esp32s2 + + .. note:: + The functions above just wrap the customized instructions defined for {IDF_TARGET_NAME}, for the details of those instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. + +.. only:: esp32s3 + + .. note:: + The functions above just wrap the customized instructions defined for {IDF_TARGET_NAME}, for the details of those instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *Processor Instruction Extensions (PIE) (to be added later)* [`PDF <{IDF_TARGET_TRM_EN_URL}#pie>`__]. + +.. only:: esp32c2 or esp32c3 + + .. note:: + The functions above just wrap the customized instructions defined for {IDF_TARGET_NAME}, for the details of those instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *ESP-RISC-V CPU* [`PDF <{IDF_TARGET_TRM_EN_URL}#riscvcpu>`__]. .. only:: SOC_DEDIC_GPIO_HAS_INTERRUPT @@ -114,25 +126,41 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod 3. Call CPU LL apis (e.g. `cpu_ll_write_dedic_gpio_mask`) or write assembly code with that mask 4. The fasted way of toggling IO is to use the dedicated "set/clear" instructions: -+----------+---------------------------+---------------------------+------------------------------------------------------------------------+ -| CPU Arch | Set bits of GPIO | Clear bits of GPIO | Remarks | -+==========+===========================+===========================+========================================================================+ -| Xtensa | set_bit_gpio_out imm[7:0] | clr_bit_gpio_out imm[7:0] | immediate value width depends on the number of dedicated GPIO channels | -+----------+---------------------------+---------------------------+------------------------------------------------------------------------+ -| RISC-V | csrrsi rd, csr, imm[4:0] | csrrci rd, csr, imm[4:0] | can only control the lowest 4 GPIO channels | -+----------+---------------------------+---------------------------+------------------------------------------------------------------------+ + .. only:: esp32s2 or esp32s3 + - Set bits of GPIO: ``set_bit_gpio_out imm[7:0]`` + - Clear bits of GPIO: ``clr_bit_gpio_out imm[7:0]`` + - Note: Immediate value width depends on the number of dedicated GPIO channels -For details of supported dedicated GPIO instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. The supported dedicated CPU instructions are also wrapped inside `soc/cpu_ll.h` as helper inline functions. + .. only:: esp32c2 or esp32c3 + + - Set bits of GPIO: ``csrrsi rd, csr, imm[4:0]`` + - Clear bits of GPIO: ``csrrci rd, csr, imm[4:0]`` + - Note: Can only control the lowest 4 GPIO channels + +.. only:: esp32s2 + + For details of supported dedicated GPIO instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. + +.. only:: esp32s3 + + For details of supported dedicated GPIO instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *Processor Instruction Extensions (PIE) (to be added later)* [`PDF <{IDF_TARGET_TRM_EN_URL}#pie>`__]. + +.. only:: esp32c2 or esp32c3 + + For details of supported dedicated GPIO instructions, please refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *ESP-RISC-V CPU* [`PDF <{IDF_TARGET_TRM_EN_URL}#riscvcpu>`__]. + +The supported dedicated CPU instructions are also wrapped inside `soc/cpu_ll.h` as helper inline functions. .. note:: Writing assembly code in application could make your code hard to port between targets, because those customized instructions are not guaranteed to remain the same format on different targets. +.. only:: esp32s2 -Application Example -------------------- + Application Example + ------------------- -Matrix keyboard example based on dedicated GPIO: :example:`peripherals/gpio/matrix_keyboard`. + Matrix keyboard example based on dedicated GPIO: :example:`peripherals/gpio/matrix_keyboard`. API Reference