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change(pm): add pm lock count check before reg backup
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parent
15df836ab4
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c1798adac6
@ -196,6 +196,9 @@ static const char* TAG = "pm";
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static void do_switch(pm_mode_t new_mode);
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static void leave_idle(void);
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static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
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#if SOC_PM_RETENTION_HAS_CLOCK_BUG
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static size_t esp_pm_get_total_lock_count(void);
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#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
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pm_mode_t esp_pm_impl_get_mode(esp_pm_lock_type_t type, int arg)
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{
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@ -972,7 +975,9 @@ void esp_pm_impl_idle_hook(void)
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it is necessary to back up the mac/bb REG before disabling the PLL clock.
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*/
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#if SOC_PM_RETENTION_HAS_CLOCK_BUG
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mac_bb_power_down_prepare();
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if (esp_pm_get_total_lock_count() <= portNUM_PROCESSORS) {
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mac_bb_power_down_prepare();
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}
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#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
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esp_pm_lock_release(s_rtos_lock_handle[core_id]);
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s_core_idle[core_id] = true;
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@ -1037,3 +1042,16 @@ void esp_pm_impl_waiti(void)
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esp_cpu_wait_for_intr();
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#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
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}
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#if SOC_PM_RETENTION_HAS_CLOCK_BUG
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static size_t esp_pm_get_total_lock_count(void)
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{
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size_t all_mode_lock_counts = 0;
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portENTER_CRITICAL(&s_switch_lock);
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for (int i = 0; i < ARRAY_SIZE(s_mode_lock_counts); i++) {
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all_mode_lock_counts += s_mode_lock_counts[i];
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}
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portEXIT_CRITICAL(&s_switch_lock);
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return all_mode_lock_counts;
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}
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#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
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