From 8db219c292d77426a382b31ed02ee49f5ed43c0b Mon Sep 17 00:00:00 2001
From: Omar Chebib <omar.chebib@espressif.com>
Date: Tue, 9 Mar 2021 14:18:28 +0800
Subject: [PATCH] hal: workaround for UART FIFO read on ESP32 with -O2
 optimization

---
 components/soc/esp32/include/hal/uart_ll.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/components/soc/esp32/include/hal/uart_ll.h b/components/soc/esp32/include/hal/uart_ll.h
index 1b70503527..33002ca47a 100644
--- a/components/soc/esp32/include/hal/uart_ll.h
+++ b/components/soc/esp32/include/hal/uart_ll.h
@@ -167,6 +167,9 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
     uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
     for(uint32_t i = 0; i < rd_len; i++) {
         buf[i] = READ_PERI_REG(fifo_addr);
+#ifdef CONFIG_COMPILER_OPTIMIZATION_PERF
+        __asm__ __volatile__("nop");
+#endif
     }
 }