From c101fc3e3df30ee24d1527acc28c2ac7051b5aab Mon Sep 17 00:00:00 2001 From: chaijie Date: Fri, 26 Mar 2021 17:24:46 +0800 Subject: [PATCH] fix c3 hardware bug before ECO3 and optimizate bbpll config: 1. deepsleep poweron reset bug in high temperature before ECO3; 2. brownout reset bug before ECO2; 3. bbpll voltage low bug before ECO3; 4. need xpd iph for xtal before ECO3; --- .../src/esp32c3/bootloader_esp32c3.c | 23 +++++++++++-------- .../esp_hw_support/port/esp32c3/rtc_clk.c | 2 ++ .../esp_hw_support/port/esp32c3/rtc_sleep.c | 13 +++++++---- .../soc/esp32c3/include/soc/rtc_cntl_reg.h | 4 ++++ 4 files changed, 28 insertions(+), 14 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index b017f76624..e2ef082005 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -263,27 +263,32 @@ static void bootloader_super_wdt_auto_feed(void) REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0); } +#if CONFIG_ESP32C3_REV_MIN < 3 static inline void bootloader_hardware_init(void) { - // TODO ESP32-C3 IDF-2452 - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1); - REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12); + if (bootloader_common_get_chip_revision() < 3) { + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1); + REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12); + } } +#endif -/* There happend clock glitch reset for some chip when testing wifi[BIT0] and brownout reset when chip startup[BIT1]. - * But super_watch_dog_reset function is ok, so open it[BIT2]. - * Whether this api will deleted or not depends on analog design & test result when ECO chip come back. - */ static inline void bootloader_glitch_reset_disable(void) { - // TODO ESP32-C3 IDF-2453 - REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, BIT2); + uint8_t chip_version = bootloader_common_get_chip_revision(); + if (chip_version < 2) { + REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); + } else { + REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST); + } } esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; +#if CONFIG_ESP32C3_REV_MIN < 3 bootloader_hardware_init(); +#endif bootloader_glitch_reset_disable(); bootloader_super_wdt_auto_feed(); // protect memory region diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 7b52bebae8..cf1f6abc5e 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -301,6 +301,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); s_cur_pll_freq = pll_freq; } diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index c03b98295f..d86cf2c7e3 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -29,6 +29,7 @@ #include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/rtc.h" #include "regi2c_ctrl.h" +#include "esp_efuse.h" /** * Configure whether certain peripherals are powered down in deep sleep @@ -95,11 +96,13 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) if (cfg.deep_slp) { REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - /* It's only a temporary configuration to set dbg 0 to make deepsleep run successfully when in high temperature. - we will restore it to RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT when ECO chip come back. - TODO ESP32-C3 IDF-2568 - */ - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, 0); + unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + #if CONFIG_ESP32C3_REV_MIN < 3 + if (esp_efuse_get_chip_ver() < 3) { + atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */ + } + #endif + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, atten_deep_sleep); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h index fe96988307..b25f644832 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -2362,6 +2362,10 @@ extern "C" { #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: */