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rtc_clk: Fix rtc8m calibration failure after cpu/core reset

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Explicitly guarantee 8md256 clk is enabled before calibration
This commit is contained in:
Song Ruo Jing 2022-10-12 12:33:47 +08:00
parent 9e863ecdb8
commit c0be4cb2ba
4 changed files with 16 additions and 0 deletions
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4
components/esp_hw_support/port/esp32/rtc_time.c
View File

@ -49,7 +49,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* Prepare calibration */
@ -100,6 +103,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
if (timeout_us == 0) {
/* timed out waiting for calibration */

4
components/esp_hw_support/port/esp32c3/rtc_time.c
View File

@ -58,7 +58,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* There may be another calibration process already running during we call this function,
@ -116,6 +119,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
return cal_val;

4
components/esp_hw_support/port/esp32s2/rtc_time.c
View File

@ -161,7 +161,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
@ -178,6 +181,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
return cal_val;

4
components/esp_hw_support/port/esp32s3/rtc_time.c
View File

@ -57,7 +57,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* There may be another calibration process already running during we call this function,
@ -115,6 +118,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
return cal_val;