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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/spi_slave_hd_dual_test_for_segment_mode' into 'master'
spi slave hd: add a dual test for segment mode when master's transactions are too long See merge request espressif/esp-idf!11176
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commit
bdaac823e3
@ -526,8 +526,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
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slave_send_buf[i] = rand();
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}
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//make the first transaction short, so that the second one will be loaded while the master is
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//still doing the first transaction.
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//make the first transaction shorter than the actual trans length of the master, so that the second one will be loaded while the master is still doing the first transaction.
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int trans_len[] = {5, send_buf_size};
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spi_slave_hd_data_t slave_trans[4] = {
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//recv, the buffer size should be aligned to 4
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@ -593,3 +592,166 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
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#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#endif //#if !DISABLED_FOR_TARGETS(ESP32C3)
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#if !DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3)
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#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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//These tests are for chips which only have 1 SPI controller
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/********************************************************************************
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* Test By Master & Slave (2 boards)
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*
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* PIN | Master(C3) | Slave (C3) |
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* ----| --------- | --------- |
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* CS | 10 | 10 |
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* CLK | 6 | 6 |
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* MOSI| 7 | 7 |
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* MISO| 2 | 2 |
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* GND | GND | GND |
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*
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********************************************************************************/
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#include "driver/spi_slave_hd.h"
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#include "unity.h"
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#include "test/test_common_spi.h"
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static void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size)
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{
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srand(199);
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for (int i = 0; i < send_buf_size * 2; i++) {
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slave_send_buf[i] = rand();
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master_send_buf[i] = rand();
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}
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}
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static void hd_master(void)
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{
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO));
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spi_device_handle_t spi;
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX;
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dev_cfg.command_bits = 8;
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dev_cfg.address_bits = 8;
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dev_cfg.dummy_bits = 8;
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dev_cfg.clock_speed_hz = 100 * 1000;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
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const int send_buf_size = 1024;
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WORD_ALIGNED_ATTR uint8_t *master_send_buf = malloc(send_buf_size * 2);
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WORD_ALIGNED_ATTR uint8_t *master_recv_buf = calloc(1, send_buf_size * 2);
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//This buffer is used for 2-board test and should be assigned totally the same as the ``hd_slave`` does.
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WORD_ALIGNED_ATTR uint8_t *slave_send_buf = malloc(send_buf_size * 2);
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get_tx_buffer(199, master_send_buf, slave_send_buf, send_buf_size);
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//This is the same as the ``hd_slave`` sets.
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int trans_len[] = {5, send_buf_size};
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unity_wait_for_signal("slave ready");
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essl_spi_wrdma(spi, master_send_buf, send_buf_size, -1, 0);
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unity_wait_for_signal("slave ready");
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essl_spi_wrdma(spi, master_send_buf + send_buf_size, send_buf_size, 5, 0);
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unity_wait_for_signal("slave ready");
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essl_spi_rddma(spi, master_recv_buf, send_buf_size, -1, 0);
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spitest_cmp_or_dump(slave_send_buf, master_recv_buf, trans_len[0]);
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unity_wait_for_signal("slave ready");
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essl_spi_rddma(spi, master_recv_buf + send_buf_size, send_buf_size, 5, 0);
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spitest_cmp_or_dump(slave_send_buf + send_buf_size, master_recv_buf + send_buf_size, trans_len[1]);
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free(master_recv_buf);
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free(master_send_buf);
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free(slave_send_buf);
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master_free_device_bus(spi);
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}
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static void hd_slave(void)
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{
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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bus_cfg.max_transfer_sz = 14000 * 30;
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spi_slave_hd_slot_config_t slave_hd_cfg = {
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.spics_io_num = PIN_NUM_CS,
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.dma_chan = SPI_DMA_CH_AUTO,
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.flags = 0,
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.mode = 0,
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.command_bits = 8,
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.address_bits = 8,
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.dummy_bits = 8,
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.queue_size = 10,
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};
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TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg));
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const int send_buf_size = 1024;
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WORD_ALIGNED_ATTR uint8_t *slave_send_buf = malloc(send_buf_size * 2);
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WORD_ALIGNED_ATTR uint8_t *slave_recv_buf = calloc(1, send_buf_size * 2);
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//This buffer is used for 2-board test and should be assigned totally the same as the ``hd_master`` does.
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WORD_ALIGNED_ATTR uint8_t *master_send_buf = malloc(send_buf_size * 2);
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get_tx_buffer(199, master_send_buf, slave_send_buf, send_buf_size);
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//make the first transaction shorter than the actual trans length of the master, so that the second one will be loaded while the master is still doing the first transaction.
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int trans_len[] = {5, send_buf_size};
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spi_slave_hd_data_t slave_trans[4] = {
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//recv, the buffer size should be aligned to 4
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{
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.data = slave_recv_buf,
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.len = (trans_len[0] + 3) & (~3),
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},
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{
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.data = slave_recv_buf + send_buf_size,
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.len = (trans_len[1] + 3) & (~3),
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},
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//send
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{
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.data = slave_send_buf,
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.len = trans_len[0],
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},
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{
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.data = slave_send_buf + send_buf_size,
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.len = trans_len[1],
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},
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};
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for (int i = 0; i < 2; i ++) {
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TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &slave_trans[i], portMAX_DELAY));
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unity_send_signal("slave ready");
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}
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for (int i = 2; i < 4; i ++) {
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TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &slave_trans[i], portMAX_DELAY));
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unity_send_signal("slave ready");
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}
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for (int i = 0; i < 2; i ++) {
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spi_slave_hd_data_t *ret_trans;
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TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
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TEST_ASSERT(ret_trans == &slave_trans[i]);
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TEST_ASSERT_EQUAL(slave_trans[i].len, ret_trans->trans_len);
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}
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for (int i = 2; i < 4; i ++) {
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spi_slave_hd_data_t *ret_trans;
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TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
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TEST_ASSERT(ret_trans == &slave_trans[i]);
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}
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spitest_cmp_or_dump(master_send_buf, slave_recv_buf, trans_len[0]);
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spitest_cmp_or_dump(master_send_buf + send_buf_size, slave_recv_buf + send_buf_size, trans_len[1]);
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free(slave_recv_buf);
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free(slave_send_buf);
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free(master_send_buf);
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spi_slave_hd_deinit(TEST_SLAVE_HOST);
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}
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TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: segment mode, master sends too long", "[spi_ms][test_env=Example_SPI_Multi_device]", hd_master, hd_slave);
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#endif //#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#endif //#if !DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3)
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