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synced 2024-10-05 20:47:46 -04:00
fix(usb/host): remove bInterval verification during pipe opening for INTR and ISOC EPs
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4cf3acb594
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@ -137,7 +137,7 @@ const fifo_mps_limits_t mps_limits_bias_ptx = {
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#define XFER_LIST_LEN_CTRL 3 // One descriptor for each stage
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#define XFER_LIST_LEN_CTRL 3 // One descriptor for each stage
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#define XFER_LIST_LEN_BULK 2 // One descriptor for transfer, one to support an extra zero length packet
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#define XFER_LIST_LEN_BULK 2 // One descriptor for transfer, one to support an extra zero length packet
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#define XFER_LIST_LEN_INTR 32
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#define XFER_LIST_LEN_INTR FRAME_LIST_LEN
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#define XFER_LIST_LEN_ISOC FRAME_LIST_LEN // Same length as the frame list makes it easier to schedule. Must be power of 2
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#define XFER_LIST_LEN_ISOC FRAME_LIST_LEN // Same length as the frame list makes it easier to schedule. Must be power of 2
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// ------------------------ Flags --------------------------
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// ------------------------ Flags --------------------------
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@ -1642,22 +1642,6 @@ static bool pipe_alloc_hcd_support_verification(const usb_ep_desc_t *ep_desc, co
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return false;
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return false;
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}
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}
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// Check if the pipe's interval is compatible with the periodic frame list's length
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if (type == USB_TRANSFER_TYPE_INTR &&
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(ep_desc->bInterval > FRAME_LIST_LEN)) {
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ESP_LOGE(HCD_DWC_TAG, "bInterval value (%d) of Interrupt pipe exceeds max supported limit",
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ep_desc->bInterval);
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return false;
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}
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if (type == USB_TRANSFER_TYPE_ISOCHRONOUS &&
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((1 << (ep_desc->bInterval - 1)) > FRAME_LIST_LEN)) {
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// (where 0 < 2^(bInterval - 1) <= FRAME_LIST_LEN)
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ESP_LOGE(HCD_DWC_TAG, "bInterval value (%d) of Isochronous pipe exceeds max supported limit",
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ep_desc->bInterval);
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return false;
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}
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// Check if pipe MPS exceeds HCD MPS limits (due to DWC FIFO sizing)
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// Check if pipe MPS exceeds HCD MPS limits (due to DWC FIFO sizing)
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int limit;
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int limit;
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if (USB_EP_DESC_GET_EP_DIR(ep_desc)) { // IN
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if (USB_EP_DESC_GET_EP_DIR(ep_desc)) { // IN
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@ -1710,12 +1694,16 @@ static void pipe_set_ep_char(const hcd_pipe_config_t *pipe_config, usb_transfer_
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ep_char->dev_addr = pipe_config->dev_addr;
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ep_char->dev_addr = pipe_config->dev_addr;
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ep_char->ls_via_fs_hub = (port_speed == USB_SPEED_FULL && pipe_config->dev_speed == USB_SPEED_LOW);
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ep_char->ls_via_fs_hub = (port_speed == USB_SPEED_FULL && pipe_config->dev_speed == USB_SPEED_LOW);
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// Calculate the pipe's interval in terms of USB frames
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// Calculate the pipe's interval in terms of USB frames
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// @see USB-OTG programming guide chapter 6.5 for more information
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if (type == USB_TRANSFER_TYPE_INTR || type == USB_TRANSFER_TYPE_ISOCHRONOUS) {
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if (type == USB_TRANSFER_TYPE_INTR || type == USB_TRANSFER_TYPE_ISOCHRONOUS) {
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int interval_frames;
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unsigned int interval_frames;
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unsigned int xfer_list_len;
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if (type == USB_TRANSFER_TYPE_INTR) {
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if (type == USB_TRANSFER_TYPE_INTR) {
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interval_frames = pipe_config->ep_desc->bInterval;
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interval_frames = pipe_config->ep_desc->bInterval;
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xfer_list_len = XFER_LIST_LEN_INTR;
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} else {
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} else {
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interval_frames = (1 << (pipe_config->ep_desc->bInterval - 1));
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interval_frames = (1 << (pipe_config->ep_desc->bInterval - 1));
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xfer_list_len = XFER_LIST_LEN_ISOC;
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}
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}
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// Round down interval to nearest power of 2
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// Round down interval to nearest power of 2
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if (interval_frames >= 32) {
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if (interval_frames >= 32) {
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@ -1733,7 +1721,7 @@ static void pipe_set_ep_char(const hcd_pipe_config_t *pipe_config, usb_transfer_
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}
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}
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ep_char->periodic.interval = interval_frames;
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ep_char->periodic.interval = interval_frames;
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// We are the Nth pipe to be allocated. Use N as a phase offset
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// We are the Nth pipe to be allocated. Use N as a phase offset
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ep_char->periodic.phase_offset_frames = pipe_idx & (XFER_LIST_LEN_ISOC - 1);
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ep_char->periodic.phase_offset_frames = pipe_idx & (xfer_list_len - 1);
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} else {
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} else {
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ep_char->periodic.interval = 0;
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ep_char->periodic.interval = 0;
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ep_char->periodic.phase_offset_frames = 0;
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ep_char->periodic.phase_offset_frames = 0;
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