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Merge branch 'bugfix/fix_psram_access_faild_after_pd_cpu_wakeup' into 'master'
fix(esp_pm): fix psram access failed after pd_cpu wakeup if uart driver driven console is used Closes WIFIBUG-238 See merge request espressif/esp-idf!27020
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bb95f9bcc6
@ -92,7 +92,7 @@ static DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention;
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#if SOC_PM_SUPPORT_TAGMEM_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL
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#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
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#if CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t code_seg_size, uint32_t data_seg_vaddr, uint32_t data_seg_size)
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{
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uint32_t sets; /* i/d-cache total set counts */
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@ -153,11 +153,11 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c
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* i/d-cache tagmem blocks (128 bits * 3 = 96 bits * 4) */
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return (((icache_tagmem_blk_gs + dcache_tagmem_blk_gs) << 2) * 3);
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}
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#endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
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#endif // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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static esp_err_t esp_sleep_tagmem_pd_low_init(void)
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{
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#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
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#if CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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if (s_cpu_retention.retent.tagmem.link_addr == NULL) {
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extern char _stext[], _etext[];
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uint32_t code_start = (uint32_t)_stext;
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@ -186,11 +186,11 @@ static esp_err_t esp_sleep_tagmem_pd_low_init(void)
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return ESP_ERR_NO_MEM;
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}
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}
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#else // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
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#else // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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s_cpu_retention.retent.tagmem.icache.enable = 0;
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s_cpu_retention.retent.tagmem.dcache.enable = 0;
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s_cpu_retention.retent.tagmem.link_addr = NULL;
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#endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
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#endif // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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return ESP_OK;
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}
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@ -108,21 +108,31 @@ menu "Power Management"
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config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
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bool "Power down CPU in light sleep"
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depends on SOC_PM_SUPPORT_CPU_PD
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select PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
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select PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
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default y
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help
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If enabled, the CPU will be powered down in light sleep. On esp32c3 soc, enabling this
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option will consume 1.68 KB of internal RAM and will reduce sleep current consumption
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by about 100 uA. On esp32s3 soc, enabling this option will consume 8.58 KB of internal
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RAM and will reduce sleep current consumption by about 650 uA.
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If enabled, the CPU will be powered down in light sleep, ESP chips supports saving and restoring CPU's running
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context before and after light sleep, the feature provides applications with seamless CPU powerdowned lightsleep
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without user awareness.
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But this will takes up some internal memory. On esp32c3 soc, enabling this option will consume 1.68 KB of internal
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RAM and will reduce sleep current consumption by about 100 uA. On esp32s3 soc, enabling this option will consume
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8.58 KB of internal RAM and will reduce sleep current consumption by about 650 uA.
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config PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
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bool "Power down I/D-cache tag memory in light sleep"
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config PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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bool "Restore I/D-cache tag memory after power down CPU light sleep"
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depends on IDF_TARGET_ESP32S3 && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
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default y
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help
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If enabled, the I/D-cache tag memory will be retained in light sleep. Depending on the the
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cache configuration, if this option is enabled, it will consume up to 9 KB of internal RAM.
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Cache tag memory and CPU both belong to the CPU power domain. ESP chips supports saving and restoring Cache tag memory
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before and after sleep, this feature supports accesses to the external memory that was cached before sleep still
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be cached when the CPU wakes up from a powerdowned CPU lightsleep. This option controls the restore method for Cache
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tag memory in lightsleep.
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If this option is enabled, the I/D-cache tag memory will be backuped to the internal RAM before sleep and restored
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upon wakeup. Depending on the the cache configuration, if this option is enabled, it will consume up to 9 KB
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of internal RAM.
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If this option is disabled, all cached data won't be kept after sleep, the DCache will be writeback before
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sleep and invalid all cached data after sleep, all accesses to external memory(Flash/PSRAM) will be cache
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missed after waking up, resulting in performance degradation due to increased memory accesses latency.
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config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)"
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@ -97,5 +97,5 @@ entries:
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if SOC_PM_CPU_RETENTION_BY_RTCCNTL = y:
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if PM_SLP_IRAM_OPT = y && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y:
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rtc_cntl_hal:rtc_cntl_hal_enable_cpu_retention (noflash)
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if PM_SLP_IRAM_OPT = y && PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP = y:
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if PM_SLP_IRAM_OPT = y && PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP = y:
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rtc_cntl_hal:rtc_cntl_hal_enable_tagmem_retention (noflash)
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@ -446,8 +446,11 @@ esp_err_t esp_pm_configure(const void* vconfig)
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min_freq_mhz,
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config->light_sleep_enable ? "ENABLED" : "DISABLED");
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portENTER_CRITICAL(&s_switch_lock);
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// CPU & Modem power down initialization, which must be initialized before s_light_sleep_en set true,
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// to avoid entering idle and sleep in this function.
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esp_pm_sleep_configure(config);
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portENTER_CRITICAL(&s_switch_lock);
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bool res __attribute__((unused));
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res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]);
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assert(res);
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@ -460,8 +463,6 @@ esp_err_t esp_pm_configure(const void* vconfig)
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s_config_changed = true;
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portEXIT_CRITICAL(&s_switch_lock);
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esp_pm_sleep_configure(config);
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return ESP_OK;
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}
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@ -1,3 +1,4 @@
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# sdkconfig replacement configurations for deprecated options formatted as
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# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
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CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
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CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -68,6 +68,14 @@ void rtc_cntl_hal_enable_cpu_retention(void *addr)
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);
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rtc_cntl_ll_enable_cpu_retention_clock();
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rtc_cntl_ll_enable_cpu_retention();
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#if SOC_PM_SUPPORT_TAGMEM_PD
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if (!retent->tagmem.dcache.enable) {
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// Here we only need to care for the safety of the PSRAM data in the DCache.
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// Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be
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// modified in the sleep process code after now, so it is safe to writeback here.
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Cache_WriteBack_All();
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}
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#endif
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}
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}
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}
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