From ba32dd30a1cc874709155da2cfb632220dbee623 Mon Sep 17 00:00:00 2001
From: jack <jack@espressif.com>
Date: Mon, 5 Jun 2017 18:26:14 +0800
Subject: [PATCH] bugfix:Fix bug that wdt reset information for CPU1 was not
 correct

---
 components/bootloader/src/main/bootloader_start.c | 7 +++----
 components/esp32/cpu_start.c                      | 8 ++++++++
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c
index 1f6274ef08..de038d4bc4 100644
--- a/components/bootloader/src/main/bootloader_start.c
+++ b/components/bootloader/src/main/bootloader_start.c
@@ -766,12 +766,11 @@ static void uart_console_configure(void)
 #endif // CONFIG_CONSOLE_UART_NONE
 }
 
-static void wdt_reset_info_enable(void)
+static void wdt_reset_cpu0_info_enable(void)
 {
+    //We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1.
     DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
     DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
-    DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
-    DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
 }
 
 static void wdt_reset_info_dump(int cpu)
@@ -841,5 +840,5 @@ static void wdt_reset_check(void)
         wdt_reset_info_dump(0);
         wdt_reset_info_dump(1);
     }
-    wdt_reset_info_enable();
+    wdt_reset_cpu0_info_enable();
 }
diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c
index e98a86b38e..ac18081102 100644
--- a/components/esp32/cpu_start.c
+++ b/components/esp32/cpu_start.c
@@ -170,6 +170,13 @@ void IRAM_ATTR call_start_cpu0()
 }
 
 #if !CONFIG_FREERTOS_UNICORE
+
+static void wdt_reset_cpu1_info_enable(void)
+{
+    DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
+    DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
+}
+
 void IRAM_ATTR call_start_cpu1()
 {
     asm volatile (\
@@ -188,6 +195,7 @@ void IRAM_ATTR call_start_cpu1()
     uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
 #endif
 
+    wdt_reset_cpu1_info_enable();
     ESP_EARLY_LOGI(TAG, "App cpu up.");
     app_cpu_started = 1;
     start_cpu1();