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Merge branch 'feature/esp32p4_sleep_support' into 'master'

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feat(esp_hw_support): esp32p4 sleep support (Stage 1: support basic pmu sleep function 💤)

Closes IDF-7528 and IDF-7527

See merge request espressif/esp-idf!28196
This commit is contained in:
Wu Zheng Hui 2024-03-14 10:17:32 +08:00
commit bb25cc1234
40 changed files with 893 additions and 495 deletions
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3
components/esp_common/include/esp_attr.h
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@ -28,6 +28,9 @@ extern "C" {
// Forces code into TCM instead of flash
#define TCM_IRAM_ATTR _SECTION_ATTR_IMPL(".tcm.text", __COUNTER__)
// Forces data into TCM instead of L2MEM
#define TCM_DRAM_ATTR _SECTION_ATTR_IMPL(".tcm.data", __COUNTER__)
// IRAM can only be accessed as an 8-bit memory on ESP32, when CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY is set
#define IRAM_8BIT_ACCESSIBLE (CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)

5
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@ -860,8 +860,7 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]")
}
#endif //SOC_USB_SERIAL_JTAG_SUPPORTED
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4, ESP32C5)
// TODO: IDF-7528 Remove when light sleep is supported on ESP32P4
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
// TODO: IDF-8638 Remove when light sleep is supported on ESP32C5
// Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep
TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
@ -879,4 +878,4 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
printf("Waked up from light sleep\n");
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO);
}
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
#endif

2
components/esp_driver_ledc/src/ledc.c
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@ -570,11 +570,9 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk);
#if !CONFIG_IDF_TARGET_ESP32P4 //depend on sleep support IDF-7528
/* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */
extern void esp_sleep_periph_use_8m(bool use_or_not);
esp_sleep_periph_use_8m(glb_clk == LEDC_SLOW_CLK_RC_FAST);
#endif
}
/* The divisor is correct, we can write in the hardware. */

2
components/esp_hw_support/CMakeLists.txt
View File

@ -165,9 +165,7 @@ if(NOT BOOTLOADER_BUILD)
if(CONFIG_IDF_TARGET_ESP32P4)
list(REMOVE_ITEM srcs
"sleep_cpu.c" # TODO: IDF-7528, IDF-7529
"sleep_modes.c" # TODO: IDF-7528, IDF-7529
"sleep_wake_stub.c" # TODO: IDF-7529
"sleep_gpio.c" # TODO: IDF-7528, IDF-7529
)
endif()
if(CONFIG_IDF_TARGET_ESP32C5)

68
components/esp_hw_support/include/esp_private/esp_pmu.h
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@ -16,6 +16,7 @@
#if SOC_PMU_SUPPORTED
#include "hal/pmu_hal.h"
#include "pmu_param.h"
#include "pmu_bit_defs.h"
#endif
#ifdef __cplusplus
@ -50,7 +51,7 @@ typedef enum {
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
#if SOC_PM_SUPPORT_EXT0_WAKEUP
#define RTC_EXT0_TRIG_EN PMU_EXT0_WAKEUP_EN //!< EXT0 wakeup
#define RTC_EXT0_TRIG_EN PMU_EXT0_WAKEUP_EN //!< EXT0 wakeup
#else
#define RTC_EXT0_TRIG_EN 0
#endif
@ -116,26 +117,6 @@ typedef enum {
RTC_USB_TRIG_EN | \
RTC_BROWNOUT_DET_TRIG_EN)
#if SOC_PM_SUPPORT_EXT0_WAKEUP
#define PMU_EXT0_WAKEUP_EN BIT(0)
#endif
#if SOC_PM_SUPPORT_EXT1_WAKEUP
#define PMU_EXT1_WAKEUP_EN BIT(1)
#endif
#define PMU_GPIO_WAKEUP_EN BIT(2)
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3)
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
#define PMU_WIFI_SOC_WAKEUP_EN BIT(5)
#define PMU_UART0_WAKEUP_EN BIT(6)
#define PMU_UART1_WAKEUP_EN BIT(7)
#define PMU_SDIO_WAKEUP_EN BIT(8)
#define PMU_BLE_SOC_WAKEUP_EN BIT(10)
#if SOC_LP_CORE_SUPPORTED
#define PMU_LP_CORE_WAKEUP_EN BIT(11)
#endif //SOC_LP_CORE_SUPPORTED
#define PMU_USB_WAKEUP_EN BIT(14)
#define PMU_SLEEP_PD_TOP BIT(0)
#define PMU_SLEEP_PD_VDDSDIO BIT(1)
@ -158,6 +139,10 @@ typedef enum {
#define PMU_SLEEP_PD_RC32K BIT(13)
#define PMU_SLEEP_PD_LP_PERIPH BIT(14)
#if SOC_PM_SUPPORT_CNNT_PD
#define PMU_SLEEP_PD_CNNT BIT(15)
#endif
typedef struct {
pmu_hal_context_t *hal;
void *mc;
@ -203,6 +188,28 @@ void pmu_sleep_disable_regdma_backup(void);
*/
bool pmu_sleep_pll_already_enabled(void);
/**
* @brief Calculate the LP system hardware time overhead during sleep
*
* @param pd_flags flags indicates the power domain that will be powered down
* @param slowclk_period re-calibrated slow clock period
* @param fastclk_period re-calibrated fast clock period
*
* @return hardware time overhead in us
*/
uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
/**
* @brief Calculate the HP system hardware time overhead during sleep
*
* @param pd_flags flags indicates the power domain that will be powered down
* @param slowclk_period re-calibrated slow clock period
* @param fastclk_period re-calibrated fast clock period
*
* @return hardware time overhead in us
*/
uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
/**
* @brief Calculate the hardware time overhead during sleep to compensate for sleep time
*
@ -246,6 +253,25 @@ const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, u
*/
void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp);
#if SOC_DCDC_SUPPORTED
/**
* @brief Increase hp_ldo voltage, in preparation for taking over the power supply from DCDC
*/
void pmu_sleep_increase_ldo_volt(void);
/**
* @brief LDO has taken over power supply, shut down DCDC to save power consumption and goto sleep
* and after shutdown the DCDC, it is also necessary to decrease the LDO voltage to save
* power in the sleep and wake-up processes.
*/
void pmu_sleep_shutdown_dcdc(void);
/**
* @brief DCDC has taken over power supply, shut down LDO to save power consumption
*/
void pmu_sleep_shutdown_ldo(void);
#endif
/**
* @brief Enter deep or light sleep mode
*

4
components/esp_hw_support/include/esp_private/sleep_event.h
View File

@ -32,8 +32,8 @@ typedef enum {
SLEEP_EVENT_HW_FLASH_BBPLL_EN_START, // Beginning of rtc_clk_bbpll_enable when using FLASH_PLL
SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP, // End of rtc_clk_bbpll_enable when using FLASH_PLL
#endif
SLEEP_EVENT_HW_BBPLL_EN_START, // Beginning of rtc_clk_bbpll_enable
SLEEP_EVENT_HW_BBPLL_EN_STOP, // End of rtc_clk_bbpll_enable
SLEEP_EVENT_HW_PLL_EN_START, // Beginning of rtc_clk_pll_enable
SLEEP_EVENT_HW_PLL_EN_STOP, // End of rtc_clk_pll_enable
SLEEP_EVENT_CB_INDEX_NUM,
} esp_sleep_event_cb_index_t;

6
components/esp_hw_support/port/esp32c5/rtc_clk.c
View File

@ -278,7 +278,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
return true;
}
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
{
}
@ -295,12 +295,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
} else if ((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) {
if ((old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) && (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M)) {
// PLL_F160M and PLL_F240M both derived from S(BB)PLL (480MHz)
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ);
}
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_8m();
if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) {

28
components/esp_hw_support/port/esp32c6/private_include/pmu_bit_defs.h Normal file
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@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define PMU_EXT0_WAKEUP_EN BIT(0)
#define PMU_EXT1_WAKEUP_EN BIT(1)
#define PMU_GPIO_WAKEUP_EN BIT(2)
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3)
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
#define PMU_WIFI_SOC_WAKEUP_EN BIT(5)
#define PMU_UART0_WAKEUP_EN BIT(6)
#define PMU_UART1_WAKEUP_EN BIT(7)
#define PMU_SDIO_WAKEUP_EN BIT(8)
#define PMU_BLE_SOC_WAKEUP_EN BIT(10)
#define PMU_LP_CORE_WAKEUP_EN BIT(11)
#define PMU_USB_WAKEUP_EN BIT(14)
#ifdef __cplusplus
}
#endif

6
components/esp_hw_support/port/esp32c6/rtc_clk.c
View File

@ -254,7 +254,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
return true;
}
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
{
}
@ -269,12 +269,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
}
} else if (config->source == SOC_CPU_CLK_SRC_PLL) {
if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL) {
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
}
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_8m();
if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {

24
components/esp_hw_support/port/esp32h2/private_include/pmu_bit_defs.h Normal file
View File

@ -0,0 +1,24 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define PMU_EXT0_WAKEUP_EN BIT(0)
#define PMU_EXT1_WAKEUP_EN BIT(1)
#define PMU_GPIO_WAKEUP_EN BIT(2)
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
#define PMU_UART0_WAKEUP_EN BIT(6)
#define PMU_UART1_WAKEUP_EN BIT(7)
#define PMU_BLE_SOC_WAKEUP_EN BIT(10)
#define PMU_USB_WAKEUP_EN BIT(14)
#ifdef __cplusplus
}
#endif

10
components/esp_hw_support/port/esp32h2/rtc_clk.c
View File

@ -298,7 +298,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
return true;
}
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
{
}
@ -313,12 +313,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
}
} else if (config->source == SOC_CPU_CLK_SRC_PLL) {
if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) {
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
}
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_8m();
if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL || old_cpu_clk_src == SOC_CPU_CLK_SRC_FLASH_PLL) &&
@ -329,12 +329,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) {
// On ESP32H2, FLASH_PLL (64MHz) is directly derived from the BBPLL (96MHz)
// Therefore, enabling and configuration are applied to BBPLL.
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_START);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_START);
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_96M_FREQ_MHZ);
}
rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div);
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP);
}
}

20
components/esp_hw_support/port/esp32p4/pmu_init.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,9 +16,6 @@
#include "esp_private/esp_pmu.h"
#include "soc/regi2c_dig_reg.h"
#include "regi2c_ctrl.h"
#include "soc/pmu_reg.h"
// TODO: IDF-7531
static __attribute__((unused)) const char *TAG = "pmu_init";
@ -35,13 +32,13 @@ typedef struct {
const pmu_lp_system_analog_param_t *analog;
} pmu_lp_system_param_t;
pmu_context_t * __attribute__((weak)) IRAM_ATTR PMU_instance(void)
pmu_context_t * __attribute__((weak)) TCM_IRAM_ATTR PMU_instance(void)
{
/* It should be explicitly defined in the internal RAM, because this
* instance will be used in pmu_sleep.c */
static DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
static DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
static DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc };
static TCM_DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
static TCM_DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
static TCM_DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc };
return &pmu_context;
}
@ -62,7 +59,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa
/* Default configuration of hp-system clock in active, modem and sleep modes */
pmu_ll_hp_set_icg_func (ctx->hal->dev, mode, clock->icg_func);
pmu_ll_hp_set_icg_apb (ctx->hal->dev, mode, clock->icg_apb);
pmu_ll_hp_set_icg_modem (ctx->hal->dev, mode, clock->icg_modem.code);
pmu_ll_hp_set_sysclk_nodiv (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_nodiv);
pmu_ll_hp_set_icg_sysclk_enable (ctx->hal->dev, mode, clock->sysclk.icg_sysclk_en);
pmu_ll_hp_set_sysclk_slp_sel (ctx->hal->dev, mode, clock->sysclk.sysclk_slp_sel);
@ -82,6 +78,7 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa
* sleep modes */
pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias);
pmu_ll_hp_set_dcm_mode (ctx->hal->dev, mode, anlg->bias.dcm_mode);
pmu_ll_hp_set_dcm_vset (ctx->hal->dev, mode, anlg->bias.dcm_vset);
pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias);
pmu_ll_hp_set_dbg_atten (ctx->hal->dev, mode, anlg->bias.dbg_atten);
pmu_ll_hp_set_current_power_off (ctx->hal->dev, mode, anlg->bias.pd_cur);
@ -97,10 +94,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa
pmu_ll_hp_set_retention_param(ctx->hal->dev, mode, ret->retention.val);
pmu_ll_hp_set_backup_icg_func(ctx->hal->dev, mode, ret->backup_clk);
/* Some PMU initial parameter configuration */
pmu_ll_imm_update_dig_icg_modem_code(ctx->hal->dev, true);
pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true);
pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP);
}
@ -171,6 +164,7 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx)
assert(ctx);
pmu_hp_system_param_t param = { 0 };
for (pmu_hp_mode_t mode = PMU_MODE_HP_ACTIVE; mode < PMU_MODE_HP_MAX; mode++) {
if (mode == PMU_MODE_HP_MODEM) continue;
pmu_hp_system_param_default(mode, &param);
pmu_hp_system_init(ctx, mode, &param);
}

31
components/esp_hw_support/port/esp32p4/pmu_param.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,7 +17,6 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#endif
// TODO: IDF-7531
#define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.mem_dslp = 0, \
@ -29,8 +28,8 @@
.clk_power = { \
.i2c_iso_en = 0, \
.i2c_retention = 0, \
.xpd_pll_i2c = 1, \
.xpd_pll = 1 \
.xpd_pll_i2c = 0xf, \
.xpd_pll = 0xf \
}, \
.xtal = { \
.xpd_xtal = 1 \
@ -60,7 +59,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod
{
static const pmu_hp_system_power_param_t hp_power[] = {
PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(),
PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(),
{{}, {}, {}}, // No Modem
PMU_HP_SLEEP_POWER_CONFIG_DEFAULT()
};
assert(mode < ARRAY_SIZE(hp_power));
@ -70,9 +69,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod
#define PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT() { \
.icg_func = 0xffffffff, \
.icg_apb = 0xffffffff, \
.icg_modem = { \
.code = PMU_HP_ICG_MODEM_CODE_ACTIVE \
}, \
.icg_modem = 0, \
.sysclk = { \
.dig_sysclk_nodiv = 0, \
.icg_sysclk_en = 1, \
@ -85,9 +82,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod
#define PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() { \
.icg_func = 0, \
.icg_apb = 0, \
.icg_modem = { \
.code = PMU_HP_ICG_MODEM_CODE_SLEEP \
}, \
.icg_modem = 0, \
.sysclk = { \
.dig_sysclk_nodiv = 0, \
.icg_sysclk_en = 0, \
@ -101,7 +96,7 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod
{
static const pmu_hp_system_clock_param_t hp_clock[] = {
PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(),
PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(),
{0, 0, 0, {}}, // No Modem
PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT()
};
assert(mode < ARRAY_SIZE(hp_clock));
@ -134,7 +129,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
{
static const pmu_hp_system_digital_param_t hp_digital[] = {
PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(),
PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(),
{{}}, // No Modem
PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT()
};
assert(mode < ARRAY_SIZE(hp_digital));
@ -143,6 +138,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
.bias = { \
.dcm_vset = 27, \
.dcm_mode = 1, \
.xpd_bias = 1, \
.dbg_atten = 0x0, \
@ -166,6 +162,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
.bias = { \
.dcm_vset = 0, \
.dcm_mode = 0, \
.xpd_bias = 0, \
.dbg_atten = 0x0, \
@ -187,7 +184,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
{
static const pmu_hp_system_analog_param_t hp_analog[] = {
PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
{{}, {}, {}}, // No Modem
PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT()
};
assert(mode < ARRAY_SIZE(hp_analog));
@ -256,7 +253,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
{
static const pmu_hp_system_retention_param_t hp_retention[] = {
PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(),
PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(),
{{}, 0}, // No Modem
PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT()
};
assert(mode < ARRAY_SIZE(hp_retention));
@ -322,7 +319,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
#define PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
.regulator0 = { \
.slp_xpd = 0, \
.slp_dbias = 0, \
.slp_dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 0x0 \
@ -338,7 +335,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
}, \
.regulator0 = { \
.slp_xpd = 0, \
.slp_dbias = 0, \
.slp_dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 0x0 \

300
components/esp_hw_support/port/esp32p4/pmu_sleep.c
View File

@ -1,7 +1,303 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// TODO: IDF-7531
#include <stdint.h>
#include <stdlib.h>
#include <sys/param.h>
#include <esp_types.h>
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/soc.h"
#include "soc/regi2c_syspll.h"
#include "soc/regi2c_cpll.h"
#include "soc/rtc.h"
#include "soc/pau_reg.h"
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "hal/lp_aon_hal.h"
#include "hal/pmu_hal.h"
#include "esp_private/esp_pmu.h"
#include "pmu_param.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
#define HP(state) (PMU_MODE_HP_ ## state)
#define LP(state) (PMU_MODE_LP_ ## state)
static bool s_pmu_sleep_regdma_backup_enabled;
void pmu_sleep_enable_regdma_backup(void)
{
if(!s_pmu_sleep_regdma_backup_enabled){
assert(PMU_instance()->hal);
/* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
* and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
* respectively. entry 3 is reserved, not used yet! */
pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
s_pmu_sleep_regdma_backup_enabled = true;
}
}
void pmu_sleep_disable_regdma_backup(void)
{
if(s_pmu_sleep_regdma_backup_enabled){
assert(PMU_instance()->hal);
pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
s_pmu_sleep_regdma_backup_enabled = false;
}
}
uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
/* LP core hardware wait time, microsecond */
const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
: rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \
+ lp_wakeup_wait_time_us + lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us \
+ mc->lp.power_up_wait_time_us;
return (uint32_t)lp_hw_wait_time_us;
}
uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
{
pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
/* HP core hardware wait time, microsecond */
const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
const int hp_regdma_wait_time_us = (pd_flags & PMU_SLEEP_PD_TOP) ? mc->hp.regdma_s2a_work_time_us : 0;
const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us;
if (pd_flags & PMU_SLEEP_PD_TOP) {
mc->hp.analog_wait_time_us = PMU_HP_ANA_WAIT_TIME_PD_TOP_US;
} else {
mc->hp.analog_wait_time_us = PMU_HP_ANA_WAIT_TIME_PU_TOP_US;
}
const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + MAX(hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us, hp_clock_wait_time_us);
return (uint32_t)hp_hw_wait_time_us;
}
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
{
const uint32_t lp_hw_wait_time_us = pmu_sleep_calculate_lp_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
const uint32_t hp_hw_wait_time_us = pmu_sleep_calculate_hp_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
const uint32_t total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
return total_hw_wait_time_us;
}
#define rtc_time_us_to_fastclk(time_us, period) rtc_time_us_to_slowclk((time_us), (period))
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t pd_flags,
const uint32_t adjustment,
const uint32_t slowclk_period,
const uint32_t fastclk_period
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->hp.analog_wait_time_us, slowclk_period);
param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
if (power->hp_sys.xtal.xpd_xtal) {
param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period);
} else {
param->hp_lp.xtal_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.xtal_wait_stable_time_us, fastclk_period);
}
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t pd_flags,
uint32_t adjustment,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
{
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
uint32_t iram_pd_flags = 0;
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0;
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0;
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0;
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0;
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
config->analog = analog_default;
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
config->analog = analog_default;
}
return config;
}
static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_config_t *power, bool dslp)
{
pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val);
pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val);
pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal);
pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val);
pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val);
pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val);
pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val);
pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal);
}
static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
{
pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
}
static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
{
assert(ctx->hal);
pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur);
pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep);
pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd);
pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_xpd);
pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_dbias);
pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias);
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_dbias);
pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.dbias);
pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.drv_b);
pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep);
pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd);
pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias);
pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias);
pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b);
}
static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp)
{
assert(ctx->hal);
pmu_ll_hp_set_min_sleep_cycle(ctx->hal->dev, param->hp_sys.min_slp_slow_clk_cycle);
pmu_ll_lp_set_min_sleep_cycle(ctx->hal->dev, param->lp_sys.min_slp_slow_clk_cycle);
pmu_ll_hp_set_analog_wait_target_cycle(ctx->hal->dev, param->hp_sys.analog_wait_target_cycle);
pmu_ll_lp_set_analog_wait_target_cycle(ctx->hal->dev, param->lp_sys.analog_wait_target_cycle);
pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle);
pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle);
pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle);
pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
}
void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
{
assert(PMU_instance());
pmu_sleep_power_init(PMU_instance(), &config->power, dslp);
if(!dslp){
pmu_sleep_digital_init(PMU_instance(), &config->digital);
}
pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
}
void pmu_sleep_increase_ldo_volt(void) {
REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, 30);
REG_SET_BIT(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
}
void pmu_sleep_shutdown_dcdc(void) {
SET_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
REG_SET_BIT(PMU_DCM_CTRL_REG, PMU_DCDC_OFF_REQ);
// Decrease the DCDC voltage to reduce the voltage difference between the DCDC and the LDO to avoid overshooting the DCDC voltage during wake-up.
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, 24);
// Decrease hp_ldo voltage.
REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, 24);
}
void pmu_sleep_enable_dcdc(void) {
CLEAR_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_ON_REQ);
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, 27);
}
void pmu_sleep_shutdown_ldo(void) {
CLEAR_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
}
TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
{
lp_aon_hal_inform_wakeup_type(dslp);
assert(PMU_instance()->hal);
pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);
pmu_ll_hp_clear_wakeup_intr_status(PMU_instance()->hal->dev);
pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
/* Start entry into sleep mode */
pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
while (!pmu_ll_hp_is_sleep_wakeup(PMU_instance()->hal->dev) &&
!pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) {
;
}
return pmu_sleep_finish();
}
TCM_IRAM_ATTR bool pmu_sleep_finish(void)
{
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, 27);
if (pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) {
// If sleep is rejected, the hardware wake-up process that turns on DCDC
// is skipped, and software is used to enable DCDC here.
pmu_sleep_enable_dcdc();
esp_rom_delay_us(950);
}
pmu_sleep_shutdown_ldo();
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}
uint32_t pmu_sleep_get_wakup_retention_cost(void)
{
return PMU_REGDMA_S2A_WORK_TIME_US;
}

36
components/esp_hw_support/port/esp32p4/private_include/pmu_bit_defs.h Normal file
View File

@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define PMU_SDIO_WAKEUP_EN BIT(0)
#define PMU_SW_WAKEUP_HP_EN BIT(1)
#define PMU_GPIO_WAKEUP_EN BIT(2)
#define PMU_USB_WAKEUP_EN BIT(3)
#define PMU_UART4_WAKEUP_EN BIT(4)
#define PMU_UART3_WAKEUP_EN BIT(5)
#define PMU_UART2_WAKEUP_EN BIT(6)
#define PMU_UART1_WAKEUP_EN BIT(7)
#define PMU_UART0_WAKEUP_EN BIT(8)
#define PMU_LP_GPIO_WAKEUP_EN BIT(9)
#define PMU_LP_UART_WAKEUP_EN BIT(10)
#define PMU_TOUCH_WAKEUP_EN BIT(11)
#define PMU_EXT_IO_WAKEUP_EN BIT(12)
#define PMU_LP_TIMER_WAKEUP_EN BIT(13)
#define PMU_BOD_WAKEUP_EN BIT(14)
#define PMU_VDDBAT_UNDERVOLT_WAKEUP_EN BIT(15)
#define PMU_LP_CORE_WAKEUP_EN BIT(16)
#define PMU_ETM_WAKEUP_EN BIT(17)
#define PMU_LP_TIMER1_WAKEUP_EN BIT(18)
#define PMU_LP_I2S_WAKEUP_EN BIT(19)
#ifdef __cplusplus
}
#endif

29
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -41,6 +41,8 @@ extern "C" {
#define PMU_HP_XPD_DEEPSLEEP 0
#define PMU_LP_DRVB_DEEPSLEEP 0
#define PMU_REGDMA_S2A_WORK_TIME_US 685
#define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 12
#define PMU_LP_DBIAS_DEEPSLEEP_0V7 23
@ -55,7 +57,7 @@ const pmu_hp_system_power_param_t* pmu_hp_system_power_param_default(pmu_hp_mode
typedef struct {
uint32_t icg_func;
uint32_t icg_apb;
pmu_hp_icg_modem_reg_t icg_modem;
uint32_t icg_modem;
pmu_hp_sysclk_reg_t sysclk;
} pmu_hp_system_clock_param_t;
@ -226,7 +228,7 @@ typedef struct {
#define PMU_HP_WAKEUP_DELAY_CYCLES (0)
#define PMU_HP_XTAL_STABLE_WAIT_CYCLES (3155) /* Not used, Fast OSC as PMU work clock source is about 201 us, corresponding to PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES */
#define PMU_HP_PLL_STABLE_WAIT_CYCLES (2)
#define PMU_HP_ANALOG_WAIT_TARGET_CYCLES (2419) /* Fast OSC as PMU work clock source is about 154 us */
#define PMU_HP_ANALOG_WAIT_TARGET_CYCLES (23) /* Slow OSC as PMU work clock source is about 400 us */
#define PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32)
#define PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES (32)
#define PMU_HP_MODEM_WAKEUP_WAIT_CYCLES (20700) /* Fast OSC as PMU work clock source is about 1318.6 us */
@ -258,7 +260,8 @@ typedef struct {
.cnnt_pd_en = ((pd_flags) & PMU_SLEEP_PD_CNNT) ? 1 : 0, \
.top_pd_en = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.mem_pd_en = ((pd_flags) & PMU_SLEEP_PD_MEM) ? 1 : 0, \
.mem_dslp = 0 \
.mem_dslp = 0, \
.dcdc_switch_pd_en = 1 \
}, \
.clk_power = { \
.i2c_iso_en = 1, \
@ -340,7 +343,7 @@ typedef struct {
.slp_xpd = 0, \
.slp_dbias = 0, \
.xpd = 1, \
.dbias = 0x1a, \
.dbias = 29, \
.drv_b = 0x0 \
} \
}, \
@ -454,6 +457,14 @@ typedef struct pmu_sleep_machine_constant {
} hp;
} pmu_sleep_machine_constant_t;
// If TOP is power down, the time the regdma runs will cover some of the time
// spent waiting for the DCDC to startup.
#define PMU_HP_ANA_WAIT_TIME_PD_TOP_US 260
// If TOP doamin is not powered down, we need to stay in HP_SWITCH longer to wait for the
// DCDC startup, which saves more power compared to waiting in the Active state.
#define PMU_HP_ANA_WAIT_TIME_PU_TOP_US (PMU_HP_ANA_WAIT_TIME_PD_TOP_US + PMU_REGDMA_S2A_WORK_TIME_US) // 945
#define PMU_SLEEP_MC_DEFAULT() { \
.lp = { \
.min_slp_time_us = 450, \
@ -469,13 +480,13 @@ typedef struct pmu_sleep_machine_constant {
.min_slp_time_us = 450, \
.clock_domain_sync_time_us = 150, \
.system_dfs_up_work_time_us = 124, \
.analog_wait_time_us = 154, \
.analog_wait_time_us = PMU_HP_ANA_WAIT_TIME_PD_TOP_US, \
.power_supply_wait_time_us = 2, \
.power_up_wait_time_us = 2, \
.regdma_s2m_work_time_us = 172, \
.regdma_s2a_work_time_us = 430, \
.regdma_m2a_work_time_us = 265, \
.regdma_a2s_work_time_us = 338, \
.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \
.regdma_m2a_work_time_us = 278, \
.regdma_a2s_work_time_us = 382, \
.regdma_rf_on_work_time_us = 70, \
.regdma_rf_off_work_time_us = 23, \
.xtal_wait_stable_time_us = 250, \

19
components/esp_hw_support/port/esp32p4/rtc_clk.c
View File

@ -19,7 +19,7 @@
#include "hal/regi2c_ctrl_ll.h"
#include "hal/gpio_ll.h"
#include "soc/io_mux_reg.h"
#include "esp_private/sleep_event.h" // TODO: IDF-7528
#include "esp_private/sleep_event.h"
static const char *TAG = "rtc_clk";
@ -234,17 +234,16 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
abort();
}
// Update bit does not control CPU clock sel mux. Therefore, there may be a middle state during the switch (CPU rises)
// We will switch cpu clock source first, and then set the desired dividers.
// It is likely that the hardware will automatically adjust dividers to meet mem_clk, apb_clk freq constraints when
// cpu clock source is set.
// However, the desired dividers will be written into registers anyways afterwards.
// This ensures the final confguration is the desired one.
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
// Since this is upscaling, we need to configure the frequency division coefficient before switching the clock source.
// Otherwise, an intermediate state will occur, in the intermediate state, the frequency of APB/MEM does not meet the
// timing requirements. If there are periperals/CPU access that depend on these two clocks at this moment, some exception
// might occur.
clk_ll_cpu_set_divider(div->integer, div->numerator, div->denominator);
clk_ll_mem_set_divider(mem_divider);
clk_ll_sys_set_divider(sys_divider);
clk_ll_apb_set_divider(apb_divider);
clk_ll_bus_update();
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
@ -301,6 +300,10 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
return true;
}
__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
{
}
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
{
soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
@ -311,6 +314,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
}
} else if (config->source == SOC_CPU_CLK_SRC_CPLL) {
if (old_cpu_clk_src != SOC_CPU_CLK_SRC_CPLL) {
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
rtc_clk_cpll_enable();
}
if (config->source_freq_mhz != s_cur_cpll_freq) {
@ -320,6 +324,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
rtc_clk_cpll_configure(xtal_freq_mhz, config->source_freq_mhz);
}
rtc_clk_cpu_freq_to_cpll_mhz(config->freq_mhz, (hal_utils_clk_div_t *)&config->div);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_8m();
if (old_cpu_clk_src == SOC_CPU_CLK_SRC_CPLL) {

13
components/esp_hw_support/port/esp32p4/rtc_time.c
View File

@ -29,8 +29,9 @@ static const char *TAG = "rtc_time";
// calibration is performed on their DIV_CLKs. The divider is configurable. We set:
#define CLK_CAL_DIV_VAL(cal_clk) \
((cal_clk == RTC_CAL_RC_SLOW || cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL) ? 1 : \
(cal_clk == RTC_CAL_LP_PLL) ? 50 : \
(cal_clk == RTC_CAL_RC_FAST) ? 200 : \
(cal_clk == RTC_CAL_LP_PLL) ? 25 : \
(cal_clk == RTC_CAL_RC_FAST) ? 50 : \
(cal_clk == RTC_CAL_APLL) ? 200 : \
4000)
// CLK_CAL_FREQ_APPROX = CLK_FREQ_APPROX / CLK_CAL_DIV_VAL
@ -38,13 +39,13 @@ static const char *TAG = "rtc_time";
((cal_clk == RTC_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk == RTC_CAL_SPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk == RTC_CAL_CPLL) ? (CLK_LL_PLL_400M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk == RTC_CAL_APLL) ? (105 * MHZ / 4000) : \
(cal_clk == RTC_CAL_APLL) ? (105 * MHZ / 200) : \
(cal_clk == RTC_CAL_SDIO_PLL0 || cal_clk == RTC_CAL_SDIO_PLL1 || cal_clk == RTC_CAL_SDIO_PLL2) ? (200 * MHZ / 4000) : \
(cal_clk == RTC_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 200) : \
(cal_clk == RTC_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \
(cal_clk == RTC_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \
(cal_clk == RTC_CAL_RC32K) ? (SOC_CLK_RC32K_FREQ_APPROX) : \
(cal_clk == RTC_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \
(cal_clk == RTC_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 50) : \
(cal_clk == RTC_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 25) : \
0)
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
@ -142,6 +143,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
}
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_M);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
@ -178,6 +180,7 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{
slowclk_cycles /= (cal_clk == RTC_CAL_RTC_MUX) ? 1 : CLK_CAL_DIV_VAL(cal_clk);
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);

4
components/esp_hw_support/sleep_gpio.c
View File

@ -22,11 +22,7 @@
#include "hal/rtc_io_hal.h"
#include "soc/rtc_io_periph.h"
#if SOC_LP_AON_SUPPORTED
#include "hal/lp_aon_hal.h"
#else
#include "hal/rtc_hal.h"
#endif
#include "esp_private/gpio.h"
#include "esp_private/sleep_gpio.h"

42
components/esp_hw_support/sleep_modes.c
View File

@ -30,12 +30,10 @@
#include "esp_private/pm_impl.h"
#endif
#if SOC_LP_AON_SUPPORTED
#include "hal/lp_aon_hal.h"
#else
#if !SOC_PMU_SUPPORTED
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_hal.h"
#endif
#include "hal/rtc_hal.h"
#include "soc/rtc.h"
#include "soc/soc_caps.h"
@ -90,6 +88,9 @@
#include "esp32h2/rom/rtc.h"
#include "soc/extmem_reg.h"
#include "hal/gpio_ll.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/rtc.h"
#include "hal/gpio_ll.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
@ -138,8 +139,12 @@
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
#elif CONFIG_IDF_TARGET_ESP32H2
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)// TODO: IDF-6267
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
#elif CONFIG_IDF_TARGET_ESP32P4
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (324)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (240)
#define LDO_POWER_TAKEOVER_PREPARATION_TIME_US (185)
#endif
// Actually costs 80us, using the fastest slow clock 150K calculation takes about 16 ticks
@ -204,6 +209,9 @@ typedef struct {
uint32_t rtc_clk_cal_period;
uint32_t fast_clk_cal_period;
uint64_t rtc_ticks_at_sleep_start;
#if SOC_DCDC_SUPPORTED
uint64_t rtc_ticks_at_ldo_prepare;
#endif
} sleep_config_t;
@ -268,7 +276,7 @@ static void touch_wakeup_prepare(void);
static void gpio_deep_sleep_wakeup_prepare(void);
#endif
#if SOC_RTC_FAST_MEM_SUPPORTED
#if SOC_RTC_FAST_MEM_SUPPORTED && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-7529
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
@ -561,10 +569,12 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep)
#endif
}
#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-6496
// TODO: IDF-7370
if (!(deep_sleep && s_adc_tsen_enabled)){
sar_periph_ctrl_power_disable();
}
#endif
}
/**
@ -575,7 +585,11 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(void)
#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
sleep_console_usj_pad_restore();
#endif
#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-6496
sar_periph_ctrl_power_enable();
#endif
#if SOC_PM_SUPPORT_CPU_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL
sleep_disable_cpu_retention();
#endif
@ -767,6 +781,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
// Enter sleep
esp_err_t result;
#if SOC_PMU_SUPPORTED
#if SOC_DCDC_SUPPORTED
s_config.rtc_ticks_at_ldo_prepare = rtc_time_get();
pmu_sleep_increase_ldo_volt();
#endif
pmu_sleep_config_t config;
pmu_sleep_init(pmu_sleep_config_default(&config, sleep_flags, s_config.sleep_time_adjustment,
s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
@ -809,7 +829,9 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
#endif
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-7529
esp_set_deep_sleep_wake_stub_default_entry();
#endif
// Enter Deep Sleep
#if SOC_PMU_SUPPORTED
result = call_rtc_sleep_start(reject_triggers, config.power.hp_sys.dig_power.mem_dslp, deep_sleep);
@ -842,6 +864,14 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
#endif
#endif
#if SOC_DCDC_SUPPORTED
uint64_t ldo_increased_us = rtc_time_slowclk_to_us(rtc_time_get() - s_config.rtc_ticks_at_ldo_prepare, s_config.rtc_clk_cal_period);
if (ldo_increased_us < LDO_POWER_TAKEOVER_PREPARATION_TIME_US) {
esp_rom_delay_us(LDO_POWER_TAKEOVER_PREPARATION_TIME_US - ldo_increased_us);
}
pmu_sleep_shutdown_dcdc();
#endif
#if SOC_PMU_SUPPORTED
#if SOC_PM_CPU_RETENTION_BY_SW
esp_sleep_execute_event_callbacks(SLEEP_EVENT_HW_GOTO_SLEEP, (void *)0);

3
components/esp_pm/linker.lf
View File

@ -36,7 +36,8 @@ entries:
sleep_system_peripheral:peripheral_domain_pd_allowed (noflash)
sleep_modem:modem_domain_pd_allowed (noflash)
sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
if IDF_TARGET_ESP32P4 = n: # TODO: IDF-6496
sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
[mapping:esp_system_pm]
archive: libesp_system.a

10
components/esp_rom/include/esp32p4/rom/rtc.h
View File

@ -64,6 +64,16 @@ extern "C" {
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
/*
* Use LP_SYS_LP_STORE8_REG to store light sleep wake stub addr and sleep mode
*
* bit[31: 2] Wake restore func addr
* bit[0]:
* 0 -- light sleep
* 1 -- deep sleep
*/
#define SLEEP_MODE_REG LP_SYSTEM_REG_LP_STORE8_REG
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.

12
components/hal/esp32c6/include/hal/lp_aon_hal.h
View File

@ -8,10 +8,12 @@
#include "hal/lp_aon_ll.h"
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#ifdef __cplusplus
extern "C" {
#endif
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)
#ifdef __cplusplus
}
#endif

12
components/hal/esp32h2/include/hal/lp_aon_hal.h
View File

@ -8,10 +8,12 @@
#include "hal/lp_aon_ll.h"
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#ifdef __cplusplus
extern "C" {
#endif
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)
#ifdef __cplusplus
}
#endif

24
components/hal/esp32p4/include/hal/cache_ll.h
View File

@ -678,12 +678,12 @@ __attribute__((always_inline))
static inline void cache_ll_l1_freeze_icache(uint32_t cache_id)
{
if (cache_id == 0) {
Cache_Freeze_L1_ICache0_Enable(CACHE_FREEZE_ACK_BUSY);
rom_cache_internal_table_ptr->freeze_l1_icache0_enable(CACHE_FREEZE_ACK_BUSY);
} else if (cache_id == 1) {
Cache_Freeze_L1_ICache1_Enable(CACHE_FREEZE_ACK_BUSY);
rom_cache_internal_table_ptr->freeze_l1_icache1_enable(CACHE_FREEZE_ACK_BUSY);
} else if (cache_id == CACHE_LL_ID_ALL) {
Cache_Freeze_L1_ICache0_Enable(CACHE_FREEZE_ACK_BUSY);
Cache_Freeze_L1_ICache1_Enable(CACHE_FREEZE_ACK_BUSY);
rom_cache_internal_table_ptr->freeze_l1_icache0_enable(CACHE_FREEZE_ACK_BUSY);
rom_cache_internal_table_ptr->freeze_l1_icache1_enable(CACHE_FREEZE_ACK_BUSY);
}
}
@ -696,7 +696,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_freeze_dcache(uint32_t cache_id)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Freeze_L1_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
rom_cache_internal_table_ptr->freeze_l1_dcache_enable(CACHE_FREEZE_ACK_BUSY);
}
}
@ -709,7 +709,7 @@ __attribute__((always_inline))
static inline void cache_ll_l2_freeze_cache(uint32_t cache_id)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Freeze_L2_Cache_Enable(CACHE_FREEZE_ACK_BUSY);
rom_cache_internal_table_ptr->freeze_l2_cache_enable(CACHE_FREEZE_ACK_BUSY);
}
}
@ -755,12 +755,12 @@ __attribute__((always_inline))
static inline void cache_ll_l1_unfreeze_icache(uint32_t cache_id)
{
if (cache_id == 0) {
Cache_Freeze_L1_ICache0_Disable();
rom_cache_internal_table_ptr->freeze_l1_icache0_disable();
} else if (cache_id == 1) {
Cache_Freeze_L1_ICache1_Disable();
rom_cache_internal_table_ptr->freeze_l1_icache1_disable();
} else if (cache_id == CACHE_LL_ID_ALL) {
Cache_Freeze_L1_ICache1_Disable();
Cache_Freeze_L1_ICache0_Disable();
rom_cache_internal_table_ptr->freeze_l1_icache1_disable();
rom_cache_internal_table_ptr->freeze_l1_icache0_disable();
}
}
@ -773,7 +773,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_unfreeze_dcache(uint32_t cache_id)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Freeze_L1_DCache_Disable();
rom_cache_internal_table_ptr->freeze_l1_dcache_disable();
}
}
@ -786,7 +786,7 @@ __attribute__((always_inline))
static inline void cache_ll_l2_unfreeze_cache(uint32_t cache_id)
{
if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
Cache_Freeze_L2_Cache_Disable();
rom_cache_internal_table_ptr->freeze_l2_cache_disable();
}
}

19
components/hal/esp32p4/include/hal/lp_aon_hal.h Normal file
View File

@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/lp_sys_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
#define lp_aon_hal_inform_wakeup_type(dslp) lp_sys_ll_inform_wakeup_type(dslp)
#ifdef __cplusplus
}
#endif

89
components/hal/esp32p4/include/hal/lp_sys_ll.h Normal file
View File

@ -0,0 +1,89 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C6 LP_SYS register operations
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/lp_system_struct.h"
#include "hal/misc.h"
#include "esp32p4/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get ext1 wakeup source status
* @return The lower 8 bits of the returned value are the bitmap of
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
*/
static inline uint32_t lp_sys_ll_ext1_get_wakeup_status(void)
{
// TODO: IDF-7529
return 0;
}
/**
* @brief Clear the ext1 wakeup source status
*/
static inline void lp_sys_ll_ext1_clear_wakeup_status(void)
{
// TODO: IDF-7529
}
/**
* @brief Set the wake-up LP_IO of the ext1 wake-up source
* @param mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
* @param mode 0: Wake the chip when all selected GPIOs go low
* 1: Wake the chip when any of the selected GPIOs go high
*/
static inline void lp_sys_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
{
// TODO: IDF-7529
}
/**
* @brief Clear all ext1 wakup-source setting
*/
static inline void lp_sys_ll_ext1_clear_wakeup_pins(void)
{
// TODO: IDF-7529
}
/**
* @brief Get ext1 wakeup source setting
* @return The lower 8 bits of the returned value are the bitmap of
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
*/
static inline uint32_t lp_sys_ll_ext1_get_wakeup_pins(void)
{
// TODO: IDF-7529
return 0;
}
/**
* @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0].
* Set the flag to inform
* @param true: deepsleep false: lightsleep
*/
static inline void lp_sys_ll_inform_wakeup_type(bool dslp)
{
if (dslp) {
REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
} else {
REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
}
}
#ifdef __cplusplus
}
#endif

97
components/hal/esp32p4/include/hal/pmu_ll.h
View File

@ -1,12 +1,11 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-P4 PMU register operations
// TODO: IDF-5731
#pragma once
#include <stdlib.h>
@ -21,15 +20,16 @@
extern "C" {
#endif
/**
* @brief Set the power domain that needs to be powered down in the digital power
*
* @param hw Beginning address of the peripheral registers.
* @param mode The pmu mode
* @param flag Digital power domain flag
*
* @return None
*/
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
{
return hw->lp_ext.int_raw.val;
}
FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
{
hw->lp_ext.int_clr.val = mask;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
{
hw->hp_sys[mode].dig_power.val = flag;
@ -45,11 +45,6 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode,
hw->hp_sys[mode].icg_apb = bitmap;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
{
hw->hp_sys[mode].icg_modem.code = code;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_detect_bypass_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool bypass_en)
{
hw->hp_sys[mode].syscntl.power_det_bypass = bypass_en;
@ -106,7 +101,12 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode,
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_mode(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dcm_mode)
{
hw->hp_sys[mode].bias.dcm_mode = mode;
hw->hp_sys[mode].bias.dcm_mode = dcm_mode;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_vset(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dcm_vset)
{
hw->hp_sys[mode].bias.dcm_vset = dcm_vset;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
@ -144,15 +144,6 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *h
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
{
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
{
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
{
@ -164,16 +155,6 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *h
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
{
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
{
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
{
hw->hp_sys[mode].backup_clk = icg_func;
@ -311,8 +292,6 @@ FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mod
hw->lp_sys[mode].bias.bias_sleep = en;
}
/****/
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
{
hw->imm.clk_power.val = flag;
@ -347,11 +326,6 @@ FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
}
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
{
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
}
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
{
if (rootclk_sel) {
@ -379,7 +353,6 @@ FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_a
}
}
/*** */
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
{
hw->power.hp_pd[domain].force_reset = rst;
@ -442,25 +415,24 @@ FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
{
// hw->power.mem_cntl.force_hp_mem_iso = iso;
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_iso = iso;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
{
// hw->power.mem_cntl.force_hp_mem_pd = fpd;
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_pd = fpd;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
{
// hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_no_iso = no_iso;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
{
// hw->power.mem_cntl.force_hp_mem_pu = fpu;
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_pu = fpu;
}
/*** */
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
{
hw->wakeup.cntl0.sleep_req = 1;
@ -479,7 +451,7 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
{
hw->wakeup.cntl2 = wakeup;
hw->wakeup.cntl2.wakeup_ena = wakeup;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
@ -507,6 +479,11 @@ FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
return (hw->hp_ext.int_raw.reject == 1);
}
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
{
hw->hp_ext.int_clr.sw = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
{
hw->hp_ext.int_clr.wakeup = 1;
@ -532,16 +509,6 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_lite_wakeup_cause(pmu_dev_t *hw)
return hw->wakeup.status2;
}
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
{
return hw->lp_ext.int_raw.val;
}
FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
{
hw->lp_ext.int_clr.val = mask;
}
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
{
hw->wakeup.cntl3.lp_min_slp_val = slow_clk_cycle;
@ -597,16 +564,6 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
return hw->wakeup.cntl5.lp_ana_wait_target;
}
FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
{
hw->wakeup.cntl5.modem_wait_target = cycle;
}
FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
{
return hw->wakeup.cntl5.modem_wait_target;
}
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
{
hw->power.clk_wait.wait_xtal_stable = cycle;

15
components/hal/esp32p4/pmu_hal.c
View File

@ -1,14 +1,11 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for PMU (ESP32-P4 specific part)
// TODO: IDF-5731
#include "soc/soc.h"
#include "esp_attr.h"
#include "hal/pmu_hal.h"
@ -51,13 +48,3 @@ void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
}
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal)
{
pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev);
}
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal)
{
pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev);
}

20
components/hal/include/hal/pmu_types.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -19,9 +19,7 @@ extern "C" {
*/
typedef enum {
PMU_MODE_HP_ACTIVE = 0, /*!< PMU in HP_ACTIVE mode */
#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-5731 Use a soc caps
PMU_MODE_HP_MODEM, /*!< PMU in HP_MODEM mode */
#endif
PMU_MODE_HP_SLEEP, /*!< PMU in HP_SLEEP mode */
PMU_MODE_HP_MAX,
} pmu_hp_mode_t;
@ -35,7 +33,13 @@ typedef enum {
PMU_MODE_LP_MAX,
} pmu_lp_mode_t;
#if !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-5731 Use a soc caps
#if CONFIG_IDF_TARGET_ESP32P4
typedef enum {
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
PMU_HP_PD_CNNT = 1, /*!< Power domain of high-speed IO peripherals such as USB/SDIO/Ethernet etc.*/
PMU_HP_PD_HPMEM = 2,
} pmu_hp_power_domain_t;
#else
typedef enum {
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
#if SOC_PM_SUPPORT_HP_AON_PD
@ -45,14 +49,6 @@ typedef enum {
PMU_HP_PD_RESERVED = 3, /*!< Reserved power domain */
PMU_HP_PD_WIFI = 4, /*!< Power domain of WIFI */
} pmu_hp_power_domain_t;
#else // TODO: check this.....
typedef enum {
PMU_HP_PD_TOP = 0, /* Power domain of digital top */
PMU_HP_PD_CNNT = 1, /* Power domain of HP CPU */
PMU_HP_PD_HPMEM = 2, /* HP_MEM */
PMU_HP_PD_RESERVED, /* Reserved power domain*/
PMU_HP_PD_MAX
} pmu_hp_power_domain_t;
#endif
#ifdef __cplusplus

17
components/hal/include/hal/rtc_hal.h
View File

@ -20,6 +20,10 @@
#include "hal/rtc_io_ll.h"
#endif
#if SOC_LP_AON_SUPPORTED
#include "hal/lp_aon_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
@ -51,16 +55,19 @@ typedef struct rtc_cntl_sleep_retent {
#if SOC_PM_SUPPORT_EXT1_WAKEUP
#if SOC_LP_AON_SUPPORTED
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#else
#define rtc_hal_ext1_get_wakeup_status() rtc_cntl_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() rtc_cntl_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) rtc_cntl_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
#define rtc_hal_ext1_clear_wakeup_pins() rtc_cntl_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() rtc_cntl_ll_ext1_get_wakeup_pins()
#endif
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0)

20
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -171,6 +171,10 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_DCDC_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
bool
default y
@ -211,6 +215,10 @@ config SOC_MULTI_USAGE_LDO_SUPPORTED
bool
default y
config SOC_LIGHT_SLEEP_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_40M
bool
default y
@ -1323,14 +1331,6 @@ config SOC_PM_SUPPORT_WIFI_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_MODEM_PD
bool
default y
config SOC_PM_SUPPORT_XTAL32K_PD
bool
default y
@ -1347,6 +1347,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
bool
default y
config SOC_PM_SUPPORT_CNNT_PD
bool
default y
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool
default y

364
components/soc/esp32p4/include/soc/pmu_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -14,32 +14,20 @@ extern "C" {
typedef union {
struct {
uint32_t reserved0 : 21;
// uint32_t vdd_spi_pd_en: 1;
uint32_t dcdc_switch_pd_en :1;//new
uint32_t dcdc_switch_pd_en :1;
uint32_t mem_dslp : 1;
uint32_t mem_pd_en : 1;
// uint32_t wifi_pd_en : 1;
uint32_t reserved1 : 6;
// uint32_t cpu_pd_en : 1;
uint32_t cnnt_pd_en : 1; //new
// uint32_t aon_pd_en : 1;
uint32_t cnnt_pd_en : 1;
uint32_t top_pd_en : 1;
};
uint32_t val;
} pmu_hp_dig_power_reg_t;
typedef union {
struct {
uint32_t reserved0: 30;
uint32_t code : 2;
};
uint32_t val;
} pmu_hp_icg_modem_reg_t;
typedef union {
struct {
uint32_t reserved0 : 23;
uint32_t power_det_bypass : 1; //new
uint32_t power_det_bypass : 1;
uint32_t uart_wakeup_en : 1;
uint32_t lp_pad_hold_all: 1;
uint32_t hp_pad_hold_all: 1;
@ -56,9 +44,8 @@ typedef union {
uint32_t reserved0 : 21;
uint32_t i2c_iso_en : 1;
uint32_t i2c_retention: 1;
// uint32_t xpd_bb_i2c : 1;
uint32_t xpd_pll_i2c : 4; //cha
uint32_t xpd_pll : 4; //cha
uint32_t xpd_pll_i2c : 4;
uint32_t xpd_pll : 4;
uint32_t reserved1 : 1;
};
uint32_t val;
@ -67,8 +54,8 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 18;
uint32_t dcm_vset : 5; //new
uint32_t dcm_mode : 2; //new
uint32_t dcm_vset : 5;
uint32_t dcm_mode : 2;
uint32_t xpd_bias : 1;
uint32_t dbg_atten : 4;
uint32_t pd_cur : 1;
@ -98,18 +85,7 @@ typedef union {
uint32_t reserved5 : 1;
};
struct { /* HP: Modem State */
uint32_t reserved6 : 4;
uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
uint32_t reserved7 : 4;
uint32_t hp_modem_retention_mode : 1;
uint32_t hp_sleep2modem_retention_en : 1;
uint32_t reserved8 : 2;
uint32_t hp_sleep2modem_backup_clk_sel : 2;
uint32_t reserved9 : 4;
uint32_t hp_sleep2modem_backup_mode : 3;
uint32_t reserved10 : 6;
uint32_t hp_sleep2modem_backup_en : 1;
uint32_t reserved11 : 2;
uint32_t reserved6 : 32;
};
struct { /* HP: Sleep State */
uint32_t reserved12 : 6;
@ -181,7 +157,7 @@ typedef struct pmu_hp_hw_regmap_t {
pmu_hp_dig_power_reg_t dig_power;
uint32_t icg_func;
uint32_t icg_apb;
pmu_hp_icg_modem_reg_t icg_modem;
uint32_t icg_modem;
pmu_hp_sys_cntl_reg_t syscntl;
pmu_hp_clk_power_reg_t clk_power;
pmu_hp_bias_reg_t bias;
@ -193,12 +169,11 @@ typedef struct pmu_hp_hw_regmap_t {
pmu_hp_xtal_reg_t xtal;
} pmu_hp_hw_regmap_t;
/** */
typedef union {
struct {
uint32_t reserved0: 21;
uint32_t slp_xpd : 1;
uint32_t xpd : 1;
uint32_t xpd : 1;
uint32_t slp_dbias: 4;
uint32_t dbias : 5;
};
@ -207,8 +182,8 @@ typedef union {
typedef union {
struct {
uint32_t reserved0: 28;
uint32_t drv_b : 4;
uint32_t reserved0: 26;
uint32_t drv_b : 6;
};
uint32_t val;
} pmu_lp_regulator1_reg_t;
@ -224,9 +199,9 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t lp_pad_slp_sel : 1; //new
uint32_t bod_source_sel : 1; //new
uint32_t vddbat_mode : 2; //new
uint32_t lp_pad_slp_sel : 1;
uint32_t bod_source_sel : 1;
uint32_t vddbat_mode : 2;
uint32_t mem_dslp : 1;
uint32_t peri_pd_en: 1;
};
@ -236,7 +211,7 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 27;
uint32_t xpd_lppll : 1; //new
uint32_t xpd_lppll : 1;
uint32_t xpd_xtal32k: 1;
uint32_t xpd_rc32k : 1;
uint32_t xpd_fosc : 1;
@ -268,25 +243,20 @@ typedef struct pmu_lp_hw_regmap_t {
typedef union {
struct {
uint32_t tie_low_cali_xtal_icg : 1; //new
uint32_t tie_low_global_pll_icg : 4;
uint32_t tie_low_global_xtal_icg : 1;
uint32_t tie_low_i2c_retention : 1;
// uint32_t tie_low_xpd_bb_i2c : 1;
uint32_t tie_low_xpd_pll_i2c : 4;
uint32_t tie_low_xpd_pll : 4;
uint32_t tie_low_xpd_xtal : 1;
uint32_t tie_high_cali_xtal_icg : 1; //new
uint32_t tie_high_global_pll_icg : 4;
// uint32_t tie_high_global_bbpll_icg: 1;
uint32_t tie_high_global_xtal_icg : 1;
uint32_t tie_high_i2c_retention : 1;
// uint32_t tie_high_xpd_bb_i2c : 1;
uint32_t tie_high_xpd_pll_i2c : 4;
// uint32_t tie_high_xpd_bbpll_i2c : 1;
uint32_t tie_high_xpd_pll : 4;
// uint32_t tie_high_xpd_bbpll : 1;
uint32_t tie_high_xpd_xtal : 1;
uint32_t tie_low_cali_xtal_icg : 1;
uint32_t tie_low_global_pll_icg : 4;
uint32_t tie_low_global_xtal_icg : 1;
uint32_t tie_low_i2c_retention : 1;
uint32_t tie_low_xpd_pll_i2c : 4;
uint32_t tie_low_xpd_pll : 4;
uint32_t tie_low_xpd_xtal : 1;
uint32_t tie_high_cali_xtal_icg : 1;
uint32_t tie_high_global_pll_icg : 4;
uint32_t tie_high_global_xtal_icg : 1;
uint32_t tie_high_i2c_retention : 1;
uint32_t tie_high_xpd_pll_i2c : 4;
uint32_t tie_high_xpd_pll : 4;
uint32_t tie_high_xpd_xtal : 1;
};
uint32_t val;
} pmu_imm_hp_clk_power_reg_t;
@ -337,12 +307,12 @@ typedef union {
typedef union {
struct {
uint32_t pad_slp_sel : 1;//new
uint32_t lp_pad_hold_all : 1;//new
uint32_t hp_pad_hold_all : 1;//new
uint32_t pad_slp_sel : 1;
uint32_t lp_pad_hold_all : 1;
uint32_t hp_pad_hold_all : 1;
uint32_t reserved0 : 23;
uint32_t tie_high_pad_slp_sel : 1;//new
uint32_t tie_low_pad_slp_sel : 1;//new
uint32_t tie_high_pad_slp_sel : 1;
uint32_t tie_low_pad_slp_sel : 1;
uint32_t tie_high_lp_pad_hold_all: 1;
uint32_t tie_low_lp_pad_hold_all : 1;
uint32_t tie_high_hp_pad_hold_all: 1;
@ -399,12 +369,10 @@ typedef union {
uint32_t force_no_reset: 1;
uint32_t force_no_iso : 1;
uint32_t force_pd : 1;
// uint32_t pd_top_mask : 5;
uint32_t reserved0 : 26; /* Invalid of lp peripherals */
// uint32_t top_pd_mask : 5;
};
uint32_t val;
} pmu_power_domain_cntl_t;
} pmu_power_domain_cntl_reg_t;
typedef union {
struct {
@ -413,39 +381,16 @@ typedef union {
uint32_t top_pd_mask : 5;
};
uint32_t val;
} pmu_power_domain_mask_t;
} pmu_power_domain_mask_reg_t;
typedef union {
struct {
uint32_t force_pu : 1; /*need_des*/
uint32_t force_pd : 1; /*need_des*/
uint32_t force_pu : 1;
uint32_t force_pd : 1;
uint32_t reserved2 : 30;
};
uint32_t val;
} pmu_power_dcdc_switch_t;
// typedef union {
// struct {
// uint32_t force_hp_mem_iso : 4;
// uint32_t force_hp_mem_pd : 4;
// uint32_t reserved0 : 16;
// uint32_t force_hp_mem_no_iso: 4;
// uint32_t force_hp_mem_pu : 4;
// };
// uint32_t val;
// } pmu_power_memory_cntl_reg_t;
// typedef union {
// struct {
// uint32_t mem2_pd_mask: 5;
// uint32_t mem1_pd_mask: 5;
// uint32_t mem0_pd_mask: 5;
// uint32_t reserved0 : 2;
// uint32_t mem2_mask : 5;
// uint32_t mem1_mask : 5;
// uint32_t mem0_mask : 5;
// };
// uint32_t val;
// } pmu_power_memory_mask_reg_t;
} pmu_power_dcdc_switch_reg_t;
typedef union {
struct {
@ -456,16 +401,6 @@ typedef union {
uint32_t val;
} pmu_power_hp_pad_reg_t;
// typedef union {
// struct {
// uint32_t reserved0 : 18;
// uint32_t pwr_wait : 11;
// uint32_t pwr_sw : 2;
// uint32_t pwr_sel_sw: 1;
// };
// uint32_t val;
// } pmu_power_vdd_spi_cntl_reg_t;
typedef union {
struct {
uint32_t wait_xtal_stable: 16;
@ -477,15 +412,12 @@ typedef union {
typedef struct pmu_power_hw_regmap_t {
pmu_power_wait_timer0_reg_t wait_timer0;
pmu_power_wait_timer1_reg_t wait_timer1;
pmu_power_domain_cntl_t hp_pd[3];
pmu_power_domain_mask_t hp_pd_mask[3];
pmu_power_dcdc_switch_t dcdc_switch;
pmu_power_domain_cntl_t lp_peri;
pmu_power_domain_mask_t lp_peri_mask;
// pmu_power_memory_cntl_reg_t mem_cntl;
// pmu_power_memory_mask_reg_t mem_mask;
pmu_power_domain_cntl_reg_t hp_pd[3];
pmu_power_domain_mask_reg_t hp_pd_mask[3];
pmu_power_dcdc_switch_reg_t dcdc_switch;
pmu_power_domain_cntl_reg_t lp_peri;
pmu_power_domain_mask_reg_t lp_peri_mask;
pmu_power_hp_pad_reg_t hp_pad;
// pmu_power_vdd_spi_cntl_reg_t vdd_spi;
pmu_power_clk_wait_cntl_reg_t clk_wait;
} pmu_power_hw_regmap_t;
@ -505,6 +437,14 @@ typedef union {
uint32_t val;
} pmu_slp_wakeup_cntl1_reg_t;
typedef union {
struct {
uint32_t wakeup_ena: 31;
uint32_t reserved0 : 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl2_reg_t;
typedef union {
struct {
uint32_t lp_min_slp_val: 8;
@ -551,8 +491,8 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t lp_lite_wakeup_ena: 1;
uint32_t reserved0 : 31;
uint32_t lp_lite_wakeup_ena : 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl8_reg_t;
@ -560,16 +500,16 @@ typedef union {
typedef struct pmu_wakeup_hw_regmap_t {
pmu_slp_wakeup_cntl0_reg_t cntl0;
pmu_slp_wakeup_cntl1_reg_t cntl1;
uint32_t cntl2;
pmu_slp_wakeup_cntl2_reg_t cntl2;
pmu_slp_wakeup_cntl3_reg_t cntl3;
pmu_slp_wakeup_cntl4_reg_t cntl4;
pmu_slp_wakeup_cntl5_reg_t cntl5;
pmu_slp_wakeup_cntl6_reg_t cntl6;
pmu_slp_wakeup_cntl7_reg_t cntl7;
pmu_slp_wakeup_cntl8_reg_t cntl8;//new
pmu_slp_wakeup_cntl8_reg_t cntl8;
uint32_t status0;
uint32_t status1;
uint32_t status2;//new
uint32_t status2;
} pmu_wakeup_hw_regmap_t;
typedef union {
@ -600,14 +540,13 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 24;
uint32_t mspi_phy_xpd : 1;//new
uint32_t sdio_pll_xpd : 1;//new
uint32_t mspi_phy_xpd : 1;
uint32_t sdio_pll_xpd : 1;
uint32_t perif_i2c_rstb: 1;
uint32_t xpd_perif_i2c : 1;
uint32_t xpd_txrf_i2c : 1;
uint32_t xpd_rfrx_pbus : 1;
uint32_t xpd_ckgen_i2c : 1;
// uint32_t xpd_pll_i2c : 1;
uint32_t reserved1 : 1;
};
uint32_t val;
@ -624,18 +563,18 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 14;
uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;//new
uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;//new
uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;//new
uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;//new
uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;//new
uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;//new
uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;//new
uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;//new
uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;//new
uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;//new
uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;//new
uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;//new
uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
uint32_t reserved1 : 1;
uint32_t lp_exception: 1;
uint32_t sdio_idle: 1;
@ -660,32 +599,26 @@ typedef struct pmu_hp_ext_hw_regmap_t {
typedef union {
struct {
uint32_t reserved0 : 13;
uint32_t sleep_reject : 1;//new
uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;//new
uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;//new
uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;//new
uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;//new
uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;//new
uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;//new
uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;//new
uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;//new
uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;//new
uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;//new
uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;//new
uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;//new
uint32_t lp_wakeup : 1;
// uint32_t modem_switch_active_end : 1;
uint32_t sleep_switch_active_end : 1;
// uint32_t sleep_switch_modem_end : 1;
// uint32_t modem_switch_sleep_end : 1;
uint32_t active_switch_sleep_end : 1;
// uint32_t modem_switch_active_start: 1;
uint32_t sleep_switch_active_start: 1;
// uint32_t sleep_switch_modem_start : 1;
// uint32_t modem_switch_sleep_start : 1;
uint32_t active_switch_sleep_start: 1;
uint32_t hp_sw_trigger : 1;
uint32_t reserved0 : 13;
uint32_t sleep_reject : 1;
uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
uint32_t lp_wakeup : 1;
uint32_t sleep_switch_active_end : 1;
uint32_t active_switch_sleep_end : 1;
uint32_t sleep_switch_active_start : 1;
uint32_t active_switch_sleep_start : 1;
uint32_t hp_sw_trigger : 1;
};
uint32_t val;
} pmu_lp_intr_reg_t;
@ -708,7 +641,6 @@ typedef union {
typedef union {
struct {
// uint32_t wakeup_en: 16;
uint32_t reserved0: 31;
uint32_t sleep_req: 1;
};
@ -721,7 +653,7 @@ typedef union {
uint32_t reserved0: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr2_reg_t; //new
} pmu_lp_cpu_pwr2_reg_t;
typedef union {
struct {
@ -729,7 +661,7 @@ typedef union {
uint32_t reserved0: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr3_reg_t; //new
} pmu_lp_cpu_pwr3_reg_t;
typedef union {
struct {
@ -737,7 +669,7 @@ typedef union {
uint32_t reserved0: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr4_reg_t; //new
} pmu_lp_cpu_pwr4_reg_t;
typedef union {
struct {
@ -745,7 +677,7 @@ typedef union {
uint32_t reserved0: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr5_reg_t; //new
} pmu_lp_cpu_pwr5_reg_t;
typedef struct pmu_lp_ext_hw_regmap_t {
pmu_lp_intr_reg_t int_raw;
@ -760,92 +692,40 @@ typedef struct pmu_lp_ext_hw_regmap_t {
pmu_lp_cpu_pwr5_reg_t pwr5;
} pmu_lp_ext_hw_regmap_t;
typedef struct {
volatile struct {
} common;
} pmu_hp_lp_hw_regmap_t;
/** Type of pmu_ext_ldo register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:7;
/** force_tieh_sel : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t force_tieh_sel:1;
/** xpd : R/W; bitpos: [8]; default: 1;
* need_des
*/
uint32_t xpd:1;
/** tieh_sel : R/W; bitpos: [11:9]; default: 0;
* need_des
*/
uint32_t tieh_sel:3;
/** tieh_pos_en : R/W; bitpos: [12]; default: 0;
* need_des
*/
uint32_t tieh_pos_en:1;
/** tieh_neg_en : R/W; bitpos: [13]; default: 0;
* need_des
*/
uint32_t tieh_neg_en:1;
/** tieh : R/W; bitpos: [14]; default: 0;
* need_des
*/
uint32_t tieh:1;
/** target1 : R/W; bitpos: [22:15]; default: 64;
* need_des
*/
uint32_t target1:8;
/** target0 : R/W; bitpos: [30:23]; default: 128;
* need_des
*/
uint32_t target0:8;
/** ldo_cnt_prescaler_sel : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ldo_cnt_prescaler_sel:1;
};
uint32_t val;
} pmu_ext_ldo_reg_t;
/** Type of pmu_ext_ldo_ana register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** mul : R/W; bitpos: [25:23]; default: 2;
* need_des
*/
uint32_t mul:3;
/** en_vdet : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t en_vdet:1;
/** en_cur_lim : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t en_cur_lim:1;
/** dref : R/W; bitpos: [31:28]; default: 11;
* need_des
*/
uint32_t dref:4;
};
uint32_t val;
} pmu_ext_ldo_ana_reg_t;
/** Type of ahb_dma_in_chn_reg_t register
* need_des
*/
typedef struct {
volatile pmu_ext_ldo_reg_t pmu_ext_ldo;
volatile pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana;
typedef struct pmu_ext_ldo_info_t {
pmu_ext_ldo_reg_t pmu_ext_ldo;
pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana;
} pmu_ext_ldo_info_t;
typedef union {
struct {
uint32_t on_req : 1;
@ -868,7 +748,7 @@ typedef union {
uint32_t reserved2 : 2;
};
uint32_t val;
} pmu_dcm_ctrl_reg_t; //new
} pmu_dcm_ctrl_reg_t;
typedef union {
struct {
@ -911,7 +791,7 @@ typedef struct pmu_dev_t {
union {
struct {
uint32_t reserved0 : 30;
volatile uint32_t reserved0 : 30;
volatile uint32_t lp_trigger_hp: 1;
volatile uint32_t hp_trigger_lp: 1;
};
@ -920,7 +800,7 @@ typedef struct pmu_dev_t {
union {
struct {
uint32_t reserved0 : 31;
volatile uint32_t reserved0 : 31;
volatile uint32_t dig_regulator_en_cal: 1;
};
volatile uint32_t val;
@ -928,8 +808,8 @@ typedef struct pmu_dev_t {
union {
struct {
volatile uint32_t en_cali_pmu_cntl : 1;//new
uint32_t reserved0 : 10;
volatile uint32_t en_cali_pmu_cntl : 1;
volatile uint32_t reserved0 : 10;
volatile uint32_t last_st : 7;
volatile uint32_t target_st : 7;
volatile uint32_t current_st: 7;
@ -939,18 +819,17 @@ typedef struct pmu_dev_t {
union {
struct {
uint32_t reserved0: 13;
volatile uint32_t reserved0: 13;
volatile uint32_t backup_st: 5;
volatile uint32_t lp_pwr_st: 5;
volatile uint32_t hp_pwr_st: 9;
};
volatile uint32_t val;
volatile int32_t val;
} pwr_state;
union {
struct {
// uint32_t stable_xpd_bbpll : 1;
volatile uint32_t stable_xpd_bbpll : 3;//new
volatile uint32_t stable_xpd_bbpll : 3;
volatile uint32_t stable_xpd_xtal : 1;
volatile uint32_t ana_xpd_pll_i2c : 3;
volatile uint32_t reserved0 : 3;
@ -966,10 +845,7 @@ typedef struct pmu_dev_t {
volatile uint32_t ana_i2c_iso_en : 1;
volatile uint32_t ana_i2c_retention: 1;
volatile uint32_t reserved1 : 1;
// uint32_t ana_xpd_bb_i2c : 1;
// uint32_t ana_xpd_bbpll_i2c: 1;
// uint32_t ana_xpd_bbpll : 1;
volatile uint32_t ana_xpd_pll : 4;//new
volatile uint32_t ana_xpd_pll : 4;
volatile uint32_t ana_xpd_xtal : 1;
};
volatile uint32_t val;
@ -985,7 +861,7 @@ typedef struct pmu_dev_t {
volatile uint32_t ext_wakeup_st;
union {
struct {
uint32_t reserved0 : 30;
volatile uint32_t reserved0 : 30;
volatile uint32_t status_clr : 1;
volatile uint32_t filter : 1;
};
@ -995,14 +871,14 @@ typedef struct pmu_dev_t {
union {
struct {
volatile uint32_t act_dnum : 10;
uint32_t reserved0 : 22;
volatile uint32_t reserved0 : 22;
};
volatile uint32_t val;
} sdio_wakeup_cntl;
union {
struct {
uint32_t reserved0 : 16;
volatile uint32_t reserved0 : 16;
volatile uint32_t cnt_target : 16;
};
volatile uint32_t val;
@ -1010,22 +886,22 @@ typedef struct pmu_dev_t {
union {
struct {
uint32_t reserved0 : 16;
volatile uint32_t reserved0 : 16;
volatile uint32_t hpcore1_stall_code : 8;
volatile uint32_t hpcore0_stall_code : 8;
};
volatile uint32_t val;
} cpu_sw_stall;
volatile pmu_dcm_ctrl_reg_t dcm_ctrl; //new
volatile pmu_dcm_wait_delay_t dcm_delay;//new
volatile pmu_vddbat_cfg_t vbat_cfg;//new
volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl;//new
volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
volatile pmu_dcm_wait_delay_t dcm_delay;
volatile pmu_vddbat_cfg_t vbat_cfg;
volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl;
union {
struct {
volatile uint32_t eco_result:1;
uint32_t reserved0 : 30;
volatile uint32_t reserved0 : 30;
volatile uint32_t eco_en: 1;
};

11
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -68,7 +68,8 @@
#define SOC_SECURE_BOOT_SUPPORTED 1
// #define SOC_BOD_SUPPORTED 1 //TODO: IDF-7519
// #define SOC_APM_SUPPORTED 1 //TODO: IDF-7542
#define SOC_PMU_SUPPORTED 1 //TODO: IDF-7531
#define SOC_PMU_SUPPORTED 1
#define SOC_DCDC_SUPPORTED 1
// #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
#define SOC_LP_TIMER_SUPPORTED 1
// #define SOC_ULP_LP_UART_SUPPORTED 1 //TODO: IDF-7533
@ -86,7 +87,7 @@
// #define SOC_RNG_SUPPORTED 1 //TODO: IDF-6522
#define SOC_MULTI_USAGE_LDO_SUPPORTED 1
// #define SOC_PPA_SUPPORTED 1 //TODO: IDF-6878
// #define SOC_LIGHT_SLEEP_SUPPORTED 1 //TODO: IDF-7528
#define SOC_LIGHT_SLEEP_SUPPORTED 1
// #define SOC_DEEP_SLEEP_SUPPORTED 1 //TODO: IDF-7529
/*-------------------------- XTAL CAPS ---------------------------------------*/
@ -560,13 +561,13 @@
// TODO: IDF-5351 (Copy from esp32c3, need check)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1)
// #define SOC_PM_SUPPORT_CPU_PD (1) //TODO: IDF-7528
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
#define SOC_PM_SUPPORT_RC32K_PD (1)
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
// #define SOC_PM_SUPPORT_TOP_PD (1) // TODO: IDF-7531
// #define SOC_PM_SUPPORT_TOP_PD (1) //TODO: IDF-7528
#define SOC_PM_SUPPORT_CNNT_PD (1)
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */

4
examples/system/esp_timer/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# ESP Timer Example (High Resolution Timer)

1
examples/system/esp_timer/pytest_esp_timer.py
View File

@ -28,7 +28,6 @@ ONE_SHOT_TIMER_PERIOD = 5000000
@pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='Light Sleep support TBD') # TODO: IDF-7528
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

4
examples/system/light_sleep/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Light Sleep Example

2
examples/system/light_sleep/main/gpio_wakeup.c
View File

@ -15,6 +15,8 @@
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 \
|| CONFIG_IDF_TARGET_ESP32C6
#define BOOT_BUTTON_NUM 9
#elif CONFIG_IDF_TARGET_ESP32P4
#define BOOT_BUTTON_NUM 35
#else
#define BOOT_BUTTON_NUM 0
#endif

8
examples/system/light_sleep/main/uart_wakeup.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -102,7 +102,11 @@ static esp_err_t uart_initialization(void)
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
.source_clk = UART_SCLK_DEFAULT,
#if SOC_UART_SUPPORT_REF_TICK
.source_clk = UART_SCLK_REF_TICK,
#elif SOC_UART_SUPPORT_XTAL_CLK
.source_clk = UART_SCLK_XTAL
#endif
};
//Install UART driver, and get the queue.
ESP_RETURN_ON_ERROR(uart_driver_install(EXAMPLE_UART_NUM, EXAMPLE_UART_BUF_SIZE, EXAMPLE_UART_BUF_SIZE, 20, &uart_evt_que, 0),

4
examples/system/light_sleep/pytest_light_sleep.py
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@ -1,6 +1,5 @@
# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import logging
import time
@ -8,7 +7,6 @@ import pytest
from pytest_embedded import Dut
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD')
@pytest.mark.supported_targets
@pytest.mark.generic
def test_light_sleep(dut: Dut) -> None:
@ -17,7 +15,7 @@ def test_light_sleep(dut: Dut) -> None:
EXIT_SLEEP_REGEX = r'Returned from light sleep, reason: (\w+), t=(\d+) ms, slept for (\d+) ms'
EXIT_SLEEP_PIN_REGEX = r'Returned from light sleep, reason: (pin), t=(\d+) ms, slept for (\d+) ms'
EXIT_SLEEP_UART_REGEX = r'Returned from light sleep, reason: (uart), t=(\d+) ms, slept for (\d+) ms'
WAITING_FOR_GPIO_STR = r'Waiting for GPIO\d to go high...'
WAITING_FOR_GPIO_STR = r'Waiting for GPIO\d+ to go high...'
WAKEUP_INTERVAL_MS = 2000