test(intr): fix intr dump test for C61 and re-enable it

tools/test_apps/system/.build-test-rules.yml

@@ -29,10 +29,6 @@ tools/test_apps/system/eh_frame:
       reason: Only relevant for riscv targets
 
 tools/test_apps/system/esp_intr_dump:
-  disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: test failed # TODO: IDF-10957
 
 tools/test_apps/system/g0_components:
   enable:

tools/test_apps/system/esp_intr_dump/expected_output/esp32c61.txt

@@ -0,0 +1,36 @@
+CPU 0 interrupt status:
+ Int  Level  Type   Status
+  0     1    Level  Shared: LP_RTC_TIMER
+  1     *      *    Reserved
+  2     1    Level  Used: CPU_FROM_CPU_0
+  3     1    Level  Used: SYSTIMER_TARGET0
+  4     1    Level  Used: TG0_WDT
+  5     1    Level  Used: UART0
+  6     *      *    Reserved
+  7     *      *    Free
+  8     *      *    Free
+  9     *      *    Free
+ 10     *      *    Free
+ 11     *      *    Free
+ 12     *      *    Free
+ 13     *      *    Free
+ 14     *      *    Free
+ 15     *      *    Free
+ 16     *      *    Free
+ 17     *      *    Free
+ 18     *      *    Free
+ 19     *      *    Free
+ 20     *      *    Free
+ 21     *      *    Free
+ 22     *      *    Free
+ 23     *      *    Free
+ 24     *      *    Reserved
+ 25     *      *    Reserved
+ 26     *      *    Free
+ 27     *      *    Free
+ 28     *      *    Free
+ 29     *      *    Free
+ 30     *      *    Free
+ 31     *      *    Free
+Interrupts available for general use: 23
+Shared interrupts: 1

tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py

@@ -48,7 +48,6 @@ def test_esp_intr_dump_shared(dut: Dut) -> None:
 
 # TODO: IDF-9512, Update the expected output of dual core RISC-V chips when the issue is resolved
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail')    # TODO: IDF-10957
 @pytest.mark.generic
 def test_esp_intr_dump_expected_output(dut: Dut) -> None:
     dut.expect_exact(PROMPT, timeout=30)