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Merge branch 'change/remove_sdm_and_glitch_filter_on_c61' into 'master'

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Change(sdm,glitch_filter): remove sdm and glitch filter on c61

Closes IDF-9340 and IDF-9335

See merge request espressif/esp-idf!32691
This commit is contained in:
Chen Ji Chang 2024-08-21 19:28:05 +08:00
commit b8b845a96a
3 changed files with 6 additions and 18 deletions
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4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@ -227,6 +227,10 @@ config SOC_GPIO_PIN_COUNT
int
default 22
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y

16
components/soc/esp32c61/include/soc/clk_tree_defs.h
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@ -258,22 +258,6 @@ typedef enum {
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
*/
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum {
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**

4
components/soc/esp32c61/include/soc/soc_caps.h
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@ -161,10 +161,10 @@
// ESP32-C61 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 22
// \#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// GPIO peripheral has the ETM extension
// \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9340
// \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9318
// Target has the full LP IO subsystem
// On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.