From b7f4c46a823251c77c5e203fa195ee6172207960 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Tue, 22 Dec 2020 19:35:05 +1100 Subject: [PATCH] soc: Update esp32c3 soc headers From internal commit 6d894813 --- .../soc/esp32c3/include/soc/dac_channel.h | 24 - .../soc/esp32c3/include/soc/host_struct.h | 602 --------------- components/soc/esp32c3/include/soc/i2s_caps.h | 9 +- .../soc/esp32c3/include/soc/i2s_struct.h | 2 +- .../soc/esp32c3/include/soc/io_mux_reg.h | 12 + components/soc/esp32c3/include/soc/mmu.h | 2 +- components/soc/esp32c3/include/soc/rtc.h | 133 ++-- .../soc/esp32c3/include/soc/rtc_cntl_reg.h | 21 +- .../esp32c3/include/soc/rtc_gpio_channel.h | 73 -- components/soc/esp32c3/include/soc/soc.h | 10 + components/soc/esp32c3/include/soc/soc_caps.h | 16 + .../soc/esp32c3/include/soc/syscon_reg.h | 45 +- .../soc/esp32c3/include/soc/usb_device_reg.h | 707 ------------------ .../esp32c3/include/soc/usb_device_struct.h | 261 ------- components/soc/esp32c3/rtc_periph.c | 0 components/soc/esp32c3/sdio_slave_periph.c | 42 -- components/soc/esp32c3/soc_memory_layout.c | 2 +- 17 files changed, 149 insertions(+), 1812 deletions(-) delete mode 100644 components/soc/esp32c3/include/soc/dac_channel.h delete mode 100644 components/soc/esp32c3/include/soc/host_struct.h delete mode 100644 components/soc/esp32c3/include/soc/rtc_gpio_channel.h delete mode 100644 components/soc/esp32c3/include/soc/usb_device_reg.h delete mode 100644 components/soc/esp32c3/include/soc/usb_device_struct.h delete mode 100644 components/soc/esp32c3/rtc_periph.c delete mode 100644 components/soc/esp32c3/sdio_slave_periph.c diff --git a/components/soc/esp32c3/include/soc/dac_channel.h b/components/soc/esp32c3/include/soc/dac_channel.h deleted file mode 100644 index 175158f785..0000000000 --- a/components/soc/esp32c3/include/soc/dac_channel.h +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _SOC_DAC_CHANNEL_H -#define _SOC_DAC_CHANNEL_H - -#define DAC_GPIO17_CHANNEL DAC_CHANNEL_1 -#define DAC_CHANNEL_1_GPIO_NUM 17 - -#define DAC_GPIO18_CHANNEL DAC_CHANNEL_2 -#define DAC_CHANNEL_2_GPIO_NUM 18 - -#endif diff --git a/components/soc/esp32c3/include/soc/host_struct.h b/components/soc/esp32c3/include/soc/host_struct.h deleted file mode 100644 index fd7844c384..0000000000 --- a/components/soc/esp32c3/include/soc/host_struct.h +++ /dev/null @@ -1,602 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_HOST_STRUCT_H_ -#define _SOC_HOST_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - uint32_t reserved_0; - uint32_t reserved_4; - uint32_t reserved_8; - uint32_t reserved_c; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - uint32_t reserved_1c; - union { - struct { - uint32_t func1_mdstat: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } func2_2; - uint32_t reserved_24; - uint32_t reserved_28; - uint32_t reserved_2c; - uint32_t reserved_30; - uint32_t gpio_status0; /**/ - union { - struct { - uint32_t sdio_int1: 22; - uint32_t reserved22: 10; - }; - uint32_t val; - } gpio_status1; - uint32_t gpio_in0; /**/ - union { - struct { - uint32_t sdio_in1: 22; - uint32_t reserved22: 10; - }; - uint32_t val; - } gpio_in1; - union { - struct { - uint32_t token0: 12; - uint32_t rx_pf_valid: 1; - uint32_t reserved13: 3; - uint32_t reg_token1: 12; - uint32_t rx_pf_eof: 4; - }; - uint32_t val; - } slc0_token_rdata; - uint32_t slc0_pf; /**/ - uint32_t reserved_4c; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_raw; - uint32_t reserved_54; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_st; - uint32_t reserved_5c; - union { - struct { - uint32_t reg_slc0_len: 20; - uint32_t reg_slc0_len_check:12; - }; - uint32_t val; - } pkt_len; - union { - struct { - uint32_t state0: 8; - uint32_t state1: 8; - uint32_t state2: 8; - uint32_t state3: 8; - }; - uint32_t val; - } state_w0; - union { - struct { - uint32_t state4: 8; - uint32_t state5: 8; - uint32_t state6: 8; - uint32_t state7: 8; - }; - uint32_t val; - } state_w1; - union { - struct { - uint32_t conf0: 8; - uint32_t conf1: 8; - uint32_t conf2: 8; - uint32_t conf3: 8; - }; - uint32_t val; - } conf_w0; - union { - struct { - uint32_t conf4: 8; - uint32_t conf5: 8; - uint32_t conf6: 8; - uint32_t conf7: 8; - }; - uint32_t val; - } conf_w1; - union { - struct { - uint32_t conf8: 8; - uint32_t conf9: 8; - uint32_t conf10: 8; - uint32_t conf11: 8; - }; - uint32_t val; - } conf_w2; - union { - struct { - uint32_t conf12: 8; - uint32_t conf13: 8; - uint32_t conf14: 8; - uint32_t conf15: 8; - }; - uint32_t val; - } conf_w3; - union { - struct { - uint32_t conf16: 8; /*SLC timeout value*/ - uint32_t conf17: 8; /*SLC timeout enable*/ - uint32_t conf18: 8; - uint32_t conf19: 8; /*Interrupt to target CPU*/ - }; - uint32_t val; - } conf_w4; - union { - struct { - uint32_t conf20: 8; - uint32_t conf21: 8; - uint32_t conf22: 8; - uint32_t conf23: 8; - }; - uint32_t val; - } conf_w5; - union { - struct { - uint32_t win_cmd: 16; - uint32_t reserved16: 16; - }; - uint32_t val; - } win_cmd; - union { - struct { - uint32_t conf24: 8; - uint32_t conf25: 8; - uint32_t conf26: 8; - uint32_t conf27: 8; - }; - uint32_t val; - } conf_w6; - union { - struct { - uint32_t conf28: 8; - uint32_t conf29: 8; - uint32_t conf30: 8; - uint32_t conf31: 8; - }; - uint32_t val; - } conf_w7; - union { - struct { - uint32_t reg_slc0_len0: 20; - uint32_t reg_slc0_len0_check:12; - }; - uint32_t val; - } pkt_len0; - union { - struct { - uint32_t reg_slc0_len1: 20; - uint32_t reg_slc0_len1_check:12; - }; - uint32_t val; - } pkt_len1; - union { - struct { - uint32_t reg_slc0_len2: 20; - uint32_t reg_slc0_len2_check:12; - }; - uint32_t val; - } pkt_len2; - union { - struct { - uint32_t conf32: 8; - uint32_t conf33: 8; - uint32_t conf34: 8; - uint32_t conf35: 8; - }; - uint32_t val; - } conf_w8; - union { - struct { - uint32_t conf36: 8; - uint32_t conf37: 8; - uint32_t conf38: 8; - uint32_t conf39: 8; - }; - uint32_t val; - } conf_w9; - union { - struct { - uint32_t conf40: 8; - uint32_t conf41: 8; - uint32_t conf42: 8; - uint32_t conf43: 8; - }; - uint32_t val; - } conf_w10; - union { - struct { - uint32_t conf44: 8; - uint32_t conf45: 8; - uint32_t conf46: 8; - uint32_t conf47: 8; - }; - uint32_t val; - } conf_w11; - union { - struct { - uint32_t conf48: 8; - uint32_t conf49: 8; - uint32_t conf50: 8; - uint32_t conf51: 8; - }; - uint32_t val; - } conf_w12; - union { - struct { - uint32_t conf52: 8; - uint32_t conf53: 8; - uint32_t conf54: 8; - uint32_t conf55: 8; - }; - uint32_t val; - } conf_w13; - union { - struct { - uint32_t conf56: 8; - uint32_t conf57: 8; - uint32_t conf58: 8; - uint32_t conf59: 8; - }; - uint32_t val; - } conf_w14; - union { - struct { - uint32_t conf60: 8; - uint32_t conf61: 8; - uint32_t conf62: 8; - uint32_t conf63: 8; - }; - uint32_t val; - } conf_w15; - uint32_t check_sum0; /**/ - uint32_t check_sum1; /**/ - uint32_t reserved_c4; - union { - struct { - uint32_t token0_wd: 12; - uint32_t reserved12: 4; - uint32_t token1_wd: 12; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_token_wdata; - uint32_t reserved_cc; - union { - struct { - uint32_t slc0_token0_dec: 1; - uint32_t slc0_token1_dec: 1; - uint32_t slc0_token0_wr: 1; - uint32_t slc0_token1_wr: 1; - uint32_t reserved4: 4; - uint32_t slc0_len_wr: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } token_con; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_clr; - uint32_t reserved_d8; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_func1_int_ena; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_ena; - uint32_t reserved_f0; - union { - struct { - uint32_t infor: 20; - uint32_t reserved20: 12; - }; - uint32_t val; - } slc0_rx_infor; - uint32_t reserved_f8; - uint32_t slc0_len_wd; /**/ - uint32_t apbwin_wdata; /**/ - union { - struct { - uint32_t addr: 28; - uint32_t wr: 1; - uint32_t start: 1; - uint32_t bus: 1; - uint32_t reserved31: 1; - }; - uint32_t val; - } apbwin_conf; - uint32_t apbwin_rdata; /**/ - union { - struct { - uint32_t bit7_clraddr: 9; - uint32_t bit6_clraddr: 9; - uint32_t reserved18: 14; - }; - uint32_t val; - } slc0_rdclr; - uint32_t reserved_110; - union { - struct { - uint32_t tohost_bit01: 1; - uint32_t tohost_bit11: 1; - uint32_t tohost_bit21: 1; - uint32_t tohost_bit31: 1; - uint32_t tohost_bit41: 1; - uint32_t tohost_bit51: 1; - uint32_t tohost_bit61: 1; - uint32_t tohost_bit71: 1; - uint32_t token0_1to01: 1; - uint32_t token1_1to01: 1; - uint32_t token0_0to11: 1; - uint32_t token1_0to11: 1; - uint32_t rx_sof1: 1; - uint32_t rx_eof1: 1; - uint32_t rx_start1: 1; - uint32_t tx_start1: 1; - uint32_t rx_udf1: 1; - uint32_t tx_ovf1: 1; - uint32_t rx_pf_valid1: 1; - uint32_t ext_bit01: 1; - uint32_t ext_bit11: 1; - uint32_t ext_bit21: 1; - uint32_t ext_bit31: 1; - uint32_t rx_new_packet1: 1; - uint32_t rd_retry1: 1; - uint32_t gpio_sdio1: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_ena1; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t date; /**/ - uint32_t id; /**/ - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - union { - struct { - uint32_t frc_sdio11: 5; - uint32_t frc_sdio20: 5; - uint32_t frc_neg_samp: 5; - uint32_t frc_pos_samp: 5; - uint32_t frc_quick_in: 5; - uint32_t sdio20_int_delay: 1; - uint32_t sdio_pad_pullup: 1; - uint32_t hspeed_con_en: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t sdio20_mode: 5; - uint32_t sdio_neg_samp: 5; - uint32_t sdio_quick_in: 5; - uint32_t reserved15: 17; - }; - uint32_t val; - } inf_st; -} host_dev_t; -extern host_dev_t HOST; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_HOST_STRUCT_H_ */ diff --git a/components/soc/esp32c3/include/soc/i2s_caps.h b/components/soc/esp32c3/include/soc/i2s_caps.h index 44c8075316..69dfb68373 100644 --- a/components/soc/esp32c3/include/soc/i2s_caps.h +++ b/components/soc/esp32c3/include/soc/i2s_caps.h @@ -14,12 +14,9 @@ #pragma once -#define APLL_MIN_FREQ (250000000) -#define APLL_MAX_FREQ (500000000) -#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware +#define SOC_I2S_APLL_MIN_FREQ (250000000) +#define SOC_I2S_APLL_MAX_FREQ (500000000) +#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware #define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated -// ESP32-S3 have 1 I2S #define SOC_I2S_NUM (1) - -#define SOC_I2S_SUPPORT_PDM (0) // ESP32-S3 do not support PDM diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h index ab788041bf..2f9c862b85 100644 --- a/components/soc/esp32c3/include/soc/i2s_struct.h +++ b/components/soc/esp32c3/include/soc/i2s_struct.h @@ -328,7 +328,7 @@ typedef volatile struct { uint32_t val; } date; } i2s_dev_t; -extern i2s_dev_t I2S1; +extern i2s_dev_t I2S0; #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/include/soc/io_mux_reg.h index 0ba14b6609..254872a5fc 100644 --- a/components/soc/esp32c3/include/soc/io_mux_reg.h +++ b/components/soc/esp32c3/include/soc/io_mux_reg.h @@ -73,6 +73,18 @@ #define MCU_SEL_V 0x7 #define MCU_SEL_S 12 +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + + #define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) #define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) #define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); diff --git a/components/soc/esp32c3/include/soc/mmu.h b/components/soc/esp32c3/include/soc/mmu.h index d8db3d5c12..27d646c301 100644 --- a/components/soc/esp32c3/include/soc/mmu.h +++ b/components/soc/esp32c3/include/soc/mmu.h @@ -32,7 +32,7 @@ extern "C" { #define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK #define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash #define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE -#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM_LOW +#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START #define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) #define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index e6700f374f..6cd86ef830 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -68,11 +68,16 @@ extern "C" { * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. * Valid if RTC_CNTL_DBG_ATTEN is 0. */ -#define RTC_CNTL_DBIAS_1V00 0 -#define RTC_CNTL_DBIAS_1V05 4 -#define RTC_CNTL_DBIAS_1V10 5 -#define RTC_CNTL_DBIAS_1V15 6 -#define RTC_CNTL_DBIAS_1V20 7 +#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias +#define RTC_CNTL_DBIAS_0V90 13 //digital voltage +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact #define DELAY_FAST_CLK_SWITCH 3 #define DELAY_SLOW_CLK_SWITCH 300 @@ -83,30 +88,29 @@ extern "C" { */ #define XTAL_FREQ_EST_CYCLES 10 -/* Core voltage needs to be increased in two cases: - * 1. running at 240 MHz - * 2. running with 80MHz Flash frequency - */ -#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 -#else #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 -#endif #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 -#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 -#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 #define RTC_CNTL_SCK_DCAP_DEFAULT 255 +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (1000) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (2) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) + /* set sleep_init default param */ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 @@ -114,19 +118,13 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define APLL_SDM_STOP_VAL_1 0x09 -#define APLL_SDM_STOP_VAL_2_REV0 0x69 -#define APLL_SDM_STOP_VAL_2_REV1 0x49 -#define APLL_CAL_DELAY_1 0x0f -#define APLL_CAL_DELAY_2 0x3f -#define APLL_CAL_DELAY_3 0x1f - /** * @brief Possible main XTAL frequency values. * * Enum values should be equal to frequency in MHz. */ typedef enum { + RTC_XTAL_FREQ_32M = 32, RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; @@ -243,23 +241,27 @@ typedef struct { typedef struct { uint16_t wifi_powerup_cycles : 7; uint16_t wifi_wait_cycles : 9; - uint16_t rtc_powerup_cycles : 7; - uint16_t rtc_wait_cycles : 9; + uint16_t bt_powerup_cycles : 7; + uint16_t bt_wait_cycles : 9; + uint16_t cpu_top_powerup_cycles : 7; + uint16_t cpu_top_wait_cycles : 9; uint16_t dg_wrap_powerup_cycles : 7; uint16_t dg_wrap_wait_cycles : 9; - uint16_t rtc_mem_powerup_cycles : 7; - uint16_t rtc_mem_wait_cycles : 9; + uint16_t dg_peri_powerup_cycles : 7; + uint16_t dg_peri_wait_cycles : 9; } rtc_init_config_t; #define RTC_INIT_CONFIG_DEFAULT() { \ .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ - .rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .rtc_wait_cycles = OTHER_BLOCKS_WAIT, \ + .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ + .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ - .rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ } void rtc_clk_divider_set(uint32_t div); @@ -589,19 +591,21 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val); * @brief Power down flags for rtc_sleep_pd function */ typedef struct { - uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep - uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep - uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep - uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep - uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep - uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep - uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep -} rtc_sleep_pd_config_t; + uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep + uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep + uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep + uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep + uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep + uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep +} rtc_sleep_pu_config_t; /** - * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value + * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value */ -#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ +#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ .dig_fpu = (val), \ .rtc_fpu = (val), \ .cpu_fpu = (val), \ @@ -609,26 +613,31 @@ typedef struct { .bb_fpu = (val), \ .nrx_fpu = (val), \ .fe_fpu = (val), \ + .sram_fpu = (val), \ + .rom_ram_fpu = (val), \ } -void rtc_sleep_pd(rtc_sleep_pd_config_t cfg); +void rtc_sleep_pu(rtc_sleep_pu_config_t cfg); /** * @brief sleep configuration for rtc_sleep_init function */ typedef struct { uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) - uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if touch is used) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t bt_pd_en : 1; //!< power down BT + uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. + uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode - uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode - uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; @@ -649,12 +658,15 @@ typedef struct { .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ + .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ + .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ + .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ - .dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_SLP, \ .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_SLP, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .deep_slp_reject = 1, \ .light_slp_reject = 1 \ @@ -666,7 +678,10 @@ typedef struct { #define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator -#define RTC_SLEEP_PD_WIFI BIT(6) +#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI +#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT +#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart +#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals /** * @brief Prepare the chip to enter sleep mode @@ -683,6 +698,17 @@ typedef struct { */ void rtc_sleep_init(rtc_sleep_config_t cfg); +/** + * @brief Low level initialize for rtc state machine waiting cycles after waking up + * + * This function configures the cycles chip need to wait for internal 8MHz + * oscillator and external 40MHz crystal. As we configure fixed time for waiting + * crystal, we need to pass period to calculate cycles. Now this function only + * used in lightsleep mode. + * + * @param slowclk_period re-calibrated slow clock period + */ +void rtc_sleep_low_init(uint32_t slowclk_period); /** * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source @@ -700,7 +726,6 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only) #define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) #define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) -#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup #define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) #define RTC_COCPU_TRIG_EN BIT(11) #define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) @@ -747,6 +772,7 @@ typedef struct { uint32_t xtal_fpu : 1; uint32_t bbpll_fpu : 1; uint32_t cpu_waiti_clk_gate : 1; + uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise. } rtc_config_t; /** @@ -764,7 +790,8 @@ typedef struct { .rtc_dboost_fpd = 1, \ .xtal_fpu = 0, \ .bbpll_fpu = 0, \ - .cpu_waiti_clk_gate = 1\ + .cpu_waiti_clk_gate = 1, \ + .cali_ocode = 0\ } /** diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h index ceab298f26..fe96988307 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -389,6 +389,7 @@ extern "C" { #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) #define RTC_CNTL_MIN_SLP_VAL_V 0xFF #define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 #define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) /* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ @@ -1035,7 +1036,6 @@ extern "C" { #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 -#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.4 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) @@ -1327,25 +1327,6 @@ extern "C" { #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 -/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, - * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. - * Valid if RTC_CNTL_DBG_ATTEN is 0. - */ -#define RTC_CNTL_DIG_DBIAS_0V85 0 -#define RTC_CNTL_DIG_DBIAS_0V90 1 -#define RTC_CNTL_DIG_DBIAS_0V95 2 -#define RTC_CNTL_DIG_DBIAS_1V00 3 -#define RTC_CNTL_DIG_DBIAS_1V05 4 -#define RTC_CNTL_DIG_DBIAS_1V10 5 -#define RTC_CNTL_DIG_DBIAS_1V15 6 -#define RTC_CNTL_DIG_DBIAS_1V20 7 - -/* The value of 1V00 can be adjusted between 0~3*/ -#define RTC_CNTL_DBIAS_1V00 0 -#define RTC_CNTL_DBIAS_1V05 4 -#define RTC_CNTL_DBIAS_1V10 5 -#define RTC_CNTL_DBIAS_1V15 6 -#define RTC_CNTL_DBIAS_1V20 7 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ /*description: SCK_DCAP*/ diff --git a/components/soc/esp32c3/include/soc/rtc_gpio_channel.h b/components/soc/esp32c3/include/soc/rtc_gpio_channel.h deleted file mode 100644 index c5107a0fb1..0000000000 --- a/components/soc/esp32c3/include/soc/rtc_gpio_channel.h +++ /dev/null @@ -1,73 +0,0 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _SOC_RTC_GPIO_CHANNEL_H -#define _SOC_RTC_GPIO_CHANNEL_H - -//RTC GPIO channels -#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0 -#define RTCIO_CHANNEL_0_GPIO_NUM 36 - -#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1 -#define RTCIO_CHANNEL_1_GPIO_NUM 37 - -#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2 -#define RTCIO_CHANNEL_2_GPIO_NUM 38 - -#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3 -#define RTCIO_CHANNEL_3_GPIO_NUM 39 - -#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4 -#define RTCIO_CHANNEL_4_GPIO_NUM 34 - -#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5 -#define RTCIO_CHANNEL_5_GPIO_NUM 35 - -#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6 -#define RTCIO_CHANNEL_6_GPIO_NUM 25 - -#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7 -#define RTCIO_CHANNEL_7_GPIO_NUM 26 - -#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8 -#define RTCIO_CHANNEL_8_GPIO_NUM 33 - -#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9 -#define RTCIO_CHANNEL_9_GPIO_NUM 32 - -#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10 -#define RTCIO_CHANNEL_10_GPIO_NUM 4 - -#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11 -#define RTCIO_CHANNEL_11_GPIO_NUM 0 - -#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12 -#define RTCIO_CHANNEL_12_GPIO_NUM 2 - -#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13 -#define RTCIO_CHANNEL_13_GPIO_NUM 15 - -#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14 -#define RTCIO_CHANNEL_14_GPIO_NUM 13 - -#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15 -#define RTCIO_CHANNEL_15_GPIO_NUM 12 - -#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16 -#define RTCIO_CHANNEL_16_GPIO_NUM 14 - -#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17 -#define RTCIO_CHANNEL_17_GPIO_NUM 27 - -#endif diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 92a40af326..3b8847418c 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -42,6 +42,8 @@ #define DR_REG_SPI1_BASE 0x60002000 #define DR_REG_SPI0_BASE 0x60003000 #define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 #define DR_REG_RTCCNTL_BASE 0x60008000 #define DR_REG_IO_MUX_BASE 0x60009000 #define DR_REG_RTC_I2C_BASE 0x6000e000 @@ -51,6 +53,8 @@ #define DR_REG_RMT_BASE 0x60016000 #define DR_REG_LEDC_BASE 0x60019000 #define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 #define DR_REG_SYS_TIMER_BASE 0x60023000 @@ -312,6 +316,9 @@ #define ETS_CACHEERR_INUM 25 #define ETS_DPORT_INUM 28 +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + //CPU0 Interrupt number used in ROM, should be cancelled in SDK #define ETS_SLC_INUM 1 #define ETS_UART0_INUM 5 @@ -324,3 +331,6 @@ //Invalid interrupt for number interrupt matrix #define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index c2b5f7e151..b34c5cafeb 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -44,10 +44,26 @@ #include "sha_caps.h" #include "spi_caps.h" #include "uart_caps.h" +#include "int_caps.h" /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ #define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ +/*-------------------------- ADC CAPS -------------------------------*/ +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_PATT_LEN_MAX (16) + +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_MAX_CHANNEL_NUM (10) + +/** + * Check if adc support digital controller (DMA) mode. + * @value + * - 1 : support; + * - 0 : not support; + */ +#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1 + /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/include/soc/syscon_reg.h index e7b437d24a..cc5a3c68cb 100644 --- a/components/soc/esp32c3/include/soc/syscon_reg.h +++ b/components/soc/esp32c3/include/soc/syscon_reg.h @@ -168,24 +168,23 @@ extern "C" { #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ /*description: */ -#define SYSTEM_WIFI_CLK_EN 0xFFFFFFFF +#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S)) -#define SYSTEM_WIFI_CLK_EN_V 0xFFFFFFFF +#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF #define SYSTEM_WIFI_CLK_EN_S 0 -/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 - Bit15 not included here because of the bit now can't be cleared */ -#define SYSTEM_WIFI_CLK_WIFI_EN 0x003807cf +/* Mask for all Wifi clock bits, 6 */ +#define SYSTEM_WIFI_CLK_WIFI_EN 0x0 #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) -#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x7cf +#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 -/* Mask for all Bluetooth clock bits - 11, 16, 17 */ -#define SYSTEM_WIFI_CLK_BT_EN 0x61 +/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */ +#define SYSTEM_WIFI_CLK_BT_EN 0x0 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) -#define SYSTEM_WIFI_CLK_BT_EN_V 0x61 -#define SYSTEM_WIFI_CLK_BT_EN_S 11 -/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ -#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 +#define SYSTEM_WIFI_CLK_BT_EN_V 0x0 +#define SYSTEM_WIFI_CLK_BT_EN_S 0 +/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ +#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F /* Digital team to check */ //bluetooth baseband bit11 @@ -204,15 +203,19 @@ extern "C" { #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG /* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSTEM_RW_BTLP_RST (BIT(10)) -#define SYSTEM_RW_BTMAC_RST (BIT(9)) -#define SYSTEM_MACPWR_RST (BIT(8)) -#define SYSTEM_SDIO_RST (BIT(5)) -#define SYSTEM_BTMAC_RST (BIT(4)) -#define SYSTEM_BT_RST (BIT(3)) -#define SYSTEM_MAC_RST (BIT(2)) -#define SYSTEM_FE_RST (BIT(1)) -#define SYSTEM_BB_RST (BIT(0)) +#define SYSTEM_BB_RST BIT(0) +#define SYSTEM_FE_RST BIT(1) +#define SYSTEM_MAC_RST BIT(2) +#define SYSTEM_BT_RST BIT(3) +#define SYSTEM_BTMAC_RST BIT(4) +#define SYSTEM_SDIO_RST BIT(5) +#define SYSTEM_EMAC_RST BIT(7) +#define SYSTEM_MACPWR_RST BIT(8) +#define SYSTEM_RW_BTMAC_RST BIT(9) +#define SYSTEM_RW_BTLP_RST BIT(10) +#define BLE_REG_REST_BIT BIT(11) +#define BLE_PWR_REG_REST_BIT BIT(12) +#define BLE_BB_REG_REST_BIT BIT(13) #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ diff --git a/components/soc/esp32c3/include/soc/usb_device_reg.h b/components/soc/esp32c3/include/soc/usb_device_reg.h deleted file mode 100644 index 611d9bb1b8..0000000000 --- a/components/soc/esp32c3/include/soc/usb_device_reg.h +++ /dev/null @@ -1,707 +0,0 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_USB_DEVICE_REG_H_ -#define _SOC_USB_DEVICE_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x000) -/* USB_DEVICE_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: Write and read byte data to/from UART Tx/Rx FIFO through this - field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received then read data from UART Rx FIFO.*/ -#define USB_DEVICE_RDWR_BYTE 0x000000FF -#define USB_DEVICE_RDWR_BYTE_M ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S)) -#define USB_DEVICE_RDWR_BYTE_V 0xFF -#define USB_DEVICE_RDWR_BYTE_S 0 - -#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x004) -/* USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1'b1: Indicate there is data in UART Rx FIFO.*/ -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_V 0x1 -#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_S 2 -/* USB_DEVICE_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into - in. After writing USB_DEVICE_WR_DONE this bit would be 0 until data in UART Tx FIFO is read by USB Host.*/ -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_M (BIT(1)) -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_V 0x1 -#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_S 1 -/* USB_DEVICE_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done.*/ -#define USB_DEVICE_WR_DONE (BIT(0)) -#define USB_DEVICE_WR_DONE_M (BIT(0)) -#define USB_DEVICE_WR_DONE_V 0x1 -#define USB_DEVICE_WR_DONE_S 0 - -#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x008) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when OUT endpoint 2 - received packet with zero palyload.*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when OUT endpoint 1 - received packet with zero palyload.*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when usb bus reset is detected.*/ -#define USB_DEVICE_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_RAW_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_RAW_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_RAW_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when IN token for IN - endpoint 1 is received.*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/* USB_DEVICE_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when stuff error is detected.*/ -#define USB_DEVICE_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_RAW_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_RAW_S 7 -/* USB_DEVICE_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when CRC16 error is detected.*/ -#define USB_DEVICE_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_RAW_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_RAW_S 6 -/* USB_DEVICE_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when CRC5 error is detected.*/ -#define USB_DEVICE_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_RAW_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_RAW_S 5 -/* USB_DEVICE_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when pid error is detected.*/ -#define USB_DEVICE_PID_ERR_INT_RAW (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_RAW_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_RAW_V 0x1 -#define USB_DEVICE_PID_ERR_INT_RAW_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */ -/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Serial Port OUT - Endpoint received one packet.*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/* USB_DEVICE_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when SOF frame is received.*/ -#define USB_DEVICE_SOF_INT_RAW (BIT(1)) -#define USB_DEVICE_SOF_INT_RAW_M (BIT(1)) -#define USB_DEVICE_SOF_INT_RAW_V 0x1 -#define USB_DEVICE_SOF_INT_RAW_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when flush cmd is received - for IN endpoint 2 of JTAG.*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_S 0 - -#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0x00C) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT - interrupt.*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT - interrupt.*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/ -#define USB_DEVICE_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ST_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ST_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_ST_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT - interrupt.*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/* USB_DEVICE_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/ -#define USB_DEVICE_STUFF_ERR_INT_ST (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ST_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ST_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_ST_S 7 -/* USB_DEVICE_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/ -#define USB_DEVICE_CRC16_ERR_INT_ST (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ST_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ST_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_ST_S 6 -/* USB_DEVICE_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/ -#define USB_DEVICE_CRC5_ERR_INT_ST (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ST_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ST_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_ST_S 5 -/* USB_DEVICE_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/ -#define USB_DEVICE_PID_ERR_INT_ST (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ST_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ST_V 0x1 -#define USB_DEVICE_PID_ERR_INT_ST_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - interrupt.*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/* USB_DEVICE_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.*/ -#define USB_DEVICE_SOF_INT_ST (BIT(1)) -#define USB_DEVICE_SOF_INT_ST_M (BIT(1)) -#define USB_DEVICE_SOF_INT_ST_V 0x1 -#define USB_DEVICE_SOF_INT_ST_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_S 0 - -#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x010) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/ -#define USB_DEVICE_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ENA_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_ENA_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_ENA_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/* USB_DEVICE_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/ -#define USB_DEVICE_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ENA_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_ENA_S 7 -/* USB_DEVICE_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/ -#define USB_DEVICE_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ENA_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_ENA_S 6 -/* USB_DEVICE_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/ -#define USB_DEVICE_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ENA_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_ENA_S 5 -/* USB_DEVICE_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.*/ -#define USB_DEVICE_PID_ERR_INT_ENA (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ENA_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_ENA_V 0x1 -#define USB_DEVICE_PID_ERR_INT_ENA_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/* USB_DEVICE_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.*/ -#define USB_DEVICE_SOF_INT_ENA (BIT(1)) -#define USB_DEVICE_SOF_INT_ENA_M (BIT(1)) -#define USB_DEVICE_SOF_INT_ENA_V 0x1 -#define USB_DEVICE_SOF_INT_ENA_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_S 0 - -#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x014) -/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11)) -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1 -#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 -/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (BIT(10)) -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x1 -#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/* USB_DEVICE_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/ -#define USB_DEVICE_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_CLR_M (BIT(9)) -#define USB_DEVICE_USB_BUS_RESET_INT_CLR_V 0x1 -#define USB_DEVICE_USB_BUS_RESET_INT_CLR_S 9 -/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.*/ -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8)) -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1 -#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/* USB_DEVICE_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.*/ -#define USB_DEVICE_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_CLR_M (BIT(7)) -#define USB_DEVICE_STUFF_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_STUFF_ERR_INT_CLR_S 7 -/* USB_DEVICE_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.*/ -#define USB_DEVICE_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_CLR_M (BIT(6)) -#define USB_DEVICE_CRC16_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_CRC16_ERR_INT_CLR_S 6 -/* USB_DEVICE_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.*/ -#define USB_DEVICE_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_CLR_M (BIT(5)) -#define USB_DEVICE_CRC5_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_CRC5_ERR_INT_CLR_S 5 -/* USB_DEVICE_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.*/ -#define USB_DEVICE_PID_ERR_INT_CLR (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_CLR_M (BIT(4)) -#define USB_DEVICE_PID_ERR_INT_CLR_V 0x1 -#define USB_DEVICE_PID_ERR_INT_CLR_S 4 -/* USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/ -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_M (BIT(3)) -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_V 0x1 -#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_S 3 -/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/ -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2)) -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1 -#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/* USB_DEVICE_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/ -#define USB_DEVICE_SOF_INT_CLR (BIT(1)) -#define USB_DEVICE_SOF_INT_CLR_M (BIT(1)) -#define USB_DEVICE_SOF_INT_CLR_V 0x1 -#define USB_DEVICE_SOF_INT_CLR_S 1 -/* USB_DEVICE_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/ -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_M (BIT(0)) -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_V 0x1 -#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_S 0 - -#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x018) -/* USB_DEVICE_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: Enable USB pad function.*/ -#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) -#define USB_DEVICE_USB_PAD_ENABLE_M (BIT(14)) -#define USB_DEVICE_USB_PAD_ENABLE_V 0x1 -#define USB_DEVICE_USB_PAD_ENABLE_S 14 -/* USB_DEVICE_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Control pull up value.*/ -#define USB_DEVICE_PULLUP_VALUE (BIT(13)) -#define USB_DEVICE_PULLUP_VALUE_M (BIT(13)) -#define USB_DEVICE_PULLUP_VALUE_V 0x1 -#define USB_DEVICE_PULLUP_VALUE_S 13 -/* USB_DEVICE_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Control USB D- pull down.*/ -#define USB_DEVICE_DM_PULLDOWN (BIT(12)) -#define USB_DEVICE_DM_PULLDOWN_M (BIT(12)) -#define USB_DEVICE_DM_PULLDOWN_V 0x1 -#define USB_DEVICE_DM_PULLDOWN_S 12 -/* USB_DEVICE_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Control USB D- pull up.*/ -#define USB_DEVICE_DM_PULLUP (BIT(11)) -#define USB_DEVICE_DM_PULLUP_M (BIT(11)) -#define USB_DEVICE_DM_PULLUP_V 0x1 -#define USB_DEVICE_DM_PULLUP_S 11 -/* USB_DEVICE_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Control USB D+ pull down.*/ -#define USB_DEVICE_DP_PULLDOWN (BIT(10)) -#define USB_DEVICE_DP_PULLDOWN_M (BIT(10)) -#define USB_DEVICE_DP_PULLDOWN_V 0x1 -#define USB_DEVICE_DP_PULLDOWN_S 10 -/* USB_DEVICE_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: Control USB D+ pull up.*/ -#define USB_DEVICE_DP_PULLUP (BIT(9)) -#define USB_DEVICE_DP_PULLUP_M (BIT(9)) -#define USB_DEVICE_DP_PULLUP_V 0x1 -#define USB_DEVICE_DP_PULLUP_S 9 -/* USB_DEVICE_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Enable software control USB D+ D- pullup pulldown*/ -#define USB_DEVICE_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_DEVICE_PAD_PULL_OVERRIDE_M (BIT(8)) -#define USB_DEVICE_PAD_PULL_OVERRIDE_V 0x1 -#define USB_DEVICE_PAD_PULL_OVERRIDE_S 8 -/* USB_DEVICE_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Enable software control input threshold*/ -#define USB_DEVICE_VREF_OVERRIDE (BIT(7)) -#define USB_DEVICE_VREF_OVERRIDE_M (BIT(7)) -#define USB_DEVICE_VREF_OVERRIDE_V 0x1 -#define USB_DEVICE_VREF_OVERRIDE_S 7 -/* USB_DEVICE_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ -/*description: Control single-end input low threshold 0.8V to 1.04V step 80mV*/ -#define USB_DEVICE_VREFL 0x00000003 -#define USB_DEVICE_VREFL_M ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S)) -#define USB_DEVICE_VREFL_V 0x3 -#define USB_DEVICE_VREFL_S 5 -/* USB_DEVICE_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: Control single-end input high threshold 1.76V to 2V step 80mV*/ -#define USB_DEVICE_VREFH 0x00000003 -#define USB_DEVICE_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S)) -#define USB_DEVICE_VREFH_V 0x3 -#define USB_DEVICE_VREFH_S 3 -/* USB_DEVICE_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: USB D+ D- exchange*/ -#define USB_DEVICE_EXCHG_PINS (BIT(2)) -#define USB_DEVICE_EXCHG_PINS_M (BIT(2)) -#define USB_DEVICE_EXCHG_PINS_V 0x1 -#define USB_DEVICE_EXCHG_PINS_S 2 -/* USB_DEVICE_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Enable software control USB D+ D- exchange*/ -#define USB_DEVICE_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_DEVICE_EXCHG_PINS_OVERRIDE_M (BIT(1)) -#define USB_DEVICE_EXCHG_PINS_OVERRIDE_V 0x1 -#define USB_DEVICE_EXCHG_PINS_OVERRIDE_S 1 -/* USB_DEVICE_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Select internal/external PHY*/ -#define USB_DEVICE_PHY_SEL (BIT(0)) -#define USB_DEVICE_PHY_SEL_M (BIT(0)) -#define USB_DEVICE_PHY_SEL_V 0x1 -#define USB_DEVICE_PHY_SEL_S 0 - -#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x01C) -/* USB_DEVICE_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: USB D- tx value in test*/ -#define USB_DEVICE_TEST_TX_DM (BIT(3)) -#define USB_DEVICE_TEST_TX_DM_M (BIT(3)) -#define USB_DEVICE_TEST_TX_DM_V 0x1 -#define USB_DEVICE_TEST_TX_DM_S 3 -/* USB_DEVICE_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: USB D+ tx value in test*/ -#define USB_DEVICE_TEST_TX_DP (BIT(2)) -#define USB_DEVICE_TEST_TX_DP_M (BIT(2)) -#define USB_DEVICE_TEST_TX_DP_V 0x1 -#define USB_DEVICE_TEST_TX_DP_S 2 -/* USB_DEVICE_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: USB pad oen in test*/ -#define USB_DEVICE_TEST_USB_OE (BIT(1)) -#define USB_DEVICE_TEST_USB_OE_M (BIT(1)) -#define USB_DEVICE_TEST_USB_OE_V 0x1 -#define USB_DEVICE_TEST_USB_OE_S 1 -/* USB_DEVICE_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Enable test of the USB pad*/ -#define USB_DEVICE_TEST_ENABLE (BIT(0)) -#define USB_DEVICE_TEST_ENABLE_M (BIT(0)) -#define USB_DEVICE_TEST_ENABLE_V 0x1 -#define USB_DEVICE_TEST_ENABLE_S 0 - -#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x020) -/* USB_DEVICE_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Write 1 to reset JTAG out fifo.*/ -#define USB_DEVICE_OUT_FIFO_RESET (BIT(9)) -#define USB_DEVICE_OUT_FIFO_RESET_M (BIT(9)) -#define USB_DEVICE_OUT_FIFO_RESET_V 0x1 -#define USB_DEVICE_OUT_FIFO_RESET_S 9 -/* USB_DEVICE_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Write 1 to reset JTAG in fifo.*/ -#define USB_DEVICE_IN_FIFO_RESET (BIT(8)) -#define USB_DEVICE_IN_FIFO_RESET_M (BIT(8)) -#define USB_DEVICE_IN_FIFO_RESET_V 0x1 -#define USB_DEVICE_IN_FIFO_RESET_S 8 -/* USB_DEVICE_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 1: JTAG out fifo is full.*/ -#define USB_DEVICE_OUT_FIFO_FULL (BIT(7)) -#define USB_DEVICE_OUT_FIFO_FULL_M (BIT(7)) -#define USB_DEVICE_OUT_FIFO_FULL_V 0x1 -#define USB_DEVICE_OUT_FIFO_FULL_S 7 -/* USB_DEVICE_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */ -/*description: 1: JTAG out fifo is empty.*/ -#define USB_DEVICE_OUT_FIFO_EMPTY (BIT(6)) -#define USB_DEVICE_OUT_FIFO_EMPTY_M (BIT(6)) -#define USB_DEVICE_OUT_FIFO_EMPTY_V 0x1 -#define USB_DEVICE_OUT_FIFO_EMPTY_S 6 -/* USB_DEVICE_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: JTAT out fifo counter.*/ -#define USB_DEVICE_OUT_FIFO_CNT 0x00000003 -#define USB_DEVICE_OUT_FIFO_CNT_M ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S)) -#define USB_DEVICE_OUT_FIFO_CNT_V 0x3 -#define USB_DEVICE_OUT_FIFO_CNT_S 4 -/* USB_DEVICE_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 1: JTAG in fifo is full.*/ -#define USB_DEVICE_IN_FIFO_FULL (BIT(3)) -#define USB_DEVICE_IN_FIFO_FULL_M (BIT(3)) -#define USB_DEVICE_IN_FIFO_FULL_V 0x1 -#define USB_DEVICE_IN_FIFO_FULL_S 3 -/* USB_DEVICE_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */ -/*description: 1: JTAG in fifo is empty.*/ -#define USB_DEVICE_IN_FIFO_EMPTY (BIT(2)) -#define USB_DEVICE_IN_FIFO_EMPTY_M (BIT(2)) -#define USB_DEVICE_IN_FIFO_EMPTY_V 0x1 -#define USB_DEVICE_IN_FIFO_EMPTY_S 2 -/* USB_DEVICE_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: JTAT in fifo counter.*/ -#define USB_DEVICE_IN_FIFO_CNT 0x00000003 -#define USB_DEVICE_IN_FIFO_CNT_M ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S)) -#define USB_DEVICE_IN_FIFO_CNT_V 0x3 -#define USB_DEVICE_IN_FIFO_CNT_S 0 - -#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x024) -/* USB_DEVICE_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */ -/*description: Frame index of received SOF frame.*/ -#define USB_DEVICE_SOF_FRAME_INDEX 0x000007FF -#define USB_DEVICE_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S)) -#define USB_DEVICE_SOF_FRAME_INDEX_V 0x7FF -#define USB_DEVICE_SOF_FRAME_INDEX_S 0 - -#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x028) -/* USB_DEVICE_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 0.*/ -#define USB_DEVICE_IN_EP0_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP0_RD_ADDR_M ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S)) -#define USB_DEVICE_IN_EP0_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP0_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 0.*/ -#define USB_DEVICE_IN_EP0_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP0_WR_ADDR_M ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S)) -#define USB_DEVICE_IN_EP0_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP0_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 0.*/ -#define USB_DEVICE_IN_EP0_STATE 0x00000003 -#define USB_DEVICE_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S)) -#define USB_DEVICE_IN_EP0_STATE_V 0x3 -#define USB_DEVICE_IN_EP0_STATE_S 0 - -#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x02C) -/* USB_DEVICE_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 1.*/ -#define USB_DEVICE_IN_EP1_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP1_RD_ADDR_M ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S)) -#define USB_DEVICE_IN_EP1_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP1_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 1.*/ -#define USB_DEVICE_IN_EP1_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP1_WR_ADDR_M ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S)) -#define USB_DEVICE_IN_EP1_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP1_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 1.*/ -#define USB_DEVICE_IN_EP1_STATE 0x00000003 -#define USB_DEVICE_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S)) -#define USB_DEVICE_IN_EP1_STATE_V 0x3 -#define USB_DEVICE_IN_EP1_STATE_S 0 - -#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x030) -/* USB_DEVICE_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 2.*/ -#define USB_DEVICE_IN_EP2_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP2_RD_ADDR_M ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S)) -#define USB_DEVICE_IN_EP2_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP2_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 2.*/ -#define USB_DEVICE_IN_EP2_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP2_WR_ADDR_M ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S)) -#define USB_DEVICE_IN_EP2_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP2_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 2.*/ -#define USB_DEVICE_IN_EP2_STATE 0x00000003 -#define USB_DEVICE_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S)) -#define USB_DEVICE_IN_EP2_STATE_V 0x3 -#define USB_DEVICE_IN_EP2_STATE_S 0 - -#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x034) -/* USB_DEVICE_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of IN endpoint 3.*/ -#define USB_DEVICE_IN_EP3_RD_ADDR 0x0000007F -#define USB_DEVICE_IN_EP3_RD_ADDR_M ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S)) -#define USB_DEVICE_IN_EP3_RD_ADDR_V 0x7F -#define USB_DEVICE_IN_EP3_RD_ADDR_S 9 -/* USB_DEVICE_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of IN endpoint 3.*/ -#define USB_DEVICE_IN_EP3_WR_ADDR 0x0000007F -#define USB_DEVICE_IN_EP3_WR_ADDR_M ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S)) -#define USB_DEVICE_IN_EP3_WR_ADDR_V 0x7F -#define USB_DEVICE_IN_EP3_WR_ADDR_S 2 -/* USB_DEVICE_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ -/*description: State of IN Endpoint 3.*/ -#define USB_DEVICE_IN_EP3_STATE 0x00000003 -#define USB_DEVICE_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S)) -#define USB_DEVICE_IN_EP3_STATE_V 0x3 -#define USB_DEVICE_IN_EP3_STATE_S 0 - -#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x038) -/* USB_DEVICE_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of OUT endpoint 0.*/ -#define USB_DEVICE_OUT_EP0_RD_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP0_RD_ADDR_M ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S)) -#define USB_DEVICE_OUT_EP0_RD_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP0_RD_ADDR_S 9 -/* USB_DEVICE_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - is detected there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.*/ -#define USB_DEVICE_OUT_EP0_WR_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP0_WR_ADDR_M ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S)) -#define USB_DEVICE_OUT_EP0_WR_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP0_WR_ADDR_S 2 -/* USB_DEVICE_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: State of OUT Endpoint 0.*/ -#define USB_DEVICE_OUT_EP0_STATE 0x00000003 -#define USB_DEVICE_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S)) -#define USB_DEVICE_OUT_EP0_STATE_V 0x3 -#define USB_DEVICE_OUT_EP0_STATE_S 0 - -#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x03C) -/* USB_DEVICE_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */ -/*description: Data count in OUT endpoint 1 when one packet is received.*/ -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT 0x0000007F -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_M ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S)) -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_V 0x7F -#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_S 16 -/* USB_DEVICE_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of OUT endpoint 1.*/ -#define USB_DEVICE_OUT_EP1_RD_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP1_RD_ADDR_M ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S)) -#define USB_DEVICE_OUT_EP1_RD_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP1_RD_ADDR_S 9 -/* USB_DEVICE_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - is detected there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/ -#define USB_DEVICE_OUT_EP1_WR_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S)) -#define USB_DEVICE_OUT_EP1_WR_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP1_WR_ADDR_S 2 -/* USB_DEVICE_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: State of OUT Endpoint 1.*/ -#define USB_DEVICE_OUT_EP1_STATE 0x00000003 -#define USB_DEVICE_OUT_EP1_STATE_M ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S)) -#define USB_DEVICE_OUT_EP1_STATE_V 0x3 -#define USB_DEVICE_OUT_EP1_STATE_S 0 - -#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x040) -/* USB_DEVICE_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ -/*description: Read data address of OUT endpoint 2.*/ -#define USB_DEVICE_OUT_EP2_RD_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP2_RD_ADDR_M ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S)) -#define USB_DEVICE_OUT_EP2_RD_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP2_RD_ADDR_S 9 -/* USB_DEVICE_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ -/*description: Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - is detected there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/ -#define USB_DEVICE_OUT_EP2_WR_ADDR 0x0000007F -#define USB_DEVICE_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S)) -#define USB_DEVICE_OUT_EP2_WR_ADDR_V 0x7F -#define USB_DEVICE_OUT_EP2_WR_ADDR_S 2 -/* USB_DEVICE_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: State of OUT Endpoint 2.*/ -#define USB_DEVICE_OUT_EP2_STATE 0x00000003 -#define USB_DEVICE_OUT_EP2_STATE_M ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S)) -#define USB_DEVICE_OUT_EP2_STATE_V 0x3 -#define USB_DEVICE_OUT_EP2_STATE_S 0 - -#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x044) -/* USB_DEVICE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when - application writes registers.*/ -#define USB_DEVICE_CLK_EN (BIT(0)) -#define USB_DEVICE_CLK_EN_M (BIT(0)) -#define USB_DEVICE_CLK_EN_V 0x1 -#define USB_DEVICE_CLK_EN_S 0 - -#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x048) -/* USB_DEVICE_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1: Force clock on for usb memory.*/ -#define USB_DEVICE_USB_MEM_CLK_EN (BIT(1)) -#define USB_DEVICE_USB_MEM_CLK_EN_M (BIT(1)) -#define USB_DEVICE_USB_MEM_CLK_EN_V 0x1 -#define USB_DEVICE_USB_MEM_CLK_EN_S 1 -/* USB_DEVICE_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: power down usb memory.*/ -#define USB_DEVICE_USB_MEM_PD (BIT(0)) -#define USB_DEVICE_USB_MEM_PD_M (BIT(0)) -#define USB_DEVICE_USB_MEM_PD_V 0x1 -#define USB_DEVICE_USB_MEM_PD_S 0 - -#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x080) -/* USB_DEVICE_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007300 ; */ -/*description: register version.*/ -#define USB_DEVICE_DATE 0xFFFFFFFF -#define USB_DEVICE_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S)) -#define USB_DEVICE_DATE_V 0xFFFFFFFF -#define USB_DEVICE_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_USB_DEVICE_REG_H_ */ diff --git a/components/soc/esp32c3/include/soc/usb_device_struct.h b/components/soc/esp32c3/include/soc/usb_device_struct.h deleted file mode 100644 index 50f5d68f93..0000000000 --- a/components/soc/esp32c3/include/soc/usb_device_struct.h +++ /dev/null @@ -1,261 +0,0 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_USB_DEVICE_STRUCT_H_ -#define _SOC_USB_DEVICE_STRUCT_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t rdwr_byte: 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received then read data from UART Rx FIFO.*/ - uint32_t reserved8: 24; /*reserved*/ - }; - uint32_t val; - } ep1; - union { - struct { - uint32_t wr_done: 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done.*/ - uint32_t serial_in_ep_data_free: 1; /*1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE this bit would be 0 until data in UART Tx FIFO is read by USB Host.*/ - uint32_t serial_out_ep_data_avail: 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/ - uint32_t reserved3: 29; /*reserved*/ - }; - uint32_t val; - } ep1_conf; - union { - struct { - uint32_t jtag_in_flush: 1; /*The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.*/ - uint32_t sof: 1; /*The raw interrupt bit turns to high level when SOF frame is received.*/ - uint32_t serial_out_recv_pkt: 1; /*The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.*/ - uint32_t serial_in_empty: 1; /*The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.*/ - uint32_t pid_err: 1; /*The raw interrupt bit turns to high level when pid error is detected.*/ - uint32_t crc5_err: 1; /*The raw interrupt bit turns to high level when CRC5 error is detected.*/ - uint32_t crc16_err: 1; /*The raw interrupt bit turns to high level when CRC16 error is detected.*/ - uint32_t stuff_err: 1; /*The raw interrupt bit turns to high level when stuff error is detected.*/ - uint32_t in_token_rec_in_ep1: 1; /*The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.*/ - uint32_t usb_bus_reset: 1; /*The raw interrupt bit turns to high level when usb bus reset is detected.*/ - uint32_t out_ep1_zero_payload: 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.*/ - uint32_t out_ep2_zero_payload: 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.*/ - uint32_t reserved12: 20; /*reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t jtag_in_flush: 1; /*The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/ - uint32_t sof: 1; /*The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.*/ - uint32_t serial_out_recv_pkt: 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/ - uint32_t serial_in_empty: 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/ - uint32_t pid_err: 1; /*The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/ - uint32_t crc5_err: 1; /*The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/ - uint32_t crc16_err: 1; /*The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/ - uint32_t stuff_err: 1; /*The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/ - uint32_t in_token_rec_in_ep1: 1; /*The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ - uint32_t usb_bus_reset: 1; /*The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/ - uint32_t out_ep1_zero_payload: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t out_ep2_zero_payload: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t reserved12: 20; /*reserved*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t jtag_in_flush: 1; /*The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/ - uint32_t sof: 1; /*The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.*/ - uint32_t serial_out_recv_pkt: 1; /*The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/ - uint32_t serial_in_empty: 1; /*The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/ - uint32_t pid_err: 1; /*The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.*/ - uint32_t crc5_err: 1; /*The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/ - uint32_t crc16_err: 1; /*The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/ - uint32_t stuff_err: 1; /*The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/ - uint32_t in_token_rec_in_ep1: 1; /*The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ - uint32_t usb_bus_reset: 1; /*The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/ - uint32_t out_ep1_zero_payload: 1; /*The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t out_ep2_zero_payload: 1; /*The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t reserved12: 20; /*reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t jtag_in_flush: 1; /*Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/ - uint32_t sof: 1; /*Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/ - uint32_t serial_out_recv_pkt: 1; /*Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/ - uint32_t serial_in_empty: 1; /*Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/ - uint32_t pid_err: 1; /*Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.*/ - uint32_t crc5_err: 1; /*Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.*/ - uint32_t crc16_err: 1; /*Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.*/ - uint32_t stuff_err: 1; /*Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.*/ - uint32_t in_token_rec_in_ep1: 1; /*Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.*/ - uint32_t usb_bus_reset: 1; /*Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/ - uint32_t out_ep1_zero_payload: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t out_ep2_zero_payload: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t reserved12: 20; /*reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t phy_sel: 1; /*Select internal/external PHY*/ - uint32_t exchg_pins_override: 1; /*Enable software control USB D+ D- exchange*/ - uint32_t exchg_pins: 1; /*USB D+ D- exchange*/ - uint32_t vrefh: 2; /*Control single-end input high threshold 1.76V to 2V step 80mV*/ - uint32_t vrefl: 2; /*Control single-end input low threshold 0.8V to 1.04V step 80mV*/ - uint32_t vref_override: 1; /*Enable software control input threshold*/ - uint32_t pad_pull_override: 1; /*Enable software control USB D+ D- pullup pulldown*/ - uint32_t dp_pullup: 1; /*Control USB D+ pull up.*/ - uint32_t dp_pulldown: 1; /*Control USB D+ pull down.*/ - uint32_t dm_pullup: 1; /*Control USB D- pull up.*/ - uint32_t dm_pulldown: 1; /*Control USB D- pull down.*/ - uint32_t pullup_value: 1; /*Control pull up value.*/ - uint32_t usb_pad_enable: 1; /*Enable USB pad function.*/ - uint32_t reserved15: 17; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t test_enable: 1; /*Enable test of the USB pad*/ - uint32_t test_usb_oe: 1; /*USB pad oen in test*/ - uint32_t test_tx_dp: 1; /*USB D+ tx value in test*/ - uint32_t test_tx_dm: 1; /*USB D- tx value in test*/ - uint32_t reserved4: 28; - }; - uint32_t val; - } test; - union { - struct { - uint32_t in_fifo_cnt: 2; /*JTAT in fifo counter.*/ - uint32_t in_fifo_empty: 1; /*1: JTAG in fifo is empty.*/ - uint32_t in_fifo_full: 1; /*1: JTAG in fifo is full.*/ - uint32_t out_fifo_cnt: 2; /*JTAT out fifo counter.*/ - uint32_t out_fifo_empty: 1; /*1: JTAG out fifo is empty.*/ - uint32_t out_fifo_full: 1; /*1: JTAG out fifo is full.*/ - uint32_t in_fifo_reset: 1; /*Write 1 to reset JTAG in fifo.*/ - uint32_t out_fifo_reset: 1; /*Write 1 to reset JTAG out fifo.*/ - uint32_t reserved10: 22; - }; - uint32_t val; - } jfifo_st; - union { - struct { - uint32_t sof_frame_index:11; /*Frame index of received SOF frame.*/ - uint32_t reserved11: 21; - }; - uint32_t val; - } fram_num; - union { - struct { - uint32_t in_ep0_state: 2; /*State of IN Endpoint 0.*/ - uint32_t in_ep0_wr_addr: 7; /*Write data address of IN endpoint 0.*/ - uint32_t in_ep0_rd_addr: 7; /*Read data address of IN endpoint 0.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } in_ep0_st; - union { - struct { - uint32_t in_ep1_state: 2; /*State of IN Endpoint 1.*/ - uint32_t in_ep1_wr_addr: 7; /*Write data address of IN endpoint 1.*/ - uint32_t in_ep1_rd_addr: 7; /*Read data address of IN endpoint 1.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } in_ep1_st; - union { - struct { - uint32_t in_ep2_state: 2; /*State of IN Endpoint 2.*/ - uint32_t in_ep2_wr_addr: 7; /*Write data address of IN endpoint 2.*/ - uint32_t in_ep2_rd_addr: 7; /*Read data address of IN endpoint 2.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } in_ep2_st; - union { - struct { - uint32_t in_ep3_state: 2; /*State of IN Endpoint 3.*/ - uint32_t in_ep3_wr_addr: 7; /*Write data address of IN endpoint 3.*/ - uint32_t in_ep3_rd_addr: 7; /*Read data address of IN endpoint 3.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } in_ep3_st; - union { - struct { - uint32_t out_ep0_state: 2; /*State of OUT Endpoint 0.*/ - uint32_t out_ep0_wr_addr: 7; /*Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.*/ - uint32_t out_ep0_rd_addr: 7; /*Read data address of OUT endpoint 0.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } out_ep0_st; - union { - struct { - uint32_t out_ep1_state: 2; /*State of OUT Endpoint 1.*/ - uint32_t out_ep1_wr_addr: 7; /*Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/ - uint32_t out_ep1_rd_addr: 7; /*Read data address of OUT endpoint 1.*/ - uint32_t out_ep1_rec_data_cnt: 7; /*Data count in OUT endpoint 1 when one packet is received.*/ - uint32_t reserved23: 9; /*reserved*/ - }; - uint32_t val; - } out_ep1_st; - union { - struct { - uint32_t out_ep2_state: 2; /*State of OUT Endpoint 2.*/ - uint32_t out_ep2_wr_addr: 7; /*Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/ - uint32_t out_ep2_rd_addr: 7; /*Read data address of OUT endpoint 2.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } out_ep2_st; - union { - struct { - uint32_t clk_en: 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } misc_conf; - union { - struct { - uint32_t usb_mem_pd: 1; /*1: power down usb memory.*/ - uint32_t usb_mem_clk_en: 1; /*1: Force clock on for usb memory.*/ - uint32_t reserved2: 30; - }; - uint32_t val; - } mem_conf; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t date; /**/ -} usb_device_dev_t; -extern usb_device_dev_t USB_DEVICE; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_USB_DEVICE_STRUCT_H_ */ diff --git a/components/soc/esp32c3/rtc_periph.c b/components/soc/esp32c3/rtc_periph.c deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/soc/esp32c3/sdio_slave_periph.c b/components/soc/esp32c3/sdio_slave_periph.c deleted file mode 100644 index e23a74dfc8..0000000000 --- a/components/soc/esp32c3/sdio_slave_periph.c +++ /dev/null @@ -1,42 +0,0 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include "soc/sdio_slave_periph.h" -#include "soc/gpio_periph.h" - -// I/O slot of sdio slave: -// 0: GPIO 6, 11, 7, 8, 9, 10, -// 1: GPIO 14, 15, 2, 4, 12, 13 for CLK, CMD, D0, D1, D2, D3 respectively. -// only one peripheral for SDIO and only one slot can work at the same time. -// currently slot 0 is occupied by SPI for flash -const sdio_slave_slot_info_t sdio_slave_slot_info[2] = { - { - .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK, - .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD, - .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0, - .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1, - .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2, - .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3, - .func = SDIO_SLAVE_SLOT0_FUNC, - }, { - .clk_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK, - .cmd_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD, - .d0_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0, - .d1_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1, - .d2_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2, - .d3_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3, - .func = SDIO_SLAVE_SLOT1_FUNC, - }, -}; diff --git a/components/soc/esp32c3/soc_memory_layout.c b/components/soc/esp32c3/soc_memory_layout.c index 2aa3469e88..b28d294d06 100644 --- a/components/soc/esp32c3/soc_memory_layout.c +++ b/components/soc/esp32c3/soc_memory_layout.c @@ -65,7 +65,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory { 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory #ifdef CONFIG_ESP32C3_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x2000, 5, 0}, //Fast RTC memory + { 0x50000000, 0x2000, 4, 0}, //Fast RTC memory #endif };