diff --git a/components/efuse/esp32c5/esp_efuse_table.c b/components/efuse/esp32c5/esp_efuse_table.c index e0ac143372..7c0837a52d 100644 --- a/components/efuse/esp32c5/esp_efuse_table.c +++ b/components/efuse/esp32c5/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table eb005412b657c9be0ce4bb699e5813c9 +// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -23,6 +23,34 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; +static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_RND_SWITCH_CYCLE, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_XTS_KEY_LENGTH_256, +}; + +static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY, +}; + static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; @@ -35,6 +63,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, }; +static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS, +}; + static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI, }; @@ -51,6 +83,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, }; +static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD, +}; + static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, }; @@ -99,6 +135,22 @@ static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, }; +static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_ECDSA_DISABLE_P192[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECDSA_DISABLE_P192, +}; + +static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME, +}; + static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, }; @@ -107,8 +159,12 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 17, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS, +static const esp_efuse_desc_t WR_DIS_XTAL_48M_SEL[] = { + {EFUSE_BLK0, 17, 1}, // [] wr_dis of XTAL_48M_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_XTAL_48M_SEL_MODE[] = { + {EFUSE_BLK0, 17, 1}, // [] wr_dis of XTAL_48M_SEL_MODE, }; static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { @@ -148,7 +204,11 @@ static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 19, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, +}; + +static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of HUK_GEN_STATE, }; static const esp_efuse_desc_t WR_DIS_BLK1[] = { @@ -163,12 +223,76 @@ static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, }; +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_PA_TRIM_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PA_TRIM_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_TRIM_N_BIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of TRIM_N_BIAS, +}; + +static const esp_efuse_desc_t WR_DIS_TRIM_P_BIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of TRIM_P_BIAS, +}; + static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK_SYS_DATA1, +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, +}; + +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, }; static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { @@ -464,8 +588,72 @@ static const esp_efuse_desc_t MAC_EXT[] = { {EFUSE_BLK1, 48, 16}, // [] Represents the extended bits of MAC address, }; -static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = { - {EFUSE_BLK2, 0, 256}, // [] System data part 1 (reserved), +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 64, 4}, // [] Minor chip version, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 68, 2}, // [] Minor chip version, +}; + +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major, +}; + +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, +}; + +static const esp_efuse_desc_t FLASH_CAP[] = { + {EFUSE_BLK1, 77, 3}, // [] Flash capacity, +}; + +static const esp_efuse_desc_t FLASH_VENDOR[] = { + {EFUSE_BLK1, 80, 3}, // [] Flash vendor, +}; + +static const esp_efuse_desc_t PSRAM_CAP[] = { + {EFUSE_BLK1, 83, 3}, // [] Psram capacity, +}; + +static const esp_efuse_desc_t PSRAM_VENDOR[] = { + {EFUSE_BLK1, 86, 2}, // [] Psram vendor, +}; + +static const esp_efuse_desc_t TEMP[] = { + {EFUSE_BLK1, 88, 2}, // [] Temp (die embedded inside), +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 90, 3}, // [] Package version, +}; + +static const esp_efuse_desc_t PA_TRIM_VERSION[] = { + {EFUSE_BLK1, 93, 3}, // [] PADC CAL PA trim version, +}; + +static const esp_efuse_desc_t TRIM_N_BIAS[] = { + {EFUSE_BLK1, 96, 5}, // [] PADC CAL N bias, +}; + +static const esp_efuse_desc_t TRIM_P_BIAS[] = { + {EFUSE_BLK1, 101, 5}, // [] PADC CAL P bias, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 137, 8}, // [] ADC OCode, }; static const esp_efuse_desc_t USER_DATA[] = { @@ -518,6 +706,41 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + &WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = { + &WR_DIS_KM_RND_SWITCH_CYCLE[0], // [] wr_dis of KM_RND_SWITCH_CYCLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { + &WR_DIS_KM_DEPLOY_ONLY_ONCE[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = { + &WR_DIS_FORCE_USE_KEY_MANAGER_KEY[0], // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { + &WR_DIS_FORCE_DISABLE_SW_INIT_KEY[0], // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[] = { + &WR_DIS_KM_XTS_KEY_LENGTH_256[0], // [] wr_dis of KM_XTS_KEY_LENGTH_256 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = { + &WR_DIS_LOCK_KM_KEY[0], // [] wr_dis of LOCK_KM_KEY + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE NULL @@ -533,6 +756,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { &WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI NULL @@ -553,6 +781,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = { + &WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL @@ -613,6 +846,26 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + &WR_DIS_XTS_DPA_PSEUDO_LEVEL[0], // [] wr_dis of XTS_DPA_PSEUDO_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = { + &WR_DIS_XTS_DPA_CLK_ENABLE[0], // [] wr_dis of XTS_DPA_CLK_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[] = { + &WR_DIS_ECDSA_DISABLE_P192[0], // [] wr_dis of ECDSA_DISABLE_P192 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = { + &WR_DIS_ECC_FORCE_CONST_TIME[0], // [] wr_dis of ECC_FORCE_CONST_TIME + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL @@ -623,8 +876,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { - &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL[] = { + &WR_DIS_XTAL_48M_SEL[0], // [] wr_dis of XTAL_48M_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL_MODE[] = { + &WR_DIS_XTAL_48M_SEL_MODE[0], // [] wr_dis of XTAL_48M_SEL_MODE NULL }; @@ -678,6 +936,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = { + &WR_DIS_HUK_GEN_STATE[0], // [] wr_dis of HUK_GEN_STATE + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 NULL @@ -693,13 +956,93 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { + &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { + &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = { + &WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = { + &WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = { + &WR_DIS_TEMP[0], // [] wr_dis of TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[] = { + &WR_DIS_PA_TRIM_VERSION[0], // [] wr_dis of PA_TRIM_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[] = { + &WR_DIS_TRIM_N_BIAS[0], // [] wr_dis of TRIM_N_BIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[] = { + &WR_DIS_TRIM_P_BIAS[0], // [] wr_dis of TRIM_P_BIAS + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = { - &WR_DIS_BLOCK_SYS_DATA1[0], // [] wr_dis of BLOCK_SYS_DATA1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE NULL }; @@ -1068,8 +1411,88 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = { - &BLOCK_SYS_DATA1[0], // [] System data part 1 (reserved) +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // [] Minor chip version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] Minor chip version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { + &FLASH_CAP[0], // [] Flash capacity + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { + &FLASH_VENDOR[0], // [] Flash vendor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { + &PSRAM_CAP[0], // [] Psram capacity + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = { + &PSRAM_VENDOR[0], // [] Psram vendor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = { + &TEMP[0], // [] Temp (die embedded inside) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // [] Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[] = { + &PA_TRIM_VERSION[0], // [] PADC CAL PA trim version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[] = { + &TRIM_N_BIAS[0], // [] PADC CAL N bias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[] = { + &TRIM_P_BIAS[0], // [] PADC CAL P bias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] ADC OCode NULL }; diff --git a/components/efuse/esp32c5/esp_efuse_table.csv b/components/efuse/esp32c5/esp_efuse_table.csv index 4dd7b43eab..29fc4e1f5c 100644 --- a/components/efuse/esp32c5/esp_efuse_table.csv +++ b/components/efuse/esp32c5/esp_efuse_table.csv @@ -9,17 +9,26 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 64acd55d57b7452dbb6838b7237c795b +# This file was generated by regtools.py based on the efuses.yaml file with the version: b09fa417de505238a601eddce188b696 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE +WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE +WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE +WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY +WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY +WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256 +WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 @@ -32,9 +41,14 @@ WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.K WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL +WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL +WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE +WR_DIS.ECDSA_DISABLE_P192, EFUSE_BLK0, 14, 1, [] wr_dis of ECDSA_DISABLE_P192 +WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS +WR_DIS.XTAL_48M_SEL, EFUSE_BLK0, 17, 1, [] wr_dis of XTAL_48M_SEL +WR_DIS.XTAL_48M_SEL_MODE, EFUSE_BLK0, 17, 1, [] wr_dis of XTAL_48M_SEL_MODE WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT @@ -44,12 +58,29 @@ WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT +WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP +WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR +WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP +WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR +WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.PA_TRIM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PA_TRIM_VERSION +WR_DIS.TRIM_N_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_N_BIAS +WR_DIS.TRIM_P_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_P_BIAS WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK_SYS_DATA1 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -127,7 +158,23 @@ MAC, EFUSE_BLK1, 40, 8, [MAC_FACT , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address MAC_EXT, EFUSE_BLK1, 48, 16, [] Represents the extended bits of MAC address -BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [] System data part 1 (reserved) +WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version +WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Minor chip version +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major +BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2 +BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2 +FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity +FLASH_VENDOR, EFUSE_BLK1, 80, 3, [] Flash vendor +PSRAM_CAP, EFUSE_BLK1, 83, 3, [] Psram capacity +PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] Psram vendor +TEMP, EFUSE_BLK1, 88, 2, [] Temp (die embedded inside) +PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version +PA_TRIM_VERSION, EFUSE_BLK1, 93, 3, [] PADC CAL PA trim version +TRIM_N_BIAS, EFUSE_BLK1, 96, 5, [] PADC CAL N bias +TRIM_P_BIAS, EFUSE_BLK1, 101, 5, [] PADC CAL P bias +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data diff --git a/components/efuse/esp32c5/include/esp_efuse_table.h b/components/efuse/esp32c5/include/esp_efuse_table.h index 9da2fda348..5cc4627354 100644 --- a/components/efuse/esp32c5/include/esp_efuse_table.h +++ b/components/efuse/esp32c5/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table eb005412b657c9be0ce4bb699e5813c9 +// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,13 +19,22 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; @@ -44,9 +53,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; #define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; @@ -57,12 +71,29 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -159,7 +190,23 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h index 414b241bd3..00bb7f61ca 100644 --- a/components/hal/esp32c5/include/hal/efuse_ll.h +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -59,38 +59,38 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - return (uint32_t)0; + return EFUSE.rd_mac_sys2.wafer_version_major; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (uint32_t)0; + return EFUSE.rd_mac_sys2.wafer_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - return (bool)0; + return EFUSE.rd_mac_sys2.disable_wafer_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return (uint32_t)0; + return EFUSE.rd_mac_sys2.blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return (uint32_t)0; + return EFUSE.rd_mac_sys2.blk_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - return (bool)0; + return EFUSE.rd_mac_sys2.disable_blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return (uint32_t)0; + return EFUSE.rd_mac_sys2.pkg_version; } __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_reg.h b/components/soc/esp32c5/beta3/include/soc/efuse_reg.h index c1454701a2..5f9b6c331d 100644 --- a/components/soc/esp32c5/beta3/include/soc/efuse_reg.h +++ b/components/soc/esp32c5/beta3/include/soc/efuse_reg.h @@ -262,14 +262,14 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) #define EFUSE_USB_DREFH_V 0x00000003U #define EFUSE_USB_DREFH_S 21 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) @@ -693,32 +693,123 @@ extern "C" { * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0; + * Minor chip version */ -#define EFUSE_MAC_RESERVED_0 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_S 0 -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. +#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_S 0 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0; + * Minor chip version */ -#define EFUSE_MAC_RESERVED_1 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_S 14 +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 4 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 8 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 11 +/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0; + * Flash capacity + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 13 +/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0; + * Flash vendor + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 16 +/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0; + * Psram capacity + */ +#define EFUSE_PSRAM_CAP 0x00000007U +#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) +#define EFUSE_PSRAM_CAP_V 0x00000007U +#define EFUSE_PSRAM_CAP_S 19 +/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0; + * Psram vendor + */ +#define EFUSE_PSRAM_VENDOR 0x00000003U +#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) +#define EFUSE_PSRAM_VENDOR_V 0x00000003U +#define EFUSE_PSRAM_VENDOR_S 22 +/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0; + * Temp (die embedded inside) + */ +#define EFUSE_TEMP 0x00000003U +#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S) +#define EFUSE_TEMP_V 0x00000003U +#define EFUSE_TEMP_S 24 +/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 26 +/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0; + * PADC CAL PA trim version + */ +#define EFUSE_PA_TRIM_VERSION 0x00000007U +#define EFUSE_PA_TRIM_VERSION_M (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S) +#define EFUSE_PA_TRIM_VERSION_V 0x00000007U +#define EFUSE_PA_TRIM_VERSION_S 29 /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. +/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0; + * PADC CAL N bias */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 +#define EFUSE_TRIM_N_BIAS 0x0000001FU +#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S) +#define EFUSE_TRIM_N_BIAS_V 0x0000001FU +#define EFUSE_TRIM_N_BIAS_S 0 +/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0; + * PADC CAL P bias + */ +#define EFUSE_TRIM_P_BIAS 0x0000001FU +#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S) +#define EFUSE_TRIM_P_BIAS_V 0x0000001FU +#define EFUSE_TRIM_P_BIAS_S 5 +/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_106 0x000000FFU +#define EFUSE_RESERVED_1_106_M (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S) +#define EFUSE_RESERVED_1_106_V 0x000000FFU +#define EFUSE_RESERVED_1_106_S 10 /** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; * Represents the first 14-bit of zeroth part of system data. */ @@ -755,61 +846,75 @@ extern "C" { * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0; + * reserved */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +#define EFUSE_RESERVED_2_128 0x000001FFU +#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S) +#define EFUSE_RESERVED_2_128_V 0x000001FFU +#define EFUSE_RESERVED_2_128_S 0 +/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 9 +/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_145 0x00007FFFU +#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S) +#define EFUSE_RESERVED_2_145_V 0x00007FFFU +#define EFUSE_RESERVED_2_145_S 17 /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 @@ -2247,7 +2352,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_struct.h b/components/soc/esp32c5/beta3/include/soc/efuse_struct.h index 88e48c0452..0c15f92126 100644 --- a/components/soc/esp32c5/beta3/include/soc/efuse_struct.h +++ b/components/soc/esp32c5/beta3/include/soc/efuse_struct.h @@ -241,11 +241,11 @@ typedef union { */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; @@ -546,14 +546,58 @@ typedef union { */ typedef union { struct { - /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. + /** wafer_version_minor : R; bitpos: [3:0]; default: 0; + * Minor chip version */ - uint32_t mac_reserved_0:14; - /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. + uint32_t wafer_version_minor:4; + /** wafer_version_major : R; bitpos: [5:4]; default: 0; + * Minor chip version */ - uint32_t mac_reserved_1:18; + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : R; bitpos: [6]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** blk_version_minor : R; bitpos: [10:8]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [12:11]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** flash_cap : R; bitpos: [15:13]; default: 0; + * Flash capacity + */ + uint32_t flash_cap:3; + /** flash_vendor : R; bitpos: [18:16]; default: 0; + * Flash vendor + */ + uint32_t flash_vendor:3; + /** psram_cap : R; bitpos: [21:19]; default: 0; + * Psram capacity + */ + uint32_t psram_cap:3; + /** psram_vendor : R; bitpos: [23:22]; default: 0; + * Psram vendor + */ + uint32_t psram_vendor:2; + /** temp : R; bitpos: [25:24]; default: 0; + * Temp (die embedded inside) + */ + uint32_t temp:2; + /** pkg_version : R; bitpos: [28:26]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** pa_trim_version : R; bitpos: [31:29]; default: 0; + * PADC CAL PA trim version + */ + uint32_t pa_trim_version:3; }; uint32_t val; } efuse_rd_mac_sys2_reg_t; @@ -563,10 +607,18 @@ typedef union { */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. + /** trim_n_bias : R; bitpos: [4:0]; default: 0; + * PADC CAL N bias */ - uint32_t mac_reserved_2:18; + uint32_t trim_n_bias:5; + /** trim_p_bias : R; bitpos: [9:5]; default: 0; + * PADC CAL P bias + */ + uint32_t trim_p_bias:5; + /** reserved_1_106 : R; bitpos: [17:10]; default: 0; + * reserved + */ + uint32_t reserved_1_106:8; /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; * Represents the first 14-bit of zeroth part of system data. */ @@ -608,10 +660,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_0:32; + uint32_t optional_unique_id:32; }; uint32_t val; } efuse_rd_sys_part1_data0_reg_t; @@ -621,10 +673,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_1:32; + uint32_t optional_unique_id_1:32; }; uint32_t val; } efuse_rd_sys_part1_data1_reg_t; @@ -634,10 +686,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_2:32; + uint32_t optional_unique_id_2:32; }; uint32_t val; } efuse_rd_sys_part1_data2_reg_t; @@ -647,10 +699,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_3:32; + uint32_t optional_unique_id_3:32; }; uint32_t val; } efuse_rd_sys_part1_data3_reg_t; @@ -660,10 +712,18 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** reserved_2_128 : R; bitpos: [8:0]; default: 0; + * reserved */ - uint32_t sys_data_part1_4:32; + uint32_t reserved_2_128:9; + /** ocode : R; bitpos: [16:9]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** reserved_2_145 : R; bitpos: [31:17]; default: 0; + * reserved + */ + uint32_t reserved_2_145:15; }; uint32_t val; } efuse_rd_sys_part1_data4_reg_t; @@ -1993,7 +2053,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { diff --git a/components/soc/esp32c5/mp/include/soc/efuse_reg.h b/components/soc/esp32c5/mp/include/soc/efuse_reg.h index 2ade523d2a..1da0dd667e 100644 --- a/components/soc/esp32c5/mp/include/soc/efuse_reg.h +++ b/components/soc/esp32c5/mp/include/soc/efuse_reg.h @@ -263,14 +263,14 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) #define EFUSE_USB_DREFH_V 0x00000003U #define EFUSE_USB_DREFH_S 21 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) @@ -694,32 +694,123 @@ extern "C" { * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0; + * Minor chip version */ -#define EFUSE_MAC_RESERVED_0 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_S 0 -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. +#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_S 0 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0; + * Minor chip version */ -#define EFUSE_MAC_RESERVED_1 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_S 14 +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 4 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 8 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 11 +/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0; + * Flash capacity + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 13 +/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0; + * Flash vendor + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 16 +/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0; + * Psram capacity + */ +#define EFUSE_PSRAM_CAP 0x00000007U +#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) +#define EFUSE_PSRAM_CAP_V 0x00000007U +#define EFUSE_PSRAM_CAP_S 19 +/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0; + * Psram vendor + */ +#define EFUSE_PSRAM_VENDOR 0x00000003U +#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) +#define EFUSE_PSRAM_VENDOR_V 0x00000003U +#define EFUSE_PSRAM_VENDOR_S 22 +/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0; + * Temp (die embedded inside) + */ +#define EFUSE_TEMP 0x00000003U +#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S) +#define EFUSE_TEMP_V 0x00000003U +#define EFUSE_TEMP_S 24 +/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 26 +/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0; + * PADC CAL PA trim version + */ +#define EFUSE_PA_TRIM_VERSION 0x00000007U +#define EFUSE_PA_TRIM_VERSION_M (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S) +#define EFUSE_PA_TRIM_VERSION_V 0x00000007U +#define EFUSE_PA_TRIM_VERSION_S 29 /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. +/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0; + * PADC CAL N bias */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 +#define EFUSE_TRIM_N_BIAS 0x0000001FU +#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S) +#define EFUSE_TRIM_N_BIAS_V 0x0000001FU +#define EFUSE_TRIM_N_BIAS_S 0 +/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0; + * PADC CAL P bias + */ +#define EFUSE_TRIM_P_BIAS 0x0000001FU +#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S) +#define EFUSE_TRIM_P_BIAS_V 0x0000001FU +#define EFUSE_TRIM_P_BIAS_S 5 +/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_106 0x000000FFU +#define EFUSE_RESERVED_1_106_M (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S) +#define EFUSE_RESERVED_1_106_V 0x000000FFU +#define EFUSE_RESERVED_1_106_S 10 /** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; * Represents the first 14-bit of zeroth part of system data. */ @@ -756,61 +847,75 @@ extern "C" { * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0; + * reserved */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +#define EFUSE_RESERVED_2_128 0x000001FFU +#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S) +#define EFUSE_RESERVED_2_128_V 0x000001FFU +#define EFUSE_RESERVED_2_128_S 0 +/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0; + * ADC OCode + */ +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 9 +/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_145 0x00007FFFU +#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S) +#define EFUSE_RESERVED_2_145_V 0x00007FFFU +#define EFUSE_RESERVED_2_145_S 17 /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 @@ -2259,7 +2364,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32c5/mp/include/soc/efuse_struct.h b/components/soc/esp32c5/mp/include/soc/efuse_struct.h index f4525d6b4d..d4825477e6 100644 --- a/components/soc/esp32c5/mp/include/soc/efuse_struct.h +++ b/components/soc/esp32c5/mp/include/soc/efuse_struct.h @@ -241,11 +241,11 @@ typedef union { */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; @@ -546,14 +546,58 @@ typedef union { */ typedef union { struct { - /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. + /** wafer_version_minor : R; bitpos: [3:0]; default: 0; + * Minor chip version */ - uint32_t mac_reserved_0:14; - /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. + uint32_t wafer_version_minor:4; + /** wafer_version_major : R; bitpos: [5:4]; default: 0; + * Minor chip version */ - uint32_t mac_reserved_1:18; + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : R; bitpos: [6]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** blk_version_minor : R; bitpos: [10:8]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [12:11]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** flash_cap : R; bitpos: [15:13]; default: 0; + * Flash capacity + */ + uint32_t flash_cap:3; + /** flash_vendor : R; bitpos: [18:16]; default: 0; + * Flash vendor + */ + uint32_t flash_vendor:3; + /** psram_cap : R; bitpos: [21:19]; default: 0; + * Psram capacity + */ + uint32_t psram_cap:3; + /** psram_vendor : R; bitpos: [23:22]; default: 0; + * Psram vendor + */ + uint32_t psram_vendor:2; + /** temp : R; bitpos: [25:24]; default: 0; + * Temp (die embedded inside) + */ + uint32_t temp:2; + /** pkg_version : R; bitpos: [28:26]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** pa_trim_version : R; bitpos: [31:29]; default: 0; + * PADC CAL PA trim version + */ + uint32_t pa_trim_version:3; }; uint32_t val; } efuse_rd_mac_sys2_reg_t; @@ -563,10 +607,18 @@ typedef union { */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. + /** trim_n_bias : R; bitpos: [4:0]; default: 0; + * PADC CAL N bias */ - uint32_t mac_reserved_2:18; + uint32_t trim_n_bias:5; + /** trim_p_bias : R; bitpos: [9:5]; default: 0; + * PADC CAL P bias + */ + uint32_t trim_p_bias:5; + /** reserved_1_106 : R; bitpos: [17:10]; default: 0; + * reserved + */ + uint32_t reserved_1_106:8; /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; * Represents the first 14-bit of zeroth part of system data. */ @@ -608,10 +660,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_0:32; + uint32_t optional_unique_id:32; }; uint32_t val; } efuse_rd_sys_part1_data0_reg_t; @@ -621,10 +673,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_1:32; + uint32_t optional_unique_id_1:32; }; uint32_t val; } efuse_rd_sys_part1_data1_reg_t; @@ -634,10 +686,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_2:32; + uint32_t optional_unique_id_2:32; }; uint32_t val; } efuse_rd_sys_part1_data2_reg_t; @@ -647,10 +699,10 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_3:32; + uint32_t optional_unique_id_3:32; }; uint32_t val; } efuse_rd_sys_part1_data3_reg_t; @@ -660,10 +712,18 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** reserved_2_128 : R; bitpos: [8:0]; default: 0; + * reserved */ - uint32_t sys_data_part1_4:32; + uint32_t reserved_2_128:9; + /** ocode : R; bitpos: [16:9]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** reserved_2_145 : R; bitpos: [31:17]; default: 0; + * reserved + */ + uint32_t reserved_2_145:15; }; uint32_t val; } efuse_rd_sys_part1_data4_reg_t; @@ -2013,7 +2073,7 @@ typedef union { /** Group: EFUSE Configure Registers */ /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { @@ -4229,7 +4289,7 @@ typedef union { } efuse_apb2otp_blk10_w10_reg_t; -/** Group: EFUSE_APB2OTP Function Enable Singal */ +/** Group: EFUSE_APB2OTP Function Enable Signal */ /** Type of apb2otp_en register * eFuse apb2otp enable configuration register. */