From 8e53e91ec9d92a201d3b985d7235368948ee0c81 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 27 Aug 2024 15:54:58 +0800 Subject: [PATCH 1/2] fix(uart): make custom console uart pins same to the default console uart pins --- .../src/bootloader_console.c | 4 ++-- components/console/esp_console.h | 5 ++-- components/esp_system/Kconfig | 24 ++++++++++--------- .../soc/linux/include/soc/uart_channel.h | 9 +++++++ tools/ci/check_soc_headers_leak.py | 3 +-- 5 files changed, 28 insertions(+), 17 deletions(-) create mode 100644 components/soc/linux/include/soc/uart_channel.h diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 2001bb52a1..f37e2e1870 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -48,8 +48,8 @@ void bootloader_console_init(void) #if CONFIG_ESP_CONSOLE_UART_CUSTOM // Some constants to make the following code less upper-case - const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO; - const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO; + const int uart_tx_gpio = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM; + const int uart_rx_gpio = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM; // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code). esp_rom_output_set_as_console(uart_num); diff --git a/components/console/esp_console.h b/components/console/esp_console.h index 0f0891f044..2cebe9b9bf 100644 --- a/components/console/esp_console.h +++ b/components/console/esp_console.h @@ -14,6 +14,7 @@ extern "C" { #include "esp_heap_caps.h" #include "esp_err.h" #include "freertos/FreeRTOS.h" +#include "soc/uart_channel.h" // Forward declaration. Definition in linenoise/linenoise.h. typedef struct linenoiseCompletions linenoiseCompletions; @@ -88,8 +89,8 @@ typedef struct { { \ .channel = CONFIG_ESP_CONSOLE_UART_NUM, \ .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \ - .tx_gpio_num = CONFIG_ESP_CONSOLE_UART_TX_GPIO, \ - .rx_gpio_num = CONFIG_ESP_CONSOLE_UART_RX_GPIO, \ + .tx_gpio_num = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM, \ + .rx_gpio_num = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM, \ } #else #define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \ diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index 10fb36e359..feeb3a580a 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -317,19 +317,20 @@ menu "ESP System Settings" config ESP_CONSOLE_UART_TX_GPIO int "UART TX on GPIO" depends on ESP_CONSOLE_UART_CUSTOM - range 0 SOC_GPIO_OUT_RANGE_MAX + range -1 SOC_GPIO_OUT_RANGE_MAX + # Specific value for old targets for compatibility. No need to add for new targets. default 1 if IDF_TARGET_ESP32 + default 43 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 20 if IDF_TARGET_ESP32C2 default 21 if IDF_TARGET_ESP32C3 - default 10 if IDF_TARGET_ESP32C5 default 16 if IDF_TARGET_ESP32C6 - default 5 if IDF_TARGET_ESP32C61 default 37 if IDF_TARGET_ESP32P4 default 24 if IDF_TARGET_ESP32H2 - default 43 + default -1 help This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including - boot log output and default standard output and standard error of the app). + boot log output and default standard output and standard error of the app). Value -1 means to + continue using the default console UART TX pin. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. @@ -337,19 +338,20 @@ menu "ESP System Settings" config ESP_CONSOLE_UART_RX_GPIO int "UART RX on GPIO" depends on ESP_CONSOLE_UART_CUSTOM - range 0 SOC_GPIO_IN_RANGE_MAX + range -1 SOC_GPIO_IN_RANGE_MAX + # Specific value for old targets for compatibility. No need to add for new targets. default 3 if IDF_TARGET_ESP32 + default 44 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 19 if IDF_TARGET_ESP32C2 default 20 if IDF_TARGET_ESP32C3 - default 11 if IDF_TARGET_ESP32C5 default 17 if IDF_TARGET_ESP32C6 - default 4 if IDF_TARGET_ESP32C61 default 38 if IDF_TARGET_ESP32P4 default 23 if IDF_TARGET_ESP32H2 - default 44 + default -1 help - This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including - default default standard input of the app). + This GPIO is used for console UART RX input in the ESP-IDF Bootloader and the app (including + default standard input of the app). Value -1 means to continue using the default console UART + RX pin. Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. diff --git a/components/soc/linux/include/soc/uart_channel.h b/components/soc/linux/include/soc/uart_channel.h new file mode 100644 index 0000000000..6eb2c7fa5a --- /dev/null +++ b/components/soc/linux/include/soc/uart_channel.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * NOTE: this is a stripped-down copy to support building on host when using mocking (CMock). + */ diff --git a/tools/ci/check_soc_headers_leak.py b/tools/ci/check_soc_headers_leak.py index dce9876489..363d049c7b 100644 --- a/tools/ci/check_soc_headers_leak.py +++ b/tools/ci/check_soc_headers_leak.py @@ -1,9 +1,7 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - # This check script is used to ensure the public APIs won't expose the unstable soc files like register files # public API header files are those taken by doxygen and have full documented docs - import fnmatch import os import re @@ -18,6 +16,7 @@ allowed_soc_headers = ( 'soc/reset_reasons.h', 'soc/reg_base.h', 'soc/clk_tree_defs.h', + 'soc/uart_channel.h', ) include_header_pattern = re.compile(r'[\s]*#[\s]*include ["<](.*)[">].*') From e1f27d04edb847f51e683f059548eaff28383ad3 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 27 Aug 2024 17:50:34 +0800 Subject: [PATCH 2/2] fix(uart): enable ci target test for uart for c5 --- components/esp_driver_uart/test_apps/uart/pytest_uart.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/components/esp_driver_uart/test_apps/uart/pytest_uart.py b/components/esp_driver_uart/test_apps/uart/pytest_uart.py index b154e64421..68b2661cda 100644 --- a/components/esp_driver_uart/test_apps/uart/pytest_uart.py +++ b/components/esp_driver_uart/test_apps/uart/pytest_uart.py @@ -11,6 +11,8 @@ input_argv = { 'esp32c6': ['uart', 'lp_uart'], 'esp32h2': ['uart'], 'esp32p4': ['uart', 'lp_uart'], + 'esp32c5': ['uart', 'lp_uart'], + 'esp32c61': ['uart'], } @@ -28,9 +30,13 @@ input_argv = { def test_uart_single_dev(case_tester) -> None: # type: ignore dut = case_tester.first_dut chip_type = dut.app.target + + uart_ports = input_argv.get(chip_type, []) + assert uart_ports, f"Error: Chip type '{chip_type}' is not defined in input_argv. Aborting..." + for case in case_tester.test_menu: if 'hp-uart-only' not in case.groups: - for uart_port in input_argv.get(chip_type, []): + for uart_port in uart_ports: dut.serial.hard_reset() dut._get_ready() dut.confirm_write(case.index, expect_str=f'Running {case.name}...')