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fix(esp_hw_support): fix esp32h2 system link restore override cpu clk configuration

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This commit is contained in:
wuzhenghui 2023-11-29 21:15:41 +08:00
parent 397f9f2274
commit b6669d76b2
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GPG Key ID: 3EFEDECDEBA39BB9
1 changed files with 16 additions and 11 deletions
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27
components/esp_hw_support/sleep_modes.c
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@ -550,9 +550,6 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep)
#endif
#if REGI2C_ANA_CALI_PD_WORKAROUND
regi2c_analog_cali_reg_read();
#endif
#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
sleep_retention_do_system_retention(true);
#endif
}
@ -569,9 +566,6 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(void)
{
#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
sleep_console_usj_pad_restore();
#endif
#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
sleep_retention_do_system_retention(false);
#endif
sar_periph_ctrl_power_enable();
#if SOC_PM_SUPPORT_CPU_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL
@ -624,6 +618,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
// Will switch to XTAL turn down MSPI speed
mspi_timing_change_speed_mode_cache_safe(true);
#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
if (!deep_sleep && (pd_flags & PMU_SLEEP_PD_TOP)) {
sleep_retention_do_system_retention(true);
}
#endif
// Save current frequency and switch to XTAL
rtc_cpu_freq_config_t cpu_freq_config;
rtc_clk_cpu_freq_get_config(&cpu_freq_config);
@ -848,18 +848,23 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
rtc_clk_cpu_freq_set_config(&cpu_freq_config);
}
if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) {
// Turn up MSPI speed if switch to PLL
mspi_timing_change_speed_mode_cache_safe(false);
}
esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CLK_READY, (void *)0);
if (!deep_sleep) {
s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
if (pd_flags & PMU_SLEEP_PD_TOP) {
sleep_retention_do_system_retention(false);
}
#endif
misc_modules_wake_prepare();
}
if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) {
// Turn up MSPI speed if switch to PLL
mspi_timing_change_speed_mode_cache_safe(false);
}
// re-enable UART output
resume_uarts();
return result ? ESP_ERR_SLEEP_REJECT : ESP_OK;