diff --git a/components/soc/esp32h2/CMakeLists.txt b/components/soc/esp32h2/CMakeLists.txt index e69de29bb2..8f5b821c67 100644 --- a/components/soc/esp32h2/CMakeLists.txt +++ b/components/soc/esp32h2/CMakeLists.txt @@ -0,0 +1,34 @@ +set(srcs + "adc_periph.c" + "dedic_gpio_periph.c" + "gdma_periph.c" + "gpio_periph.c" + "interrupts.c" + "spi_periph.c" + "ledc_periph.c" + "rmt_periph.c" + "sdm_periph.c" + "i2s_periph.c" + "i2c_periph.c" + "uart_periph.c" + "temperature_sensor_periph.c" + "timer_periph.c") + + +#// ESP32H2-TODO +list(REMOVE_ITEM srcs + "adc_periph.c" + "dedic_gpio_periph.c" + "ledc_periph.c" + "i2s_periph.c" + "i2c_periph.c" + "temperature_sensor_periph.c" + "adc_periph.c" + ) + + + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + +target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") +target_include_directories(${COMPONENT_LIB} PUBLIC . include) diff --git a/components/soc/esp32h2/adc_periph.c b/components/soc/esp32h2/adc_periph.c new file mode 100644 index 0000000000..d235bdf947 --- /dev/null +++ b/components/soc/esp32h2/adc_periph.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { + /* ADC1 */ + { + ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM + }, + /* ADC2 */ + { + ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1 + } +}; diff --git a/components/soc/esp32h2/dedic_gpio_periph.c b/components/soc/esp32h2/dedic_gpio_periph.c new file mode 100644 index 0000000000..711274f893 --- /dev/null +++ b/components/soc/esp32h2/dedic_gpio_periph.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_sig_map.h" +#include "soc/dedic_gpio_periph.h" + +const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { + .module = -1, + .irq = -1, + .cores = { + [0] = { + .in_sig_per_channel = { + [0] = CPU_GPIO_IN0_IDX, + [1] = CPU_GPIO_IN1_IDX, + [2] = CPU_GPIO_IN2_IDX, + [3] = CPU_GPIO_IN3_IDX, + [4] = CPU_GPIO_IN4_IDX, + [5] = CPU_GPIO_IN5_IDX, + [6] = CPU_GPIO_IN6_IDX, + [7] = CPU_GPIO_IN7_IDX, + }, + .out_sig_per_channel = { + [0] = CPU_GPIO_OUT0_IDX, + [1] = CPU_GPIO_OUT1_IDX, + [2] = CPU_GPIO_OUT2_IDX, + [3] = CPU_GPIO_OUT3_IDX, + [4] = CPU_GPIO_OUT4_IDX, + [5] = CPU_GPIO_OUT5_IDX, + [6] = CPU_GPIO_OUT6_IDX, + [7] = CPU_GPIO_OUT7_IDX, + } + }, + }, +}; diff --git a/components/soc/esp32h2/gdma_periph.c b/components/soc/esp32h2/gdma_periph.c new file mode 100644 index 0000000000..83fe4ddbb5 --- /dev/null +++ b/components/soc/esp32h2/gdma_periph.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_GDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE, + } + } + } + } +}; diff --git a/components/soc/esp32h2/gpio_periph.c b/components/soc/esp32h2/gpio_periph.c new file mode 100644 index 0000000000..649624a3e4 --- /dev/null +++ b/components/soc/esp32h2/gpio_periph.c @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { + IO_MUX_GPIO0_REG, + IO_MUX_GPIO1_REG, + IO_MUX_GPIO2_REG, + IO_MUX_GPIO3_REG, + IO_MUX_GPIO4_REG, + IO_MUX_GPIO5_REG, + IO_MUX_GPIO6_REG, + IO_MUX_GPIO7_REG, + IO_MUX_GPIO8_REG, + IO_MUX_GPIO9_REG, + IO_MUX_GPIO10_REG, + IO_MUX_GPIO11_REG, + IO_MUX_GPIO12_REG, + IO_MUX_GPIO13_REG, + IO_MUX_GPIO14_REG, + IO_MUX_GPIO15_REG, + IO_MUX_GPIO16_REG, + IO_MUX_GPIO17_REG, + IO_MUX_GPIO18_REG, + IO_MUX_GPIO19_REG, + IO_MUX_GPIO20_REG, + IO_MUX_GPIO21_REG, + IO_MUX_GPIO22_REG, + IO_MUX_GPIO23_REG, + IO_MUX_GPIO24_REG, + IO_MUX_GPIO25_REG, + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG +}; + +const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { + BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(7), //GPIO7 + BIT(8), //GPIO8 + BIT(9), //GPIO9 + BIT(10), //GPIO10 + BIT(11), //GPIO11 + BIT(12), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(16), //GPIO16 + BIT(17), //GPIO17 + BIT(18), //GPIO18 + BIT(19), //GPIO19 + BIT(20), //GPIO20 + BIT(21), //GPIO21 + BIT(22), //GPIO22 + BIT(23), //GPIO23 + BIT(24), //GPIO24 + BIT(25), //GPIO25 + BIT(26), //GPIO26 + BIT(27), //GPIO27 +}; diff --git a/components/soc/esp32h2/i2c_periph.c b/components/soc/esp32h2/i2c_periph.c new file mode 100644 index 0000000000..cb8e7fa246 --- /dev/null +++ b/components/soc/esp32h2/i2c_periph.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2c_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { + { + .sda_out_sig = I2CEXT0_SDA_OUT_IDX, + .sda_in_sig = I2CEXT0_SDA_IN_IDX, + .scl_out_sig = I2CEXT0_SCL_OUT_IDX, + .scl_in_sig = I2CEXT0_SCL_IN_IDX, + .irq = ETS_I2C_EXT0_INTR_SOURCE, + .module = PERIPH_I2C0_MODULE, + }, +}; diff --git a/components/soc/esp32h2/i2s_periph.c b/components/soc/esp32h2/i2s_periph.c new file mode 100644 index 0000000000..daa8057277 --- /dev/null +++ b/components/soc/esp32h2/i2s_periph.c @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2s_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { + { + .mck_out_sig = I2S_MCLK_OUT_IDX, + + .m_tx_bck_sig = I2SO_BCK_OUT_IDX, + .m_rx_bck_sig = I2SI_BCK_OUT_IDX, + .m_tx_ws_sig = I2SO_WS_OUT_IDX, + .m_rx_ws_sig = I2SI_WS_OUT_IDX, + + .s_tx_bck_sig = I2SO_BCK_IN_IDX, + .s_rx_bck_sig = I2SI_BCK_IN_IDX, + .s_tx_ws_sig = I2SO_WS_IN_IDX, + .s_rx_ws_sig = I2SI_WS_IN_IDX, + + .data_out_sig = I2SO_SD_OUT_IDX, + .data_in_sig = I2SI_SD_IN_IDX, + + .irq = -1, + .module = PERIPH_I2S1_MODULE, + } +}; diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in new file mode 100644 index 0000000000..a59ee41652 --- /dev/null +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,796 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_DEDICATED_GPIO_SUPPORTED + bool + default y + +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_BT_SUPPORTED + bool + default y + +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + +config SOC_SUPPORTS_SECURE_DL_MODE + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_HAS_EFUSE_RST_BUG + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_SUPPORT_COEXISTENCE + bool + default y + +config SOC_MPI_SUPPORTED + bool + default y + +config SOC_HMAC_SUPPORTED + bool + default y + +config SOC_SECURE_BOOT_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_32M + bool + default y + +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_ADC_DIG_CTRL_SUPPORTED + bool + default y + +config SOC_ADC_ARBITER_SUPPORTED + bool + default y + +config SOC_ADC_FILTER_SUPPORTED + bool + default y + +config SOC_ADC_MONITOR_SUPPORTED + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 2 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 5 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_CALIBRATION_V1_SUPPORTED + bool + default n + +config SOC_APB_BACKUP_DMA + bool + default n + +config SOC_BROWNOUT_RESET_SUPPORTED + bool + default y + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_PLIC_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_SIZE + hex + default 0x80000000 + +config SOC_MMU_PAGE_SIZE_CONFIGURABLE + bool + default y + +config SOC_DS_SIGNATURE_MAX_BIT_LEN + int + default 3072 + +config SOC_DS_KEY_PARAM_MD_IV_LENGTH + int + default 16 + +config SOC_DS_KEY_CHECK_MAX_WAIT_US + int + default 1100 + +config SOC_GDMA_GROUPS + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP + int + default 3 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 31 + +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT + bool + default y + +config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP + bool + default y + +config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK + int + default 0 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000000007FFFFF00 + +config SOC_GPIO_SUPPORT_SLP_SWITCH + bool + default y + +config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_GPIO_IN_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_PERIPH_ALWAYS_ENABLE + bool + default y + +config SOC_I2C_NUM + int + default 1 + +config SOC_I2C_FIFO_LEN + int + default 32 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_HW_CLR_BUS + bool + default y + +config SOC_I2C_SUPPORT_XTAL + bool + default y + +config SOC_I2C_SUPPORT_RTC + bool + default y + +config SOC_I2S_NUM + bool + default y + +config SOC_I2S_HW_VERSION_2 + bool + default y + +config SOC_I2S_SUPPORTS_XTAL + bool + default y + +config SOC_I2S_SUPPORTS_PCM + bool + default y + +config SOC_I2S_SUPPORTS_PDM + bool + default y + +config SOC_I2S_SUPPORTS_PDM_TX + bool + default y + +config SOC_I2S_PDM_MAX_TX_LINES + int + default 2 + +config SOC_I2S_SUPPORTS_TDM + bool + default y + +config SOC_LEDC_SUPPORT_APB_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_CHANNEL_NUM + int + default 6 + +config SOC_LEDC_TIMER_BIT_WIDE_NUM + int + default 14 + +config SOC_LEDC_SUPPORT_FADE_STOP + bool + default y + +config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED + bool + default n + +config SOC_MPU_MIN_REGION_SIZE + hex + default 0x20000000 + +config SOC_MPU_REGIONS_MAX_NUM + int + default 8 + +config SOC_MPU_REGION_RO_SUPPORTED + bool + default n + +config SOC_MPU_REGION_WO_SUPPORTED + bool + default n + +config SOC_PCNT_GROUPS + int + default 1 + +config SOC_PCNT_UNITS_PER_GROUP + int + default 4 + +config SOC_PCNT_CHANNELS_PER_UNIT + int + default 2 + +config SOC_PCNT_THRES_POINT_PER_UNIT + int + default 2 + +config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE + bool + default y + +config SOC_RMT_GROUPS + int + default 1 + +config SOC_RMT_TX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_RX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_CHANNELS_PER_GROUP + int + default 4 + +config SOC_RMT_MEM_WORDS_PER_CHANNEL + int + default 48 + +config SOC_RMT_SUPPORT_RX_PINGPONG + bool + default y + +config SOC_RMT_SUPPORT_RX_DEMODULATION + bool + default y + +config SOC_RMT_SUPPORT_TX_ASYNC_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_COUNT + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_SYNCHRO + bool + default y + +config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY + bool + default y + +config SOC_RMT_SUPPORT_XTAL + bool + default y + +config SOC_RMT_SUPPORT_APB + bool + default y + +config SOC_MCPWM_GROUPS + int + default 1 + +config SOC_MCPWM_TIMERS_PER_GROUP + int + default 3 + +config SOC_MCPWM_OPERATORS_PER_GROUP + int + default 3 + +config SOC_MCPWM_COMPARATORS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_GENERATORS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_TRIGGERS_PER_OPERATOR + int + default 2 + +config SOC_MCPWM_GPIO_FAULTS_PER_GROUP + int + default 3 + +config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP + bool + default y + +config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER + int + default 3 + +config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP + int + default 3 + +config SOC_MCPWM_SWSYNC_CAN_PROPAGATE + bool + default y + +config SOC_MCPWM_SUPPORT_ETM + bool + default y + +config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP + bool + default y + +config SOC_MCPWM_CLK_SUPPORT_PLL160M + bool + default y + +config SOC_MCPWM_CLK_SUPPORT_XTAL + bool + default y + +config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH + int + default 128 + +config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM + int + default 108 + +config SOC_RTCIO_PIN_COUNT + int + default 0 + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SDM_GROUPS + int + default 1 + +config SOC_SDM_CHANNELS_PER_GROUP + int + default 4 + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 16 + +config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_RESUME + bool + default y + +config SOC_SPI_MEM_SUPPORT_IDLE_INTR + bool + default y + +config SOC_SPI_MEM_SUPPORT_SW_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_CHECK_SUS + bool + default y + +config SOC_MEMSPI_SRC_FREQ_48M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_SUPPORT_APB + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_TWAI_CONTROLLER_NUM + bool + default y + +config SOC_TWAI_CLK_SUPPORT_XTAL + bool + default y + +config SOC_TWAI_BRP_MIN + int + default 2 + +config SOC_TWAI_BRP_MAX + int + default 32768 + +config SOC_TWAI_SUPPORTS_RX_STATUS + bool + default y + +config SOC_SECURE_BOOT_V2_RSA + bool + default y + +config SOC_SECURE_BOOT_V2_ECC + bool + default y + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS + bool + default y + +config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + bool + default y + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 32 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE + int + default 16 + +config SOC_MEMPROT_MEM_ALIGN_SIZE + int + default 512 + +config SOC_UART_NUM + int + default 2 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_APB_CLK + bool + default y + +config SOC_UART_SUPPORT_RTC_CLK + bool + default n + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_REQUIRE_CORE_RESET + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_COEX_HW_PTI + bool + default y + +config SOC_PHY_DIG_REGS_MEM_SIZE + int + default 21 + +config SOC_MAC_BB_PD_MEM_SIZE + int + default 192 + +config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH + int + default 12 + +config SOC_PM_SUPPORT_WIFI_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_BT_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_WIFI_PD + bool + default y + +config SOC_PM_SUPPORT_BT_PD + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL + bool + default y + +config SOC_BLE_SUPPORTED + bool + default y diff --git a/components/soc/esp32h2/include/soc/adc_channel.h b/components/soc/esp32h2/include/soc/adc_channel.h new file mode 100644 index 0000000000..194e7bdd99 --- /dev/null +++ b/components/soc/esp32h2/include/soc/adc_channel.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ADC1_GPIO0_CHANNEL ADC1_CHANNEL_0 +#define ADC1_CHANNEL_0_GPIO_NUM 0 + +#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_1 +#define ADC1_CHANNEL_1_GPIO_NUM 1 + +#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_2 +#define ADC1_CHANNEL_2_GPIO_NUM 2 + +#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_3 +#define ADC1_CHANNEL_3_GPIO_NUM 3 + +#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_4 +#define ADC1_CHANNEL_4_GPIO_NUM 4 + +#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0 +#define ADC2_CHANNEL_0_GPIO_NUM 5 diff --git a/components/soc/esp32h2/include/soc/aes_reg.h b/components/soc/esp32h2/include/soc/aes_reg.h new file mode 100644 index 0000000000..c096489ca4 --- /dev/null +++ b/components/soc/esp32h2/include/soc/aes_reg.h @@ -0,0 +1,417 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** AES_KEY_0_REG register + * Key material key_0 configure register + */ +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_1_REG register + * Key material key_1 configure register + */ +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) +/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ +#define AES_KEY_1 0xFFFFFFFFU +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFFU +#define AES_KEY_1_S 0 + +/** AES_KEY_2_REG register + * Key material key_2 configure register + */ +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) +/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ +#define AES_KEY_2 0xFFFFFFFFU +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFFU +#define AES_KEY_2_S 0 + +/** AES_KEY_3_REG register + * Key material key_3 configure register + */ +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) +/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ +#define AES_KEY_3 0xFFFFFFFFU +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFFU +#define AES_KEY_3_S 0 + +/** AES_KEY_4_REG register + * Key material key_4 configure register + */ +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) +/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ +#define AES_KEY_4 0xFFFFFFFFU +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFFU +#define AES_KEY_4_S 0 + +/** AES_KEY_5_REG register + * Key material key_5 configure register + */ +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) +/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ +#define AES_KEY_5 0xFFFFFFFFU +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFFU +#define AES_KEY_5_S 0 + +/** AES_KEY_6_REG register + * Key material key_6 configure register + */ +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) +/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ +#define AES_KEY_6 0xFFFFFFFFU +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFFU +#define AES_KEY_6_S 0 + +/** AES_KEY_7_REG register + * Key material key_7 configure register + */ +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) +/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ +#define AES_KEY_7 0xFFFFFFFFU +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFFU +#define AES_KEY_7_S 0 + +/** AES_TEXT_IN_0_REG register + * source text material text_in_0 configure register + */ +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_1_REG register + * source text material text_in_1 configure register + */ +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) +/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ +#define AES_TEXT_IN_1 0xFFFFFFFFU +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFFU +#define AES_TEXT_IN_1_S 0 + +/** AES_TEXT_IN_2_REG register + * source text material text_in_2 configure register + */ +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) +/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ +#define AES_TEXT_IN_2 0xFFFFFFFFU +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFFU +#define AES_TEXT_IN_2_S 0 + +/** AES_TEXT_IN_3_REG register + * source text material text_in_3 configure register + */ +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) +/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ +#define AES_TEXT_IN_3 0xFFFFFFFFU +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFFU +#define AES_TEXT_IN_3_S 0 + +/** AES_TEXT_OUT_0_REG register + * result text material text_out_0 configure register + */ +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_1_REG register + * result text material text_out_1 configure register + */ +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) +/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ +#define AES_TEXT_OUT_1 0xFFFFFFFFU +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFFU +#define AES_TEXT_OUT_1_S 0 + +/** AES_TEXT_OUT_2_REG register + * result text material text_out_2 configure register + */ +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) +/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ +#define AES_TEXT_OUT_2 0xFFFFFFFFU +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFFU +#define AES_TEXT_OUT_2_S 0 + +/** AES_TEXT_OUT_3_REG register + * result text material text_out_3 configure register + */ +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) +/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ +#define AES_TEXT_OUT_3 0xFFFFFFFFU +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFFU +#define AES_TEXT_OUT_3_S 0 + +/** AES_MODE_REG register + * AES Mode register + */ +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) +/** AES_MODE : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ +#define AES_MODE 0x00000007U +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007U +#define AES_MODE_S 0 + +/** AES_ENDIAN_REG register + * AES Endian configure register + */ +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) +/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out + * endian or out_stream endian + */ +#define AES_ENDIAN 0x0000003FU +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003FU +#define AES_ENDIAN_S 0 + +/** AES_TRIGGER_REG register + * AES trigger register + */ +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) +/** AES_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001U +#define AES_TRIGGER_S 0 + +/** AES_STATE_REG register + * AES state register + */ +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) +/** AES_STATE : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ +#define AES_STATE 0x00000003U +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003U +#define AES_STATE_S 0 + +/** AES_IV_MEM register + * The memory that stores initialization vector + */ +#define AES_IV_MEM (DR_REG_AES_BASE + 0x50) +#define AES_IV_MEM_SIZE_BYTES 16 + +/** AES_H_MEM register + * The memory that stores GCM hash subkey + */ +#define AES_H_MEM (DR_REG_AES_BASE + 0x60) +#define AES_H_MEM_SIZE_BYTES 16 + +/** AES_J0_MEM register + * The memory that stores J0 + */ +#define AES_J0_MEM (DR_REG_AES_BASE + 0x70) +#define AES_J0_MEM_SIZE_BYTES 16 + +/** AES_T0_MEM register + * The memory that stores T0 + */ +#define AES_T0_MEM (DR_REG_AES_BASE + 0x80) +#define AES_T0_MEM_SIZE_BYTES 16 + +/** AES_DMA_ENABLE_REG register + * DMA-AES working mode register + */ +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) +/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001U +#define AES_DMA_ENABLE_S 0 + +/** AES_BLOCK_MODE_REG register + * AES cipher block mode register + */ +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) +/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ +#define AES_BLOCK_MODE 0x00000007U +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007U +#define AES_BLOCK_MODE_S 0 + +/** AES_BLOCK_NUM_REG register + * AES block number register + */ +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) +/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ +#define AES_BLOCK_NUM 0xFFFFFFFFU +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_BLOCK_NUM_S 0 + +/** AES_INC_SEL_REG register + * Standard incrementing function configure register + */ +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) +/** AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001U +#define AES_INC_SEL_S 0 + +/** AES_AAD_BLOCK_NUM_REG register + * Additional Authential Data block number register + */ +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) +/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of AAD block. + */ +#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_AAD_BLOCK_NUM_S 0 + +/** AES_REMAINDER_BIT_NUM_REG register + * AES remainder bit number register + */ +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) +/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Those bits stores the number of remainder bit. + */ +#define AES_REMAINDER_BIT_NUM 0x0000007FU +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007FU +#define AES_REMAINDER_BIT_NUM_S 0 + +/** AES_CONTINUE_REG register + * AES continue register + */ +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) +/** AES_CONTINUE : WT; bitpos: [0]; default: 0; + * Set this bit to continue GCM operation. + */ +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001U +#define AES_CONTINUE_S 0 + +/** AES_INT_CLEAR_REG register + * AES Interrupt clear register + */ +#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac) +/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ +#define AES_INT_CLEAR (BIT(0)) +#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S) +#define AES_INT_CLEAR_V 0x00000001U +#define AES_INT_CLEAR_S 0 + +/** AES_INT_ENA_REG register + * AES Interrupt enable register + */ +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) +/** AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001U +#define AES_INT_ENA_S 0 + +/** AES_DATE_REG register + * AES version control register + */ +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) +/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ +#define AES_DATE 0x3FFFFFFFU +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFFU +#define AES_DATE_S 0 + +/** AES_DMA_EXIT_REG register + * AES-DMA exit config + */ +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) +/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001U +#define AES_DMA_EXIT_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/aes_struct.h b/components/soc/esp32h2/include/soc/aes_struct.h new file mode 100644 index 0000000000..6849243328 --- /dev/null +++ b/components/soc/esp32h2/include/soc/aes_struct.h @@ -0,0 +1,496 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: key register */ +/** Type of key_0 register + * Key material key_0 configure register + */ +typedef union { + struct { + /** key_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ + uint32_t key_0:32; + }; + uint32_t val; +} aes_key_0_reg_t; + +/** Type of key_1 register + * Key material key_1 configure register + */ +typedef union { + struct { + /** key_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ + uint32_t key_1:32; + }; + uint32_t val; +} aes_key_1_reg_t; + +/** Type of key_2 register + * Key material key_2 configure register + */ +typedef union { + struct { + /** key_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ + uint32_t key_2:32; + }; + uint32_t val; +} aes_key_2_reg_t; + +/** Type of key_3 register + * Key material key_3 configure register + */ +typedef union { + struct { + /** key_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ + uint32_t key_3:32; + }; + uint32_t val; +} aes_key_3_reg_t; + +/** Type of key_4 register + * Key material key_4 configure register + */ +typedef union { + struct { + /** key_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ + uint32_t key_4:32; + }; + uint32_t val; +} aes_key_4_reg_t; + +/** Type of key_5 register + * Key material key_5 configure register + */ +typedef union { + struct { + /** key_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ + uint32_t key_5:32; + }; + uint32_t val; +} aes_key_5_reg_t; + +/** Type of key_6 register + * Key material key_6 configure register + */ +typedef union { + struct { + /** key_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ + uint32_t key_6:32; + }; + uint32_t val; +} aes_key_6_reg_t; + +/** Type of key_7 register + * Key material key_7 configure register + */ +typedef union { + struct { + /** key_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ + uint32_t key_7:32; + }; + uint32_t val; +} aes_key_7_reg_t; + + +/** Group: text in register */ +/** Type of text_in_0 register + * source text material text_in_0 configure register + */ +typedef union { + struct { + /** text_in_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ + uint32_t text_in_0:32; + }; + uint32_t val; +} aes_text_in_0_reg_t; + +/** Type of text_in_1 register + * source text material text_in_1 configure register + */ +typedef union { + struct { + /** text_in_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ + uint32_t text_in_1:32; + }; + uint32_t val; +} aes_text_in_1_reg_t; + +/** Type of text_in_2 register + * source text material text_in_2 configure register + */ +typedef union { + struct { + /** text_in_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ + uint32_t text_in_2:32; + }; + uint32_t val; +} aes_text_in_2_reg_t; + +/** Type of text_in_3 register + * source text material text_in_3 configure register + */ +typedef union { + struct { + /** text_in_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ + uint32_t text_in_3:32; + }; + uint32_t val; +} aes_text_in_3_reg_t; + + +/** Group: text out register */ +/** Type of text_out_0 register + * result text material text_out_0 configure register + */ +typedef union { + struct { + /** text_out_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ + uint32_t text_out_0:32; + }; + uint32_t val; +} aes_text_out_0_reg_t; + +/** Type of text_out_1 register + * result text material text_out_1 configure register + */ +typedef union { + struct { + /** text_out_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ + uint32_t text_out_1:32; + }; + uint32_t val; +} aes_text_out_1_reg_t; + +/** Type of text_out_2 register + * result text material text_out_2 configure register + */ +typedef union { + struct { + /** text_out_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ + uint32_t text_out_2:32; + }; + uint32_t val; +} aes_text_out_2_reg_t; + +/** Type of text_out_3 register + * result text material text_out_3 configure register + */ +typedef union { + struct { + /** text_out_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ + uint32_t text_out_3:32; + }; + uint32_t val; +} aes_text_out_3_reg_t; + + +/** Group: Configuration register */ +/** Type of mode register + * AES Mode register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_mode_reg_t; + +/** Type of endian register + * AES Endian configure register + */ +typedef union { + struct { + /** endian : R/W; bitpos: [5:0]; default: 0; + * endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out + * endian or out_stream endian + */ + uint32_t endian:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} aes_endian_reg_t; + +/** Type of block_mode register + * AES cipher block mode register + */ +typedef union { + struct { + /** block_mode : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ + uint32_t block_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_block_mode_reg_t; + +/** Type of block_num register + * AES block number register + */ +typedef union { + struct { + /** block_num : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ + uint32_t block_num:32; + }; + uint32_t val; +} aes_block_num_reg_t; + +/** Type of inc_sel register + * Standard incrementing function configure register + */ +typedef union { + struct { + /** inc_sel : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ + uint32_t inc_sel:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_inc_sel_reg_t; + +/** Type of aad_block_num register + * Additional Authential Data block number register + */ +typedef union { + struct { + /** aad_block_num : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of AAD block. + */ + uint32_t aad_block_num:32; + }; + uint32_t val; +} aes_aad_block_num_reg_t; + +/** Type of remainder_bit_num register + * AES remainder bit number register + */ +typedef union { + struct { + /** remainder_bit_num : R/W; bitpos: [6:0]; default: 0; + * Those bits stores the number of remainder bit. + */ + uint32_t remainder_bit_num:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} aes_remainder_bit_num_reg_t; + + +/** Group: Control/Status register */ +/** Type of trigger register + * AES trigger register + */ +typedef union { + struct { + /** trigger : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ + uint32_t trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_trigger_reg_t; + +/** Type of state register + * AES state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} aes_state_reg_t; + +/** Type of dma_enable register + * DMA-AES working mode register + */ +typedef union { + struct { + /** dma_enable : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ + uint32_t dma_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_enable_reg_t; + +/** Type of continue register + * AES continue register + */ +typedef union { + struct { + /** continue : WT; bitpos: [0]; default: 0; + * Set this bit to continue GCM operation. + */ + uint32_t continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_continue_reg_t; + +/** Type of dma_exit register + * AES-DMA exit config + */ +typedef union { + struct { + /** dma_exit : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ + uint32_t dma_exit:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_exit_reg_t; + + +/** Group: memory type */ + +/** Group: interrupt register */ +/** Type of int_clear register + * AES Interrupt clear register + */ +typedef union { + struct { + /** int_clear : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ + uint32_t int_clear:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_clear_reg_t; + +/** Type of int_ena register + * AES Interrupt enable register + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_ena_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * AES version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} aes_date_reg_t; + + +typedef struct { + volatile aes_key_0_reg_t key_0; + volatile aes_key_1_reg_t key_1; + volatile aes_key_2_reg_t key_2; + volatile aes_key_3_reg_t key_3; + volatile aes_key_4_reg_t key_4; + volatile aes_key_5_reg_t key_5; + volatile aes_key_6_reg_t key_6; + volatile aes_key_7_reg_t key_7; + volatile aes_text_in_0_reg_t text_in_0; + volatile aes_text_in_1_reg_t text_in_1; + volatile aes_text_in_2_reg_t text_in_2; + volatile aes_text_in_3_reg_t text_in_3; + volatile aes_text_out_0_reg_t text_out_0; + volatile aes_text_out_1_reg_t text_out_1; + volatile aes_text_out_2_reg_t text_out_2; + volatile aes_text_out_3_reg_t text_out_3; + volatile aes_mode_reg_t mode; + volatile aes_endian_reg_t endian; + volatile aes_trigger_reg_t trigger; + volatile aes_state_reg_t state; + volatile uint32_t iv[4]; + volatile uint32_t h[4]; + volatile uint32_t j0[4]; + volatile uint32_t t0[4]; + volatile aes_dma_enable_reg_t dma_enable; + volatile aes_block_mode_reg_t block_mode; + volatile aes_block_num_reg_t block_num; + volatile aes_inc_sel_reg_t inc_sel; + volatile aes_aad_block_num_reg_t aad_block_num; + volatile aes_remainder_bit_num_reg_t remainder_bit_num; + volatile aes_continue_reg_t continue; + volatile aes_int_clear_reg_t int_clear; + volatile aes_int_ena_reg_t int_ena; + volatile aes_date_reg_t date; + volatile aes_dma_exit_reg_t dma_exit; +} aes_dev_t; + +extern aes_dev_t AES; + +#ifndef __cplusplus +_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/apb_saradc_reg.h b/components/soc/esp32h2/include/soc/apb_saradc_reg.h new file mode 100644 index 0000000000..2a55f48436 --- /dev/null +++ b/components/soc/esp32h2/include/soc/apb_saradc_reg.h @@ -0,0 +1,884 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** APB_SARADC_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0) +/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ +#define APB_SARADC_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) +#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U +#define APB_SARADC_SARADC_START_FORCE_S 0 +/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ +#define APB_SARADC_SARADC_START (BIT(1)) +#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) +#define APB_SARADC_SARADC_START_V 0x00000001U +#define APB_SARADC_SARADC_START_S 1 +/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ +#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) +#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U +#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 +/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ +#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) +#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 +/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ +#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) +#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 +/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 +/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ +#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) +#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 +/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ +#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29)) +#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S) +#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U +#define APB_SARADC_SARADC2_PWDET_DRV_S 29 +/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 + +/** APB_SARADC_CTRL2_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4) +/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ +#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) +#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 +/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) +#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR1_INV_S 9 +/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) +#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR2_INV_S 10 +/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ +#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) +#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_S 12 +/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ +#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) +#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U +#define APB_SARADC_SARADC_TIMER_EN_S 24 + +/** APB_SARADC_FILTER_CTRL1_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8) +/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26 +/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29 + +/** APB_SARADC_FSM_WAIT_REG register + * digital saradc configure register + */ +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_BASE + 0xc) +/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; + * saradc_xpd_wait + */ +#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU +#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S) +#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_XPD_WAIT_S 0 +/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; + * saradc_rstb_wait + */ +#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU +#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S) +#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_RSTB_WAIT_S 8 +/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; + * saradc_standby_wait + */ +#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU +#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S) +#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_STANDBY_WAIT_S 16 + +/** APB_SARADC_SAR1_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_BASE + 0x10) +/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912; + * saradc1 status about data and channel + */ +#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S) +#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR1_STATUS_S 0 + +/** APB_SARADC_SAR2_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_BASE + 0x14) +/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912; + * saradc2 status about data and channel + */ +#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S) +#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR2_STATUS_S 0 + +/** APB_SARADC_SAR_PATT_TAB1_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18) +/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 + +/** APB_SARADC_SAR_PATT_TAB2_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c) +/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 + +/** APB_SARADC_ONETIME_SAMPLE_REG register + * digital saradc configure register + */ +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20) +/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ +#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) +#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ +#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) +#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 +/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ +#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) +#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U +#define APB_SARADC_SARADC_ONETIME_START_S 29 +/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ +#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 +/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ +#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 + +/** APB_SARADC_ARB_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24) +/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 +/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 + +/** APB_SARADC_FILTER_CTRL0_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28) +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18 +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22 +/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ +#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S) +#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U +#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31 + +/** APB_SARADC_SAR1DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c) +/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ +#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S) +#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_S 0 + +/** APB_SARADC_SAR2DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30) +/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ +#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S) +#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_S 0 + +/** APB_SARADC_THRES0_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34) +/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18 + +/** APB_SARADC_THRES1_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38) +/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18 + +/** APB_SARADC_THRES_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c) +/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ +#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27 +/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ +#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S) +#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_EN_S 30 +/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ +#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S) +#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_EN_S 31 + +/** APB_SARADC_INT_ENA_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40) +/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31 + +/** APB_SARADC_INT_RAW_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44) +/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31 + +/** APB_SARADC_INT_ST_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48) +/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31 + +/** APB_SARADC_INT_CLR_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c) +/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31 + +/** APB_SARADC_DMA_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50) +/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 +/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) +#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U +#define APB_SARADC_APB_ADC_TRANS_S 31 + +/** APB_SARADC_CLKM_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54) +/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S) +#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_S 0 +/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ +#define APB_SARADC_CLKM_DIV_B 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S) +#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_S 8 +/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ +#define APB_SARADC_CLKM_DIV_A 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S) +#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_S 14 +/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; + * reg clk en + */ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) +#define APB_SARADC_CLK_EN_V 0x00000001U +#define APB_SARADC_CLK_EN_S 20 +/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ +#define APB_SARADC_CLK_SEL 0x00000003U +#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S) +#define APB_SARADC_CLK_SEL_V 0x00000003U +#define APB_SARADC_CLK_SEL_S 21 + +/** APB_SARADC_APB_TSENS_CTRL_REG register + * digital tsens configure register + */ +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58) +/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ +#define APB_SARADC_TSENS_OUT 0x000000FFU +#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S) +#define APB_SARADC_TSENS_OUT_V 0x000000FFU +#define APB_SARADC_TSENS_OUT_S 0 +/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ +#define APB_SARADC_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S) +#define APB_SARADC_TSENS_IN_INV_V 0x00000001U +#define APB_SARADC_TSENS_IN_INV_S 13 +/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ +#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S) +#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_S 14 +/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ +#define APB_SARADC_TSENS_PU (BIT(22)) +#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S) +#define APB_SARADC_TSENS_PU_V 0x00000001U +#define APB_SARADC_TSENS_PU_S 22 + +/** APB_SARADC_TSENS_CTRL2_REG register + * digital tsens configure register + */ +#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c) +/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; + * the time that power up tsens need wait + */ +#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFFU +#define APB_SARADC_TSENS_XPD_WAIT_M (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S) +#define APB_SARADC_TSENS_XPD_WAIT_V 0x00000FFFU +#define APB_SARADC_TSENS_XPD_WAIT_S 0 +/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0; + * force power up tsens + */ +#define APB_SARADC_TSENS_XPD_FORCE 0x00000003U +#define APB_SARADC_TSENS_XPD_FORCE_M (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S) +#define APB_SARADC_TSENS_XPD_FORCE_V 0x00000003U +#define APB_SARADC_TSENS_XPD_FORCE_S 12 +/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1; + * inv tsens clk + */ +#define APB_SARADC_TSENS_CLK_INV (BIT(14)) +#define APB_SARADC_TSENS_CLK_INV_M (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S) +#define APB_SARADC_TSENS_CLK_INV_V 0x00000001U +#define APB_SARADC_TSENS_CLK_INV_S 14 +/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ +#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) +#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U +#define APB_SARADC_TSENS_CLK_SEL_S 15 + +/** APB_SARADC_CALI_REG register + * digital saradc configure register + */ +#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60) +/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ +#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S) +#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_S 0 + +/** APB_TSENS_WAKE_REG register + * digital tsens configure register + */ +#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64) +/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ +#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S) +#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_S 0 +/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ +#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S) +#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_S 8 +/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ +#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16)) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16 +/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ +#define APB_SARADC_WAKEUP_MODE (BIT(17)) +#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S) +#define APB_SARADC_WAKEUP_MODE_V 0x00000001U +#define APB_SARADC_WAKEUP_MODE_S 17 +/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ +#define APB_SARADC_WAKEUP_EN (BIT(18)) +#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S) +#define APB_SARADC_WAKEUP_EN_V 0x00000001U +#define APB_SARADC_WAKEUP_EN_S 18 + +/** APB_TSENS_SAMPLE_REG register + * digital tsens configure register + */ +#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68) +/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ +#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S) +#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_S 0 +/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0; + * HW sample en + */ +#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16)) +#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S) +#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U +#define APB_SARADC_TSENS_SAMPLE_EN_S 16 + +/** APB_SARADC_CTRL_DATE_REG register + * version + */ +#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc) +/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; + * version + */ +#define APB_SARADC_DATE 0xFFFFFFFFU +#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) +#define APB_SARADC_DATE_V 0xFFFFFFFFU +#define APB_SARADC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/apb_saradc_struct.h b/components/soc/esp32h2/include/soc/apb_saradc_struct.h new file mode 100644 index 0000000000..11c8a8501a --- /dev/null +++ b/components/soc/esp32h2/include/soc/apb_saradc_struct.h @@ -0,0 +1,757 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Register */ +/** Type of saradc_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ + uint32_t saradc_saradc_start_force:1; + /** saradc_saradc_start : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ + uint32_t saradc_saradc_start:1; + uint32_t reserved_2:4; + /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ + uint32_t saradc_saradc_sar_clk_gated:1; + /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + uint32_t saradc_saradc_sar_clk_div:8; + /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ + uint32_t saradc_saradc_sar_patt_len:3; + uint32_t reserved_18:5; + /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + uint32_t saradc_saradc_sar_patt_p_clear:1; + uint32_t reserved_24:3; + /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ + uint32_t saradc_saradc_xpd_sar_force:2; + /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ + uint32_t saradc_saradc2_pwdet_drv:1; + /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ + uint32_t saradc_saradc_wait_arb_cycle:2; + }; + uint32_t val; +} apb_saradc_ctrl_reg_t; + +/** Type of saradc_ctrl2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ + uint32_t saradc_saradc_meas_num_limit:1; + /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ + uint32_t saradc_saradc_max_meas_num:8; + /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar1_inv:1; + /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar2_inv:1; + uint32_t reserved_11:1; + /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ + uint32_t saradc_saradc_timer_target:12; + /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ + uint32_t saradc_saradc_timer_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} apb_saradc_ctrl2_reg_t; + +/** Type of saradc_filter_ctrl1 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ + uint32_t saradc_apb_saradc_filter_factor1:3; + /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ + uint32_t saradc_apb_saradc_filter_factor0:3; + }; + uint32_t val; +} apb_saradc_filter_ctrl1_reg_t; + +/** Type of saradc_fsm_wait register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8; + * saradc_xpd_wait + */ + uint32_t saradc_saradc_xpd_wait:8; + /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8; + * saradc_rstb_wait + */ + uint32_t saradc_saradc_rstb_wait:8; + /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255; + * saradc_standby_wait + */ + uint32_t saradc_saradc_standby_wait:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_fsm_wait_reg_t; + +/** Type of saradc_sar1_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912; + * saradc1 status about data and channel + */ + uint32_t saradc_saradc_sar1_status:32; + }; + uint32_t val; +} apb_saradc_sar1_status_reg_t; + +/** Type of saradc_sar2_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912; + * saradc2 status about data and channel + */ + uint32_t saradc_saradc_sar2_status:32; + }; + uint32_t val; +} apb_saradc_sar2_status_reg_t; + +/** Type of saradc_sar_patt_tab1 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab1_reg_t; + +/** Type of saradc_sar_patt_tab2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab2_reg_t; + +/** Type of saradc_onetime_sample register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ + uint32_t saradc_saradc_onetime_atten:2; + /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ + uint32_t saradc_saradc_onetime_channel:4; + /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ + uint32_t saradc_saradc_onetime_start:1; + /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ + uint32_t saradc_saradc2_onetime_sample:1; + /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ + uint32_t saradc_saradc1_onetime_sample:1; + }; + uint32_t val; +} apb_saradc_onetime_sample_reg_t; + +/** Type of saradc_arb_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ + uint32_t saradc_adc_arb_apb_force:1; + /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ + uint32_t saradc_adc_arb_rtc_force:1; + /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ + uint32_t saradc_adc_arb_wifi_force:1; + /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ + uint32_t saradc_adc_arb_grant_force:1; + /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ + uint32_t saradc_adc_arb_apb_priority:2; + /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ + uint32_t saradc_adc_arb_rtc_priority:2; + /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ + uint32_t saradc_adc_arb_wifi_priority:2; + /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ + uint32_t saradc_adc_arb_fix_priority:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} apb_saradc_arb_ctrl_reg_t; + +/** Type of saradc_filter_ctrl0 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel1:4; + /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel0:4; + uint32_t reserved_26:5; + /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ + uint32_t saradc_apb_saradc_filter_reset:1; + }; + uint32_t val; +} apb_saradc_filter_ctrl0_reg_t; + +/** Type of saradc_sar1data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ + uint32_t saradc_apb_saradc1_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar1data_status_reg_t; + +/** Type of saradc_sar2data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ + uint32_t saradc_apb_saradc2_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar2data_status_reg_t; + +/** Type of saradc_thres0_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ + uint32_t saradc_apb_saradc_thres0_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_high:13; + /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres0_ctrl_reg_t; + +/** Type of saradc_thres1_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ + uint32_t saradc_apb_saradc_thres1_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_high:13; + /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres1_ctrl_reg_t; + +/** Type of saradc_thres_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ + uint32_t saradc_apb_saradc_thres_all_en:1; + uint32_t reserved_28:2; + /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ + uint32_t saradc_apb_saradc_thres1_en:1; + /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ + uint32_t saradc_apb_saradc_thres0_en:1; + }; + uint32_t val; +} apb_saradc_thres_ctrl_reg_t; + +/** Type of saradc_int_ena register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ + uint32_t saradc_apb_saradc_tsens_int_ena:1; + /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_low_int_ena:1; + /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_low_int_ena:1; + /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_high_int_ena:1; + /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_high_int_ena:1; + /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ + uint32_t saradc_apb_saradc2_done_int_ena:1; + /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ + uint32_t saradc_apb_saradc1_done_int_ena:1; + }; + uint32_t val; +} apb_saradc_int_ena_reg_t; + +/** Type of saradc_int_raw register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ + uint32_t saradc_apb_saradc_tsens_int_raw:1; + /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_low_int_raw:1; + /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_low_int_raw:1; + /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_high_int_raw:1; + /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_high_int_raw:1; + /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ + uint32_t saradc_apb_saradc2_done_int_raw:1; + /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ + uint32_t saradc_apb_saradc1_done_int_raw:1; + }; + uint32_t val; +} apb_saradc_int_raw_reg_t; + +/** Type of saradc_int_st register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ + uint32_t saradc_apb_saradc_tsens_int_st:1; + /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ + uint32_t saradc_apb_saradc_thres1_low_int_st:1; + /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ + uint32_t saradc_apb_saradc_thres0_low_int_st:1; + /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ + uint32_t saradc_apb_saradc_thres1_high_int_st:1; + /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ + uint32_t saradc_apb_saradc_thres0_high_int_st:1; + /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ + uint32_t saradc_apb_saradc2_done_int_st:1; + /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ + uint32_t saradc_apb_saradc1_done_int_st:1; + }; + uint32_t val; +} apb_saradc_int_st_reg_t; + +/** Type of saradc_int_clr register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ + uint32_t saradc_apb_saradc_tsens_int_clr:1; + /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_low_int_clr:1; + /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_low_int_clr:1; + /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_high_int_clr:1; + /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_high_int_clr:1; + /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ + uint32_t saradc_apb_saradc2_done_int_clr:1; + /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ + uint32_t saradc_apb_saradc1_done_int_clr:1; + }; + uint32_t val; +} apb_saradc_int_clr_reg_t; + +/** Type of saradc_dma_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ + uint32_t saradc_apb_adc_eof_num:16; + uint32_t reserved_16:14; + /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ + uint32_t saradc_apb_adc_reset_fsm:1; + /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ + uint32_t saradc_apb_adc_trans:1; + }; + uint32_t val; +} apb_saradc_dma_conf_reg_t; + +/** Type of saradc_clkm_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clk_en : R/W; bitpos: [20]; default: 0; + * reg clk en + */ + uint32_t saradc_clk_en:1; + /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ + uint32_t saradc_clk_sel:2; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_clkm_conf_reg_t; + +/** Type of saradc_apb_tsens_ctrl register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ + uint32_t saradc_tsens_out:8; + uint32_t reserved_8:5; + /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ + uint32_t saradc_tsens_in_inv:1; + /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ + uint32_t saradc_tsens_clk_div:8; + /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ + uint32_t saradc_tsens_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_apb_tsens_ctrl_reg_t; + +/** Type of saradc_tsens_ctrl2 register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2; + * the time that power up tsens need wait + */ + uint32_t saradc_tsens_xpd_wait:12; + /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0; + * force power up tsens + */ + uint32_t saradc_tsens_xpd_force:2; + /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1; + * inv tsens clk + */ + uint32_t saradc_tsens_clk_inv:1; + /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ + uint32_t saradc_tsens_clk_sel:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} apb_saradc_tsens_ctrl2_reg_t; + +/** Type of saradc_cali register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ + uint32_t saradc_apb_saradc_cali_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_cali_reg_t; + +/** Type of tsens_wake register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ + uint32_t saradc_wakeup_th_low:8; + /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ + uint32_t saradc_wakeup_th_high:8; + /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ + uint32_t saradc_wakeup_over_upper_th:1; + /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ + uint32_t saradc_wakeup_mode:1; + /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ + uint32_t saradc_wakeup_en:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} apb_tsens_wake_reg_t; + +/** Type of tsens_sample register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ + uint32_t saradc_tsens_sample_rate:16; + /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0; + * HW sample en + */ + uint32_t saradc_tsens_sample_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_tsens_sample_reg_t; + +/** Type of saradc_ctrl_date register + * version + */ +typedef union { + struct { + /** saradc_date : R/W; bitpos: [31:0]; default: 35676736; + * version + */ + uint32_t saradc_date:32; + }; + uint32_t val; +} apb_saradc_ctrl_date_reg_t; + + +typedef struct { + volatile apb_saradc_ctrl_reg_t saradc_ctrl; + volatile apb_saradc_ctrl2_reg_t saradc_ctrl2; + volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1; + volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait; + volatile apb_saradc_sar1_status_reg_t saradc_sar1_status; + volatile apb_saradc_sar2_status_reg_t saradc_sar2_status; + volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; + volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; + volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample; + volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl; + volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0; + volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status; + volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status; + volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl; + volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl; + volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl; + volatile apb_saradc_int_ena_reg_t saradc_int_ena; + volatile apb_saradc_int_raw_reg_t saradc_int_raw; + volatile apb_saradc_int_st_reg_t saradc_int_st; + volatile apb_saradc_int_clr_reg_t saradc_int_clr; + volatile apb_saradc_dma_conf_reg_t saradc_dma_conf; + volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; + volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2; + volatile apb_saradc_cali_reg_t saradc_cali; + volatile apb_tsens_wake_reg_t tsens_wake; + volatile apb_tsens_sample_reg_t tsens_sample; + uint32_t reserved_06c[228]; + volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date; +} apb_dev_t; + +extern apb_saradc_dev_t APB_SARADC; + +#ifndef __cplusplus +_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/assist_debug_reg.h b/components/soc/esp32h2/include/soc/assist_debug_reg.h new file mode 100644 index 0000000000..e77c2575d6 --- /dev/null +++ b/components/soc/esp32h2/include/soc/assist_debug_reg.h @@ -0,0 +1,778 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register + * core0 monitor enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor enable + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor enbale + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register + * core0 monitor interrupt status register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; + * DBUS busy monitor initerrupt status + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register + * core0 monitor interrupt enable register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt enbale + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register + * core0 monitor interrupt clr register + */ +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register + * core0 area pc status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) +/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register + * core0 area sp status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) +/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register + * stack min value + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) +/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register + * stack max value + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) +/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_PC_REG register + * stack monitor pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) +/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register + * record enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) +/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 + +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register2 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register3 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register + * exception monitor status register4 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register + * exception monitor status register5 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 + +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register6 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register7 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 +/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 + +/** ASSIST_DEBUG_CLOCK_GATE_REG register + * clock register + */ +#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78) +/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ +#define ASSIST_DEBUG_CLK_EN (BIT(0)) +#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) +#define ASSIST_DEBUG_CLK_EN_V 0x00000001U +#define ASSIST_DEBUG_CLK_EN_S 0 + +/** ASSIST_DEBUG_DATE_REG register + * version register + */ +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) +/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S) +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/assist_debug_struct.h b/components/soc/esp32h2/include/soc/assist_debug_struct.h new file mode 100644 index 0000000000..c03f579229 --- /dev/null +++ b/components/soc/esp32h2/include/soc/assist_debug_struct.h @@ -0,0 +1,717 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: monitor configuration registers */ +/** Type of core_0_intr_ena register + * core0 monitor enable configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ + uint32_t core_0_area_dram0_0_rd_ena:1; + /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ + uint32_t core_0_area_dram0_0_wr_ena:1; + /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ + uint32_t core_0_area_dram0_1_rd_ena:1; + /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ + uint32_t core_0_area_dram0_1_wr_ena:1; + /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ + uint32_t core_0_area_pif_0_rd_ena:1; + /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ + uint32_t core_0_area_pif_0_wr_ena:1; + /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ + uint32_t core_0_area_pif_1_rd_ena:1; + /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ + uint32_t core_0_area_pif_1_wr_ena:1; + /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ + uint32_t core_0_sp_spill_min_ena:1; + /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ + uint32_t core_0_sp_spill_max_ena:1; + /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor enable + */ + uint32_t core_0_iram0_exception_monitor_ena:1; + /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor enbale + */ + uint32_t core_0_dram0_exception_monitor_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_ena_reg_t; + +/** Type of core_0_area_dram0_0_min register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ + uint32_t core_0_area_dram0_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_min_reg_t; + +/** Type of core_0_area_dram0_0_max register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ + uint32_t core_0_area_dram0_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_max_reg_t; + +/** Type of core_0_area_dram0_1_min register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ + uint32_t core_0_area_dram0_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_min_reg_t; + +/** Type of core_0_area_dram0_1_max register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ + uint32_t core_0_area_dram0_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_max_reg_t; + +/** Type of core_0_area_pif_0_min register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ + uint32_t core_0_area_pif_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_min_reg_t; + +/** Type of core_0_area_pif_0_max register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ + uint32_t core_0_area_pif_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_max_reg_t; + +/** Type of core_0_area_pif_1_min register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ + uint32_t core_0_area_pif_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_min_reg_t; + +/** Type of core_0_area_pif_1_max register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ + uint32_t core_0_area_pif_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_max_reg_t; + +/** Type of core_0_area_pc register + * core0 area pc status register + */ +typedef union { + struct { + /** core_0_area_pc : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ + uint32_t core_0_area_pc:32; + }; + uint32_t val; +} assist_debug_core_0_area_pc_reg_t; + +/** Type of core_0_area_sp register + * core0 area sp status register + */ +typedef union { + struct { + /** core_0_area_sp : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ + uint32_t core_0_area_sp:32; + }; + uint32_t val; +} assist_debug_core_0_area_sp_reg_t; + +/** Type of core_0_sp_min register + * stack min value + */ +typedef union { + struct { + /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ + uint32_t core_0_sp_min:32; + }; + uint32_t val; +} assist_debug_core_0_sp_min_reg_t; + +/** Type of core_0_sp_max register + * stack max value + */ +typedef union { + struct { + /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ + uint32_t core_0_sp_max:32; + }; + uint32_t val; +} assist_debug_core_0_sp_max_reg_t; + +/** Type of core_0_sp_pc register + * stack monitor pc status register + */ +typedef union { + struct { + /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ + uint32_t core_0_sp_pc:32; + }; + uint32_t val; +} assist_debug_core_0_sp_pc_reg_t; + + +/** Group: interrupt configuration register */ +/** Type of core_0_intr_raw register + * core0 monitor interrupt status register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ + uint32_t core_0_area_dram0_0_rd_raw:1; + /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ + uint32_t core_0_area_dram0_0_wr_raw:1; + /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ + uint32_t core_0_area_dram0_1_rd_raw:1; + /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ + uint32_t core_0_area_dram0_1_wr_raw:1; + /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ + uint32_t core_0_area_pif_0_rd_raw:1; + /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ + uint32_t core_0_area_pif_0_wr_raw:1; + /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ + uint32_t core_0_area_pif_1_rd_raw:1; + /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ + uint32_t core_0_area_pif_1_wr_raw:1; + /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ + uint32_t core_0_sp_spill_min_raw:1; + /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ + uint32_t core_0_sp_spill_max_raw:1; + /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt status + */ + uint32_t core_0_iram0_exception_monitor_raw:1; + /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0; + * DBUS busy monitor initerrupt status + */ + uint32_t core_0_dram0_exception_monitor_raw:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_raw_reg_t; + +/** Type of core_0_intr_rls register + * core0 monitor interrupt enable register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_rd_rls:1; + /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_wr_rls:1; + /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_rd_rls:1; + /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_wr_rls:1; + /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ + uint32_t core_0_area_pif_0_rd_rls:1; + /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ + uint32_t core_0_area_pif_0_wr_rls:1; + /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ + uint32_t core_0_area_pif_1_rd_rls:1; + /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ + uint32_t core_0_area_pif_1_wr_rls:1; + /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_min_rls:1; + /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_max_rls:1; + /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt enable + */ + uint32_t core_0_iram0_exception_monitor_rls:1; + /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt enbale + */ + uint32_t core_0_dram0_exception_monitor_rls:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_rls_reg_t; + +/** Type of core_0_intr_clr register + * core0 monitor interrupt clr register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_rd_clr:1; + /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_wr_clr:1; + /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_rd_clr:1; + /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_wr_clr:1; + /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ + uint32_t core_0_area_pif_0_rd_clr:1; + /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ + uint32_t core_0_area_pif_0_wr_clr:1; + /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ + uint32_t core_0_area_pif_1_rd_clr:1; + /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ + uint32_t core_0_area_pif_1_wr_clr:1; + /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_min_clr:1; + /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_max_clr:1; + /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt clr + */ + uint32_t core_0_iram0_exception_monitor_clr:1; + /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt clr + */ + uint32_t core_0_dram0_exception_monitor_clr:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_clr_reg_t; + + +/** Group: pc reording configuration register */ +/** Type of core_0_rcd_en register + * record enable configuration register + */ +typedef union { + struct { + /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ + uint32_t core_0_rcd_recorden:1; + /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ + uint32_t core_0_rcd_pdebugen:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_rcd_en_reg_t; + + +/** Group: pc reording status register */ +/** Type of core_0_rcd_pdebugpc register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ + uint32_t core_0_rcd_pdebugpc:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugpc_reg_t; + +/** Type of core_0_rcd_pdebugsp register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ + uint32_t core_0_rcd_pdebugsp:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugsp_reg_t; + + +/** Group: exception monitor regsiter */ +/** Type of core_0_iram0_exception_monitor_0 register + * exception monitor status register0 + */ +typedef union { + struct { + /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_0 + */ + uint32_t core_0_iram0_recording_addr_0:24; + /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_0 + */ + uint32_t core_0_iram0_recording_wr_0:1; + /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_0 + */ + uint32_t core_0_iram0_recording_loadstore_0:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} assist_debug_core_0_iram0_exception_monitor_0_reg_t; + +/** Type of core_0_iram0_exception_monitor_1 register + * exception monitor status register1 + */ +typedef union { + struct { + /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_1 + */ + uint32_t core_0_iram0_recording_addr_1:24; + /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_1 + */ + uint32_t core_0_iram0_recording_wr_1:1; + /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_1 + */ + uint32_t core_0_iram0_recording_loadstore_1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} assist_debug_core_0_iram0_exception_monitor_1_reg_t; + +/** Type of core_0_dram0_exception_monitor_0 register + * exception monitor status register2 + */ +typedef union { + struct { + /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_0 + */ + uint32_t core_0_dram0_recording_addr_0:24; + /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_0 + */ + uint32_t core_0_dram0_recording_wr_0:1; + /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_0 + */ + uint32_t core_0_dram0_recording_byteen_0:4; + uint32_t reserved_29:3; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_0_reg_t; + +/** Type of core_0_dram0_exception_monitor_1 register + * exception monitor status register3 + */ +typedef union { + struct { + /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_0 + */ + uint32_t core_0_dram0_recording_pc_0:32; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_1_reg_t; + +/** Type of core_0_dram0_exception_monitor_2 register + * exception monitor status register4 + */ +typedef union { + struct { + /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_1 + */ + uint32_t core_0_dram0_recording_addr_1:24; + /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_1 + */ + uint32_t core_0_dram0_recording_wr_1:1; + /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_1 + */ + uint32_t core_0_dram0_recording_byteen_1:4; + uint32_t reserved_29:3; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_2_reg_t; + +/** Type of core_0_dram0_exception_monitor_3 register + * exception monitor status register5 + */ +typedef union { + struct { + /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_1 + */ + uint32_t core_0_dram0_recording_pc_1:32; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_3_reg_t; + +/** Type of core_x_iram0_dram0_exception_monitor_0 register + * exception monitor status register6 + */ +typedef union { + struct { + /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ + uint32_t core_x_iram0_dram0_limit_cycle_0:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t; + +/** Type of core_x_iram0_dram0_exception_monitor_1 register + * exception monitor status register7 + */ +typedef union { + struct { + /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ + uint32_t core_x_iram0_dram0_limit_cycle_1:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t; + + +/** Group: cpu status registers */ +/** Type of core_0_lastpc_before_exception register + * cpu status register + */ +typedef union { + struct { + /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ + uint32_t core_0_lastpc_before_exc:32; + }; + uint32_t val; +} assist_debug_core_0_lastpc_before_exception_reg_t; + +/** Type of core_0_debug_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_debug_mode : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ + uint32_t core_0_debug_mode:1; + /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ + uint32_t core_0_debug_module_active:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_debug_mode_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * clock register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_clock_gate_reg_t; + +/** Type of date register + * version register + */ +typedef union { + struct { + /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ + uint32_t assist_debug_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} assist_debug_date_reg_t; + + +typedef struct { + volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; + volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; + volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls; + volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; + volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; + volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; + volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; + volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; + volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; + volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; + volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0; + volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1; + volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0; + volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1; + volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2; + volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3; + volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0; + volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1; + volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; + volatile assist_debug_clock_gate_reg_t clock_gate; + uint32_t reserved_07c[224]; + volatile assist_debug_date_reg_t date; +} assist_debug_dev_t; + +extern assist_debug_dev_t ASSIST_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/boot_mode.h b/components/soc/esp32h2/include/soc/boot_mode.h new file mode 100644 index 0000000000..f782959272 --- /dev/null +++ b/components/soc/esp32h2/include/soc/boot_mode.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32h2/include/soc/cache_reg.h b/components/soc/esp32h2/include/soc/cache_reg.h new file mode 100644 index 0000000000..d811eda10a --- /dev/null +++ b/components/soc/esp32h2/include/soc/cache_reg.h @@ -0,0 +1,6235 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CACHE_L1_ICACHE_CTRL_REG register + * L1 instruction Cache(L1-ICache) control register + */ +#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0) +/** CACHE_L1_ICACHE_SHUT_IBUS0 : HRO; bitpos: [0]; default: 0; + * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + */ +#define CACHE_L1_ICACHE_SHUT_IBUS0 (BIT(0)) +#define CACHE_L1_ICACHE_SHUT_IBUS0_M (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S) +#define CACHE_L1_ICACHE_SHUT_IBUS0_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS0_S 0 +/** CACHE_L1_ICACHE_SHUT_IBUS1 : HRO; bitpos: [1]; default: 0; + * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + */ +#define CACHE_L1_ICACHE_SHUT_IBUS1 (BIT(1)) +#define CACHE_L1_ICACHE_SHUT_IBUS1_M (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S) +#define CACHE_L1_ICACHE_SHUT_IBUS1_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS1_S 1 +/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE_SHUT_IBUS2 (BIT(2)) +#define CACHE_L1_ICACHE_SHUT_IBUS2_M (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S) +#define CACHE_L1_ICACHE_SHUT_IBUS2_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS2_S 2 +/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE_SHUT_IBUS3 (BIT(3)) +#define CACHE_L1_ICACHE_SHUT_IBUS3_M (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S) +#define CACHE_L1_ICACHE_SHUT_IBUS3_V 0x00000001U +#define CACHE_L1_ICACHE_SHUT_IBUS3_S 3 +/** CACHE_L1_ICACHE_UNDEF_OP : HRO; bitpos: [7:4]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE_UNDEF_OP 0x0000000FU +#define CACHE_L1_ICACHE_UNDEF_OP_M (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S) +#define CACHE_L1_ICACHE_UNDEF_OP_V 0x0000000FU +#define CACHE_L1_ICACHE_UNDEF_OP_S 4 + +/** CACHE_L1_CACHE_CTRL_REG register + * L1 data Cache(L1-Cache) control register + */ +#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) +/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) +#define CACHE_L1_CACHE_SHUT_BUS0_M (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S) +#define CACHE_L1_CACHE_SHUT_BUS0_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS0_S 0 +/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) +#define CACHE_L1_CACHE_SHUT_BUS1_M (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S) +#define CACHE_L1_CACHE_SHUT_BUS1_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS1_S 1 +/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS2 (BIT(2)) +#define CACHE_L1_CACHE_SHUT_DBUS2_M (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S) +#define CACHE_L1_CACHE_SHUT_DBUS2_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS2_S 2 +/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS3 (BIT(3)) +#define CACHE_L1_CACHE_SHUT_DBUS3_M (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S) +#define CACHE_L1_CACHE_SHUT_DBUS3_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS3_S 3 +/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_DMA (BIT(4)) +#define CACHE_L1_CACHE_SHUT_DMA_M (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S) +#define CACHE_L1_CACHE_SHUT_DMA_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DMA_S 4 +/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [11:8]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_UNDEF_OP 0x0000000FU +#define CACHE_L1_CACHE_UNDEF_OP_M (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S) +#define CACHE_L1_CACHE_UNDEF_OP_V 0x0000000FU +#define CACHE_L1_CACHE_UNDEF_OP_S 8 + +/** CACHE_L1_BYPASS_CACHE_CONF_REG register + * Bypass Cache configure register + */ +#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8) +/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L1_ICACHE0_EN (BIT(0)) +#define CACHE_BYPASS_L1_ICACHE0_EN_M (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S) +#define CACHE_BYPASS_L1_ICACHE0_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE0_EN_S 0 +/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L1_ICACHE1_EN (BIT(1)) +#define CACHE_BYPASS_L1_ICACHE1_EN_M (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S) +#define CACHE_BYPASS_L1_ICACHE1_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE1_EN_S 1 +/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_BYPASS_L1_ICACHE2_EN (BIT(2)) +#define CACHE_BYPASS_L1_ICACHE2_EN_M (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S) +#define CACHE_BYPASS_L1_ICACHE2_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE2_EN_S 2 +/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_BYPASS_L1_ICACHE3_EN (BIT(3)) +#define CACHE_BYPASS_L1_ICACHE3_EN_M (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S) +#define CACHE_BYPASS_L1_ICACHE3_EN_V 0x00000001U +#define CACHE_BYPASS_L1_ICACHE3_EN_S 3 +/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0; + * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L1_DCACHE_EN (BIT(4)) +#define CACHE_BYPASS_L1_DCACHE_EN_M (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S) +#define CACHE_BYPASS_L1_DCACHE_EN_V 0x00000001U +#define CACHE_BYPASS_L1_DCACHE_EN_S 4 + +/** CACHE_L1_CACHE_ATOMIC_CONF_REG register + * L1 Cache atomic feature configure register + */ +#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc) +/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable atomic feature on L1-Cache when multiple cores access + * L1-Cache. 1: disable, 1: enable. + */ +#define CACHE_L1_CACHE_ATOMIC_EN (BIT(0)) +#define CACHE_L1_CACHE_ATOMIC_EN_M (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S) +#define CACHE_L1_CACHE_ATOMIC_EN_V 0x00000001U +#define CACHE_L1_CACHE_ATOMIC_EN_S 0 + +/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register + * L1 instruction Cache CacheSize mode configure register + */ +#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10) +/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_1K (BIT(0)) +#define CACHE_L1_ICACHE_CACHESIZE_1K_M (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S) +#define CACHE_L1_ICACHE_CACHESIZE_1K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_1K_S 0 +/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_2K (BIT(1)) +#define CACHE_L1_ICACHE_CACHESIZE_2K_M (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S) +#define CACHE_L1_ICACHE_CACHESIZE_2K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_2K_S 1 +/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_4K (BIT(2)) +#define CACHE_L1_ICACHE_CACHESIZE_4K_M (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S) +#define CACHE_L1_ICACHE_CACHESIZE_4K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_4K_S 2 +/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_8K (BIT(3)) +#define CACHE_L1_ICACHE_CACHESIZE_8K_M (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S) +#define CACHE_L1_ICACHE_CACHESIZE_8K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_8K_S 3 +/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_16K (BIT(4)) +#define CACHE_L1_ICACHE_CACHESIZE_16K_M (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S) +#define CACHE_L1_ICACHE_CACHESIZE_16K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_16K_S 4 +/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_32K (BIT(5)) +#define CACHE_L1_ICACHE_CACHESIZE_32K_M (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S) +#define CACHE_L1_ICACHE_CACHESIZE_32K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_32K_S 5 +/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_64K (BIT(6)) +#define CACHE_L1_ICACHE_CACHESIZE_64K_M (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S) +#define CACHE_L1_ICACHE_CACHESIZE_64K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_64K_S 6 +/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_128K (BIT(7)) +#define CACHE_L1_ICACHE_CACHESIZE_128K_M (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S) +#define CACHE_L1_ICACHE_CACHESIZE_128K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_128K_S 7 +/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_256K (BIT(8)) +#define CACHE_L1_ICACHE_CACHESIZE_256K_M (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S) +#define CACHE_L1_ICACHE_CACHESIZE_256K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_256K_S 8 +/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_512K (BIT(9)) +#define CACHE_L1_ICACHE_CACHESIZE_512K_M (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S) +#define CACHE_L1_ICACHE_CACHESIZE_512K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_512K_S 9 +/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_1024K (BIT(10)) +#define CACHE_L1_ICACHE_CACHESIZE_1024K_M (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S) +#define CACHE_L1_ICACHE_CACHESIZE_1024K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_1024K_S 10 +/** CACHE_L1_ICACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2048k bytes. This field + * and all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_2048K (BIT(11)) +#define CACHE_L1_ICACHE_CACHESIZE_2048K_M (CACHE_L1_ICACHE_CACHESIZE_2048K_V << CACHE_L1_ICACHE_CACHESIZE_2048K_S) +#define CACHE_L1_ICACHE_CACHESIZE_2048K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_2048K_S 11 +/** CACHE_L1_ICACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4096k bytes. This field + * and all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_CACHESIZE_4096K (BIT(12)) +#define CACHE_L1_ICACHE_CACHESIZE_4096K_M (CACHE_L1_ICACHE_CACHESIZE_4096K_V << CACHE_L1_ICACHE_CACHESIZE_4096K_S) +#define CACHE_L1_ICACHE_CACHESIZE_4096K_V 0x00000001U +#define CACHE_L1_ICACHE_CACHESIZE_4096K_S 12 + +/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register + * L1 instruction Cache BlockSize mode configure register + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14) +/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_8 (BIT(0)) +#define CACHE_L1_ICACHE_BLOCKSIZE_8_M (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_8_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_8_S 0 +/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_16 (BIT(1)) +#define CACHE_L1_ICACHE_BLOCKSIZE_16_M (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_16_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_16_S 1 +/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_32 (BIT(2)) +#define CACHE_L1_ICACHE_BLOCKSIZE_32_M (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_32_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_32_S 2 +/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_64 (BIT(3)) +#define CACHE_L1_ICACHE_BLOCKSIZE_64_M (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_64_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_64_S 3 +/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_128 (BIT(4)) +#define CACHE_L1_ICACHE_BLOCKSIZE_128_M (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_128_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_128_S 4 +/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_ICACHE_BLOCKSIZE_256 (BIT(5)) +#define CACHE_L1_ICACHE_BLOCKSIZE_256_M (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S) +#define CACHE_L1_ICACHE_BLOCKSIZE_256_V 0x00000001U +#define CACHE_L1_ICACHE_BLOCKSIZE_256_S 5 + +/** CACHE_L1_CACHE_CACHESIZE_CONF_REG register + * L1 data Cache CacheSize mode configure register + */ +#define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18) +/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_1K (BIT(0)) +#define CACHE_L1_CACHE_CACHESIZE_1K_M (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S) +#define CACHE_L1_CACHE_CACHESIZE_1K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_1K_S 0 +/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_2K (BIT(1)) +#define CACHE_L1_CACHE_CACHESIZE_2K_M (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S) +#define CACHE_L1_CACHE_CACHESIZE_2K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_2K_S 1 +/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_4K (BIT(2)) +#define CACHE_L1_CACHE_CACHESIZE_4K_M (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S) +#define CACHE_L1_CACHE_CACHESIZE_4K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_4K_S 2 +/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_8K (BIT(3)) +#define CACHE_L1_CACHE_CACHESIZE_8K_M (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S) +#define CACHE_L1_CACHE_CACHESIZE_8K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_8K_S 3 +/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 1; + * The field is used to configure cachesize of L1-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_16K (BIT(4)) +#define CACHE_L1_CACHE_CACHESIZE_16K_M (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S) +#define CACHE_L1_CACHE_CACHESIZE_16K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_16K_S 4 +/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_32K (BIT(5)) +#define CACHE_L1_CACHE_CACHESIZE_32K_M (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S) +#define CACHE_L1_CACHE_CACHESIZE_32K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_32K_S 5 +/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_64K (BIT(6)) +#define CACHE_L1_CACHE_CACHESIZE_64K_M (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S) +#define CACHE_L1_CACHE_CACHESIZE_64K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_64K_S 6 +/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_128K (BIT(7)) +#define CACHE_L1_CACHE_CACHESIZE_128K_M (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S) +#define CACHE_L1_CACHE_CACHESIZE_128K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_128K_S 7 +/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_256K (BIT(8)) +#define CACHE_L1_CACHE_CACHESIZE_256K_M (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S) +#define CACHE_L1_CACHE_CACHESIZE_256K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_256K_S 8 +/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_512K (BIT(9)) +#define CACHE_L1_CACHE_CACHESIZE_512K_M (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S) +#define CACHE_L1_CACHE_CACHESIZE_512K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_512K_S 9 +/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_1024K (BIT(10)) +#define CACHE_L1_CACHE_CACHESIZE_1024K_M (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S) +#define CACHE_L1_CACHE_CACHESIZE_1024K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_1024K_S 10 +/** CACHE_L1_CACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_2048K (BIT(11)) +#define CACHE_L1_CACHE_CACHESIZE_2048K_M (CACHE_L1_CACHE_CACHESIZE_2048K_V << CACHE_L1_CACHE_CACHESIZE_2048K_S) +#define CACHE_L1_CACHE_CACHESIZE_2048K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_2048K_S 11 +/** CACHE_L1_CACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_CACHESIZE_4096K (BIT(12)) +#define CACHE_L1_CACHE_CACHESIZE_4096K_M (CACHE_L1_CACHE_CACHESIZE_4096K_V << CACHE_L1_CACHE_CACHESIZE_4096K_S) +#define CACHE_L1_CACHE_CACHESIZE_4096K_V 0x00000001U +#define CACHE_L1_CACHE_CACHESIZE_4096K_S 12 + +/** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register + * L1 data Cache BlockSize mode configure register + */ +#define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c) +/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_8 (BIT(0)) +#define CACHE_L1_CACHE_BLOCKSIZE_8_M (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S) +#define CACHE_L1_CACHE_BLOCKSIZE_8_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_8_S 0 +/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_16 (BIT(1)) +#define CACHE_L1_CACHE_BLOCKSIZE_16_M (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S) +#define CACHE_L1_CACHE_BLOCKSIZE_16_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_16_S 1 +/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1; + * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_32 (BIT(2)) +#define CACHE_L1_CACHE_BLOCKSIZE_32_M (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S) +#define CACHE_L1_CACHE_BLOCKSIZE_32_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_32_S 2 +/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_64 (BIT(3)) +#define CACHE_L1_CACHE_BLOCKSIZE_64_M (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S) +#define CACHE_L1_CACHE_BLOCKSIZE_64_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_64_S 3 +/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_128 (BIT(4)) +#define CACHE_L1_CACHE_BLOCKSIZE_128_M (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S) +#define CACHE_L1_CACHE_BLOCKSIZE_128_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_128_S 4 +/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L1_CACHE_BLOCKSIZE_256 (BIT(5)) +#define CACHE_L1_CACHE_BLOCKSIZE_256_M (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S) +#define CACHE_L1_CACHE_BLOCKSIZE_256_V 0x00000001U +#define CACHE_L1_CACHE_BLOCKSIZE_256_S 5 + +/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) +/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to enable L1-ICache0 wrap around mode. + */ +#define CACHE_L1_ICACHE0_WRAP (BIT(0)) +#define CACHE_L1_ICACHE0_WRAP_M (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S) +#define CACHE_L1_ICACHE0_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE0_WRAP_S 0 +/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to enable L1-ICache1 wrap around mode. + */ +#define CACHE_L1_ICACHE1_WRAP (BIT(1)) +#define CACHE_L1_ICACHE1_WRAP_M (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S) +#define CACHE_L1_ICACHE1_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE1_WRAP_S 1 +/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_WRAP (BIT(2)) +#define CACHE_L1_ICACHE2_WRAP_M (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S) +#define CACHE_L1_ICACHE2_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE2_WRAP_S 2 +/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_WRAP (BIT(3)) +#define CACHE_L1_ICACHE3_WRAP_M (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S) +#define CACHE_L1_ICACHE3_WRAP_V 0x00000001U +#define CACHE_L1_ICACHE3_WRAP_S 3 +/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ +#define CACHE_L1_CACHE_WRAP (BIT(4)) +#define CACHE_L1_CACHE_WRAP_M (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S) +#define CACHE_L1_CACHE_WRAP_V 0x00000001U +#define CACHE_L1_CACHE_WRAP_S 4 + +/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register + * Cache tag memory power control register + */ +#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24) +/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, + * 0: open clock gating. + */ +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON (BIT(0)) +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S 0 +/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD (BIT(1)) +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S 1 +/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU (BIT(2)) +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S 2 +/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, + * 0: open clock gating. + */ +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON (BIT(4)) +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S 4 +/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD (BIT(5)) +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S 5 +/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU (BIT(6)) +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S 6 +/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON (BIT(8)) +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S 8 +/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD (BIT(9)) +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S 9 +/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU (BIT(10)) +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S 10 +/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON (BIT(12)) +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S 12 +/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD (BIT(13)) +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S 13 +/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU (BIT(14)) +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S 14 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M (CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S 16 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M (CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S 17 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M (CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register + * Cache data memory power control register + */ +#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28) +/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, + * 0: open clock gating. + */ +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON (BIT(0)) +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S 0 +/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD (BIT(1)) +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S 1 +/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU (BIT(2)) +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S 2 +/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, + * 0: open clock gating. + */ +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON (BIT(4)) +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S 4 +/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD (BIT(5)) +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S 5 +/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU (BIT(6)) +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S 6 +/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON (BIT(8)) +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S 8 +/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD (BIT(9)) +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S 9 +/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU (BIT(10)) +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S 10 +/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON (BIT(12)) +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S 12 +/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD (BIT(13)) +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S 13 +/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU (BIT(14)) +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S 14 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M (CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S 16 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M (CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S 17 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M (CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S 18 + +/** CACHE_L1_CACHE_FREEZE_CTRL_REG register + * Cache Freeze control register + */ +#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c) +/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by + * software. + */ +#define CACHE_L1_ICACHE0_FREEZE_EN (BIT(0)) +#define CACHE_L1_ICACHE0_FREEZE_EN_M (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S) +#define CACHE_L1_ICACHE0_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_FREEZE_EN_S 0 +/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_ICACHE0_FREEZE_MODE (BIT(1)) +#define CACHE_L1_ICACHE0_FREEZE_MODE_M (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S) +#define CACHE_L1_ICACHE0_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE0_FREEZE_MODE_S 1 +/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE0_FREEZE_DONE (BIT(2)) +#define CACHE_L1_ICACHE0_FREEZE_DONE_M (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S) +#define CACHE_L1_ICACHE0_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE0_FREEZE_DONE_S 2 +/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0; + * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by + * software. + */ +#define CACHE_L1_ICACHE1_FREEZE_EN (BIT(4)) +#define CACHE_L1_ICACHE1_FREEZE_EN_M (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S) +#define CACHE_L1_ICACHE1_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_FREEZE_EN_S 4 +/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_ICACHE1_FREEZE_MODE (BIT(5)) +#define CACHE_L1_ICACHE1_FREEZE_MODE_M (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S) +#define CACHE_L1_ICACHE1_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE1_FREEZE_MODE_S 5 +/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE1_FREEZE_DONE (BIT(6)) +#define CACHE_L1_ICACHE1_FREEZE_DONE_M (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S) +#define CACHE_L1_ICACHE1_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE1_FREEZE_DONE_S 6 +/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FREEZE_EN (BIT(8)) +#define CACHE_L1_ICACHE2_FREEZE_EN_M (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S) +#define CACHE_L1_ICACHE2_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_FREEZE_EN_S 8 +/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FREEZE_MODE (BIT(9)) +#define CACHE_L1_ICACHE2_FREEZE_MODE_M (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S) +#define CACHE_L1_ICACHE2_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE2_FREEZE_MODE_S 9 +/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FREEZE_DONE (BIT(10)) +#define CACHE_L1_ICACHE2_FREEZE_DONE_M (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S) +#define CACHE_L1_ICACHE2_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE2_FREEZE_DONE_S 10 +/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FREEZE_EN (BIT(12)) +#define CACHE_L1_ICACHE3_FREEZE_EN_M (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S) +#define CACHE_L1_ICACHE3_FREEZE_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_FREEZE_EN_S 12 +/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FREEZE_MODE (BIT(13)) +#define CACHE_L1_ICACHE3_FREEZE_MODE_M (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S) +#define CACHE_L1_ICACHE3_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_ICACHE3_FREEZE_MODE_S 13 +/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FREEZE_DONE (BIT(14)) +#define CACHE_L1_ICACHE3_FREEZE_DONE_M (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S) +#define CACHE_L1_ICACHE3_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_ICACHE3_FREEZE_DONE_S 14 +/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ +#define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) +#define CACHE_L1_CACHE_FREEZE_EN_M (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S) +#define CACHE_L1_CACHE_FREEZE_EN_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_EN_S 16 +/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) +#define CACHE_L1_CACHE_FREEZE_MODE_M (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S) +#define CACHE_L1_CACHE_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_MODE_S 17 +/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) +#define CACHE_L1_CACHE_FREEZE_DONE_M (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S) +#define CACHE_L1_CACHE_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_DONE_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register + * Cache data memory access configure register + */ +#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) +/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN (BIT(0)) +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S 0 +/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, + * 1: enable. + */ +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN (BIT(1)) +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S 1 +/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN (BIT(4)) +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S 4 +/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, + * 1: enable. + */ +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN (BIT(5)) +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S 5 +/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN (BIT(8)) +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S 8 +/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN (BIT(9)) +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S 9 +/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN (BIT(12)) +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S) +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S 12 +/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN (BIT(13)) +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S) +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S 13 +/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 + +/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register + * Cache tag memory access configure register + */ +#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34) +/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN (BIT(0)) +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S 0 +/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN (BIT(1)) +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S 1 +/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN (BIT(4)) +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S 4 +/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN (BIT(5)) +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S 5 +/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN (BIT(8)) +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S 8 +/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN (BIT(9)) +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S 9 +/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN (BIT(12)) +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S) +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S 12 +/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN (BIT(13)) +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S) +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S 13 +/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 + +/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register + * L1 instruction Cache 0 prelock configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38) +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache0 prelock. + */ +#define CACHE_L1_ICACHE0_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOCK_RGID_M (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE0_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 0 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c) +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 0 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40) +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 0 prelock section size configure register + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44) +/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register + * L1 instruction Cache 1 prelock configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48) +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache1 prelock. + */ +#define CACHE_L1_ICACHE1_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOCK_RGID_M (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE1_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 1 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c) +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 1 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50) +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 1 prelock section size configure register + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54) +/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register + * L1 instruction Cache 2 prelock configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58) +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache2 prelock. + */ +#define CACHE_L1_ICACHE2_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOCK_RGID_M (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE2_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 2 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c) +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 2 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60) +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 2 prelock section size configure register + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64) +/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register + * L1 instruction Cache 3 prelock configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68) +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache3 prelock. + */ +#define CACHE_L1_ICACHE3_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOCK_RGID_M (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S) +#define CACHE_L1_ICACHE3_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOCK_RGID_S 2 + +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register + * L1 instruction Cache 3 prelock section0 address configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c) +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register + * L1 instruction Cache 3 prelock section1 address configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70) +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register + * L1 instruction Cache 3 prelock section size configure register + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74) +/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L1_CACHE_PRELOCK_CONF_REG register + * L1 Cache prelock configure register + */ +#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78) +/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ +#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_M (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S) +#define CACHE_L1_CACHE_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 + +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register + * L1 Cache prelock section0 address configure register + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register + * L1 Cache prelock section1 address configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80) +/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register + * L1 Cache prelock section size configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84) +/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_LOCK_CTRL_REG register + * Lock-class (manual lock) operation control register + */ +#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88) +/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ +#define CACHE_LOCK_ENA (BIT(0)) +#define CACHE_LOCK_ENA_M (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S) +#define CACHE_LOCK_ENA_V 0x00000001U +#define CACHE_LOCK_ENA_S 0 +/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ +#define CACHE_UNLOCK_ENA (BIT(1)) +#define CACHE_UNLOCK_ENA_M (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S) +#define CACHE_UNLOCK_ENA_V 0x00000001U +#define CACHE_UNLOCK_ENA_S 1 +/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ +#define CACHE_LOCK_DONE (BIT(2)) +#define CACHE_LOCK_DONE_M (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S) +#define CACHE_LOCK_DONE_V 0x00000001U +#define CACHE_LOCK_DONE_S 2 +/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ +#define CACHE_LOCK_RGID 0x0000000FU +#define CACHE_LOCK_RGID_M (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S) +#define CACHE_LOCK_RGID_V 0x0000000FU +#define CACHE_LOCK_RGID_S 3 + +/** CACHE_LOCK_MAP_REG register + * Lock (manual lock) map configure register + */ +#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c) +/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ +#define CACHE_LOCK_MAP 0x0000003FU +#define CACHE_LOCK_MAP_M (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S) +#define CACHE_LOCK_MAP_V 0x0000003FU +#define CACHE_LOCK_MAP_S 0 + +/** CACHE_LOCK_ADDR_REG register + * Lock (manual lock) address configure register + */ +#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90) +/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ +#define CACHE_LOCK_ADDR 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_M (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S) +#define CACHE_LOCK_ADDR_V 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_S 0 + +/** CACHE_LOCK_SIZE_REG register + * Lock (manual lock) size configure register + */ +#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94) +/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ +#define CACHE_LOCK_SIZE 0x0000FFFFU +#define CACHE_LOCK_SIZE_M (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S) +#define CACHE_LOCK_SIZE_V 0x0000FFFFU +#define CACHE_LOCK_SIZE_S 0 + +/** CACHE_SYNC_CTRL_REG register + * Sync-class operation control register + */ +#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98) +/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_INVALIDATE_ENA (BIT(0)) +#define CACHE_INVALIDATE_ENA_M (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S) +#define CACHE_INVALIDATE_ENA_V 0x00000001U +#define CACHE_INVALIDATE_ENA_S 0 +/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ +#define CACHE_CLEAN_ENA (BIT(1)) +#define CACHE_CLEAN_ENA_M (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S) +#define CACHE_CLEAN_ENA_V 0x00000001U +#define CACHE_CLEAN_ENA_S 1 +/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_ENA (BIT(2)) +#define CACHE_WRITEBACK_ENA_M (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S) +#define CACHE_WRITEBACK_ENA_V 0x00000001U +#define CACHE_WRITEBACK_ENA_S 2 +/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define CACHE_WRITEBACK_INVALIDATE_ENA_M (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S) +#define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x00000001U +#define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ +#define CACHE_SYNC_DONE (BIT(4)) +#define CACHE_SYNC_DONE_M (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S) +#define CACHE_SYNC_DONE_V 0x00000001U +#define CACHE_SYNC_DONE_S 4 +/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ +#define CACHE_SYNC_RGID 0x0000000FU +#define CACHE_SYNC_RGID_M (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S) +#define CACHE_SYNC_RGID_V 0x0000000FU +#define CACHE_SYNC_RGID_S 5 + +/** CACHE_SYNC_MAP_REG register + * Sync map configure register + */ +#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c) +/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ +#define CACHE_SYNC_MAP 0x0000003FU +#define CACHE_SYNC_MAP_M (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S) +#define CACHE_SYNC_MAP_V 0x0000003FU +#define CACHE_SYNC_MAP_S 0 + +/** CACHE_SYNC_ADDR_REG register + * Sync address configure register + */ +#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0) +/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ +#define CACHE_SYNC_ADDR 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_M (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S) +#define CACHE_SYNC_ADDR_V 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_S 0 + +/** CACHE_SYNC_SIZE_REG register + * Sync size configure register + */ +#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4) +/** CACHE_SYNC_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ +#define CACHE_SYNC_SIZE 0x00FFFFFFU +#define CACHE_SYNC_SIZE_M (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S) +#define CACHE_SYNC_SIZE_V 0x00FFFFFFU +#define CACHE_SYNC_SIZE_S 0 + +/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register + * L1 instruction Cache 0 preload-operation control register + */ +#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8) +/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache0. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE0_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_PRELOAD_ENA_M (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE0_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE0_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE0_PRELOAD_DONE_M (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE0_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE0_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache0 preload. + */ +#define CACHE_L1_ICACHE0_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOAD_RGID_M (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE0_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE0_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register + * L1 instruction Cache 0 preload address configure register + */ +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac) +/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE0_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register + * L1 instruction Cache 0 preload size configure register + */ +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0) +/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE0_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register + * L1 instruction Cache 1 preload-operation control register + */ +#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4) +/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache1. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE1_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE1_PRELOAD_ENA_M (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE1_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE1_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE1_PRELOAD_DONE_M (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE1_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE1_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache1 preload. + */ +#define CACHE_L1_ICACHE1_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOAD_RGID_M (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE1_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE1_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register + * L1 instruction Cache 1 preload address configure register + */ +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8) +/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE1_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register + * L1 instruction Cache 1 preload size configure register + */ +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc) +/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE1_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register + * L1 instruction Cache 2 preload-operation control register + */ +#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0) +/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache2. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE2_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE2_PRELOAD_ENA_M (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE2_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE2_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE2_PRELOAD_DONE_M (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE2_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE2_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache2 preload. + */ +#define CACHE_L1_ICACHE2_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOAD_RGID_M (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE2_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE2_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register + * L1 instruction Cache 2 preload address configure register + */ +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4) +/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE2_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register + * L1 instruction Cache 2 preload size configure register + */ +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8) +/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE2_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register + * L1 instruction Cache 3 preload-operation control register + */ +#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc) +/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache3. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_ICACHE3_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE3_PRELOAD_ENA_M (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S) +#define CACHE_L1_ICACHE3_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOAD_ENA_S 0 +/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_ICACHE3_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE3_PRELOAD_DONE_M (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S) +#define CACHE_L1_ICACHE3_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOAD_DONE_S 1 +/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_ICACHE3_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S) +#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S 2 +/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache3 preload. + */ +#define CACHE_L1_ICACHE3_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOAD_RGID_M (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S) +#define CACHE_L1_ICACHE3_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE3_PRELOAD_RGID_S 3 + +/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register + * L1 instruction Cache 3 preload address configure register + */ +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0) +/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + */ +#define CACHE_L1_ICACHE3_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S) +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S 0 + +/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register + * L1 instruction Cache 3 preload size configure register + */ +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4) +/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + */ +#define CACHE_L1_ICACHE3_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S) +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S 0 + +/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register + * L1 Cache preload-operation control register + */ +#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8) +/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_PRELOAD_ENA_M (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S) +#define CACHE_L1_CACHE_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ENA_S 0 +/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_PRELOAD_DONE_M (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S) +#define CACHE_L1_CACHE_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_DONE_S 1 +/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_PRELOAD_ORDER_M (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S) +#define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 +/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ +#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_M (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S) +#define CACHE_L1_CACHE_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 + +/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register + * L1 Cache preload address configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc) +/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_M (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S) +#define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register + * L1 Cache preload size configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0) +/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_M (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S) +#define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 0 autoload-operation control register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4) +/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache0. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache0. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache0 autoload. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 0 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 0 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 0 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 0 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4) +/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 1 autoload-operation control register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8) +/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache1. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache1. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache1 autoload. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 1 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 1 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 1 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 1 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108) +/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 2 autoload-operation control register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c) +/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache2. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache2. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache2 autoload. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 2 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 2 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 2 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 2 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c) +/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register + * L1 instruction Cache 3 autoload-operation control register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120) +/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, + * 0: disable. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S 0 +/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S 1 +/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache3. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache3. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache3 autoload. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S 10 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register + * L1 instruction Cache 3 autoload section 0 address configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register + * L1 instruction Cache 3 autoload section 0 size configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register + * L1 instruction Cache 3 autoload section 1 address configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register + * L1 instruction Cache 3 autoload section 1 size configure register + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130) +/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register + * L1 Cache autoload-operation control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134) +/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_M (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 +/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_M (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 +/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S 10 +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S 11 +/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l1 cache autoload. + */ +#define CACHE_L1_CACHE_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L1_CACHE_AUTOLOAD_RGID_M (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S) +#define CACHE_L1_CACHE_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_AUTOLOAD_RGID_S 12 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register + * L1 Cache autoload section 0 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register + * L1 Cache autoload section 0 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register + * L1 Cache autoload section 1 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register + * L1 Cache autoload section 1 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register + * L1 Cache autoload section 2 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148) +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register + * L1 Cache autoload section 2 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c) +/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register + * L1 Cache autoload section 1 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150) +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register + * L1 Cache autoload section 1 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154) +/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S 0 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register + * Cache Access Counter Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158) +/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_ENA (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_ENA_M (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S) +#define CACHE_L1_IBUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_ENA_S 0 +/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_ENA (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_ENA_M (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S) +#define CACHE_L1_IBUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_ENA_S 1 +/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_OVF_INT_ENA (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_ENA_M (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S) +#define CACHE_L1_IBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_ENA_S 2 +/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_OVF_INT_ENA (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_ENA_M (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S) +#define CACHE_L1_IBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_ENA_S 3 +/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ENA_M (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S) +#define CACHE_L1_BUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ENA_S 4 +/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ENA_M (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S) +#define CACHE_L1_BUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ENA_S 5 +/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_OVF_INT_ENA (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_ENA_M (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S) +#define CACHE_L1_DBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_ENA_S 6 +/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_OVF_INT_ENA (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_ENA_M (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S) +#define CACHE_L1_DBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_ENA_S 7 + +/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register + * Cache Access Counter Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c) +/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due + * to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_CLR (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_CLR_M (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S) +#define CACHE_L1_IBUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_CLR_S 0 +/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due + * to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_CLR (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_CLR_M (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S) +#define CACHE_L1_IBUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_CLR_S 1 +/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_OVF_INT_CLR (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_CLR_M (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S) +#define CACHE_L1_IBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_CLR_S 2 +/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_OVF_INT_CLR (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_CLR_M (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S) +#define CACHE_L1_IBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_CLR_S 3 +/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_CLR_M (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S) +#define CACHE_L1_BUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_CLR_S 4 +/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_CLR_M (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S) +#define CACHE_L1_BUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_CLR_S 5 +/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_OVF_INT_CLR (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_CLR_M (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S) +#define CACHE_L1_DBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_CLR_S 6 +/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_OVF_INT_CLR (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_CLR_M (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S) +#define CACHE_L1_DBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_CLR_S 7 + +/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register + * Cache Access Counter Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160) +/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 + * due to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_RAW (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_RAW_M (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S) +#define CACHE_L1_IBUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_RAW_S 0 +/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 + * due to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_RAW (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_RAW_M (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S) +#define CACHE_L1_IBUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_RAW_S 1 +/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 + * due to bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_OVF_INT_RAW (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_RAW_M (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S) +#define CACHE_L1_IBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_RAW_S 2 +/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 + * due to bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_OVF_INT_RAW (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_RAW_M (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S) +#define CACHE_L1_IBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_RAW_S 3 +/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_RAW_M (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S) +#define CACHE_L1_BUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_RAW_S 4 +/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_RAW_M (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S) +#define CACHE_L1_BUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_RAW_S 5 +/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_OVF_INT_RAW (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_RAW_M (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S) +#define CACHE_L1_DBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_RAW_S 6 +/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_OVF_INT_RAW (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_RAW_M (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S) +#define CACHE_L1_DBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_RAW_S 7 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register + * Cache Access Counter Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164) +/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_OVF_INT_ST (BIT(0)) +#define CACHE_L1_IBUS0_OVF_INT_ST_M (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S) +#define CACHE_L1_IBUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS0_OVF_INT_ST_S 0 +/** CACHE_L1_IBUS1_OVF_INT_ST : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_OVF_INT_ST (BIT(1)) +#define CACHE_L1_IBUS1_OVF_INT_ST_M (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S) +#define CACHE_L1_IBUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS1_OVF_INT_ST_S 1 +/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_OVF_INT_ST (BIT(2)) +#define CACHE_L1_IBUS2_OVF_INT_ST_M (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S) +#define CACHE_L1_IBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS2_OVF_INT_ST_S 2 +/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_OVF_INT_ST (BIT(3)) +#define CACHE_L1_IBUS3_OVF_INT_ST_M (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S) +#define CACHE_L1_IBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_IBUS3_OVF_INT_ST_S 3 +/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ST_M (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S) +#define CACHE_L1_BUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ST_S 4 +/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ST_M (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S) +#define CACHE_L1_BUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ST_S 5 +/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_OVF_INT_ST (BIT(6)) +#define CACHE_L1_DBUS2_OVF_INT_ST_M (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S) +#define CACHE_L1_DBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_DBUS2_OVF_INT_ST_S 6 +/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_OVF_INT_ST (BIT(7)) +#define CACHE_L1_DBUS3_OVF_INT_ST_M (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S) +#define CACHE_L1_DBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_DBUS3_OVF_INT_ST_S 7 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register + * Cache Access Fail Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168) +/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_ENA (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FAIL_INT_ENA (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FAIL_INT_ENA (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S) +#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S 3 +/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ENA_M (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S) +#define CACHE_L1_CACHE_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register + * L1-Cache Access Fail Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c) +/** CACHE_L1_ICACHE0_FAIL_INT_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FAIL_INT_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FAIL_INT_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S) +#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S 3 +/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_CLR_M (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S) +#define CACHE_L1_CACHE_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register + * Cache Access Fail Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170) +/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache0. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_RAW (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache1. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_RAW (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache2. + */ +#define CACHE_L1_ICACHE2_FAIL_INT_RAW (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache3. + */ +#define CACHE_L1_ICACHE3_FAIL_INT_RAW (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S) +#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S 3 +/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_RAW_M (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S) +#define CACHE_L1_CACHE_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register + * Cache Access Fail Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174) +/** CACHE_L1_ICACHE0_FAIL_INT_ST : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due + * to cpu accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_INT_ST (BIT(0)) +#define CACHE_L1_ICACHE0_FAIL_INT_ST_M (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE0_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE0_FAIL_INT_ST_S 0 +/** CACHE_L1_ICACHE1_FAIL_INT_ST : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due + * to cpu accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_INT_ST (BIT(1)) +#define CACHE_L1_ICACHE1_FAIL_INT_ST_M (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE1_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE1_FAIL_INT_ST_S 1 +/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_FAIL_INT_ST (BIT(2)) +#define CACHE_L1_ICACHE2_FAIL_INT_ST_M (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE2_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE2_FAIL_INT_ST_S 2 +/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_FAIL_INT_ST (BIT(3)) +#define CACHE_L1_ICACHE3_FAIL_INT_ST_M (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S) +#define CACHE_L1_ICACHE3_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE3_FAIL_INT_ST_S 3 +/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ST_M (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S) +#define CACHE_L1_CACHE_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ST_S 4 + +/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register + * Cache Access Counter enable and clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178) +/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable ibus0 counter in L1-ICache0. + */ +#define CACHE_L1_IBUS0_CNT_ENA (BIT(0)) +#define CACHE_L1_IBUS0_CNT_ENA_M (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S) +#define CACHE_L1_IBUS0_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS0_CNT_ENA_S 0 +/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable ibus1 counter in L1-ICache1. + */ +#define CACHE_L1_IBUS1_CNT_ENA (BIT(1)) +#define CACHE_L1_IBUS1_CNT_ENA_M (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S) +#define CACHE_L1_IBUS1_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS1_CNT_ENA_S 1 +/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_CNT_ENA (BIT(2)) +#define CACHE_L1_IBUS2_CNT_ENA_M (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S) +#define CACHE_L1_IBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS2_CNT_ENA_S 2 +/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_CNT_ENA (BIT(3)) +#define CACHE_L1_IBUS3_CNT_ENA_M (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S) +#define CACHE_L1_IBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L1_IBUS3_CNT_ENA_S 3 +/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_ENA (BIT(4)) +#define CACHE_L1_BUS0_CNT_ENA_M (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S) +#define CACHE_L1_BUS0_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_CNT_ENA_S 4 +/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_ENA (BIT(5)) +#define CACHE_L1_BUS1_CNT_ENA_M (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S) +#define CACHE_L1_BUS1_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_CNT_ENA_S 5 +/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_CNT_ENA (BIT(6)) +#define CACHE_L1_DBUS2_CNT_ENA_M (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S) +#define CACHE_L1_DBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L1_DBUS2_CNT_ENA_S 6 +/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_CNT_ENA (BIT(7)) +#define CACHE_L1_DBUS3_CNT_ENA_M (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S) +#define CACHE_L1_DBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L1_DBUS3_CNT_ENA_S 7 +/** CACHE_L1_IBUS0_CNT_CLR : HRO; bitpos: [16]; default: 0; + * The bit is used to clear ibus0 counter in L1-ICache0. + */ +#define CACHE_L1_IBUS0_CNT_CLR (BIT(16)) +#define CACHE_L1_IBUS0_CNT_CLR_M (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S) +#define CACHE_L1_IBUS0_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS0_CNT_CLR_S 16 +/** CACHE_L1_IBUS1_CNT_CLR : HRO; bitpos: [17]; default: 0; + * The bit is used to clear ibus1 counter in L1-ICache1. + */ +#define CACHE_L1_IBUS1_CNT_CLR (BIT(17)) +#define CACHE_L1_IBUS1_CNT_CLR_M (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S) +#define CACHE_L1_IBUS1_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS1_CNT_CLR_S 17 +/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS2_CNT_CLR (BIT(18)) +#define CACHE_L1_IBUS2_CNT_CLR_M (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S) +#define CACHE_L1_IBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS2_CNT_CLR_S 18 +/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0; + * Reserved + */ +#define CACHE_L1_IBUS3_CNT_CLR (BIT(19)) +#define CACHE_L1_IBUS3_CNT_CLR_M (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S) +#define CACHE_L1_IBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L1_IBUS3_CNT_CLR_S 19 +/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_CLR (BIT(20)) +#define CACHE_L1_BUS0_CNT_CLR_M (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S) +#define CACHE_L1_BUS0_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_CNT_CLR_S 20 +/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_CLR (BIT(21)) +#define CACHE_L1_BUS1_CNT_CLR_M (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S) +#define CACHE_L1_BUS1_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_CNT_CLR_S 21 +/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS2_CNT_CLR (BIT(22)) +#define CACHE_L1_DBUS2_CNT_CLR_M (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S) +#define CACHE_L1_DBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L1_DBUS2_CNT_CLR_S 22 +/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0; + * Reserved + */ +#define CACHE_L1_DBUS3_CNT_CLR (BIT(23)) +#define CACHE_L1_DBUS3_CNT_CLR_M (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S) +#define CACHE_L1_DBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L1_DBUS3_CNT_CLR_S 23 + +/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register + * L1-ICache bus0 Hit-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c) +/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_HIT_CNT_M (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S) +#define CACHE_L1_IBUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_HIT_CNT_S 0 + +/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register + * L1-ICache bus0 Miss-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180) +/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_MISS_CNT_M (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S) +#define CACHE_L1_IBUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_MISS_CNT_S 0 + +/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register + * L1-ICache bus0 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184) +/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-ICache0. + */ +#define CACHE_L1_IBUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_CONFLICT_CNT_M (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S) +#define CACHE_L1_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS0_ACS_NXTLVL_CNT_REG register + * L1-ICache bus0 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x188) +/** CACHE_L1_IBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ +#define CACHE_L1_IBUS0_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS0_NXTLVL_CNT_M (CACHE_L1_IBUS0_NXTLVL_CNT_V << CACHE_L1_IBUS0_NXTLVL_CNT_S) +#define CACHE_L1_IBUS0_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS0_NXTLVL_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register + * L1-ICache bus1 Hit-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c) +/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_HIT_CNT_M (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S) +#define CACHE_L1_IBUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_HIT_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register + * L1-ICache bus1 Miss-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190) +/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_MISS_CNT_M (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S) +#define CACHE_L1_IBUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_MISS_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register + * L1-ICache bus1 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194) +/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-ICache1. + */ +#define CACHE_L1_IBUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_CONFLICT_CNT_M (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S) +#define CACHE_L1_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS1_ACS_NXTLVL_CNT_REG register + * L1-ICache bus1 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x198) +/** CACHE_L1_IBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ +#define CACHE_L1_IBUS1_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS1_NXTLVL_CNT_M (CACHE_L1_IBUS1_NXTLVL_CNT_V << CACHE_L1_IBUS1_NXTLVL_CNT_S) +#define CACHE_L1_IBUS1_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS1_NXTLVL_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register + * L1-ICache bus2 Hit-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c) +/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_HIT_CNT_M (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S) +#define CACHE_L1_IBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_HIT_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register + * L1-ICache bus2 Miss-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0) +/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_MISS_CNT_M (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S) +#define CACHE_L1_IBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_MISS_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register + * L1-ICache bus2 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4) +/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-ICache2. + */ +#define CACHE_L1_IBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_CONFLICT_CNT_M (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S) +#define CACHE_L1_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS2_ACS_NXTLVL_CNT_REG register + * L1-ICache bus2 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1a8) +/** CACHE_L1_IBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ +#define CACHE_L1_IBUS2_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS2_NXTLVL_CNT_M (CACHE_L1_IBUS2_NXTLVL_CNT_V << CACHE_L1_IBUS2_NXTLVL_CNT_S) +#define CACHE_L1_IBUS2_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS2_NXTLVL_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register + * L1-ICache bus3 Hit-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac) +/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_HIT_CNT_M (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S) +#define CACHE_L1_IBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_HIT_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register + * L1-ICache bus3 Miss-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0) +/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_MISS_CNT_M (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S) +#define CACHE_L1_IBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_MISS_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register + * L1-ICache bus3 Conflict-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4) +/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-ICache3. + */ +#define CACHE_L1_IBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_CONFLICT_CNT_M (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S) +#define CACHE_L1_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L1_IBUS3_ACS_NXTLVL_CNT_REG register + * L1-ICache bus3 Next-Level-Access Counter register + */ +#define CACHE_L1_IBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1b8) +/** CACHE_L1_IBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ +#define CACHE_L1_IBUS3_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_IBUS3_NXTLVL_CNT_M (CACHE_L1_IBUS3_NXTLVL_CNT_V << CACHE_L1_IBUS3_NXTLVL_CNT_S) +#define CACHE_L1_IBUS3_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_IBUS3_NXTLVL_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register + * L1-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc) +/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_M (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S) +#define CACHE_L1_BUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register + * L1-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0) +/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_M (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S) +#define CACHE_L1_BUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register + * L1-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4) +/** CACHE_L1_BUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_CNT_M (CACHE_L1_BUS0_CONFLICT_CNT_V << CACHE_L1_BUS0_CONFLICT_CNT_S) +#define CACHE_L1_BUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG register + * L1-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) +/** CACHE_L1_BUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_CNT_M (CACHE_L1_BUS0_NXTLVL_CNT_V << CACHE_L1_BUS0_NXTLVL_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register + * L1-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) +/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_M (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S) +#define CACHE_L1_BUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register + * L1-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d0) +/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_M (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S) +#define CACHE_L1_BUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register + * L1-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4) +/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_M (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S) +#define CACHE_L1_BUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG register + * L1-Cache bus1 Next-Level-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1d8) +/** CACHE_L1_BUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ +#define CACHE_L1_BUS1_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_CNT_M (CACHE_L1_BUS1_NXTLVL_CNT_V << CACHE_L1_BUS1_NXTLVL_CNT_S) +#define CACHE_L1_BUS1_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register + * L1-DCache bus2 Hit-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc) +/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_HIT_CNT_M (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S) +#define CACHE_L1_DBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_HIT_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register + * L1-DCache bus2 Miss-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e0) +/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_MISS_CNT_M (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S) +#define CACHE_L1_DBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_MISS_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register + * L1-DCache bus2 Conflict-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4) +/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-DCache. + */ +#define CACHE_L1_DBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_CONFLICT_CNT_M (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S) +#define CACHE_L1_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS2_ACS_NXTLVL_CNT_REG register + * L1-DCache bus2 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1e8) +/** CACHE_L1_DBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ +#define CACHE_L1_DBUS2_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS2_NXTLVL_CNT_M (CACHE_L1_DBUS2_NXTLVL_CNT_V << CACHE_L1_DBUS2_NXTLVL_CNT_S) +#define CACHE_L1_DBUS2_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS2_NXTLVL_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register + * L1-DCache bus3 Hit-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec) +/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_HIT_CNT_M (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S) +#define CACHE_L1_DBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_HIT_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register + * L1-DCache bus3 Miss-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1f0) +/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_MISS_CNT_M (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S) +#define CACHE_L1_DBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_MISS_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register + * L1-DCache bus3 Conflict-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f4) +/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-DCache. + */ +#define CACHE_L1_DBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_CONFLICT_CNT_M (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S) +#define CACHE_L1_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS3_ACS_NXTLVL_CNT_REG register + * L1-DCache bus3 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1f8) +/** CACHE_L1_DBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ +#define CACHE_L1_DBUS3_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS3_NXTLVL_CNT_M (CACHE_L1_DBUS3_NXTLVL_CNT_V << CACHE_L1_DBUS3_NXTLVL_CNT_S) +#define CACHE_L1_DBUS3_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS3_NXTLVL_CNT_S 0 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x1fc) +/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_M (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S) +#define CACHE_L1_ICACHE0_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_S 0 +/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_M (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S) +#define CACHE_L1_ICACHE0_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x200) +/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_M (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S) +#define CACHE_L1_ICACHE0_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x204) +/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_M (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S) +#define CACHE_L1_ICACHE1_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_S 0 +/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_M (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S) +#define CACHE_L1_ICACHE1_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x208) +/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_M (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S) +#define CACHE_L1_ICACHE1_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c) +/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache2 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE2_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ID_M (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S) +#define CACHE_L1_ICACHE2_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ID_S 0 +/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache2 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE2_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ATTR_M (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S) +#define CACHE_L1_ICACHE2_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE2_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210) +/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache2 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE2_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_FAIL_ADDR_M (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S) +#define CACHE_L1_ICACHE2_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE2_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214) +/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache3 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE3_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ID_M (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S) +#define CACHE_L1_ICACHE3_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ID_S 0 +/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache3 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE3_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ATTR_M (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S) +#define CACHE_L1_ICACHE3_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE3_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218) +/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache3 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE3_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_FAIL_ADDR_M (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S) +#define CACHE_L1_ICACHE3_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE3_FAIL_ADDR_S 0 + +/** CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG register + * L1-Cache Access Fail ID/attribution information register + */ +#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c) +/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ID 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_M (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S) +#define CACHE_L1_CACHE_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_S 0 +/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_M (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S) +#define CACHE_L1_CACHE_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_S 16 + +/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register + * L1-Cache Access Fail Address information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220) +/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_M (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S) +#define CACHE_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_S 0 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register + * L1-Cache Access Fail Interrupt enable register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x224) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 +/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ +#define CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define CACHE_SYNC_DONE_INT_ENA_M (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S) +#define CACHE_SYNC_DONE_INT_ENA_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ENA_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation error. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation error. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 +/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define CACHE_SYNC_ERR_INT_ENA_M (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S) +#define CACHE_SYNC_ERR_INT_ENA_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ENA_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register + * Sync Preload operation Interrupt clear register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x228) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 +/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ +#define CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define CACHE_SYNC_DONE_INT_CLR_M (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S) +#define CACHE_SYNC_DONE_INT_CLR_V 0x00000001U +#define CACHE_SYNC_DONE_INT_CLR_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0; + * The bit is used to clear interrupt of L1-ICache0 preload-operation error. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; + * The bit is used to clear interrupt of L1-ICache1 preload-operation error. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 +/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define CACHE_SYNC_ERR_INT_CLR_M (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S) +#define CACHE_SYNC_ERR_INT_CLR_V 0x00000001U +#define CACHE_SYNC_ERR_INT_CLR_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register + * Sync Preload operation Interrupt raw register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x22c) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is + * done. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is + * done. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 +/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define CACHE_SYNC_DONE_INT_RAW_M (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S) +#define CACHE_SYNC_DONE_INT_RAW_V 0x00000001U +#define CACHE_SYNC_DONE_INT_RAW_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation + * error occurs. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation + * error occurs. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 +/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ +#define CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define CACHE_SYNC_ERR_INT_RAW_M (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S) +#define CACHE_SYNC_ERR_INT_RAW_V 0x00000001U +#define CACHE_SYNC_ERR_INT_RAW_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register + * L1-Cache Access Fail Interrupt status register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x230) +/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S 0 +/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S 1 +/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S 2 +/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S) +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S 3 +/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 +/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define CACHE_SYNC_DONE_INT_ST_M (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S) +#define CACHE_SYNC_DONE_INT_ST_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ST_S 6 +/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST (BIT(7)) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S 7 +/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST (BIT(8)) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S 8 +/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST (BIT(9)) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S 9 +/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST (BIT(10)) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S) +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S 10 +/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 +/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define CACHE_SYNC_ERR_INT_ST_M (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S) +#define CACHE_SYNC_ERR_INT_ST_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ST_S 13 + +/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register + * Cache Sync/Preload Operation exception register + */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x234) +/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache0. + */ +#define CACHE_L1_ICACHE0_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S 0 +/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache1. + */ +#define CACHE_L1_ICACHE1_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S 2 +/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S 4 +/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S) +#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S 6 +/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ +#define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_M (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S) +#define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 +/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ +#define CACHE_SYNC_ERR_CODE 0x00000003U +#define CACHE_SYNC_ERR_CODE_M (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S) +#define CACHE_SYNC_ERR_CODE_V 0x00000003U +#define CACHE_SYNC_ERR_CODE_S 12 + +/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register + * Cache Sync Reset control register + */ +#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x238) +/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0; + * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_ICACHE0_SYNC_RST (BIT(0)) +#define CACHE_L1_ICACHE0_SYNC_RST_M (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S) +#define CACHE_L1_ICACHE0_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE0_SYNC_RST_S 0 +/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0; + * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_ICACHE1_SYNC_RST (BIT(1)) +#define CACHE_L1_ICACHE1_SYNC_RST_M (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S) +#define CACHE_L1_ICACHE1_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE1_SYNC_RST_S 1 +/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_SYNC_RST (BIT(2)) +#define CACHE_L1_ICACHE2_SYNC_RST_M (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S) +#define CACHE_L1_ICACHE2_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE2_SYNC_RST_S 2 +/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_SYNC_RST (BIT(3)) +#define CACHE_L1_ICACHE3_SYNC_RST_M (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S) +#define CACHE_L1_ICACHE3_SYNC_RST_V 0x00000001U +#define CACHE_L1_ICACHE3_SYNC_RST_S 3 +/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_CACHE_SYNC_RST (BIT(4)) +#define CACHE_L1_CACHE_SYNC_RST_M (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S) +#define CACHE_L1_CACHE_SYNC_RST_V 0x00000001U +#define CACHE_L1_CACHE_SYNC_RST_S 4 + +/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register + * Cache Preload Reset control register + */ +#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x23c) +/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0; + * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_ICACHE0_PLD_RST (BIT(0)) +#define CACHE_L1_ICACHE0_PLD_RST_M (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S) +#define CACHE_L1_ICACHE0_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE0_PLD_RST_S 0 +/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0; + * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_ICACHE1_PLD_RST (BIT(1)) +#define CACHE_L1_ICACHE1_PLD_RST_M (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S) +#define CACHE_L1_ICACHE1_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE1_PLD_RST_S 1 +/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_PLD_RST (BIT(2)) +#define CACHE_L1_ICACHE2_PLD_RST_M (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S) +#define CACHE_L1_ICACHE2_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE2_PLD_RST_S 2 +/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_PLD_RST (BIT(3)) +#define CACHE_L1_ICACHE3_PLD_RST_M (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S) +#define CACHE_L1_ICACHE3_PLD_RST_V 0x00000001U +#define CACHE_L1_ICACHE3_PLD_RST_S 3 +/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_CACHE_PLD_RST (BIT(4)) +#define CACHE_L1_CACHE_PLD_RST_M (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S) +#define CACHE_L1_CACHE_PLD_RST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_RST_S 4 + +/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register + * Cache Autoload buffer clear control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x240) +/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, + * autoload will not work in L1-ICache0. This bit should not be active when autoload + * works in L1-ICache0. + */ +#define CACHE_L1_ICACHE0_ALD_BUF_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S 0 +/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, + * autoload will not work in L1-ICache1. This bit should not be active when autoload + * works in L1-ICache1. + */ +#define CACHE_L1_ICACHE1_ALD_BUF_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S 1 +/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_ALD_BUF_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S 2 +/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_ALD_BUF_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S) +#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S 3 +/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ +#define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) +#define CACHE_L1_CACHE_ALD_BUF_CLR_M (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S) +#define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 + +/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register + * Unallocate request buffer clear registers + */ +#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244) +/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache0 where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) +#define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE0_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 +/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache1 where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) +#define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE1_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE1_UNALLOC_CLR_S 1 +/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_UNALLOC_CLR (BIT(2)) +#define CACHE_L1_ICACHE2_UNALLOC_CLR_M (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE2_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE2_UNALLOC_CLR_S 2 +/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_UNALLOC_CLR (BIT(3)) +#define CACHE_L1_ICACHE3_UNALLOC_CLR_M (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S) +#define CACHE_L1_ICACHE3_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 +/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) +#define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) +#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 + +/** CACHE_L1_CACHE_OBJECT_CTRL_REG register + * Cache Tag and Data memory Object control register + */ +#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x248) +/** CACHE_L1_ICACHE0_TAG_OBJECT : HRO; bitpos: [0]; default: 0; + * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_ICACHE0_TAG_OBJECT (BIT(0)) +#define CACHE_L1_ICACHE0_TAG_OBJECT_M (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S) +#define CACHE_L1_ICACHE0_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE0_TAG_OBJECT_S 0 +/** CACHE_L1_ICACHE1_TAG_OBJECT : HRO; bitpos: [1]; default: 0; + * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_ICACHE1_TAG_OBJECT (BIT(1)) +#define CACHE_L1_ICACHE1_TAG_OBJECT_M (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S) +#define CACHE_L1_ICACHE1_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE1_TAG_OBJECT_S 1 +/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_TAG_OBJECT (BIT(2)) +#define CACHE_L1_ICACHE2_TAG_OBJECT_M (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S) +#define CACHE_L1_ICACHE2_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE2_TAG_OBJECT_S 2 +/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_TAG_OBJECT (BIT(3)) +#define CACHE_L1_ICACHE3_TAG_OBJECT_M (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S) +#define CACHE_L1_ICACHE3_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE3_TAG_OBJECT_S 3 +/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) +#define CACHE_L1_CACHE_TAG_OBJECT_M (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S) +#define CACHE_L1_CACHE_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_TAG_OBJECT_S 4 +/** CACHE_L1_ICACHE0_MEM_OBJECT : HRO; bitpos: [6]; default: 0; + * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ +#define CACHE_L1_ICACHE0_MEM_OBJECT (BIT(6)) +#define CACHE_L1_ICACHE0_MEM_OBJECT_M (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S) +#define CACHE_L1_ICACHE0_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE0_MEM_OBJECT_S 6 +/** CACHE_L1_ICACHE1_MEM_OBJECT : HRO; bitpos: [7]; default: 0; + * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ +#define CACHE_L1_ICACHE1_MEM_OBJECT (BIT(7)) +#define CACHE_L1_ICACHE1_MEM_OBJECT_M (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S) +#define CACHE_L1_ICACHE1_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE1_MEM_OBJECT_S 7 +/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE2_MEM_OBJECT (BIT(8)) +#define CACHE_L1_ICACHE2_MEM_OBJECT_M (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S) +#define CACHE_L1_ICACHE2_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE2_MEM_OBJECT_S 8 +/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0; + * Reserved + */ +#define CACHE_L1_ICACHE3_MEM_OBJECT (BIT(9)) +#define CACHE_L1_ICACHE3_MEM_OBJECT_M (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S) +#define CACHE_L1_ICACHE3_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_ICACHE3_MEM_OBJECT_S 9 +/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) +#define CACHE_L1_CACHE_MEM_OBJECT_M (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S) +#define CACHE_L1_CACHE_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_MEM_OBJECT_S 10 + +/** CACHE_L1_CACHE_WAY_OBJECT_REG register + * Cache Tag and Data memory way register + */ +#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x24c) +/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ +#define CACHE_L1_CACHE_WAY_OBJECT 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_M (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S) +#define CACHE_L1_CACHE_WAY_OBJECT_V 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_S 0 + +/** CACHE_L1_CACHE_VADDR_REG register + * Cache Vaddr register + */ +#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x250) +/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ +#define CACHE_L1_CACHE_VADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_VADDR_M (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S) +#define CACHE_L1_CACHE_VADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_VADDR_S 0 + +/** CACHE_L1_CACHE_DEBUG_BUS_REG register + * Cache Tag/data memory content register + */ +#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x254) +/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 596; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ +#define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_M (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S) +#define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_S 0 + +/** CACHE_LEVEL_SPLIT0_REG register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x258) +/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 600; + * Reserved + */ +#define CACHE_LEVEL_SPLIT0 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT0_M (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S) +#define CACHE_LEVEL_SPLIT0_V 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT0_S 0 + +/** CACHE_L2_CACHE_CTRL_REG register + * L2 Cache(L2-Cache) control register + */ +#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x25c) +/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + */ +#define CACHE_L2_CACHE_SHUT_DMA (BIT(4)) +#define CACHE_L2_CACHE_SHUT_DMA_M (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S) +#define CACHE_L2_CACHE_SHUT_DMA_V 0x00000001U +#define CACHE_L2_CACHE_SHUT_DMA_S 4 +/** CACHE_L2_CACHE_UNDEF_OP : HRO; bitpos: [8:5]; default: 0; + * Reserved + */ +#define CACHE_L2_CACHE_UNDEF_OP 0x0000000FU +#define CACHE_L2_CACHE_UNDEF_OP_M (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S) +#define CACHE_L2_CACHE_UNDEF_OP_V 0x0000000FU +#define CACHE_L2_CACHE_UNDEF_OP_S 5 + +/** CACHE_L2_BYPASS_CACHE_CONF_REG register + * Bypass Cache configure register + */ +#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x260) +/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0; + * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + */ +#define CACHE_BYPASS_L2_CACHE_EN (BIT(5)) +#define CACHE_BYPASS_L2_CACHE_EN_M (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S) +#define CACHE_BYPASS_L2_CACHE_EN_V 0x00000001U +#define CACHE_BYPASS_L2_CACHE_EN_S 5 + +/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register + * L2 Cache CacheSize mode configure register + */ +#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x264) +/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_1K (BIT(0)) +#define CACHE_L2_CACHE_CACHESIZE_1K_M (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S) +#define CACHE_L2_CACHE_CACHESIZE_1K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_1K_S 0 +/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_2K (BIT(1)) +#define CACHE_L2_CACHE_CACHESIZE_2K_M (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S) +#define CACHE_L2_CACHE_CACHESIZE_2K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_2K_S 1 +/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_4K (BIT(2)) +#define CACHE_L2_CACHE_CACHESIZE_4K_M (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S) +#define CACHE_L2_CACHE_CACHESIZE_4K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_4K_S 2 +/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_8K (BIT(3)) +#define CACHE_L2_CACHE_CACHESIZE_8K_M (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S) +#define CACHE_L2_CACHE_CACHESIZE_8K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_8K_S 3 +/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_16K (BIT(4)) +#define CACHE_L2_CACHE_CACHESIZE_16K_M (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S) +#define CACHE_L2_CACHE_CACHESIZE_16K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_16K_S 4 +/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_32K (BIT(5)) +#define CACHE_L2_CACHE_CACHESIZE_32K_M (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S) +#define CACHE_L2_CACHE_CACHESIZE_32K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_32K_S 5 +/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_64K (BIT(6)) +#define CACHE_L2_CACHE_CACHESIZE_64K_M (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S) +#define CACHE_L2_CACHE_CACHESIZE_64K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_64K_S 6 +/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_128K (BIT(7)) +#define CACHE_L2_CACHE_CACHESIZE_128K_M (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S) +#define CACHE_L2_CACHE_CACHESIZE_128K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_128K_S 7 +/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_256K (BIT(8)) +#define CACHE_L2_CACHE_CACHESIZE_256K_M (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S) +#define CACHE_L2_CACHE_CACHESIZE_256K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_256K_S 8 +/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_512K (BIT(9)) +#define CACHE_L2_CACHE_CACHESIZE_512K_M (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S) +#define CACHE_L2_CACHE_CACHESIZE_512K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_512K_S 9 +/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_1024K (BIT(10)) +#define CACHE_L2_CACHE_CACHESIZE_1024K_M (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S) +#define CACHE_L2_CACHE_CACHESIZE_1024K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_1024K_S 10 +/** CACHE_L2_CACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_2048K (BIT(11)) +#define CACHE_L2_CACHE_CACHESIZE_2048K_M (CACHE_L2_CACHE_CACHESIZE_2048K_V << CACHE_L2_CACHE_CACHESIZE_2048K_S) +#define CACHE_L2_CACHE_CACHESIZE_2048K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_2048K_S 11 +/** CACHE_L2_CACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_CACHESIZE_4096K (BIT(12)) +#define CACHE_L2_CACHE_CACHESIZE_4096K_M (CACHE_L2_CACHE_CACHESIZE_4096K_V << CACHE_L2_CACHE_CACHESIZE_4096K_S) +#define CACHE_L2_CACHE_CACHESIZE_4096K_V 0x00000001U +#define CACHE_L2_CACHE_CACHESIZE_4096K_S 12 + +/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register + * L2 Cache BlockSize mode configure register + */ +#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x268) +/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_8 (BIT(0)) +#define CACHE_L2_CACHE_BLOCKSIZE_8_M (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S) +#define CACHE_L2_CACHE_BLOCKSIZE_8_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_8_S 0 +/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_16 (BIT(1)) +#define CACHE_L2_CACHE_BLOCKSIZE_16_M (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S) +#define CACHE_L2_CACHE_BLOCKSIZE_16_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_16_S 1 +/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_32 (BIT(2)) +#define CACHE_L2_CACHE_BLOCKSIZE_32_M (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S) +#define CACHE_L2_CACHE_BLOCKSIZE_32_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_32_S 2 +/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all + * other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_64 (BIT(3)) +#define CACHE_L2_CACHE_BLOCKSIZE_64_M (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S) +#define CACHE_L2_CACHE_BLOCKSIZE_64_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_64_S 3 +/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_128 (BIT(4)) +#define CACHE_L2_CACHE_BLOCKSIZE_128_M (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S) +#define CACHE_L2_CACHE_BLOCKSIZE_128_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_128_S 4 +/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ +#define CACHE_L2_CACHE_BLOCKSIZE_256 (BIT(5)) +#define CACHE_L2_CACHE_BLOCKSIZE_256_M (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S) +#define CACHE_L2_CACHE_BLOCKSIZE_256_V 0x00000001U +#define CACHE_L2_CACHE_BLOCKSIZE_256_S 5 + +/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x26c) +/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to enable L2-Cache wrap around mode. + */ +#define CACHE_L2_CACHE_WRAP (BIT(5)) +#define CACHE_L2_CACHE_WRAP_M (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S) +#define CACHE_L2_CACHE_WRAP_V 0x00000001U +#define CACHE_L2_CACHE_WRAP_S 5 + +/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register + * Cache tag memory power control register + */ +#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x270) +/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON (BIT(20)) +#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S) +#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S 20 +/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD (BIT(21)) +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S) +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S 21 +/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU (BIT(22)) +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S) +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S 22 + +/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register + * Cache data memory power control register + */ +#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x274) +/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON (BIT(20)) +#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S) +#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S 20 +/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD (BIT(21)) +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S) +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S 21 +/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU (BIT(22)) +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S) +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S 22 + +/** CACHE_L2_CACHE_FREEZE_CTRL_REG register + * Cache Freeze control register + */ +#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x278) +/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0; + * The bit is used to enable freeze operation on L2-Cache. It can be cleared by + * software. + */ +#define CACHE_L2_CACHE_FREEZE_EN (BIT(20)) +#define CACHE_L2_CACHE_FREEZE_EN_M (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S) +#define CACHE_L2_CACHE_FREEZE_EN_V 0x00000001U +#define CACHE_L2_CACHE_FREEZE_EN_S 20 +/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0; + * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L2_CACHE_FREEZE_MODE (BIT(21)) +#define CACHE_L2_CACHE_FREEZE_MODE_M (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S) +#define CACHE_L2_CACHE_FREEZE_MODE_V 0x00000001U +#define CACHE_L2_CACHE_FREEZE_MODE_S 21 +/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0; + * The bit is used to indicate whether freeze operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L2_CACHE_FREEZE_DONE (BIT(22)) +#define CACHE_L2_CACHE_FREEZE_DONE_M (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S) +#define CACHE_L2_CACHE_FREEZE_DONE_V 0x00000001U +#define CACHE_L2_CACHE_FREEZE_DONE_S 22 + +/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register + * Cache data memory access configure register + */ +#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x27c) +/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_DATA_MEM_RD_EN (BIT(20)) +#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S) +#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S 20 +/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_DATA_MEM_WR_EN (BIT(21)) +#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S) +#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S 21 + +/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register + * Cache tag memory access configure register + */ +#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x280) +/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_TAG_MEM_RD_EN (BIT(20)) +#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S) +#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S 20 +/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L2_CACHE_TAG_MEM_WR_EN (BIT(21)) +#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S) +#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S 21 + +/** CACHE_L2_CACHE_PRELOCK_CONF_REG register + * L2 Cache prelock configure register + */ +#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x284) +/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L2-Cache. + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S) +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S 0 +/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L2-Cache. + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S) +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S 1 +/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l2 cache prelock. + */ +#define CACHE_L2_CACHE_PRELOCK_RGID 0x0000000FU +#define CACHE_L2_CACHE_PRELOCK_RGID_M (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S) +#define CACHE_L2_CACHE_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L2_CACHE_PRELOCK_RGID_S 2 + +/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register + * L2 Cache prelock section0 address configure register + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x288) +/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S) +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register + * L2 Cache prelock section1 address configure register + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x28c) +/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S) +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register + * L2 Cache prelock section size configure register + */ +#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x290) +/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S) +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535; + * Those bits are used to configure the size of the second section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S) +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register + * L2 Cache preload-operation control register + */ +#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x294) +/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L2-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L2_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L2_CACHE_PRELOAD_ENA_M (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S) +#define CACHE_L2_CACHE_PRELOAD_ENA_V 0x00000001U +#define CACHE_L2_CACHE_PRELOAD_ENA_S 0 +/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L2_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L2_CACHE_PRELOAD_DONE_M (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S) +#define CACHE_L2_CACHE_PRELOAD_DONE_V 0x00000001U +#define CACHE_L2_CACHE_PRELOAD_DONE_S 1 +/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L2_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L2_CACHE_PRELOAD_ORDER_M (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S) +#define CACHE_L2_CACHE_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L2_CACHE_PRELOAD_ORDER_S 2 +/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l2 cache preload. + */ +#define CACHE_L2_CACHE_PRELOAD_RGID 0x0000000FU +#define CACHE_L2_CACHE_PRELOAD_RGID_M (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S) +#define CACHE_L2_CACHE_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L2_CACHE_PRELOAD_RGID_S 3 + +/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register + * L2 Cache preload address configure register + */ +#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x298) +/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L2-Cache, + * which should be used together with L2_CACHE_PRELOAD_SIZE_REG + */ +#define CACHE_L2_CACHE_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOAD_ADDR_M (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S) +#define CACHE_L2_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_PRELOAD_ADDR_S 0 + +/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register + * L2 Cache preload size configure register + */ +#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x29c) +/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + */ +#define CACHE_L2_CACHE_PRELOAD_SIZE 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOAD_SIZE_M (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S) +#define CACHE_L2_CACHE_PRELOAD_SIZE_V 0x0000FFFFU +#define CACHE_L2_CACHE_PRELOAD_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register + * L2 Cache autoload-operation control register + */ +#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0) +/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, + * 0: disable. + */ +#define CACHE_L2_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L2_CACHE_AUTOLOAD_ENA_M (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_ENA_S 0 +/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L2_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L2_CACHE_AUTOLOAD_DONE_M (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S) +#define CACHE_L2_CACHE_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_DONE_S 1 +/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L2-Cache. 0: + * ascending. 1: descending. + */ +#define CACHE_L2_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S) +#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S 2 +/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S 9 +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S 10 +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L2-Cache. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S 11 +/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l2 cache autoload. + */ +#define CACHE_L2_CACHE_AUTOLOAD_RGID 0x0000000FU +#define CACHE_L2_CACHE_AUTOLOAD_RGID_M (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S) +#define CACHE_L2_CACHE_AUTOLOAD_RGID_V 0x0000000FU +#define CACHE_L2_CACHE_AUTOLOAD_RGID_S 12 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register + * L2 Cache autoload section 0 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4) +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register + * L2 Cache autoload section 0 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8) +/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register + * L2 Cache autoload section 1 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac) +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register + * L2 Cache autoload section 1 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0) +/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register + * L2 Cache autoload section 2 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2b4) +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register + * L2 Cache autoload section 2 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2b8) +/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register + * L2 Cache autoload section 3 address configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2bc) +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S 0 + +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register + * L2 Cache autoload section 3 size configure register + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2c0) +/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S) +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V 0x0FFFFFFFU +#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S 0 + +/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register + * Cache Access Counter Interrupt enable register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2c4) +/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_IBUS0_OVF_INT_ENA (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_ENA_M (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S) +#define CACHE_L2_IBUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_ENA_S 8 +/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_IBUS1_OVF_INT_ENA (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_ENA_M (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S) +#define CACHE_L2_IBUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_ENA_S 9 +/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_OVF_INT_ENA (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_ENA_M (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S) +#define CACHE_L2_IBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_ENA_S 10 +/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_OVF_INT_ENA (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_ENA_M (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S) +#define CACHE_L2_IBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_ENA_S 11 +/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_DBUS0_OVF_INT_ENA (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_ENA_M (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S) +#define CACHE_L2_DBUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_ENA_S 12 +/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_DBUS1_OVF_INT_ENA (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_ENA_M (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S) +#define CACHE_L2_DBUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_ENA_S 13 +/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_OVF_INT_ENA (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_ENA_M (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S) +#define CACHE_L2_DBUS2_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_ENA_S 14 +/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_OVF_INT_ENA (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_ENA_M (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S) +#define CACHE_L2_DBUS3_OVF_INT_ENA_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_ENA_S 15 + +/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register + * Cache Access Counter Interrupt clear register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2c8) +/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ +#define CACHE_L2_IBUS0_OVF_INT_CLR (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_CLR_M (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S) +#define CACHE_L2_IBUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_CLR_S 8 +/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ +#define CACHE_L2_IBUS1_OVF_INT_CLR (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_CLR_M (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S) +#define CACHE_L2_IBUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_CLR_S 9 +/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_OVF_INT_CLR (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_CLR_M (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S) +#define CACHE_L2_IBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_CLR_S 10 +/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_OVF_INT_CLR (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_CLR_M (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S) +#define CACHE_L2_IBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_CLR_S 11 +/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ +#define CACHE_L2_DBUS0_OVF_INT_CLR (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_CLR_M (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S) +#define CACHE_L2_DBUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_CLR_S 12 +/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ +#define CACHE_L2_DBUS1_OVF_INT_CLR (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_CLR_M (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S) +#define CACHE_L2_DBUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_CLR_S 13 +/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_OVF_INT_CLR (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_CLR_M (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S) +#define CACHE_L2_DBUS2_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_CLR_S 14 +/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_OVF_INT_CLR (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_CLR_M (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S) +#define CACHE_L2_DBUS3_OVF_INT_CLR_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_CLR_S 15 + +/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register + * Cache Access Counter Interrupt raw register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2cc) +/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-ICache0. + */ +#define CACHE_L2_IBUS0_OVF_INT_RAW (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_RAW_M (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S) +#define CACHE_L2_IBUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_RAW_S 8 +/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-ICache1. + */ +#define CACHE_L2_IBUS1_OVF_INT_RAW (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_RAW_M (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S) +#define CACHE_L2_IBUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_RAW_S 9 +/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-ICache2. + */ +#define CACHE_L2_IBUS2_OVF_INT_RAW (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_RAW_M (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S) +#define CACHE_L2_IBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_RAW_S 10 +/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-ICache3. + */ +#define CACHE_L2_IBUS3_OVF_INT_RAW (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_RAW_M (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S) +#define CACHE_L2_IBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_RAW_S 11 +/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-DCache. + */ +#define CACHE_L2_DBUS0_OVF_INT_RAW (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_RAW_M (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S) +#define CACHE_L2_DBUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_RAW_S 12 +/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-DCache. + */ +#define CACHE_L2_DBUS1_OVF_INT_RAW (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_RAW_M (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S) +#define CACHE_L2_DBUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_RAW_S 13 +/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-DCache. + */ +#define CACHE_L2_DBUS2_OVF_INT_RAW (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_RAW_M (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S) +#define CACHE_L2_DBUS2_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_RAW_S 14 +/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-DCache. + */ +#define CACHE_L2_DBUS3_OVF_INT_RAW (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_RAW_M (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S) +#define CACHE_L2_DBUS3_OVF_INT_RAW_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_RAW_S 15 + +/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register + * Cache Access Counter Interrupt status register + */ +#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2d0) +/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_IBUS0_OVF_INT_ST (BIT(8)) +#define CACHE_L2_IBUS0_OVF_INT_ST_M (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S) +#define CACHE_L2_IBUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS0_OVF_INT_ST_S 8 +/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_IBUS1_OVF_INT_ST (BIT(9)) +#define CACHE_L2_IBUS1_OVF_INT_ST_M (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S) +#define CACHE_L2_IBUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS1_OVF_INT_ST_S 9 +/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_OVF_INT_ST (BIT(10)) +#define CACHE_L2_IBUS2_OVF_INT_ST_M (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S) +#define CACHE_L2_IBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS2_OVF_INT_ST_S 10 +/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_OVF_INT_ST (BIT(11)) +#define CACHE_L2_IBUS3_OVF_INT_ST_M (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S) +#define CACHE_L2_IBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_IBUS3_OVF_INT_ST_S 11 +/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ +#define CACHE_L2_DBUS0_OVF_INT_ST (BIT(12)) +#define CACHE_L2_DBUS0_OVF_INT_ST_M (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S) +#define CACHE_L2_DBUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS0_OVF_INT_ST_S 12 +/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ +#define CACHE_L2_DBUS1_OVF_INT_ST (BIT(13)) +#define CACHE_L2_DBUS1_OVF_INT_ST_M (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S) +#define CACHE_L2_DBUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS1_OVF_INT_ST_S 13 +/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_OVF_INT_ST (BIT(14)) +#define CACHE_L2_DBUS2_OVF_INT_ST_M (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S) +#define CACHE_L2_DBUS2_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS2_OVF_INT_ST_S 14 +/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_OVF_INT_ST (BIT(15)) +#define CACHE_L2_DBUS3_OVF_INT_ST_M (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S) +#define CACHE_L2_DBUS3_OVF_INT_ST_V 0x00000001U +#define CACHE_L2_DBUS3_OVF_INT_ST_S 15 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register + * Cache Access Fail Interrupt enable register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d4) +/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to + * l1 cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_ENA (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_ENA_M (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S) +#define CACHE_L2_CACHE_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_ENA_S 5 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register + * L1-Cache Access Fail Interrupt clear register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d8) +/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 + * cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_CLR (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_CLR_M (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S) +#define CACHE_L2_CACHE_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_CLR_S 5 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register + * Cache Access Fail Interrupt raw register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2dc) +/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_RAW (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_RAW_M (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S) +#define CACHE_L2_CACHE_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_RAW_S 5 + +/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register + * Cache Access Fail Interrupt status register + */ +#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e0) +/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L2-Cache due + * to l1 cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_INT_ST (BIT(5)) +#define CACHE_L2_CACHE_FAIL_INT_ST_M (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S) +#define CACHE_L2_CACHE_FAIL_INT_ST_V 0x00000001U +#define CACHE_L2_CACHE_FAIL_INT_ST_S 5 + +/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register + * Cache Access Counter enable and clear register + */ +#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2e4) +/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0; + * The bit is used to enable ibus0 counter in L2-Cache. + */ +#define CACHE_L2_IBUS0_CNT_ENA (BIT(8)) +#define CACHE_L2_IBUS0_CNT_ENA_M (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S) +#define CACHE_L2_IBUS0_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS0_CNT_ENA_S 8 +/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0; + * The bit is used to enable ibus1 counter in L2-Cache. + */ +#define CACHE_L2_IBUS1_CNT_ENA (BIT(9)) +#define CACHE_L2_IBUS1_CNT_ENA_M (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S) +#define CACHE_L2_IBUS1_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS1_CNT_ENA_S 9 +/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_CNT_ENA (BIT(10)) +#define CACHE_L2_IBUS2_CNT_ENA_M (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S) +#define CACHE_L2_IBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS2_CNT_ENA_S 10 +/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_CNT_ENA (BIT(11)) +#define CACHE_L2_IBUS3_CNT_ENA_M (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S) +#define CACHE_L2_IBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L2_IBUS3_CNT_ENA_S 11 +/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0; + * The bit is used to enable dbus0 counter in L2-Cache. + */ +#define CACHE_L2_DBUS0_CNT_ENA (BIT(12)) +#define CACHE_L2_DBUS0_CNT_ENA_M (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S) +#define CACHE_L2_DBUS0_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS0_CNT_ENA_S 12 +/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0; + * The bit is used to enable dbus1 counter in L2-Cache. + */ +#define CACHE_L2_DBUS1_CNT_ENA (BIT(13)) +#define CACHE_L2_DBUS1_CNT_ENA_M (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S) +#define CACHE_L2_DBUS1_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS1_CNT_ENA_S 13 +/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_CNT_ENA (BIT(14)) +#define CACHE_L2_DBUS2_CNT_ENA_M (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S) +#define CACHE_L2_DBUS2_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS2_CNT_ENA_S 14 +/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_CNT_ENA (BIT(15)) +#define CACHE_L2_DBUS3_CNT_ENA_M (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S) +#define CACHE_L2_DBUS3_CNT_ENA_V 0x00000001U +#define CACHE_L2_DBUS3_CNT_ENA_S 15 +/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0; + * The bit is used to clear ibus0 counter in L2-Cache. + */ +#define CACHE_L2_IBUS0_CNT_CLR (BIT(24)) +#define CACHE_L2_IBUS0_CNT_CLR_M (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S) +#define CACHE_L2_IBUS0_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS0_CNT_CLR_S 24 +/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0; + * The bit is used to clear ibus1 counter in L2-Cache. + */ +#define CACHE_L2_IBUS1_CNT_CLR (BIT(25)) +#define CACHE_L2_IBUS1_CNT_CLR_M (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S) +#define CACHE_L2_IBUS1_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS1_CNT_CLR_S 25 +/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS2_CNT_CLR (BIT(26)) +#define CACHE_L2_IBUS2_CNT_CLR_M (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S) +#define CACHE_L2_IBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS2_CNT_CLR_S 26 +/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0; + * Reserved + */ +#define CACHE_L2_IBUS3_CNT_CLR (BIT(27)) +#define CACHE_L2_IBUS3_CNT_CLR_M (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S) +#define CACHE_L2_IBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L2_IBUS3_CNT_CLR_S 27 +/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0; + * The bit is used to clear dbus0 counter in L2-Cache. + */ +#define CACHE_L2_DBUS0_CNT_CLR (BIT(28)) +#define CACHE_L2_DBUS0_CNT_CLR_M (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S) +#define CACHE_L2_DBUS0_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS0_CNT_CLR_S 28 +/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0; + * The bit is used to clear dbus1 counter in L2-Cache. + */ +#define CACHE_L2_DBUS1_CNT_CLR (BIT(29)) +#define CACHE_L2_DBUS1_CNT_CLR_M (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S) +#define CACHE_L2_DBUS1_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS1_CNT_CLR_S 29 +/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS2_CNT_CLR (BIT(30)) +#define CACHE_L2_DBUS2_CNT_CLR_M (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S) +#define CACHE_L2_DBUS2_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS2_CNT_CLR_S 30 +/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0; + * Reserved + */ +#define CACHE_L2_DBUS3_CNT_CLR (BIT(31)) +#define CACHE_L2_DBUS3_CNT_CLR_M (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S) +#define CACHE_L2_DBUS3_CNT_CLR_V 0x00000001U +#define CACHE_L2_DBUS3_CNT_CLR_S 31 + +/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register + * L2-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2e8) +/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_HIT_CNT_M (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S) +#define CACHE_L2_IBUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_HIT_CNT_S 0 + +/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register + * L2-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2ec) +/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_MISS_CNT_M (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S) +#define CACHE_L2_IBUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_MISS_CNT_S 0 + +/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register + * L2-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x2f0) +/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache0 accesses + * L2-Cache due to bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_CONFLICT_CNT_M (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S) +#define CACHE_L2_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS0_ACS_NXTLVL_CNT_REG register + * L2-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x2f4) +/** CACHE_L2_IBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + */ +#define CACHE_L2_IBUS0_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS0_NXTLVL_CNT_M (CACHE_L2_IBUS0_NXTLVL_CNT_V << CACHE_L2_IBUS0_NXTLVL_CNT_S) +#define CACHE_L2_IBUS0_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS0_NXTLVL_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register + * L2-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8) +/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_HIT_CNT_M (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S) +#define CACHE_L2_IBUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_HIT_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register + * L2-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc) +/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_MISS_CNT_M (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S) +#define CACHE_L2_IBUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_MISS_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register + * L2-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300) +/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache1 accesses + * L2-Cache due to bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_CONFLICT_CNT_M (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S) +#define CACHE_L2_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS1_ACS_NXTLVL_CNT_REG register + * L2-Cache bus1 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x304) +/** CACHE_L2_IBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + */ +#define CACHE_L2_IBUS1_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS1_NXTLVL_CNT_M (CACHE_L2_IBUS1_NXTLVL_CNT_V << CACHE_L2_IBUS1_NXTLVL_CNT_S) +#define CACHE_L2_IBUS1_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS1_NXTLVL_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register + * L2-Cache bus2 Hit-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308) +/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_HIT_CNT_M (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S) +#define CACHE_L2_IBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_HIT_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register + * L2-Cache bus2 Miss-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c) +/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_MISS_CNT_M (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S) +#define CACHE_L2_IBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_MISS_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register + * L2-Cache bus2 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310) +/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache2 accesses + * L2-Cache due to bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_CONFLICT_CNT_M (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S) +#define CACHE_L2_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS2_ACS_NXTLVL_CNT_REG register + * L2-Cache bus2 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x314) +/** CACHE_L2_IBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + */ +#define CACHE_L2_IBUS2_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS2_NXTLVL_CNT_M (CACHE_L2_IBUS2_NXTLVL_CNT_V << CACHE_L2_IBUS2_NXTLVL_CNT_S) +#define CACHE_L2_IBUS2_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS2_NXTLVL_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register + * L2-Cache bus3 Hit-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318) +/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_HIT_CNT_M (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S) +#define CACHE_L2_IBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_HIT_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register + * L2-Cache bus3 Miss-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c) +/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_MISS_CNT_M (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S) +#define CACHE_L2_IBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_MISS_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register + * L2-Cache bus3 Conflict-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320) +/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache3 accesses + * L2-Cache due to bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_CONFLICT_CNT_M (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S) +#define CACHE_L2_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L2_IBUS3_ACS_NXTLVL_CNT_REG register + * L2-Cache bus3 Next-Level-Access Counter register + */ +#define CACHE_L2_IBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x324) +/** CACHE_L2_IBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + */ +#define CACHE_L2_IBUS3_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_IBUS3_NXTLVL_CNT_M (CACHE_L2_IBUS3_NXTLVL_CNT_V << CACHE_L2_IBUS3_NXTLVL_CNT_S) +#define CACHE_L2_IBUS3_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_IBUS3_NXTLVL_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register + * L2-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328) +/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_HIT_CNT_M (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S) +#define CACHE_L2_DBUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_HIT_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register + * L2-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c) +/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_MISS_CNT_M (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S) +#define CACHE_L2_DBUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_MISS_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register + * L2-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330) +/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_CONFLICT_CNT_M (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S) +#define CACHE_L2_DBUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS0_ACS_NXTLVL_CNT_REG register + * L2-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x334) +/** CACHE_L2_DBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + */ +#define CACHE_L2_DBUS0_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS0_NXTLVL_CNT_M (CACHE_L2_DBUS0_NXTLVL_CNT_V << CACHE_L2_DBUS0_NXTLVL_CNT_S) +#define CACHE_L2_DBUS0_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS0_NXTLVL_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register + * L2-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338) +/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_HIT_CNT_M (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S) +#define CACHE_L2_DBUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_HIT_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register + * L2-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c) +/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_MISS_CNT_M (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S) +#define CACHE_L2_DBUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_MISS_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register + * L2-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340) +/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_CONFLICT_CNT_M (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S) +#define CACHE_L2_DBUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS1_ACS_NXTLVL_CNT_REG register + * L2-Cache bus1 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x344) +/** CACHE_L2_DBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + */ +#define CACHE_L2_DBUS1_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS1_NXTLVL_CNT_M (CACHE_L2_DBUS1_NXTLVL_CNT_V << CACHE_L2_DBUS1_NXTLVL_CNT_S) +#define CACHE_L2_DBUS1_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS1_NXTLVL_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register + * L2-Cache bus2 Hit-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x348) +/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_HIT_CNT_M (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S) +#define CACHE_L2_DBUS2_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_HIT_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register + * L2-Cache bus2 Miss-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x34c) +/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_MISS_CNT_M (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S) +#define CACHE_L2_DBUS2_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_MISS_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register + * L2-Cache bus2 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x350) +/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_CONFLICT_CNT_M (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S) +#define CACHE_L2_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS2_ACS_NXTLVL_CNT_REG register + * L2-Cache bus2 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x354) +/** CACHE_L2_DBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + */ +#define CACHE_L2_DBUS2_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS2_NXTLVL_CNT_M (CACHE_L2_DBUS2_NXTLVL_CNT_V << CACHE_L2_DBUS2_NXTLVL_CNT_S) +#define CACHE_L2_DBUS2_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS2_NXTLVL_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register + * L2-Cache bus3 Hit-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x358) +/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_HIT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_HIT_CNT_M (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S) +#define CACHE_L2_DBUS3_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_HIT_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register + * L2-Cache bus3 Miss-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x35c) +/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_MISS_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_MISS_CNT_M (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S) +#define CACHE_L2_DBUS3_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_MISS_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register + * L2-Cache bus3 Conflict-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x360) +/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_CONFLICT_CNT_M (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S) +#define CACHE_L2_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_CONFLICT_CNT_S 0 + +/** CACHE_L2_DBUS3_ACS_NXTLVL_CNT_REG register + * L2-Cache bus3 Next-Level-Access Counter register + */ +#define CACHE_L2_DBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x364) +/** CACHE_L2_DBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + */ +#define CACHE_L2_DBUS3_NXTLVL_CNT 0xFFFFFFFFU +#define CACHE_L2_DBUS3_NXTLVL_CNT_M (CACHE_L2_DBUS3_NXTLVL_CNT_V << CACHE_L2_DBUS3_NXTLVL_CNT_S) +#define CACHE_L2_DBUS3_NXTLVL_CNT_V 0xFFFFFFFFU +#define CACHE_L2_DBUS3_NXTLVL_CNT_S 0 + +/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register + * L2-Cache Access Fail ID/attribution information register + */ +#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x368) +/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when L1-Cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_ID 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ID_M (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S) +#define CACHE_L2_CACHE_FAIL_ID_V 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ID_S 0 +/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when L1-Cache accesses L2-Cache + * due to cache accessing L1-Cache. + */ +#define CACHE_L2_CACHE_FAIL_ATTR 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ATTR_M (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S) +#define CACHE_L2_CACHE_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L2_CACHE_FAIL_ATTR_S 16 + +/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register + * L2-Cache Access Fail Address information register + */ +#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x36c) +/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when L1-Cache accesses L2-Cache. + */ +#define CACHE_L2_CACHE_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_FAIL_ADDR_M (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S) +#define CACHE_L2_CACHE_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_FAIL_ADDR_S 0 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register + * L1-Cache Access Fail Interrupt enable register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x370) +/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation error. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register + * Sync Preload operation Interrupt clear register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x374) +/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation + * is done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0; + * The bit is used to clear interrupt of L2-Cache preload-operation error. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register + * Sync Preload operation Interrupt raw register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x378) +/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is + * done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error + * occurs. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register + * L1-Cache Access Fail Interrupt status register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x37c) +/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L2-Cache + * preload-operation is done. + */ +#define CACHE_L2_CACHE_PLD_DONE_INT_ST (BIT(5)) +#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S) +#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S 5 +/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0; + * The bit indicates the status of the interrupt of L2-Cache preload-operation error. + */ +#define CACHE_L2_CACHE_PLD_ERR_INT_ST (BIT(12)) +#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S) +#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S 12 + +/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register + * Cache Sync/Preload Operation exception register + */ +#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x380) +/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0; + * The value 2 is Only available which means preload size is error in L2-Cache. + */ +#define CACHE_L2_CACHE_PLD_ERR_CODE 0x00000003U +#define CACHE_L2_CACHE_PLD_ERR_CODE_M (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S) +#define CACHE_L2_CACHE_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L2_CACHE_PLD_ERR_CODE_S 10 + +/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register + * Cache Sync Reset control register + */ +#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x384) +/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0; + * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L2_CACHE_SYNC_RST (BIT(5)) +#define CACHE_L2_CACHE_SYNC_RST_M (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S) +#define CACHE_L2_CACHE_SYNC_RST_V 0x00000001U +#define CACHE_L2_CACHE_SYNC_RST_S 5 + +/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register + * Cache Preload Reset control register + */ +#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x388) +/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0; + * set this bit to reset preload-logic inside L2-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L2_CACHE_PLD_RST (BIT(5)) +#define CACHE_L2_CACHE_PLD_RST_M (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S) +#define CACHE_L2_CACHE_PLD_RST_V 0x00000001U +#define CACHE_L2_CACHE_PLD_RST_S 5 + +/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register + * Cache Autoload buffer clear control register + */ +#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x38c) +/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0; + * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, + * autoload will not work in L2-Cache. This bit should not be active when autoload + * works in L2-Cache. + */ +#define CACHE_L2_CACHE_ALD_BUF_CLR (BIT(5)) +#define CACHE_L2_CACHE_ALD_BUF_CLR_M (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S) +#define CACHE_L2_CACHE_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L2_CACHE_ALD_BUF_CLR_S 5 + +/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register + * Unallocate request buffer clear registers + */ +#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x390) +/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0; + * The bit is used to clear the unallocate request buffer of l2 icache where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) +#define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) +#define CACHE_L2_CACHE_UNALLOC_CLR_V 0x00000001U +#define CACHE_L2_CACHE_UNALLOC_CLR_S 5 + +/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register + * L1 Cache access Attribute propagation control register + */ +#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x394) +/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1; + * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and + * non-cacheable. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_CC (BIT(0)) +#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S 0 +/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1; + * Set this bit to force the request to l2 cache with write-back attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of write-back and + * write-through. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_WB (BIT(1)) +#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S 1 +/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1; + * Set this bit to force the request to l2 cache with write-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * write-miss-allocate and write-miss-no-allocate. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA (BIT(2)) +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S 2 +/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1; + * Set this bit to force the request to l2 cache with read-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * read-miss-allocate and read-miss-no-allocate. + */ +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA (BIT(3)) +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S) +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V 0x00000001U +#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S 3 + +/** CACHE_L2_CACHE_OBJECT_CTRL_REG register + * Cache Tag and Data memory Object control register + */ +#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x398) +/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0; + * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L2_CACHE_TAG_OBJECT (BIT(5)) +#define CACHE_L2_CACHE_TAG_OBJECT_M (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S) +#define CACHE_L2_CACHE_TAG_OBJECT_V 0x00000001U +#define CACHE_L2_CACHE_TAG_OBJECT_S 5 +/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0; + * Set this bit to set L2-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L2_CACHE_MEM_OBJECT (BIT(11)) +#define CACHE_L2_CACHE_MEM_OBJECT_M (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S) +#define CACHE_L2_CACHE_MEM_OBJECT_V 0x00000001U +#define CACHE_L2_CACHE_MEM_OBJECT_S 11 + +/** CACHE_L2_CACHE_WAY_OBJECT_REG register + * Cache Tag and Data memory way register + */ +#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x39c) +/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ +#define CACHE_L2_CACHE_WAY_OBJECT 0x00000007U +#define CACHE_L2_CACHE_WAY_OBJECT_M (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S) +#define CACHE_L2_CACHE_WAY_OBJECT_V 0x00000007U +#define CACHE_L2_CACHE_WAY_OBJECT_S 0 + +/** CACHE_L2_CACHE_VADDR_REG register + * Cache Vaddr register + */ +#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3a0) +/** CACHE_L2_CACHE_VADDR : HRO; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ +#define CACHE_L2_CACHE_VADDR 0xFFFFFFFFU +#define CACHE_L2_CACHE_VADDR_M (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S) +#define CACHE_L2_CACHE_VADDR_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_VADDR_S 0 + +/** CACHE_L2_CACHE_DEBUG_BUS_REG register + * Cache Tag/data memory content register + */ +#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3a4) +/** CACHE_L2_CACHE_DEBUG_BUS : HRO; bitpos: [31:0]; default: 932; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ +#define CACHE_L2_CACHE_DEBUG_BUS 0xFFFFFFFFU +#define CACHE_L2_CACHE_DEBUG_BUS_M (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S) +#define CACHE_L2_CACHE_DEBUG_BUS_V 0xFFFFFFFFU +#define CACHE_L2_CACHE_DEBUG_BUS_S 0 + +/** CACHE_LEVEL_SPLIT1_REG register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3a8) +/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 936; + * Reserved + */ +#define CACHE_LEVEL_SPLIT1 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT1_M (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S) +#define CACHE_LEVEL_SPLIT1_V 0xFFFFFFFFU +#define CACHE_LEVEL_SPLIT1_S 0 + +/** CACHE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3ac) +/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define CACHE_CLK_EN (BIT(0)) +#define CACHE_CLK_EN_M (CACHE_CLK_EN_V << CACHE_CLK_EN_S) +#define CACHE_CLK_EN_V 0x00000001U +#define CACHE_CLK_EN_S 0 + +/** CACHE_REDUNDANCY_SIG0_REG register + * Cache redundancy signal 0 register + */ +#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3b0) +/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG0 0xFFFFFFFFU +#define CACHE_REDCY_SIG0_M (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S) +#define CACHE_REDCY_SIG0_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG0_S 0 + +/** CACHE_REDUNDANCY_SIG1_REG register + * Cache redundancy signal 1 register + */ +#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3b4) +/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG1 0xFFFFFFFFU +#define CACHE_REDCY_SIG1_M (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S) +#define CACHE_REDCY_SIG1_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG1_S 0 + +/** CACHE_REDUNDANCY_SIG2_REG register + * Cache redundancy signal 2 register + */ +#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3b8) +/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG2 0xFFFFFFFFU +#define CACHE_REDCY_SIG2_M (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S) +#define CACHE_REDCY_SIG2_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG2_S 0 + +/** CACHE_REDUNDANCY_SIG3_REG register + * Cache redundancy signal 3 register + */ +#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3bc) +/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG3 0xFFFFFFFFU +#define CACHE_REDCY_SIG3_M (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S) +#define CACHE_REDCY_SIG3_V 0xFFFFFFFFU +#define CACHE_REDCY_SIG3_S 0 + +/** CACHE_REDUNDANCY_SIG4_REG register + * Cache redundancy signal 0 register + */ +#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3c0) +/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0; + * Those bits are prepared for ECO. + */ +#define CACHE_REDCY_SIG4 0x0000000FU +#define CACHE_REDCY_SIG4_M (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S) +#define CACHE_REDCY_SIG4_V 0x0000000FU +#define CACHE_REDCY_SIG4_S 0 + +/** CACHE_DATE_REG register + * Version control register + */ +#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) +/** CACHE_DATE : R/W; bitpos: [27:0]; default: 35680848; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define CACHE_DATE 0x0FFFFFFFU +#define CACHE_DATE_M (CACHE_DATE_V << CACHE_DATE_S) +#define CACHE_DATE_V 0x0FFFFFFFU +#define CACHE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/cache_struct.h b/components/soc/esp32h2/include/soc/cache_struct.h new file mode 100644 index 0000000000..7398f887ab --- /dev/null +++ b/components/soc/esp32h2/include/soc/cache_struct.h @@ -0,0 +1,5747 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of l1_icache_ctrl register + * L1 instruction Cache(L1-ICache) control register + */ +typedef union { + struct { + /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0; + * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus0:1; + /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0; + * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus1:1; + /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus2:1; + /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus3:1; + /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0; + * Reserved + */ + uint32_t l1_icache_undef_op:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_icache_ctrl_reg_t; + +/** Type of l1_cache_ctrl register + * L1 data Cache(L1-Cache) control register + */ +typedef union { + struct { + /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus0:1; + /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus1:1; + /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus2:1; + /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus3:1; + /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_dma:1; + uint32_t reserved_5:3; + /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0; + * Reserved + */ + uint32_t l1_cache_undef_op:4; + uint32_t reserved_12:20; + }; + uint32_t val; +} cache_l1_cache_ctrl_reg_t; + +/** Type of l2_cache_ctrl register + * L2 Cache(L2-Cache) control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + */ + uint32_t l2_cache_shut_dma:1; + /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0; + * Reserved + */ + uint32_t l2_cache_undef_op:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} cache_l2_cache_ctrl_reg_t; + + +/** Group: Bypass Cache Control and configuration registers */ +/** Type of l1_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache0_en:1; + /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache1_en:1; + /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache2_en:1; + /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache3_en:1; + /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_dcache_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_bypass_cache_conf_reg_t; + +/** Type of l2_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; + * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l2_cache_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_bypass_cache_conf_reg_t; + + +/** Group: Cache Atomic Control and configuration registers */ +/** Type of l1_cache_atomic_conf register + * L1 Cache atomic feature configure register + */ +typedef union { + struct { + /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable atomic feature on L1-Cache when multiple cores access + * L1-Cache. 1: disable, 1: enable. + */ + uint32_t l1_cache_atomic_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cache_l1_cache_atomic_conf_reg_t; + + +/** Group: Cache Mode Control and configuration registers */ +/** Type of l1_icache_cachesize_conf register + * L1 instruction Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1k:1; + /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2k:1; + /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4k:1; + /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_8k:1; + /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_16k:1; + /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_32k:1; + /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_64k:1; + /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_128k:1; + /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_256k:1; + /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_512k:1; + /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1024k:1; + /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2048k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2048k:1; + /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4096k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l1_icache_cachesize_conf_reg_t; + +/** Type of l1_icache_blocksize_conf register + * L1 instruction Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_8:1; + /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_16:1; + /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_32:1; + /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_64:1; + /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_128:1; + /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache_blocksize_conf_reg_t; + +/** Type of l1_cache_cachesize_conf register + * L1 data Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1k:1; + /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2k:1; + /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4k:1; + /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_8k:1; + /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 1; + * The field is used to configure cachesize of L1-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_16k:1; + /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_32k:1; + /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_64k:1; + /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_128k:1; + /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_256k:1; + /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_512k:1; + /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1024k:1; + /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2048k:1; + /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l1_cache_cachesize_conf_reg_t; + +/** Type of l1_cache_blocksize_conf register + * L1 data Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_8:1; + /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_16:1; + /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; + * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_32:1; + /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_64:1; + /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_128:1; + /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_blocksize_conf_reg_t; + +/** Type of l2_cache_cachesize_conf register + * L2 Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1k:1; + /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2k:1; + /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4k:1; + /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_8k:1; + /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_16k:1; + /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_32k:1; + /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_64k:1; + /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_128k:1; + /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_256k:1; + /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_512k:1; + /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1024k:1; + /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2048k:1; + /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_cachesize_conf_reg_t; + +/** Type of l2_cache_blocksize_conf register + * L2 Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_8:1; + /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_16:1; + /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_32:1; + /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_64:1; + /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_128:1; + /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_blocksize_conf_reg_t; + + +/** Group: Wrap Mode Control and configuration registers */ +/** Type of l1_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to enable L1-ICache0 wrap around mode. + */ + uint32_t l1_icache0_wrap:1; + /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to enable L1-ICache1 wrap around mode. + */ + uint32_t l1_icache1_wrap:1; + /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_wrap:1; + /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_wrap:1; + /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ + uint32_t l1_cache_wrap:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_wrap_around_ctrl_reg_t; + +/** Type of l2_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to enable L2-Cache wrap around mode. + */ + uint32_t l2_cache_wrap:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_wrap_around_ctrl_reg_t; + + +/** Group: Cache Tag Memory Power Control registers */ +/** Type of l1_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache0_tag_mem_force_on:1; + /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache0_tag_mem_force_pd:1; + /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache0_tag_mem_force_pu:1; + uint32_t reserved_3:1; + /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache1_tag_mem_force_on:1; + /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache1_tag_mem_force_pd:1; + /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache1_tag_mem_force_pu:1; + uint32_t reserved_7:1; + /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_on:1; + /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_pd:1; + /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_pu:1; + uint32_t reserved_11:1; + /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_on:1; + /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_pd:1; + /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_pu:1; + uint32_t reserved_15:1; + /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_tag_mem_force_on:1; + /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l1_cache_tag_mem_force_pd:1; + /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_tag_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_tag_mem_power_ctrl_reg_t; + +/** Type of l2_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l2_cache_tag_mem_force_on:1; + /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l2_cache_tag_mem_force_pd:1; + /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l2_cache_tag_mem_force_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} cache_l2_cache_tag_mem_power_ctrl_reg_t; + + +/** Group: Cache Data Memory Power Control registers */ +/** Type of l1_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache0_data_mem_force_on:1; + /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache0_data_mem_force_pd:1; + /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache0_data_mem_force_pu:1; + uint32_t reserved_3:1; + /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache1_data_mem_force_on:1; + /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache1_data_mem_force_pd:1; + /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache1_data_mem_force_pu:1; + uint32_t reserved_7:1; + /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_on:1; + /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_pd:1; + /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_pu:1; + uint32_t reserved_11:1; + /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_on:1; + /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_pd:1; + /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_pu:1; + uint32_t reserved_15:1; + /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_data_mem_force_on:1; + /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_cache_data_mem_force_pd:1; + /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_data_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_data_mem_power_ctrl_reg_t; + +/** Type of l2_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l2_cache_data_mem_force_on:1; + /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l2_cache_data_mem_force_pd:1; + /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l2_cache_data_mem_force_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} cache_l2_cache_data_mem_power_ctrl_reg_t; + + +/** Group: Cache Freeze Control registers */ +/** Type of l1_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by + * software. + */ + uint32_t l1_icache0_freeze_en:1; + /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache0_freeze_mode:1; + /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_freeze_done:1; + uint32_t reserved_3:1; + /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by + * software. + */ + uint32_t l1_icache1_freeze_en:1; + /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache1_freeze_mode:1; + /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_freeze_done:1; + uint32_t reserved_7:1; + /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_en:1; + /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_mode:1; + /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_done:1; + uint32_t reserved_11:1; + /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_en:1; + /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_mode:1; + /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_done:1; + uint32_t reserved_15:1; + /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ + uint32_t l1_cache_freeze_en:1; + /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_cache_freeze_mode:1; + /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_freeze_done:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_freeze_ctrl_reg_t; + +/** Type of l2_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable freeze operation on L2-Cache. It can be cleared by + * software. + */ + uint32_t l2_cache_freeze_en:1; + /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; + * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l2_cache_freeze_mode:1; + /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; + * The bit is used to indicate whether freeze operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_freeze_done:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} cache_l2_cache_freeze_ctrl_reg_t; + + +/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Type of l1_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_data_mem_rd_en:1; + /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache0_data_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_data_mem_rd_en:1; + /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache1_data_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_rd_en:1; + /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_rd_en:1; + /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_rd_en:1; + /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_data_mem_acs_conf_reg_t; + +/** Type of l2_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_rd_en:1; + /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} cache_l2_cache_data_mem_acs_conf_reg_t; + + +/** Group: Cache Tag Memory Access Control and Configuration registers */ +/** Type of l1_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_rd_en:1; + /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_rd_en:1; + /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_rd_en:1; + /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_rd_en:1; + /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_rd_en:1; + /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_tag_mem_acs_conf_reg_t; + +/** Type of l2_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_rd_en:1; + /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} cache_l2_cache_tag_mem_acs_conf_reg_t; + + +/** Group: Prelock Control and configuration registers */ +/** Type of l1_icache0_prelock_conf register + * L1 instruction Cache 0 prelock configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct0_en:1; + /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct1_en:1; + /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache0 prelock. + */ + uint32_t l1_icache0_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache0_prelock_conf_reg_t; + +/** Type of l1_icache0_prelock_sct0_addr register + * L1 instruction Cache 0 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache0_prelock_sct0_addr_reg_t; + +/** Type of l1_icache0_prelock_sct1_addr register + * L1 instruction Cache 0 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache0_prelock_sct1_addr_reg_t; + +/** Type of l1_icache0_prelock_sct_size register + * L1 instruction Cache 0 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache0_prelock_sct_size_reg_t; + +/** Type of l1_icache1_prelock_conf register + * L1 instruction Cache 1 prelock configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct0_en:1; + /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct1_en:1; + /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache1 prelock. + */ + uint32_t l1_icache1_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache1_prelock_conf_reg_t; + +/** Type of l1_icache1_prelock_sct0_addr register + * L1 instruction Cache 1 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache1_prelock_sct0_addr_reg_t; + +/** Type of l1_icache1_prelock_sct1_addr register + * L1 instruction Cache 1 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache1_prelock_sct1_addr_reg_t; + +/** Type of l1_icache1_prelock_sct_size register + * L1 instruction Cache 1 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache1_prelock_sct_size_reg_t; + +/** Type of l1_icache2_prelock_conf register + * L1 instruction Cache 2 prelock configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct0_en:1; + /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct1_en:1; + /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache2 prelock. + */ + uint32_t l1_icache2_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache2_prelock_conf_reg_t; + +/** Type of l1_icache2_prelock_sct0_addr register + * L1 instruction Cache 2 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache2_prelock_sct0_addr_reg_t; + +/** Type of l1_icache2_prelock_sct1_addr register + * L1 instruction Cache 2 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache2_prelock_sct1_addr_reg_t; + +/** Type of l1_icache2_prelock_sct_size register + * L1 instruction Cache 2 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache2_prelock_sct_size_reg_t; + +/** Type of l1_icache3_prelock_conf register + * L1 instruction Cache 3 prelock configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct0_en:1; + /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct1_en:1; + /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache3 prelock. + */ + uint32_t l1_icache3_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_icache3_prelock_conf_reg_t; + +/** Type of l1_icache3_prelock_sct0_addr register + * L1 instruction Cache 3 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache3_prelock_sct0_addr_reg_t; + +/** Type of l1_icache3_prelock_sct1_addr register + * L1 instruction Cache 3 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache3_prelock_sct1_addr_reg_t; + +/** Type of l1_icache3_prelock_sct_size register + * L1 instruction Cache 3 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_icache3_prelock_sct_size_reg_t; + +/** Type of l1_cache_prelock_conf register + * L1 Cache prelock configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct0_en:1; + /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct1_en:1; + /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ + uint32_t l1_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_prelock_conf_reg_t; + +/** Type of l1_cache_prelock_sct0_addr register + * L1 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_prelock_sct0_addr_reg_t; + +/** Type of l1_dcache_prelock_sct1_addr register + * L1 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct1_addr_reg_t; + +/** Type of l1_dcache_prelock_sct_size register + * L1 Cache prelock section size configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_cache_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_cache_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct_size_reg_t; + +/** Type of l2_cache_prelock_conf register + * L2 Cache prelock configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct0_en:1; + /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct1_en:1; + /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l2 cache prelock. + */ + uint32_t l2_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_prelock_conf_reg_t; + +/** Type of l2_cache_prelock_sct0_addr register + * L2 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l2_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l2_cache_prelock_sct0_addr_reg_t; + +/** Type of l2_cache_prelock_sct1_addr register + * L2 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l2_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l2_cache_prelock_sct1_addr_reg_t; + +/** Type of l2_cache_prelock_sct_size register + * L2 Cache prelock section size configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l2_cache_prelock_sct0_size:16; + /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; + * Those bits are used to configure the size of the second section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l2_cache_prelock_sct1_size:16; + }; + uint32_t val; +} cache_l2_cache_prelock_sct_size_reg_t; + + +/** Group: Lock Control and configuration registers */ +/** Type of lock_ctrl register + * Lock-class (manual lock) operation control register + */ +typedef union { + struct { + /** lock_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ + uint32_t lock_ena:1; + /** unlock_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ + uint32_t unlock_ena:1; + /** lock_done : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ + uint32_t lock_done:1; + /** lock_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ + uint32_t lock_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_lock_ctrl_reg_t; + +/** Type of lock_map register + * Lock (manual lock) map configure register + */ +typedef union { + struct { + /** lock_map : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ + uint32_t lock_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_lock_map_reg_t; + +/** Type of lock_addr register + * Lock (manual lock) address configure register + */ +typedef union { + struct { + /** lock_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ + uint32_t lock_addr:32; + }; + uint32_t val; +} cache_lock_addr_reg_t; + +/** Type of lock_size register + * Lock (manual lock) size configure register + */ +typedef union { + struct { + /** lock_size : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ + uint32_t lock_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_lock_size_reg_t; + + +/** Group: Sync Control and configuration registers */ +/** Type of sync_ctrl register + * Sync-class operation control register + */ +typedef union { + struct { + /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t invalidate_ena:1; + /** clean_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ + uint32_t clean_ena:1; + /** writeback_ena : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_ena:1; + /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_invalidate_ena:1; + /** sync_done : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ + uint32_t sync_done:1; + /** sync_rgid : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ + uint32_t sync_rgid:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} cache_sync_ctrl_reg_t; + +/** Type of sync_map register + * Sync map configure register + */ +typedef union { + struct { + /** sync_map : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ + uint32_t sync_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_sync_map_reg_t; + +/** Type of sync_addr register + * Sync address configure register + */ +typedef union { + struct { + /** sync_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ + uint32_t sync_addr:32; + }; + uint32_t val; +} cache_sync_addr_reg_t; + +/** Type of sync_size register + * Sync size configure register + */ +typedef union { + struct { + /** sync_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ + uint32_t sync_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_sync_size_reg_t; + + +/** Group: Preload Control and configuration registers */ +/** Type of l1_icache0_preload_ctrl register + * L1 instruction Cache 0 preload-operation control register + */ +typedef union { + struct { + /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache0. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache0_preload_ena:1; + /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache0_preload_done:1; + /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache0_preload_order:1; + /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache0 preload. + */ + uint32_t l1_icache0_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache0_preload_ctrl_reg_t; + +/** Type of l1_icache0_preload_addr register + * L1 instruction Cache 0 preload address configure register + */ +typedef union { + struct { + /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + */ + uint32_t l1_icache0_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache0_preload_addr_reg_t; + +/** Type of l1_icache0_preload_size register + * L1 instruction Cache 0 preload size configure register + */ +typedef union { + struct { + /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + */ + uint32_t l1_icache0_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache0_preload_size_reg_t; + +/** Type of l1_icache1_preload_ctrl register + * L1 instruction Cache 1 preload-operation control register + */ +typedef union { + struct { + /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache1. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache1_preload_ena:1; + /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache1_preload_done:1; + /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache1_preload_order:1; + /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache1 preload. + */ + uint32_t l1_icache1_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache1_preload_ctrl_reg_t; + +/** Type of l1_icache1_preload_addr register + * L1 instruction Cache 1 preload address configure register + */ +typedef union { + struct { + /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + */ + uint32_t l1_icache1_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache1_preload_addr_reg_t; + +/** Type of l1_icache1_preload_size register + * L1 instruction Cache 1 preload size configure register + */ +typedef union { + struct { + /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + */ + uint32_t l1_icache1_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache1_preload_size_reg_t; + +/** Type of l1_icache2_preload_ctrl register + * L1 instruction Cache 2 preload-operation control register + */ +typedef union { + struct { + /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache2. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache2_preload_ena:1; + /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache2_preload_done:1; + /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache2_preload_order:1; + /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache2 preload. + */ + uint32_t l1_icache2_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache2_preload_ctrl_reg_t; + +/** Type of l1_icache2_preload_addr register + * L1 instruction Cache 2 preload address configure register + */ +typedef union { + struct { + /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + */ + uint32_t l1_icache2_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache2_preload_addr_reg_t; + +/** Type of l1_icache2_preload_size register + * L1 instruction Cache 2 preload size configure register + */ +typedef union { + struct { + /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + */ + uint32_t l1_icache2_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache2_preload_size_reg_t; + +/** Type of l1_icache3_preload_ctrl register + * L1 instruction Cache 3 preload-operation control register + */ +typedef union { + struct { + /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache3. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache3_preload_ena:1; + /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache3_preload_done:1; + /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache3_preload_order:1; + /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache3 preload. + */ + uint32_t l1_icache3_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_icache3_preload_ctrl_reg_t; + +/** Type of l1_icache3_preload_addr register + * L1 instruction Cache 3 preload address configure register + */ +typedef union { + struct { + /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + */ + uint32_t l1_icache3_preload_addr:32; + }; + uint32_t val; +} cache_l1_icache3_preload_addr_reg_t; + +/** Type of l1_icache3_preload_size register + * L1 instruction Cache 3 preload size configure register + */ +typedef union { + struct { + /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + */ + uint32_t l1_icache3_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache3_preload_size_reg_t; + +/** Type of l1_cache_preload_ctrl register + * L1 Cache preload-operation control register + */ +typedef union { + struct { + /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_cache_preload_ena:1; + /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_cache_preload_done:1; + /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_cache_preload_order:1; + /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ + uint32_t l1_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_cache_preload_ctrl_reg_t; + +/** Type of l1_dcache_preload_addr register + * L1 Cache preload address configure register + */ +typedef union { + struct { + /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l1_cache_preload_addr:32; + }; + uint32_t val; +} cache_l1_dcache_preload_addr_reg_t; + +/** Type of l1_dcache_preload_size register + * L1 Cache preload size configure register + */ +typedef union { + struct { + /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l1_cache_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_dcache_preload_size_reg_t; + +/** Type of l2_cache_preload_ctrl register + * L2 Cache preload-operation control register + */ +typedef union { + struct { + /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L2-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l2_cache_preload_ena:1; + /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l2_cache_preload_done:1; + /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l2_cache_preload_order:1; + /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l2 cache preload. + */ + uint32_t l2_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l2_cache_preload_ctrl_reg_t; + +/** Type of l2_cache_preload_addr register + * L2 Cache preload address configure register + */ +typedef union { + struct { + /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L2-Cache, + * which should be used together with L2_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l2_cache_preload_addr:32; + }; + uint32_t val; +} cache_l2_cache_preload_addr_reg_t; + +/** Type of l2_cache_preload_size register + * L2 Cache preload size configure register + */ +typedef union { + struct { + /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l2_cache_preload_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_preload_size_reg_t; + + +/** Group: Autoload Control and configuration registers */ +/** Type of l1_icache0_autoload_ctrl register + * L1 instruction Cache 0 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, + * 0: disable. + */ + uint32_t l1_icache0_autoload_ena:1; + /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_autoload_done:1; + /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache0_autoload_order:1; + /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache0. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache0_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct0_ena:1; + /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct1_ena:1; + /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache0 autoload. + */ + uint32_t l1_icache0_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache0_autoload_ctrl_reg_t; + +/** Type of l1_icache0_autoload_sct0_addr register + * L1 instruction Cache 0 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct0_addr_reg_t; + +/** Type of l1_icache0_autoload_sct0_size register + * L1 instruction Cache 0 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct0_size_reg_t; + +/** Type of l1_icache0_autoload_sct1_addr register + * L1 instruction Cache 0 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct1_addr_reg_t; + +/** Type of l1_icache0_autoload_sct1_size register + * L1 instruction Cache 0 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache0_autoload_sct1_size_reg_t; + +/** Type of l1_icache1_autoload_ctrl register + * L1 instruction Cache 1 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, + * 0: disable. + */ + uint32_t l1_icache1_autoload_ena:1; + /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_autoload_done:1; + /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache1_autoload_order:1; + /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache1. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache1_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct0_ena:1; + /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct1_ena:1; + /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache1 autoload. + */ + uint32_t l1_icache1_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache1_autoload_ctrl_reg_t; + +/** Type of l1_icache1_autoload_sct0_addr register + * L1 instruction Cache 1 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct0_addr_reg_t; + +/** Type of l1_icache1_autoload_sct0_size register + * L1 instruction Cache 1 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct0_size_reg_t; + +/** Type of l1_icache1_autoload_sct1_addr register + * L1 instruction Cache 1 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct1_addr_reg_t; + +/** Type of l1_icache1_autoload_sct1_size register + * L1 instruction Cache 1 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache1_autoload_sct1_size_reg_t; + +/** Type of l1_icache2_autoload_ctrl register + * L1 instruction Cache 2 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, + * 0: disable. + */ + uint32_t l1_icache2_autoload_ena:1; + /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache2_autoload_done:1; + /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache2_autoload_order:1; + /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache2. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache2_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct0_ena:1; + /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct1_ena:1; + /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache2 autoload. + */ + uint32_t l1_icache2_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache2_autoload_ctrl_reg_t; + +/** Type of l1_icache2_autoload_sct0_addr register + * L1 instruction Cache 2 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct0_addr_reg_t; + +/** Type of l1_icache2_autoload_sct0_size register + * L1 instruction Cache 2 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct0_size_reg_t; + +/** Type of l1_icache2_autoload_sct1_addr register + * L1 instruction Cache 2 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct1_addr_reg_t; + +/** Type of l1_icache2_autoload_sct1_size register + * L1 instruction Cache 2 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache2_autoload_sct1_size_reg_t; + +/** Type of l1_icache3_autoload_ctrl register + * L1 instruction Cache 3 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, + * 0: disable. + */ + uint32_t l1_icache3_autoload_ena:1; + /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache3_autoload_done:1; + /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache3_autoload_order:1; + /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache3. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache3_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct0_ena:1; + /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct1_ena:1; + /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache3 autoload. + */ + uint32_t l1_icache3_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_icache3_autoload_ctrl_reg_t; + +/** Type of l1_icache3_autoload_sct0_addr register + * L1 instruction Cache 3 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct0_addr_reg_t; + +/** Type of l1_icache3_autoload_sct0_size register + * L1 instruction Cache 3 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct0_size_reg_t; + +/** Type of l1_icache3_autoload_sct1_addr register + * L1 instruction Cache 3 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache3_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct1_addr_reg_t; + +/** Type of l1_icache3_autoload_sct1_size register + * L1 instruction Cache 3 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Reserved + */ + uint32_t l1_icache3_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l1_icache3_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_ctrl register + * L1 Cache autoload-operation control register + */ +typedef union { + struct { + /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ + uint32_t l1_cache_autoload_ena:1; + /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_autoload_done:1; + /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l1_cache_autoload_order:1; + /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct0_ena:1; + /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct1_ena:1; + /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct2_ena:1; + /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct3_ena:1; + /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l1 cache autoload. + */ + uint32_t l1_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l1_cache_autoload_ctrl_reg_t; + +/** Type of l1_cache_autoload_sct0_addr register + * L1 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_addr_reg_t; + +/** Type of l1_cache_autoload_sct0_size register + * L1 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_size_reg_t; + +/** Type of l1_cache_autoload_sct1_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_addr_reg_t; + +/** Type of l1_cache_autoload_sct1_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_sct2_addr register + * L1 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct2_addr_reg_t; + +/** Type of l1_cache_autoload_sct2_size register + * L1 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_size : HRO; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct2_size_reg_t; + +/** Type of l1_cache_autoload_sct3_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct3_addr_reg_t; + +/** Type of l1_cache_autoload_sct3_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_size : HRO; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct3_size_reg_t; + +/** Type of l2_cache_autoload_ctrl register + * L2 Cache autoload-operation control register + */ +typedef union { + struct { + /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, + * 0: disable. + */ + uint32_t l2_cache_autoload_ena:1; + /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_autoload_done:1; + /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L2-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l2_cache_autoload_order:1; + /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l2_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct0_ena:1; + /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct1_ena:1; + /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct2_ena:1; + /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct3_ena:1; + /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l2 cache autoload. + */ + uint32_t l2_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_autoload_ctrl_reg_t; + +/** Type of l2_cache_autoload_sct0_addr register + * L2 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct0_addr_reg_t; + +/** Type of l2_cache_autoload_sct0_size register + * L2 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct0_size_reg_t; + +/** Type of l2_cache_autoload_sct1_addr register + * L2 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct1_addr_reg_t; + +/** Type of l2_cache_autoload_sct1_size register + * L2 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct1_size_reg_t; + +/** Type of l2_cache_autoload_sct2_addr register + * L2 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct2_addr_reg_t; + +/** Type of l2_cache_autoload_sct2_size register + * L2 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct2_size_reg_t; + +/** Type of l2_cache_autoload_sct3_addr register + * L2 Cache autoload section 3 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} cache_l2_cache_autoload_sct3_addr_reg_t; + +/** Type of l2_cache_autoload_sct3_size register + * L2 Cache autoload section 3 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_l2_cache_autoload_sct3_size_reg_t; + + +/** Group: Interrupt registers */ +/** Type of l1_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_ena:1; + /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_ena:1; + /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_ena:1; + /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_ena:1; + /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_ena:1; + /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_ena:1; + /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_ena:1; + /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_ena_reg_t; + +/** Type of l1_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due + * to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_clr:1; + /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due + * to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_clr:1; + /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_clr:1; + /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_clr:1; + /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_clr:1; + /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_clr:1; + /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_clr:1; + /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_clr_reg_t; + +/** Type of l1_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 + * due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_raw:1; + /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 + * due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_raw:1; + /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 + * due to bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_ovf_int_raw:1; + /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 + * due to bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_ovf_int_raw:1; + /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_raw:1; + /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_raw:1; + /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_ovf_int_raw:1; + /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_ovf_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_raw_reg_t; + +/** Type of l1_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_st:1; + /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_st:1; + /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_st:1; + /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_st:1; + /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_st:1; + /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_st:1; + /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_st:1; + /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_st_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_ena:1; + /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_ena:1; + /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_ena:1; + /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_ena:1; + /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_ena_reg_t; + +/** Type of l1_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_clr:1; + /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_clr:1; + /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_clr:1; + /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_clr:1; + /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_clr_reg_t; + +/** Type of l1_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache0. + */ + uint32_t l1_icache0_fail_int_raw:1; + /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache1. + */ + uint32_t l1_icache1_fail_int_raw:1; + /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache2. + */ + uint32_t l1_icache2_fail_int_raw:1; + /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache3. + */ + uint32_t l1_icache3_fail_int_raw:1; + /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ + uint32_t l1_cache_fail_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_raw_reg_t; + +/** Type of l1_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache0_fail_int_st:1; + /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache1_fail_int_st:1; + /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_st:1; + /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_st:1; + /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_st_reg_t; + +/** Type of l1_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache0_pld_done_int_ena:1; + /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache1_pld_done_int_ena:1; + /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_ena:1; + /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_ena:1; + /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_cache_pld_done_int_ena:1; + uint32_t reserved_5:1; + /** sync_done_int_ena : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ + uint32_t sync_done_int_ena:1; + /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_ena:1; + /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_ena:1; + /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_ena:1; + /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_ena:1; + /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_ena:1; + uint32_t reserved_12:1; + /** sync_err_int_ena : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_ena_reg_t; + +/** Type of l1_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_clr:1; + /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_clr:1; + /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_clr:1; + /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_clr:1; + /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ + uint32_t l1_cache_pld_done_int_clr:1; + uint32_t reserved_5:1; + /** sync_done_int_clr : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ + uint32_t sync_done_int_clr:1; + /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; + * The bit is used to clear interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_clr:1; + /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_clr:1; + /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_clr:1; + /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_clr:1; + /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_clr:1; + uint32_t reserved_12:1; + /** sync_err_int_clr : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_clr_reg_t; + +/** Type of l1_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is + * done. + */ + uint32_t l1_icache0_pld_done_int_raw:1; + /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is + * done. + */ + uint32_t l1_icache1_pld_done_int_raw:1; + /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_raw:1; + /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_raw:1; + /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ + uint32_t l1_cache_pld_done_int_raw:1; + uint32_t reserved_5:1; + /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ + uint32_t sync_done_int_raw:1; + /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation + * error occurs. + */ + uint32_t l1_icache0_pld_err_int_raw:1; + /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation + * error occurs. + */ + uint32_t l1_icache1_pld_err_int_raw:1; + /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_raw:1; + /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_raw:1; + /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ + uint32_t l1_cache_pld_err_int_raw:1; + uint32_t reserved_12:1; + /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ + uint32_t sync_err_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_raw_reg_t; + +/** Type of l1_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_st:1; + /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_st:1; + /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_st:1; + /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_st:1; + /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ + uint32_t l1_cache_pld_done_int_st:1; + uint32_t reserved_5:1; + /** sync_done_int_st : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ + uint32_t sync_done_int_st:1; + /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_st:1; + /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_st:1; + /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_st:1; + /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_st:1; + /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_st:1; + uint32_t reserved_12:1; + /** sync_err_int_st : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_int_st_reg_t; + +/** Type of l2_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_ena:1; + /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_ena:1; + /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_ena:1; + /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_ena:1; + /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_ena:1; + /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_ena:1; + /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_ena:1; + /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_ena_reg_t; + +/** Type of l2_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_clr:1; + /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_clr:1; + /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_clr:1; + /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_clr:1; + /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_clr:1; + /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_clr:1; + /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_clr:1; + /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_clr_reg_t; + +/** Type of l2_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-ICache0. + */ + uint32_t l2_ibus0_ovf_int_raw:1; + /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-ICache1. + */ + uint32_t l2_ibus1_ovf_int_raw:1; + /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-ICache2. + */ + uint32_t l2_ibus2_ovf_int_raw:1; + /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-ICache3. + */ + uint32_t l2_ibus3_ovf_int_raw:1; + /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-DCache. + */ + uint32_t l2_dbus0_ovf_int_raw:1; + /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-DCache. + */ + uint32_t l2_dbus1_ovf_int_raw:1; + /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-DCache. + */ + uint32_t l2_dbus2_ovf_int_raw:1; + /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-DCache. + */ + uint32_t l2_dbus3_ovf_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_raw_reg_t; + +/** Type of l2_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_st:1; + /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_st:1; + /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_st:1; + /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_st:1; + /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_st:1; + /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_st:1; + /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_st:1; + /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_int_st_reg_t; + +/** Type of l2_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to + * l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_ena_reg_t; + +/** Type of l2_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 + * cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_clr_reg_t; + +/** Type of l2_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L2-Cache. + */ + uint32_t l2_cache_fail_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_raw_reg_t; + +/** Type of l2_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L2-Cache due + * to l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_acs_fail_int_st_reg_t; + +/** Type of l2_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation done. + */ + uint32_t l2_cache_pld_done_int_ena:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_ena:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_ena_reg_t; + +/** Type of l2_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation + * is done. + */ + uint32_t l2_cache_pld_done_int_clr:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_clr:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_clr_reg_t; + +/** Type of l2_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is + * done. + */ + uint32_t l2_cache_pld_done_int_raw:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error + * occurs. + */ + uint32_t l2_cache_pld_err_int_raw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_raw_reg_t; + +/** Type of l2_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L2-Cache + * preload-operation is done. + */ + uint32_t l2_cache_pld_done_int_st:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the status of the interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_st:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} cache_l2_cache_sync_preload_int_st_reg_t; + + +/** Group: Access Statistics registers */ +/** Type of l1_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_ena:1; + /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_ena:1; + /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_ena:1; + /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_ena:1; + /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_ena:1; + /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_ena:1; + /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_ena:1; + /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_ena:1; + uint32_t reserved_8:8; + /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0; + * The bit is used to clear ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_clr:1; + /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0; + * The bit is used to clear ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_clr:1; + /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_clr:1; + /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_clr:1; + /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_clr:1; + /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_clr:1; + /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_clr:1; + /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_clr:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_ctrl_reg_t; + +/** Type of l1_ibus0_acs_hit_cnt register + * L1-ICache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_hit_cnt_reg_t; + +/** Type of l1_ibus0_acs_miss_cnt register + * L1-ICache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_miss_cnt_reg_t; + +/** Type of l1_ibus0_acs_conflict_cnt register + * L1-ICache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus0_acs_nxtlvl_cnt register + * L1-ICache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l1_ibus0_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_ibus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus1_acs_hit_cnt register + * L1-ICache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_hit_cnt_reg_t; + +/** Type of l1_ibus1_acs_miss_cnt register + * L1-ICache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_miss_cnt_reg_t; + +/** Type of l1_ibus1_acs_conflict_cnt register + * L1-ICache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus1_acs_nxtlvl_cnt register + * L1-ICache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l1_ibus1_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_ibus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus2_acs_hit_cnt register + * L1-ICache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_hit_cnt_reg_t; + +/** Type of l1_ibus2_acs_miss_cnt register + * L1-ICache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_miss_cnt_reg_t; + +/** Type of l1_ibus2_acs_conflict_cnt register + * L1-ICache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus2_acs_nxtlvl_cnt register + * L1-ICache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l1_ibus2_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_ibus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus3_acs_hit_cnt register + * L1-ICache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_hit_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_hit_cnt_reg_t; + +/** Type of l1_ibus3_acs_miss_cnt register + * L1-ICache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_miss_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_miss_cnt_reg_t; + +/** Type of l1_ibus3_acs_conflict_cnt register + * L1-ICache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus3_acs_nxtlvl_cnt register + * L1-ICache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l1_ibus3_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_ibus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_bus0_acs_hit_cnt register + * L1-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_hit_cnt_reg_t; + +/** Type of l1_bus0_acs_miss_cnt register + * L1-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_miss_cnt_reg_t; + +/** Type of l1_bus0_acs_conflict_cnt register + * L1-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_conflict_cnt_reg_t; + +/** Type of l1_bus0_acs_nxtlvl_cnt register + * L1-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_bus1_acs_hit_cnt register + * L1-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_hit_cnt_reg_t; + +/** Type of l1_bus1_acs_miss_cnt register + * L1-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_miss_cnt_reg_t; + +/** Type of l1_bus1_acs_conflict_cnt register + * L1-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_conflict_cnt_reg_t; + +/** Type of l1_bus1_acs_nxtlvl_cnt register + * L1-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ + uint32_t l1_bus1_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_dbus2_acs_hit_cnt register + * L1-DCache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_hit_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_hit_cnt_reg_t; + +/** Type of l1_dbus2_acs_miss_cnt register + * L1-DCache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_miss_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_miss_cnt_reg_t; + +/** Type of l1_dbus2_acs_conflict_cnt register + * L1-DCache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus2_acs_nxtlvl_cnt register + * L1-DCache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l1_dbus2_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_dbus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_dbus3_acs_hit_cnt register + * L1-DCache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_hit_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_hit_cnt_reg_t; + +/** Type of l1_dbus3_acs_miss_cnt register + * L1-DCache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_miss_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_miss_cnt_reg_t; + +/** Type of l1_dbus3_acs_conflict_cnt register + * L1-DCache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus3_acs_nxtlvl_cnt register + * L1-DCache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l1_dbus3_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l1_dbus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_ena:1; + /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_ena:1; + /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_ena:1; + /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_ena:1; + /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_ena:1; + /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_ena:1; + /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_ena:1; + /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_ena:1; + uint32_t reserved_16:8; + /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; + * The bit is used to clear ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_clr:1; + /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; + * The bit is used to clear ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_clr:1; + /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_clr:1; + /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_clr:1; + /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; + * The bit is used to clear dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_clr:1; + /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; + * The bit is used to clear dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_clr:1; + /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_clr:1; + /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_clr:1; + }; + uint32_t val; +} cache_l2_cache_acs_cnt_ctrl_reg_t; + +/** Type of l2_ibus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_hit_cnt_reg_t; + +/** Type of l2_ibus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_miss_cnt_reg_t; + +/** Type of l2_ibus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache0 accesses + * L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus0_acs_nxtlvl_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_ibus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_hit_cnt_reg_t; + +/** Type of l2_ibus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_miss_cnt_reg_t; + +/** Type of l2_ibus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache1 accesses + * L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus1_acs_nxtlvl_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_ibus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_hit_cnt_reg_t; + +/** Type of l2_ibus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_miss_cnt_reg_t; + +/** Type of l2_ibus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache2 accesses + * L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus2_acs_nxtlvl_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_ibus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_hit_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_hit_cnt_reg_t; + +/** Type of l2_ibus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_miss_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_miss_cnt_reg_t; + +/** Type of l2_ibus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache3 accesses + * L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus3_acs_nxtlvl_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_ibus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_hit_cnt_reg_t; + +/** Type of l2_dbus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_miss_cnt_reg_t; + +/** Type of l2_dbus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus0_acs_nxtlvl_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_dbus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_hit_cnt_reg_t; + +/** Type of l2_dbus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_miss_cnt_reg_t; + +/** Type of l2_dbus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus1_acs_nxtlvl_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_dbus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_hit_cnt_reg_t; + +/** Type of l2_dbus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_miss_cnt_reg_t; + +/** Type of l2_dbus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus2_acs_nxtlvl_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_dbus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_hit_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_hit_cnt_reg_t; + +/** Type of l2_dbus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_miss_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_miss_cnt_reg_t; + +/** Type of l2_dbus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_conflict_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus3_acs_nxtlvl_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_nxtlvl_cnt:32; + }; + uint32_t val; +} cache_l2_dbus3_acs_nxtlvl_cnt_reg_t; + + +/** Group: Access Fail Debug registers */ +/** Type of l1_icache0_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_id:16; + /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_id_attr_reg_t; + +/** Type of l1_icache0_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_addr_reg_t; + +/** Type of l1_icache1_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_id:16; + /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_id_attr_reg_t; + +/** Type of l1_icache1_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_addr_reg_t; + +/** Type of l1_icache2_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_id:16; + /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache2_acs_fail_id_attr_reg_t; + +/** Type of l1_icache2_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache2_acs_fail_addr_reg_t; + +/** Type of l1_icache3_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_id:16; + /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache3_acs_fail_id_attr_reg_t; + +/** Type of l1_icache3_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache3_acs_fail_addr_reg_t; + +/** Type of l1_cache_acs_fail_id_attr register + * L1-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_id:16; + /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_attr:16; + }; + uint32_t val; +} cache_l1_cache_acs_fail_id_attr_reg_t; + +/** Type of l1_dcache_acs_fail_addr register + * L1-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_addr:32; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_addr_reg_t; + +/** Type of l2_cache_acs_fail_id_attr register + * L2-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_id:16; + /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when L1-Cache accesses L2-Cache + * due to cache accessing L1-Cache. + */ + uint32_t l2_cache_fail_attr:16; + }; + uint32_t val; +} cache_l2_cache_acs_fail_id_attr_reg_t; + +/** Type of l2_cache_acs_fail_addr register + * L2-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_addr:32; + }; + uint32_t val; +} cache_l2_cache_acs_fail_addr_reg_t; + + +/** Group: Operation Exception registers */ +/** Type of l1_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache0. + */ + uint32_t l1_icache0_pld_err_code:2; + /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache1. + */ + uint32_t l1_icache1_pld_err_code:2; + /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_code:2; + /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_code:2; + /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ + uint32_t l1_cache_pld_err_code:2; + uint32_t reserved_10:2; + /** sync_err_code : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ + uint32_t sync_err_code:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_cache_sync_preload_exception_reg_t; + +/** Type of l2_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; + * The value 2 is Only available which means preload size is error in L2-Cache. + */ + uint32_t l2_cache_pld_err_code:2; + uint32_t reserved_12:20; + }; + uint32_t val; +} cache_l2_cache_sync_preload_exception_reg_t; + + +/** Group: Sync Reset control and configuration registers */ +/** Type of l1_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache0_sync_rst:1; + /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache1_sync_rst:1; + /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_sync_rst:1; + /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_sync_rst:1; + /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_cache_sync_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_sync_rst_ctrl_reg_t; + +/** Type of l2_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l2_cache_sync_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_sync_rst_ctrl_reg_t; + + +/** Group: Preload Reset control and configuration registers */ +/** Type of l1_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache0_pld_rst:1; + /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache1_pld_rst:1; + /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_rst:1; + /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_rst:1; + /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_cache_pld_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_preload_rst_ctrl_reg_t; + +/** Type of l2_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset preload-logic inside L2-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l2_cache_pld_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_preload_rst_ctrl_reg_t; + + +/** Group: Autoload buffer clear control and configuration registers */ +/** Type of l1_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, + * autoload will not work in L1-ICache0. This bit should not be active when autoload + * works in L1-ICache0. + */ + uint32_t l1_icache0_ald_buf_clr:1; + /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, + * autoload will not work in L1-ICache1. This bit should not be active when autoload + * works in L1-ICache1. + */ + uint32_t l1_icache1_ald_buf_clr:1; + /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_ald_buf_clr:1; + /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_ald_buf_clr:1; + /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ + uint32_t l1_cache_ald_buf_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_autoload_buf_clr_ctrl_reg_t; + +/** Type of l2_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; + * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, + * autoload will not work in L2-Cache. This bit should not be active when autoload + * works in L2-Cache. + */ + uint32_t l2_cache_ald_buf_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_cache_autoload_buf_clr_ctrl_reg_t; + + +/** Group: Unallocate request buffer clear registers */ +/** Type of l1_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache0 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache0_unalloc_clr:1; + /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache1 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache1_unalloc_clr:1; + /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_unalloc_clr:1; + /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_unalloc_clr:1; + /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_cache_unalloc_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_unallocate_buffer_clear_reg_t; + +/** Type of l2_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear the unallocate request buffer of l2 icache where the + * unallocate request is responsed but not completed. + */ + uint32_t l2_cache_unalloc_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l2_unallocate_buffer_clear_reg_t; + + +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0; + * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache0_tag_object:1; + /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0; + * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache1_tag_object:1; + /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_object:1; + /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_object:1; + /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_tag_object:1; + uint32_t reserved_5:1; + /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0; + * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache0_mem_object:1; + /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0; + * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache1_mem_object:1; + /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_mem_object:1; + /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache3_mem_object:1; + /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_mem_object:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} cache_l1_cache_object_ctrl_reg_t; + +/** Type of l1_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l1_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} cache_l1_cache_way_object_reg_t; + +/** Type of l1_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l1_cache_vaddr:32; + }; + uint32_t val; +} cache_l1_cache_vaddr_reg_t; + +/** Type of l1_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l1_cache_debug_bus:32; + }; + uint32_t val; +} cache_l1_cache_debug_bus_reg_t; + +/** Type of l2_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; + * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_tag_object:1; + uint32_t reserved_6:5; + /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; + * Set this bit to set L2-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_mem_object:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} cache_l2_cache_object_ctrl_reg_t; + +/** Type of l2_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l2_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} cache_l2_cache_way_object_reg_t; + +/** Type of l2_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l2_cache_vaddr:32; + }; + uint32_t val; +} cache_l2_cache_vaddr_reg_t; + +/** Type of l2_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l2_cache_debug_bus:32; + }; + uint32_t val; +} cache_l2_cache_debug_bus_reg_t; + + +/** Group: Split L1 and L2 registers */ +/** Type of level_split0 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split0 : HRO; bitpos: [31:0]; default: 600; + * Reserved + */ + uint32_t level_split0:32; + }; + uint32_t val; +} cache_level_split0_reg_t; + +/** Type of level_split1 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split1 : HRO; bitpos: [31:0]; default: 936; + * Reserved + */ + uint32_t level_split1:32; + }; + uint32_t val; +} cache_level_split1_reg_t; + + +/** Group: L2 cache access attribute control register */ +/** Type of l2_cache_access_attr_ctrl register + * L1 Cache access Attribute propagation control register + */ +typedef union { + struct { + /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; + * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and + * non-cacheable. + */ + uint32_t l2_cache_access_force_cc:1; + /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; + * Set this bit to force the request to l2 cache with write-back attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of write-back and + * write-through. + */ + uint32_t l2_cache_access_force_wb:1; + /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; + * Set this bit to force the request to l2 cache with write-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * write-miss-allocate and write-miss-no-allocate. + */ + uint32_t l2_cache_access_force_wma:1; + /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; + * Set this bit to force the request to l2 cache with read-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * read-miss-allocate and read-miss-no-allocate. + */ + uint32_t l2_cache_access_force_rma:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} cache_l2_cache_access_attr_ctrl_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cache_clock_gate_reg_t; + + +/** Group: Redundancy register (Prepare for ECO) */ +/** Type of redundancy_sig0 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig0:32; + }; + uint32_t val; +} cache_redundancy_sig0_reg_t; + +/** Type of redundancy_sig1 register + * Cache redundancy signal 1 register + */ +typedef union { + struct { + /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig1:32; + }; + uint32_t val; +} cache_redundancy_sig1_reg_t; + +/** Type of redundancy_sig2 register + * Cache redundancy signal 2 register + */ +typedef union { + struct { + /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig2:32; + }; + uint32_t val; +} cache_redundancy_sig2_reg_t; + +/** Type of redundancy_sig3 register + * Cache redundancy signal 3 register + */ +typedef union { + struct { + /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig3:32; + }; + uint32_t val; +} cache_redundancy_sig3_reg_t; + +/** Type of redundancy_sig4 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** redcy_sig4 : RO; bitpos: [3:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t redcy_sig4:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} cache_redundancy_sig4_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35680848; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_date_reg_t; + + +typedef struct { + volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl; + volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl; + volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; + volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; + volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; + volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; + volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; + volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; + volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; + volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl; + volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl; + volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; + volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; + volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; + volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; + volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; + volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; + volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; + volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; + volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; + volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; + volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; + volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; + volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; + volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; + volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; + volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; + volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; + volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; + volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; + volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; + volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; + volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; + volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile cache_lock_ctrl_reg_t lock_ctrl; + volatile cache_lock_map_reg_t lock_map; + volatile cache_lock_addr_reg_t lock_addr; + volatile cache_lock_size_reg_t lock_size; + volatile cache_sync_ctrl_reg_t sync_ctrl; + volatile cache_sync_map_reg_t sync_map; + volatile cache_sync_addr_reg_t sync_addr; + volatile cache_sync_size_reg_t sync_size; + volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; + volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; + volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size; + volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; + volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; + volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size; + volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; + volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; + volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size; + volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; + volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; + volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size; + volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; + volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; + volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size; + volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; + volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; + volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; + volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; + volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; + volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; + volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; + volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; + volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; + volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; + volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; + volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; + volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; + volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; + volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; + volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; + volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; + volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; + volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; + volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; + volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; + volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; + volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; + volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; + volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; + volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; + volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; + volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; + volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; + volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; + volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; + volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; + volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; + volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; + volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; + volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; + volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; + volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; + volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; + volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; + volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; + volatile cache_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt; + volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; + volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; + volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; + volatile cache_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt; + volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; + volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; + volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; + volatile cache_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt; + volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; + volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; + volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; + volatile cache_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt; + volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; + volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; + volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; + volatile cache_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt; + volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; + volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; + volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; + volatile cache_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt; + volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; + volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; + volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; + volatile cache_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt; + volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; + volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; + volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; + volatile cache_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt; + volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; + volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; + volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; + volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; + volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; + volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; + volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; + volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; + volatile cache_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr; + volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; + volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; + volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; + volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st; + volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception; + volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; + volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; + volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; + volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; + volatile cache_l1_cache_way_object_reg_t l1_cache_way_object; + volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr; + volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus; + volatile cache_level_split0_reg_t level_split0; + volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl; + volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; + volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; + volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; + volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; + volatile cache_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl; + volatile cache_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl; + volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; + volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; + volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; + volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; + volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; + volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; + volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; + volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; + volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr; + volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size; + volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; + volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; + volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; + volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; + volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; + volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; + volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; + volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; + volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; + volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; + volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; + volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; + volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; + volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; + volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; + volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; + volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; + volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; + volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; + volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; + volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; + volatile cache_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt; + volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; + volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; + volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; + volatile cache_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt; + volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; + volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; + volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; + volatile cache_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt; + volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; + volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; + volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; + volatile cache_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt; + volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; + volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; + volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; + volatile cache_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt; + volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; + volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; + volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; + volatile cache_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt; + volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; + volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; + volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; + volatile cache_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt; + volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; + volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; + volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; + volatile cache_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt; + volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; + volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; + volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; + volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; + volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; + volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; + volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; + volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; + volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; + volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; + volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; + volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; + volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; + volatile cache_l2_cache_way_object_reg_t l2_cache_way_object; + volatile cache_l2_cache_vaddr_reg_t l2_cache_vaddr; + volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus; + volatile cache_level_split1_reg_t level_split1; + volatile cache_clock_gate_reg_t clock_gate; + volatile cache_redundancy_sig0_reg_t redundancy_sig0; + volatile cache_redundancy_sig1_reg_t redundancy_sig1; + volatile cache_redundancy_sig2_reg_t redundancy_sig2; + volatile cache_redundancy_sig3_reg_t redundancy_sig3; + volatile cache_redundancy_sig4_reg_t redundancy_sig4; + uint32_t reserved_3c4[14]; + volatile cache_date_reg_t date; +} cache_dev_t; + +extern cache_dev_t CACHE; + +#ifndef __cplusplus +_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/clint_reg.h b/components/soc/esp32h2/include/soc/clint_reg.h new file mode 100644 index 0000000000..828ff818b7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/clint_reg.h @@ -0,0 +1,162 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define DR_REG_CLINT_M_BASE ( 0x20001800) +#define DR_REG_CLINT_U_BASE ( 0x20001C00) + +/*CLINT MINT*/ +#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0) +/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_SIP 0xFFFFFFFF +#define CLINT_CPU_MINT_SIP_M ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S)) +#define CLINT_CPU_MINT_SIP_V 0xFFFFFFFF +#define CLINT_CPU_MINT_SIP_S 0 + +#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4) +/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_MINT_SAMPLING_MODE 0x00000003 +#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) +#define CLINT_MINT_SAMPLING_MODE_V 0x3 +#define CLINT_MINT_SAMPLING_MODE_S 4 +/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_MINT_COUNTER_OVERFLOW_S 3 +/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_TIMERINT_PENDING (BIT(2)) +#define CLINT_MINT_TIMERINT_PENDING_M (BIT(2)) +#define CLINT_MINT_TIMERINT_PENDING_V 0x1 +#define CLINT_MINT_TIMERINT_PENDING_S 2 +/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_TIMERINT_EN (BIT(1)) +#define CLINT_MINT_TIMERINT_EN_M (BIT(1)) +#define CLINT_MINT_TIMERINT_EN_V 0x1 +#define CLINT_MINT_TIMERINT_EN_S 1 +/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_EN (BIT(0)) +#define CLINT_MINT_COUNTER_EN_M (BIT(0)) +#define CLINT_MINT_COUNTER_EN_V 0x1 +#define CLINT_MINT_COUNTER_EN_S 0 + +#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0x8) +/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) +#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_S 0 + +#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xC) +/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) +#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_S 0 + +#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x10) +/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) +#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_S 0 + +#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x14) +/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) +#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_S 0 + +/*CLINT UINT*/ +#define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0) +/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_SIP 0xFFFFFFFF +#define CLINT_CPU_UINT_SIP_M ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S)) +#define CLINT_CPU_UINT_SIP_V 0xFFFFFFFF +#define CLINT_CPU_UINT_SIP_S 0 + +#define CLINT_UINT_TIMECTL_REG (DR_REG_CLINT_U_BASE + 0x4) +/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_UINT_SAMPLING_MODE 0x00000003 +#define CLINT_UINT_SAMPLING_MODE_M ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S)) +#define CLINT_UINT_SAMPLING_MODE_V 0x3 +#define CLINT_UINT_SAMPLING_MODE_S 4 +/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_UINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_UINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_UINT_COUNTER_OVERFLOW_S 3 +/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_TIMERINT_PENDING (BIT(2)) +#define CLINT_UINT_TIMERINT_PENDING_M (BIT(2)) +#define CLINT_UINT_TIMERINT_PENDING_V 0x1 +#define CLINT_UINT_TIMERINT_PENDING_S 2 +/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_TIMERINT_EN (BIT(1)) +#define CLINT_UINT_TIMERINT_EN_M (BIT(1)) +#define CLINT_UINT_TIMERINT_EN_V 0x1 +#define CLINT_UINT_TIMERINT_EN_S 1 +/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_COUNTER_EN (BIT(0)) +#define CLINT_UINT_COUNTER_EN_M (BIT(0)) +#define CLINT_UINT_COUNTER_EN_V 0x1 +#define CLINT_UINT_COUNTER_EN_S 0 + +#define CLINT_UINT_UTIME_L_REG (DR_REG_CLINT_U_BASE + 0x8) +/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S)) +#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_L_S 0 + +#define CLINT_UINT_UTIME_H_REG (DR_REG_CLINT_U_BASE + 0xC) +/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIME_H 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_H_M ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S)) +#define CLINT_CPU_UINT_UTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_H_S 0 + +#define CLINT_UINT_UTIMECMP_L_REG (DR_REG_CLINT_U_BASE + 0x10) +/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_L_M ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S)) +#define CLINT_CPU_UINT_UTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_L_S 0 + +#define CLINT_UINT_UTIMECMP_H_REG (DR_REG_CLINT_U_BASE + 0x14) +/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S)) +#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_H_S 0 +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h new file mode 100644 index 0000000000..4ae491b7af --- /dev/null +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -0,0 +1,343 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "sdkconfig.h" // ESP32H2 TODO: IDF-5973 + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-6265 Copied from C6, need to update +/* + ************************* ESP32H2 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock + * frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description). + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK. + * + * 2) External 40MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the + * XTAL_32K_P pin. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + */ + +/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: APB, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */ + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER/////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#if CONFIG_IDF_ENV_FPGA +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL} +#else +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { + GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if CONFIG_IDF_ENV_FPGA + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#else + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ +#endif +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { + TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group clock source is APB */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */ +} soc_periph_tg_clk_src_legacy_t; + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of RMT + */ +#if CONFIG_IDF_ENV_FPGA +#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL} +#else +#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief Type of RMT clock source + */ +typedef enum { + RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if CONFIG_IDF_ENV_FPGA + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#else + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ +#endif +} soc_periph_rmt_clk_src_t; + +/** + * @brief Type of RMT clock source, reserved for the legacy RMT driver + */ +typedef enum { + RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB */ + RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ +} soc_periph_rmt_clk_src_legacy_t; + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Temperature Sensor + */ +#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of Temp Sensor clock source + */ +typedef enum { + TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +} soc_periph_temperature_sensor_clk_src_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { + UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ +} soc_periph_uart_clk_src_legacy_t; + +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { + MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if CONFIG_IDF_ENV_FPGA + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +#else + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +#endif +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { + MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if CONFIG_IDF_ENV_FPGA + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +#else + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +#endif +} soc_periph_mcpwm_capture_clk_src_t; + +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#if CONFIG_IDF_ENV_FPGA +#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL} +#else +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief I2S clock source enum + */ +typedef enum { +#if CONFIG_IDF_ENV_FPGA + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, +#else + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ +#endif + I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +} soc_periph_i2s_clk_src_t; + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2C + */ +#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of I2C clock source. + */ +typedef enum { + I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, + I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, + I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, +} soc_periph_i2c_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SDM + */ +#define SOC_SDM_CLKS {SOC_MOD_CLK_APB} + +/** + * @brief Sigma Delta Modulator clock source + */ +typedef enum { + SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ +} soc_periph_sdm_clk_src_t; + +//////////////////////////////////////////////////TWAI///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of TWAI + */ +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} + +/** + * @brief TWAI clock source + */ +typedef enum { + TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +} soc_periph_twai_clk_src_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/clkout_channel.h b/components/soc/esp32h2/include/soc/clkout_channel.h new file mode 100644 index 0000000000..dac7b9886b --- /dev/null +++ b/components/soc/esp32h2/include/soc/clkout_channel.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +//CLKOUT channels +// ESP32H2-TODO: IDF-6388 please check +#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 +#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 +#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 +#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 +#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 +#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 diff --git a/components/soc/esp32h2/include/soc/dport_access.h b/components/soc/esp32h2/include/soc/dport_access.h new file mode 100644 index 0000000000..bc42aa9fec --- /dev/null +++ b/components/soc/esp32h2/include/soc/dport_access.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc.h" +#include "uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ds_reg.h b/components/soc/esp32h2/include/soc/ds_reg.h new file mode 100644 index 0000000000..4ca749c1de --- /dev/null +++ b/components/soc/esp32h2/include/soc/ds_reg.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** DS_Y_MEM register + * memory that stores Y + */ +#define DS_Y_MEM (DR_REG_DS_BASE + 0x0) +#define DS_Y_MEM_SIZE_BYTES 512 + +/** DS_M_MEM register + * memory that stores M + */ +#define DS_M_MEM (DR_REG_DS_BASE + 0x200) +#define DS_M_MEM_SIZE_BYTES 512 + +/** DS_RB_MEM register + * memory that stores Rb + */ +#define DS_RB_MEM (DR_REG_DS_BASE + 0x400) +#define DS_RB_MEM_SIZE_BYTES 512 + +/** DS_BOX_MEM register + * memory that stores BOX + */ +#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600) +#define DS_BOX_MEM_SIZE_BYTES 48 + +/** DS_IV_MEM register + * memory that stores IV + */ +#define DS_IV_MEM (DR_REG_DS_BASE + 0x630) +#define DS_IV_MEM_SIZE_BYTES 16 + +/** DS_X_MEM register + * memory that stores X + */ +#define DS_X_MEM (DR_REG_DS_BASE + 0x800) +#define DS_X_MEM_SIZE_BYTES 512 + +/** DS_Z_MEM register + * memory that stores Z + */ +#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00) +#define DS_Z_MEM_SIZE_BYTES 512 + +/** DS_SET_START_REG register + * DS start control register + */ +#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00) +/** DS_SET_START : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ +#define DS_SET_START (BIT(0)) +#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S) +#define DS_SET_START_V 0x00000001U +#define DS_SET_START_S 0 + +/** DS_SET_CONTINUE_REG register + * DS continue control register + */ +#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04) +/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ +#define DS_SET_CONTINUE (BIT(0)) +#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S) +#define DS_SET_CONTINUE_V 0x00000001U +#define DS_SET_CONTINUE_S 0 + +/** DS_SET_FINISH_REG register + * DS finish control register + */ +#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08) +/** DS_SET_FINISH : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ +#define DS_SET_FINISH (BIT(0)) +#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S) +#define DS_SET_FINISH_V 0x00000001U +#define DS_SET_FINISH_S 0 + +/** DS_QUERY_BUSY_REG register + * DS query busy register + */ +#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c) +/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ +#define DS_QUERY_BUSY (BIT(0)) +#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S) +#define DS_QUERY_BUSY_V 0x00000001U +#define DS_QUERY_BUSY_S 0 + +/** DS_QUERY_KEY_WRONG_REG register + * DS query key-wrong counter register + */ +#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10) +/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ +#define DS_QUERY_KEY_WRONG 0x0000000FU +#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S) +#define DS_QUERY_KEY_WRONG_V 0x0000000FU +#define DS_QUERY_KEY_WRONG_S 0 + +/** DS_QUERY_CHECK_REG register + * DS query check result register + */ +#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14) +/** DS_MD_ERROR : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ +#define DS_MD_ERROR (BIT(0)) +#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S) +#define DS_MD_ERROR_V 0x00000001U +#define DS_MD_ERROR_S 0 +/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ +#define DS_PADDING_BAD (BIT(1)) +#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S) +#define DS_PADDING_BAD_V 0x00000001U +#define DS_PADDING_BAD_S 1 + +/** DS_DATE_REG register + * DS version control register + */ +#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20) +/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ +#define DS_DATE 0x3FFFFFFFU +#define DS_DATE_M (DS_DATE_V << DS_DATE_S) +#define DS_DATE_V 0x3FFFFFFFU +#define DS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ds_struct.h b/components/soc/esp32h2/include/soc/ds_struct.h new file mode 100644 index 0000000000..48d5e498ed --- /dev/null +++ b/components/soc/esp32h2/include/soc/ds_struct.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: memory type */ + +/** Group: Control/Status registers */ +/** Type of set_start register + * DS start control register + */ +typedef union { + struct { + /** set_start : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_start_reg_t; + +/** Type of set_continue register + * DS continue control register + */ +typedef union { + struct { + /** set_continue : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ + uint32_t set_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_continue_reg_t; + +/** Type of set_finish register + * DS finish control register + */ +typedef union { + struct { + /** set_finish : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ + uint32_t set_finish:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_finish_reg_t; + +/** Type of query_busy register + * DS query busy register + */ +typedef union { + struct { + /** query_busy : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ + uint32_t query_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_query_busy_reg_t; + +/** Type of query_key_wrong register + * DS query key-wrong counter register + */ +typedef union { + struct { + /** query_key_wrong : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ + uint32_t query_key_wrong:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ds_query_key_wrong_reg_t; + +/** Type of query_check register + * DS query check result register + */ +typedef union { + struct { + /** md_error : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ + uint32_t md_error:1; + /** padding_bad : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ + uint32_t padding_bad:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ds_query_check_reg_t; + + +/** Group: version control register */ +/** Type of date register + * DS version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} ds_date_reg_t; + + +typedef struct { + volatile uint32_t y[128]; + volatile uint32_t m[128]; + volatile uint32_t rb[128]; + volatile uint32_t box[12]; + volatile uint32_t iv[4]; + uint32_t reserved_640[112]; + volatile uint32_t x[128]; + volatile uint32_t z[128]; + uint32_t reserved_c00[128]; + volatile ds_set_start_reg_t set_start; + volatile ds_set_continue_reg_t set_continue; + volatile ds_set_finish_reg_t set_finish; + volatile ds_query_busy_reg_t query_busy; + volatile ds_query_key_wrong_reg_t query_key_wrong; + volatile ds_query_check_reg_t query_check; + uint32_t reserved_e18[2]; + volatile ds_date_reg_t date; +} ds_dev_t; + +extern ds_dev_t DS; + +#ifndef __cplusplus +_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ecc_mult_reg.h b/components/soc/esp32h2/include/soc/ecc_mult_reg.h new file mode 100644 index 0000000000..4060ce107d --- /dev/null +++ b/components/soc/esp32h2/include/soc/ecc_mult_reg.h @@ -0,0 +1,167 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECC_MULT_INT_RAW_REG register + * ECC interrupt raw register, valid in level. + */ +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) +/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +/** ECC_MULT_INT_ST_REG register + * ECC interrupt status register. + */ +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) +/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +/** ECC_MULT_INT_ENA_REG register + * ECC interrupt enable register. + */ +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) +/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +/** ECC_MULT_INT_CLR_REG register + * ECC interrupt clear register. + */ +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) +/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +/** ECC_MULT_CONF_REG register + * ECC configure register + */ +#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) +/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) +#define ECC_MULT_START_V 0x00000001U +#define ECC_MULT_START_S 0 +/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) +#define ECC_MULT_RESET_V 0x00000001U +#define ECC_MULT_RESET_S 1 +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ +#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) +#define ECC_MULT_KEY_LENGTH_V 0x00000001U +#define ECC_MULT_KEY_LENGTH_S 2 +/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0; + * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). + * 1: p(mod base of curve) + */ +#define ECC_MULT_MOD_BASE (BIT(3)) +#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) +#define ECC_MULT_MOD_BASE_V 0x00000001U +#define ECC_MULT_MOD_BASE_S 3 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point + * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point + * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + */ +#define ECC_MULT_WORK_MODE 0x0000000FU +#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) +#define ECC_MULT_WORK_MODE_V 0x0000000FU +#define ECC_MULT_WORK_MODE_S 4 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define ECC_MULT_SECURITY_MODE (BIT(8)) +#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) +#define ECC_MULT_SECURITY_MODE_V 0x00000001U +#define ECC_MULT_SECURITY_MODE_S 8 +/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ +#define ECC_MULT_VERIFICATION_RESULT (BIT(29)) +#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) +#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U +#define ECC_MULT_VERIFICATION_RESULT_S 29 +/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECC_MULT_CLK_EN (BIT(30)) +#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) +#define ECC_MULT_CLK_EN_V 0x00000001U +#define ECC_MULT_CLK_EN_S 30 +/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1; + * ECC memory clock gate force on register + */ +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 + +/** ECC_MULT_DATE_REG register + * Version control register + */ +#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35680640; + * ECC mult version control register + */ +#define ECC_MULT_DATE 0x0FFFFFFFU +#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) +#define ECC_MULT_DATE_V 0x0FFFFFFFU +#define ECC_MULT_DATE_S 0 + +/** ECC_MULT_K_MEM register + * The memory that stores k. + */ +#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) +#define ECC_MULT_K_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PX_MEM register + * The memory that stores Px. + */ +#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) +#define ECC_MULT_PX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PY_MEM register + * The memory that stores Py. + */ +#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) +#define ECC_MULT_PY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ecc_mult_struct.h b/components/soc/esp32h2/include/soc/ecc_mult_struct.h new file mode 100644 index 0000000000..dd71b8b917 --- /dev/null +++ b/components/soc/esp32h2/include/soc/ecc_mult_struct.h @@ -0,0 +1,164 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECC interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_raw_reg_t; + +/** Type of int_st register + * ECC interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_st_reg_t; + +/** Type of int_ena register + * ECC interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_ena_reg_t; + +/** Type of int_clr register + * ECC interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of conf register + * ECC configure register + */ +typedef union { + struct { + /** start : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ + uint32_t start:1; + /** reset : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ + uint32_t reset:1; + /** key_length : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ + uint32_t key_length:1; + /** mod_base : R/W; bitpos: [3]; default: 0; + * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). + * 1: p(mod base of curve) + */ + uint32_t mod_base:1; + /** work_mode : R/W; bitpos: [7:4]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point + * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point + * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + */ + uint32_t work_mode:4; + /** security_mode : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t security_mode:1; + uint32_t reserved_9:20; + /** verification_result : RO/SS; bitpos: [29]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ + uint32_t verification_result:1; + /** clk_en : R/W; bitpos: [30]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1; + * ECC memory clock gate force on register + */ + uint32_t mem_clock_gate_force_on:1; + }; + uint32_t val; +} ecc_mult_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35680640; + * ECC mult version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecc_mult_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile ecc_mult_int_raw_reg_t int_raw; + volatile ecc_mult_int_st_reg_t int_st; + volatile ecc_mult_int_ena_reg_t int_ena; + volatile ecc_mult_int_clr_reg_t int_clr; + volatile ecc_mult_conf_reg_t conf; + uint32_t reserved_020[55]; + volatile ecc_mult_date_reg_t date; + volatile uint32_t k[8]; + volatile uint32_t px[8]; + volatile uint32_t py[8]; +} ecc_mult_dev_t; + +extern ecc_mult_dev_t ECC; + +#ifndef __cplusplus +_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ecdsa_reg.h b/components/soc/esp32h2/include/soc/ecdsa_reg.h new file mode 100644 index 0000000000..b68718ec5d --- /dev/null +++ b/components/soc/esp32h2/include/soc/ecdsa_reg.h @@ -0,0 +1,295 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECDSA_CONF_REG register + * ECDSA configure register + */ +#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) +/** ECDSA_WORK_MODE : R/W; bitpos: [0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Generate Mode. 1: Signature + * Verify Mode. + */ +#define ECDSA_WORK_MODE (BIT(0)) +#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) +#define ECDSA_WORK_MODE_V 0x00000001U +#define ECDSA_WORK_MODE_S 0 +/** ECDSA_ECC_CURVE : R/W; bitpos: [1]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ +#define ECDSA_ECC_CURVE (BIT(1)) +#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) +#define ECDSA_ECC_CURVE_V 0x00000001U +#define ECDSA_ECC_CURVE_S 1 +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [2]; default: 0; + * The source of k select bit. 0: k is automatically generated by TRNG. 1: k is + * written by software. + */ +#define ECDSA_SOFTWARE_SET_K (BIT(2)) +#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) +#define ECDSA_SOFTWARE_SET_K_V 0x00000001U +#define ECDSA_SOFTWARE_SET_K_S 2 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [3]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ +#define ECDSA_SOFTWARE_SET_Z (BIT(3)) +#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) +#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U +#define ECDSA_SOFTWARE_SET_Z_S 3 + +/** ECDSA_CLK_REG register + * ECDSA clock gate register + */ +#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) +/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) +#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) +#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U +#define ECDSA_CLK_GATE_FORCE_ON_S 0 + +/** ECDSA_INT_RAW_REG register + * ECDSA interrupt raw register, valid in level. + */ +#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) +/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_RAW (BIT(0)) +#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S) +#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U +#define ECDSA_CALC_DONE_INT_RAW_S 0 +/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) +#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_RAW_S 1 + +/** ECDSA_INT_ST_REG register + * ECDSA interrupt status register. + */ +#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) +/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_ST (BIT(0)) +#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S) +#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U +#define ECDSA_CALC_DONE_INT_ST_S 0 +/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ST (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) +#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ST_S 1 + +/** ECDSA_INT_ENA_REG register + * ECDSA interrupt enable register. + */ +#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) +/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_ENA (BIT(0)) +#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S) +#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U +#define ECDSA_CALC_DONE_INT_ENA_S 0 +/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) +#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ENA_S 1 + +/** ECDSA_INT_CLR_REG register + * ECDSA interrupt clear register. + */ +#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) +/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_CLR (BIT(0)) +#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S) +#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U +#define ECDSA_CALC_DONE_INT_CLR_S 0 +/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) +#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_CLR_S 1 + +/** ECDSA_START_REG register + * ECDSA start register + */ +#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) +/** ECDSA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ +#define ECDSA_START (BIT(0)) +#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) +#define ECDSA_START_V 0x00000001U +#define ECDSA_START_S 0 +/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_LOAD_DONE (BIT(1)) +#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) +#define ECDSA_LOAD_DONE_V 0x00000001U +#define ECDSA_LOAD_DONE_S 1 +/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_GET_DONE (BIT(2)) +#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) +#define ECDSA_GET_DONE_V 0x00000001U +#define ECDSA_GET_DONE_S 2 + +/** ECDSA_STATE_REG register + * ECDSA status register + */ +#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) +/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ +#define ECDSA_BUSY 0x00000003U +#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) +#define ECDSA_BUSY_V 0x00000003U +#define ECDSA_BUSY_S 0 + +/** ECDSA_RESULT_REG register + * ECDSA result register + */ +#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) +/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ +#define ECDSA_OPERATION_RESULT (BIT(0)) +#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) +#define ECDSA_OPERATION_RESULT_V 0x00000001U +#define ECDSA_OPERATION_RESULT_S 0 + +/** ECDSA_DATE_REG register + * Version control register + */ +#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 35684752; + * ECDSA version control register + */ +#define ECDSA_DATE 0x0FFFFFFFU +#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) +#define ECDSA_DATE_V 0x0FFFFFFFU +#define ECDSA_DATE_S 0 + +/** ECDSA_SHA_MODE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) +/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ +#define ECDSA_SHA_MODE 0x00000007U +#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) +#define ECDSA_SHA_MODE_V 0x00000007U +#define ECDSA_SHA_MODE_S 0 + +/** ECDSA_SHA_START_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) +/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_START (BIT(0)) +#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) +#define ECDSA_SHA_START_V 0x00000001U +#define ECDSA_SHA_START_S 0 + +/** ECDSA_SHA_CONTINUE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) +/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_CONTINUE (BIT(0)) +#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) +#define ECDSA_SHA_CONTINUE_V 0x00000001U +#define ECDSA_SHA_CONTINUE_S 0 + +/** ECDSA_SHA_BUSY_REG register + * ECDSA status register + */ +#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) +/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ +#define ECDSA_SHA_BUSY (BIT(0)) +#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) +#define ECDSA_SHA_BUSY_V 0x00000001U +#define ECDSA_SHA_BUSY_S 0 + +/** ECDSA_MESSAGE_MEM register + * The memory that stores message. + */ +#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 + +/** ECDSA_R_MEM register + * The memory that stores r. + */ +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00) +#define ECDSA_R_MEM_SIZE_BYTES 32 + +/** ECDSA_S_MEM register + * The memory that stores s. + */ +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20) +#define ECDSA_S_MEM_SIZE_BYTES 32 + +/** ECDSA_Z_MEM register + * The memory that stores software written z. + */ +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40) +#define ECDSA_Z_MEM_SIZE_BYTES 32 + +/** ECDSA_QAX_MEM register + * The memory that stores x coordinates of QA or software written k. + */ +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60) +#define ECDSA_QAX_MEM_SIZE_BYTES 32 + +/** ECDSA_QAY_MEM register + * The memory that stores y coordinates of QA. + */ +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80) +#define ECDSA_QAY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ecdsa_struct.h b/components/soc/esp32h2/include/soc/ecdsa_struct.h new file mode 100644 index 0000000000..4693e7e900 --- /dev/null +++ b/components/soc/esp32h2/include/soc/ecdsa_struct.h @@ -0,0 +1,310 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Data Memory */ + +/** Group: Configuration registers */ +/** Type of conf register + * ECDSA configure register + */ +typedef union { + struct { + /** work_mode : R/W; bitpos: [0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Generate Mode. 1: Signature + * Verify Mode. + */ + uint32_t work_mode:1; + /** ecc_curve : R/W; bitpos: [1]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ + uint32_t ecc_curve:1; + /** software_set_k : R/W; bitpos: [2]; default: 0; + * The source of k select bit. 0: k is automatically generated by TRNG. 1: k is + * written by software. + */ + uint32_t software_set_k:1; + /** software_set_z : R/W; bitpos: [3]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ + uint32_t software_set_z:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_conf_reg_t; + +/** Type of start register + * ECDSA start register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ + uint32_t start:1; + /** load_done : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t load_done:1; + /** get_done : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t get_done:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_start_reg_t; + + +/** Group: Clock and reset registers */ +/** Type of clk register + * ECDSA clock gate register + */ +typedef union { + struct { + /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_gate_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECDSA interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_raw_reg_t; + +/** Type of int_st register + * ECDSA interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + /** sha_release_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_st_reg_t; + +/** Type of int_ena register + * ECDSA interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + /** sha_release_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_ena_reg_t; + +/** Type of int_clr register + * ECDSA interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + /** sha_release_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_clr_reg_t; + + +/** Group: Status registers */ +/** Type of state register + * ECDSA status register + */ +typedef union { + struct { + /** busy : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ + uint32_t busy:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * ECDSA result register + */ +typedef union { + struct { + /** operation_result : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ + uint32_t operation_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_result_reg_t; + + +/** Group: SHA register */ +/** Type of sha_mode register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_mode : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ + uint32_t sha_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_sha_mode_reg_t; + +/** Type of sha_start register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_start : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_start_reg_t; + +/** Type of sha_continue register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_continue : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_continue_reg_t; + +/** Type of sha_busy register + * ECDSA status register + */ +typedef union { + struct { + /** sha_busy : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ + uint32_t sha_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_busy_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684752; + * ECDSA version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecdsa_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile ecdsa_conf_reg_t conf; + volatile ecdsa_clk_reg_t clk; + volatile ecdsa_int_raw_reg_t int_raw; + volatile ecdsa_int_st_reg_t int_st; + volatile ecdsa_int_ena_reg_t int_ena; + volatile ecdsa_int_clr_reg_t int_clr; + volatile ecdsa_start_reg_t start; + volatile ecdsa_state_reg_t state; + volatile ecdsa_result_reg_t result; + uint32_t reserved_028[53]; + volatile ecdsa_date_reg_t date; + uint32_t reserved_100[64]; + volatile ecdsa_sha_mode_reg_t sha_mode; + uint32_t reserved_204[3]; + volatile ecdsa_sha_start_reg_t sha_start; + volatile ecdsa_sha_continue_reg_t sha_continue; + volatile ecdsa_sha_busy_reg_t sha_busy; + uint32_t reserved_21c[25]; + volatile uint32_t message[8]; + uint32_t reserved_2a0[472]; + volatile uint32_t r[8]; + volatile uint32_t s[8]; + volatile uint32_t z[8]; + volatile uint32_t qax[8]; + volatile uint32_t qay[8]; +} ecdsa_dev_t; + +extern ecdsa_dev_t ECDSA; + +#ifndef __cplusplus +_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/include/soc/efuse_reg.h new file mode 100644 index 0000000000..e4139bd422 --- /dev/null +++ b/components/soc/esp32h2/include/soc/efuse_reg.h @@ -0,0 +1,2482 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 + +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 + +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_S 0 + +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_WR_DIS_S 0 + +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_4 (BIT(7)) +#define EFUSE_RPT4_RESERVED0_4_M (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S) +#define EFUSE_RPT4_RESERVED0_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_4_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + */ +#define EFUSE_POWERGLITCH_EN (BIT(10)) +#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) +#define EFUSE_POWERGLITCH_EN_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 +/** EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_CAN (BIT(14)) +#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) +#define EFUSE_DIS_CAN_V 0x00000001U +#define EFUSE_DIS_CAN_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_M (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S) +#define EFUSE_RPT4_RESERVED0_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_S 27 +/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_1_M (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S) +#define EFUSE_RPT4_RESERVED0_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_1_S 29 +/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_M (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S) +#define EFUSE_RPT4_RESERVED0_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_S 30 + +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_1 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_1_M (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S) +#define EFUSE_RPT4_RESERVED1_1_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_1_S 0 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 + +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ +#define EFUSE_SEC_DPA_LEVEL 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) +#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_S 16 +/** EFUSE_ECDSA_FORCE_USE_HARDWARE_K : RO; bitpos: [18]; default: 1; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. + */ +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K (BIT(18)) +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_M (EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V << EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S) +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V 0x00000001U +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ +#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) +#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_S 19 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_M (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S) +#define EFUSE_RPT4_RESERVED2_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_S 22 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 + +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ +#define EFUSE_DIS_USB_PRINT (BIT(2)) +#define EFUSE_DIS_USB_PRINT_M (EFUSE_DIS_USB_PRINT_V << EFUSE_DIS_USB_PRINT_S) +#define EFUSE_DIS_USB_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_PRINT_S 2 +/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_5_M (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S) +#define EFUSE_RPT4_RESERVED3_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_5_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 8 +/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 +/** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ +#define EFUSE_HYS_EN_PAD0 0x0000003FU +#define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S) +#define EFUSE_HYS_EN_PAD0_V 0x0000003FU +#define EFUSE_HYS_EN_PAD0_S 26 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ +#define EFUSE_HYS_EN_PAD1 0x003FFFFFU +#define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S) +#define EFUSE_HYS_EN_PAD1_V 0x003FFFFFU +#define EFUSE_HYS_EN_PAD1_S 0 +/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_1 0x00000003U +#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S) +#define EFUSE_RPT4_RESERVED4_1_V 0x00000003U +#define EFUSE_RPT4_RESERVED4_1_S 22 +/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_M (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S) +#define EFUSE_RPT4_RESERVED4_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_S 24 + +/** EFUSE_RD_MAC_SYS_0_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU +#define EFUSE_MAC_0_S 0 + +/** EFUSE_RD_MAC_SYS_1_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 + +/** EFUSE_RD_MAC_SYS_2_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_S 0 +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_0 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_S 14 + +/** EFUSE_RD_MAC_SYS_3_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/** EFUSE_RD_MAC_SYS_4_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/** EFUSE_RD_MAC_SYS_5_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/** EFUSE_RD_USR_DATA0_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU +#define EFUSE_USR_DATA0_S 0 + +/** EFUSE_RD_USR_DATA1_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU +#define EFUSE_USR_DATA1_S 0 + +/** EFUSE_RD_USR_DATA2_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU +#define EFUSE_USR_DATA2_S 0 + +/** EFUSE_RD_USR_DATA3_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU +#define EFUSE_USR_DATA3_S 0 + +/** EFUSE_RD_USR_DATA4_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU +#define EFUSE_USR_DATA4_S 0 + +/** EFUSE_RD_USR_DATA5_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU +#define EFUSE_USR_DATA5_S 0 + +/** EFUSE_RD_USR_DATA6_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 + +/** EFUSE_RD_USR_DATA7_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_S 0 + +/** EFUSE_RD_KEY0_DATA1_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_S 0 + +/** EFUSE_RD_KEY0_DATA2_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_S 0 + +/** EFUSE_RD_KEY0_DATA3_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_S 0 + +/** EFUSE_RD_KEY0_DATA4_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_S 0 + +/** EFUSE_RD_KEY0_DATA5_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_S 0 + +/** EFUSE_RD_KEY0_DATA6_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_S 0 + +/** EFUSE_RD_KEY0_DATA7_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_S 0 + +/** EFUSE_RD_KEY1_DATA0_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_S 0 + +/** EFUSE_RD_KEY1_DATA1_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_S 0 + +/** EFUSE_RD_KEY1_DATA2_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_S 0 + +/** EFUSE_RD_KEY1_DATA3_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_S 0 + +/** EFUSE_RD_KEY1_DATA4_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_S 0 + +/** EFUSE_RD_KEY1_DATA5_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_S 0 + +/** EFUSE_RD_KEY1_DATA6_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_S 0 + +/** EFUSE_RD_KEY1_DATA7_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_S 0 + +/** EFUSE_RD_KEY2_DATA0_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_S 0 + +/** EFUSE_RD_KEY2_DATA1_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_S 0 + +/** EFUSE_RD_KEY2_DATA2_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_S 0 + +/** EFUSE_RD_KEY2_DATA3_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_S 0 + +/** EFUSE_RD_KEY2_DATA4_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_S 0 + +/** EFUSE_RD_KEY2_DATA5_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_S 0 + +/** EFUSE_RD_KEY2_DATA6_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_S 0 + +/** EFUSE_RD_KEY2_DATA7_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_S 0 + +/** EFUSE_RD_KEY3_DATA0_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_S 0 + +/** EFUSE_RD_KEY3_DATA1_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_S 0 + +/** EFUSE_RD_KEY3_DATA2_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_S 0 + +/** EFUSE_RD_KEY3_DATA3_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_S 0 + +/** EFUSE_RD_KEY3_DATA4_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_S 0 + +/** EFUSE_RD_KEY3_DATA5_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_S 0 + +/** EFUSE_RD_KEY3_DATA6_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_S 0 + +/** EFUSE_RD_KEY3_DATA7_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_S 0 + +/** EFUSE_RD_KEY4_DATA0_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_S 0 + +/** EFUSE_RD_KEY4_DATA1_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_S 0 + +/** EFUSE_RD_KEY4_DATA2_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_S 0 + +/** EFUSE_RD_KEY4_DATA3_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_S 0 + +/** EFUSE_RD_KEY4_DATA4_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_S 0 + +/** EFUSE_RD_KEY4_DATA5_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_S 0 + +/** EFUSE_RD_KEY4_DATA6_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_S 0 + +/** EFUSE_RD_KEY4_DATA7_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_S 0 + +/** EFUSE_RD_KEY5_DATA0_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_S 0 + +/** EFUSE_RD_KEY5_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_S 0 + +/** EFUSE_RD_KEY5_DATA2_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_S 0 + +/** EFUSE_RD_KEY5_DATA3_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_S 0 + +/** EFUSE_RD_KEY5_DATA4_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_S 0 + +/** EFUSE_RD_KEY5_DATA5_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_S 0 + +/** EFUSE_RD_KEY5_DATA6_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_S 0 + +/** EFUSE_RD_KEY5_DATA7_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_S 0 + +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_4 (BIT(7)) +#define EFUSE_RPT4_RESERVED0_ERR_4_M (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S) +#define EFUSE_RPT4_RESERVED0_ERR_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_4_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; + * Indicates a programming error of POWERGLITCH_EN. + */ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) +#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U +#define EFUSE_POWERGLITCH_EN_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 +/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) +#define EFUSE_DIS_TWAI_ERR_V 0x00000001U +#define EFUSE_DIS_TWAI_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_M (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S) +#define EFUSE_RPT4_RESERVED0_ERR_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_S 27 +/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_ERR_1_M (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S) +#define EFUSE_RPT4_RESERVED0_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_1_S 29 +/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_M (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S) +#define EFUSE_RPT4_RESERVED0_ERR_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_S 30 + +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR_0 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_M (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S) +#define EFUSE_RPT4_RESERVED1_ERR_0_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_S 0 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 +/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR_1 (BIT(18)) +#define EFUSE_RPT4_RESERVED2_ERR_1_M (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S) +#define EFUSE_RPT4_RESERVED2_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED2_ERR_1_S 18 +/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ +#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_M (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S) +#define EFUSE_RPT4_RESERVED2_ERR_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_S 22 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ +#define EFUSE_USB_PRINT_ERR (BIT(2)) +#define EFUSE_USB_PRINT_ERR_M (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S) +#define EFUSE_USB_PRINT_ERR_V 0x00000001U +#define EFUSE_USB_PRINT_ERR_S 2 +/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_5_M (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S) +#define EFUSE_RPT4_RESERVED3_ERR_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_5_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 +/** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0; + * Indicates a programming error of HYS_EN_PAD0. + */ +#define EFUSE_HYS_EN_PAD0_ERR 0x0000003FU +#define EFUSE_HYS_EN_PAD0_ERR_M (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S) +#define EFUSE_HYS_EN_PAD0_ERR_V 0x0000003FU +#define EFUSE_HYS_EN_PAD0_ERR_S 26 + +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +/** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0; + * Indicates a programming error of HYS_EN_PAD1. + */ +#define EFUSE_HYS_EN_PAD1_ERR 0x003FFFFFU +#define EFUSE_HYS_EN_PAD1_ERR_M (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S) +#define EFUSE_HYS_EN_PAD1_ERR_V 0x003FFFFFU +#define EFUSE_HYS_EN_PAD1_ERR_S 0 +/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR_1 0x00000003U +#define EFUSE_RPT4_RESERVED4_ERR_1_M (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S) +#define EFUSE_RPT4_RESERVED4_ERR_1_V 0x00000003U +#define EFUSE_RPT4_RESERVED4_ERR_1_S 22 +/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_M (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S) +#define EFUSE_RPT4_RESERVED4_ERR_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_S 24 + +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 + +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 + +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 + +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 + +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U +#define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 + +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U +#define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U +#define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U +#define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U +#define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 + +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU +#define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 + +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU +#define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 + +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 + +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ +#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U +#define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/include/soc/efuse_struct.h new file mode 100644 index 0000000000..28a76865aa --- /dev/null +++ b/components/soc/esp32h2/include/soc/efuse_struct.h @@ -0,0 +1,2295 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: ******** Registers */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t rd_dis:7; + /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_4:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_jtag:1; + /** powerglitch_en : RO; bitpos: [10]; default: 0; + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + */ + uint32_t powerglitch_en:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t spi_download_mspi_dis:1; + /** dis_can : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_can:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ + uint32_t vdd_spi_as_gpio:1; + /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_2:2; + /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_1:1; + /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_0:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_1:16; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t sec_dpa_level:2; + /** ecdsa_force_use_hardware_k : RO; bitpos: [18]; default: 1; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. + */ + uint32_t ecdsa_force_use_hardware_k:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ + uint32_t crypt_dpa_enable:1; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_0:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ + uint32_t dis_usb_print:1; + /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_5:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ + uint32_t hys_en_pad0:6; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ + uint32_t hys_en_pad1:22; + /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_1:2; + /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_0:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_sys_0 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys_0_reg_t; + +/** Type of rd_mac_sys_1 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys_1_reg_t; + +/** Type of rd_mac_sys_2 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_1:14; + /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_0:18; + }; + uint32_t val; +} efuse_rd_mac_sys_2_reg_t; + +/** Type of rd_mac_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys_3_reg_t; + +/** Type of rd_mac_sys_4 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys_4_reg_t; + +/** Type of rd_mac_sys_5 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_0:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data6:32; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ + uint32_t usr_data7:32; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ + uint32_t rd_dis_err:7; + /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_4:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ + uint32_t dis_usb_jtag_err:1; + /** powerglitch_en_err : RO; bitpos: [10]; default: 0; + * Indicates a programming error of POWERGLITCH_EN. + */ + uint32_t powerglitch_en_err:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ + uint32_t dis_usb_serial_jtag_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ + uint32_t spi_download_mspi_dis_err:1; + /** dis_twai_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ + uint32_t dis_twai_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ + uint32_t vdd_spi_as_gpio_err:1; + /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_2:2; + /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_1:1; + /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_0:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err_0:16; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_level_err:2; + /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_err_1:1; + /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ + uint32_t crypt_dpa_enable_err:1; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_err_0:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ + uint32_t dis_direct_boot_err:1; + /** usb_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ + uint32_t usb_print_err:1; + /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_5:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ + uint32_t secure_version_err:16; + /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ + uint32_t secure_boot_disable_fast_wake_err:1; + /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0; + * Indicates a programming error of HYS_EN_PAD0. + */ + uint32_t hys_en_pad0_err:6; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0; + * Indicates a programming error of HYS_EN_PAD1. + */ + uint32_t hys_en_pad1_err:22; + /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err_1:2; + /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err_0:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ + uint32_t op_code:16; + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_190[12]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h new file mode 100644 index 0000000000..6b56344174 --- /dev/null +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _CACHE_MEMORY_H_ +#define _CACHE_MEMORY_H_ + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*IRAM0 is connected with Cache IBUS0*/ +#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 128)) // MMU has 256 pages, first 128 for instruction +#define IRAM0_ADDRESS_LOW 0x40000000 +#define IRAM0_ADDRESS_HIGH(page_size) IRAM0_CACHE_ADDRESS_HIGH(page_size) + +/*DRAM0 is connected with Cache DBUS0*/ +#define DRAM0_ADDRESS_LOW 0x42000000 +#define DRAM0_ADDRESS_HIGH 0x43000000 +#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE) // ESP32H2-TODO : IDF-6370 +#define DRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_HIGH(page_size) + ((page_size) * 128)) // MMU has 256 pages, second 128 for data +#define DRAM0_CACHE_OPERATION_HIGH(page_size) DRAM0_CACHE_ADDRESS_HIGH(page_size) +#define ESP_CACHE_TEMP_ADDR 0x42000000 + +#define BUS_SIZE(bus_name, page_size) (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW) +#define ADDRESS_IN_BUS(bus_name, vaddr, page_size) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size)) + +#define ADDRESS_IN_IRAM0(vaddr, page_size) ADDRESS_IN_BUS(IRAM0, vaddr, page_size) +#define ADDRESS_IN_IRAM0_CACHE(vaddr, page_size) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr, page_size) +#define ADDRESS_IN_DRAM0(vaddr, page_size) ADDRESS_IN_BUS(DRAM0, vaddr, page_size) +#define ADDRESS_IN_DRAM0_CACHE(vaddr, page_size) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr, page_size) + +#define BUS_IRAM0_CACHE_SIZE(page_size) BUS_SIZE(IRAM0_CACHE, page_size) +#define BUS_DRAM0_CACHE_SIZE(page_size) BUS_SIZE(DRAM0_CACHE, page_size) + +#define CACHE_IBUS 0 +#define CACHE_IBUS_MMU_START 0 +#define CACHE_IBUS_MMU_END 0x200 + +#define CACHE_DBUS 1 +#define CACHE_DBUS_MMU_START 0 +#define CACHE_DBUS_MMU_END 0x200 + +//TODO, remove these cache function dependencies +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define ICACHE_MMU_SIZE 0x200 +#define DCACHE_MMU_SIZE 0x200 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x200 + +#define MMU_MSPI_ACCESS_FLASH 0 +#define MMU_MSPI_VALID BIT(9) +#define MMU_MSPI_INVALID 0 +#define MMU_MSPI_SENSITIVE BIT(10) + +#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH +#define MMU_ACCESS_SPIRAM MMU_MSPI_ACCESS_SPIRAM +#define MMU_VALID MMU_MSPI_VALID +#define MMU_SENSITIVE MMU_MSPI_SENSITIVE + +// ESP32H2-TODO : IDF-6251 +#define MMU_INVALID_MASK MMU_MSPI_VALID +#define MMU_INVALID MMU_MSPI_INVALID + + + +#define CACHE_MAX_SYNC_NUM 0x400000 +#define CACHE_MAX_LOCK_NUM 0x8000 + +#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) +#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define MMU_VALID_VAL_MASK 0x1ff +/** + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define MMU_MAX_PADDR_PAGE_NUM 256 +//MMU entry num +#define MMU_ENTRY_NUM 256 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & MMU_VADDR_MASK + */ +#define MMU_VADDR_MASK(page_size) ((page_size) * MMU_ENTRY_NUM - 1) + +#define CACHE_MEMORY_IBANK0_ADDR 0x40800000 + +#ifdef __cplusplus +} +#endif + +#endif /*_CACHE_MEMORY_H_ */ diff --git a/components/soc/esp32h2/include/soc/extmem_reg.h b/components/soc/esp32h2/include/soc/extmem_reg.h new file mode 100644 index 0000000000..42cea3bdb3 --- /dev/null +++ b/components/soc/esp32h2/include/soc/extmem_reg.h @@ -0,0 +1,951 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-5797 + +#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) + +#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) +/* EXTMEM_DCACHE_SHUT_DBUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable.*/ +#define EXTMEM_DCACHE_SHUT_DBUS1 (BIT(1)) +#define EXTMEM_DCACHE_SHUT_DBUS1_M (BIT(1)) +#define EXTMEM_DCACHE_SHUT_DBUS1_V 0x1 +#define EXTMEM_DCACHE_SHUT_DBUS1_S 1 +/* EXTMEM_DCACHE_SHUT_DBUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable.*/ +#define EXTMEM_DCACHE_SHUT_DBUS0 (BIT(0)) +#define EXTMEM_DCACHE_SHUT_DBUS0_M (BIT(0)) +#define EXTMEM_DCACHE_SHUT_DBUS0_V 0x1 +#define EXTMEM_DCACHE_SHUT_DBUS0_S 0 + +#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) +/* EXTMEM_DCACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/ +#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(4)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(4)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 4 + +#define EXTMEM_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) +/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power u +p.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(18)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 18 +/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power + down.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 17 +/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, + 0: open clock gating..*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 16 + +#define EXTMEM_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) +/* EXTMEM_DCACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power +up.*/ +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_M (BIT(18)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_S 18 +/* EXTMEM_DCACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: powe +r down.*/ +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_M (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_S 17 +/* EXTMEM_DCACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-DCache data memory. 1: close gating +, 0: open clock gating..*/ +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_M (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_S 16 + +#define EXTMEM_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) +/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ +/*description: The bit is used to indicate whether freeze operation on L1-DCache is finished or + not. 0: not finished. 1: finished..*/ +#define EXTMEM_DCACHE_FREEZE_DONE (BIT(18)) +#define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(18)) +#define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 +#define EXTMEM_DCACHE_FREEZE_DONE_S 18 +/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-acces +s will not stuck. 1: a miss-access will stuck..*/ +#define EXTMEM_DCACHE_FREEZE_MODE (BIT(17)) +#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(17)) +#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 +#define EXTMEM_DCACHE_FREEZE_MODE_S 17 +/* EXTMEM_DCACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: The bit is used to enable freeze operation on L1-DCache. It can be cleared by so +ftware..*/ +#define EXTMEM_DCACHE_FREEZE_EN (BIT(16)) +#define EXTMEM_DCACHE_FREEZE_EN_M (BIT(16)) +#define EXTMEM_DCACHE_FREEZE_EN_V 0x1 +#define EXTMEM_DCACHE_FREEZE_EN_S 16 + +#define EXTMEM_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) +/* EXTMEM_DCACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, + 1: enable..*/ +#define EXTMEM_DCACHE_DATA_MEM_WR_EN (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_WR_EN_M (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_WR_EN_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_WR_EN_S 17 +/* EXTMEM_DCACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, +1: enable..*/ +#define EXTMEM_DCACHE_DATA_MEM_RD_EN (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_RD_EN_M (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_RD_EN_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_RD_EN_S 16 + +#define EXTMEM_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) +/* EXTMEM_DCACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, +1: enable..*/ +#define EXTMEM_DCACHE_TAG_MEM_WR_EN (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_WR_EN_M (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_WR_EN_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_WR_EN_S 17 +/* EXTMEM_DCACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1 +: enable..*/ +#define EXTMEM_DCACHE_TAG_MEM_RD_EN (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_RD_EN_M (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_RD_EN_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_RD_EN_S 16 + +#define EXTMEM_DCACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) +/* EXTMEM_DCACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 dcache prelock..*/ +#define EXTMEM_DCACHE_PRELOCK_RGID 0x0000000F +#define EXTMEM_DCACHE_PRELOCK_RGID_M ((EXTMEM_DCACHE_PRELOCK_RGID_V)<<(EXTMEM_DCACHE_PRELOCK_RGID_S)) +#define EXTMEM_DCACHE_PRELOCK_RGID_V 0xF +#define EXTMEM_DCACHE_PRELOCK_RGID_S 2 +/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function on L1-DCache..*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 +/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function on L1-DCache..*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) +/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the first section +of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SC +T0_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) +/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the second section + of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_S +CT1_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) +/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ +/*description: Those bits are used to configure the size of the second section of prelock on L1 +-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x00003FFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x3FFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 16 +/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ +/*description: Those bits are used to configure the size of the first section of prelock on L1- +DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x00003FFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x3FFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 0 + +#define EXTMEM_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) +/* EXTMEM_CACHE_LOCK_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of cache lock/unlock..*/ +#define EXTMEM_CACHE_LOCK_RGID 0x0000000F +#define EXTMEM_CACHE_LOCK_RGID_M ((EXTMEM_CACHE_LOCK_RGID_V)<<(EXTMEM_CACHE_LOCK_RGID_S)) +#define EXTMEM_CACHE_LOCK_RGID_V 0xF +#define EXTMEM_CACHE_LOCK_RGID_S 3 +/* EXTMEM_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0: + not finished. 1: finished..*/ +#define EXTMEM_CACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_CACHE_LOCK_DONE_M (BIT(2)) +#define EXTMEM_CACHE_LOCK_DONE_V 0x1 +#define EXTMEM_CACHE_LOCK_DONE_S 2 +/* EXTMEM_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared by hardware after + unlock operation done. Note that (1) this bit and lock_ena bit are mutually exc +lusive, that is, those bits can not be set to 1 at the same time. (2) unlock ope +ration can be applied on L1-ICache, L1-DCache and L2-Cache..*/ +#define EXTMEM_CACHE_UNLOCK_ENA (BIT(1)) +#define EXTMEM_CACHE_UNLOCK_ENA_M (BIT(1)) +#define EXTMEM_CACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_CACHE_UNLOCK_ENA_S 1 +/* EXTMEM_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared by hardware after l +ock operation done. Note that (1) this bit and unlock_ena bit are mutually exclu +sive, that is, those bits can not be set to 1 at the same time. (2) lock operati +on can be applied on LL1-ICache, L1-DCache and L2-Cache..*/ +#define EXTMEM_CACHE_LOCK_ENA (BIT(0)) +#define EXTMEM_CACHE_LOCK_ENA_M (BIT(0)) +#define EXTMEM_CACHE_LOCK_ENA_V 0x1 +#define EXTMEM_CACHE_LOCK_ENA_S 0 + +#define EXTMEM_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) +/* EXTMEM_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: Those bits are used to indicate which caches in the two-level cache structure wi +ll apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-I +Cache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ +#define EXTMEM_CACHE_LOCK_MAP 0x0000003F +#define EXTMEM_CACHE_LOCK_MAP_M ((EXTMEM_CACHE_LOCK_MAP_V)<<(EXTMEM_CACHE_LOCK_MAP_S)) +#define EXTMEM_CACHE_LOCK_MAP_V 0x3F +#define EXTMEM_CACHE_LOCK_MAP_S 0 + +#define EXTMEM_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) +/* EXTMEM_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the lock/unlock op +eration, which should be used together with CACHE_LOCK_SIZE_REG.*/ +#define EXTMEM_CACHE_LOCK_ADDR 0xFFFFFFFF +#define EXTMEM_CACHE_LOCK_ADDR_M ((EXTMEM_CACHE_LOCK_ADDR_V)<<(EXTMEM_CACHE_LOCK_ADDR_S)) +#define EXTMEM_CACHE_LOCK_ADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_LOCK_ADDR_S 0 + +#define EXTMEM_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) +/* EXTMEM_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: Those bits are used to configure the size of the lock/unlock operation, which sh +ould be used together with CACHE_LOCK_ADDR_REG.*/ +#define EXTMEM_CACHE_LOCK_SIZE 0x0000FFFF +#define EXTMEM_CACHE_LOCK_SIZE_M ((EXTMEM_CACHE_LOCK_SIZE_V)<<(EXTMEM_CACHE_LOCK_SIZE_S)) +#define EXTMEM_CACHE_LOCK_SIZE_V 0xFFFF +#define EXTMEM_CACHE_LOCK_SIZE_S 0 + +#define EXTMEM_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) +/* EXTMEM_CACHE_SYNC_RGID : HRO ;bitpos:[8:5] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of cache sync operation (invalidate, clean, writ +eback, writeback_invalidate).*/ +#define EXTMEM_CACHE_SYNC_RGID 0x0000000F +#define EXTMEM_CACHE_SYNC_RGID_M ((EXTMEM_CACHE_SYNC_RGID_V)<<(EXTMEM_CACHE_SYNC_RGID_S)) +#define EXTMEM_CACHE_SYNC_RGID_V 0xF +#define EXTMEM_CACHE_SYNC_RGID_S 5 +/* EXTMEM_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback +, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/ +#define EXTMEM_CACHE_SYNC_DONE (BIT(4)) +#define EXTMEM_CACHE_SYNC_DONE_M (BIT(4)) +#define EXTMEM_CACHE_SYNC_DONE_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_S 4 +/* EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by +hardware after writeback-invalidate operation done. Note that this bit and the o +ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive +, that is, those bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/* EXTMEM_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to enable writeback operation. It will be cleared by hardware af +ter writeback operation done. Note that this bit and the other sync-bits (invali +date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, +those bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_WRITEBACK_ENA (BIT(2)) +#define EXTMEM_CACHE_WRITEBACK_ENA_M (BIT(2)) +#define EXTMEM_CACHE_WRITEBACK_ENA_V 0x1 +#define EXTMEM_CACHE_WRITEBACK_ENA_S 2 +/* EXTMEM_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable clean operation. It will be cleared by hardware after +clean operation done. Note that this bit and the other sync-bits (invalidate_ena +, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos +e bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_CLEAN_ENA (BIT(1)) +#define EXTMEM_CACHE_CLEAN_ENA_M (BIT(1)) +#define EXTMEM_CACHE_CLEAN_ENA_V 0x1 +#define EXTMEM_CACHE_CLEAN_ENA_S 1 +/* EXTMEM_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a +fter invalidate operation done. Note that this bit and the other sync-bits (clea +n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, + those bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_INVALIDATE_ENA (BIT(0)) +#define EXTMEM_CACHE_INVALIDATE_ENA_M (BIT(0)) +#define EXTMEM_CACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_CACHE_INVALIDATE_ENA_S 0 + +#define EXTMEM_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) +/* EXTMEM_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: Those bits are used to indicate which caches in the two-level cache structure wi +ll apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, +[3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ +#define EXTMEM_CACHE_SYNC_MAP 0x0000003F +#define EXTMEM_CACHE_SYNC_MAP_M ((EXTMEM_CACHE_SYNC_MAP_V)<<(EXTMEM_CACHE_SYNC_MAP_S)) +#define EXTMEM_CACHE_SYNC_MAP_V 0x3F +#define EXTMEM_CACHE_SYNC_MAP_S 0 + +#define EXTMEM_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) +/* EXTMEM_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the sync operation +, which should be used together with CACHE_SYNC_SIZE_REG.*/ +#define EXTMEM_CACHE_SYNC_ADDR 0xFFFFFFFF +#define EXTMEM_CACHE_SYNC_ADDR_M ((EXTMEM_CACHE_SYNC_ADDR_V)<<(EXTMEM_CACHE_SYNC_ADDR_S)) +#define EXTMEM_CACHE_SYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_SYNC_ADDR_S 0 + +#define EXTMEM_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) +/* EXTMEM_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Those bits are used to configure the size of the sync operation, which should be + used together with CACHE_SYNC_ADDR_REG.*/ +#define EXTMEM_CACHE_SYNC_SIZE 0x00FFFFFF +#define EXTMEM_CACHE_SYNC_SIZE_M ((EXTMEM_CACHE_SYNC_SIZE_V)<<(EXTMEM_CACHE_SYNC_SIZE_S)) +#define EXTMEM_CACHE_SYNC_SIZE_V 0xFFFFFF +#define EXTMEM_CACHE_SYNC_SIZE_S 0 + +#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) +/* EXTMEM_DCACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 dcache preload..*/ +#define EXTMEM_DCACHE_PRELOAD_RGID 0x0000000F +#define EXTMEM_DCACHE_PRELOAD_RGID_M ((EXTMEM_DCACHE_PRELOAD_RGID_V)<<(EXTMEM_DCACHE_PRELOAD_RGID_S)) +#define EXTMEM_DCACHE_PRELOAD_RGID_V 0xF +#define EXTMEM_DCACHE_PRELOAD_RGID_S 3 +/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1 +: descending..*/ +#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) +#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) +#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 +/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether preload operation is finished or not. 0: not + finished. 1: finished..*/ +#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) +#define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) +#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 +/* EXTMEM_DCACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable preload operation on L1-DCache. It will be cleared by +hardware automatically after preload operation is done..*/ +#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) +#define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 + +#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) +/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of preload on L1-DCac +he, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) +#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) +/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: Those bits are used to configure the size of the first section of prelock on L1- +DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOAD_SIZE 0x00003FFF +#define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) +#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x3FFF +#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section for autoload operation on L1-DCache +..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 9 +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section for autoload operation on L1-DCache..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 8 +/* EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: The field is used to configure trigger mode of autoload operation on L1-DCache. +0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to configure the direction of autoload operation on L1-DCache. 0 +: ascending. 1: descending..*/ +#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(2)) +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(2)) +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 2 +/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether autoload operation on L1-DCache is finished +or not. 0: not finished. 1: finished..*/ +#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(1)) +#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(1)) +#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 1 +/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable and disable autoload operation on L1-DCache. 1: enabl +e, 0: disable..*/ +#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(0)) +#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the first section +for autoload operation on L1-DCache. Note that it should be used together with L +1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +/*description: Those bits are used to configure the size of the first section for autoload oper +ation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD +_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the second section + for autoload operation on L1-DCache. Note that it should be used together with +L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +/*description: Those bits are used to configure the size of the second section for autoload ope +ration on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOA +D_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) +/* EXTMEM_DBUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L +1-DCache due to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_ENA (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ENA_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_ENA_S 5 +/* EXTMEM_DBUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L +1-DCache due to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_ENA (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ENA_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_ENA_S 4 + +#define EXTMEM_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) +/* EXTMEM_DBUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d +ue to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_CLR (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_CLR_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_CLR_S 5 +/* EXTMEM_DBUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d +ue to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_CLR (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_CLR_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_CLR_S 4 + +#define EXTMEM_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) +/* EXTMEM_DBUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach +e due to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_RAW (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_RAW_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_RAW_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_RAW_S 5 +/* EXTMEM_DBUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach +e due to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_RAW (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_RAW_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_RAW_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_RAW_S 4 + +#define EXTMEM_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) +/* EXTMEM_DBUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit indicates the interrupt status of one of counters overflow that occurs i +n L1-DCache due to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_ST (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ST_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ST_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_ST_S 5 +/* EXTMEM_DBUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the interrupt status of one of counters overflow that occurs i +n L1-DCache due to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_ST (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ST_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ST_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_ST_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) +/* EXTMEM_DCACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due +to cpu accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_ENA_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) +/* EXTMEM_DCACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t +o cpu accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_CLR (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_CLR_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) +/* EXTMEM_DCACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_RAW (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_RAW_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_RAW_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_RAW_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) +/* EXTMEM_DCACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d +ue to cpu accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_ST (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ST_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ST_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_ST_S 4 + +#define EXTMEM_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) +/* EXTMEM_DBUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The bit is used to clear dbus1 counter in L1-DCache..*/ +#define EXTMEM_DBUS1_CNT_CLR (BIT(21)) +#define EXTMEM_DBUS1_CNT_CLR_M (BIT(21)) +#define EXTMEM_DBUS1_CNT_CLR_V 0x1 +#define EXTMEM_DBUS1_CNT_CLR_S 21 +/* EXTMEM_DBUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The bit is used to clear dbus0 counter in L1-DCache..*/ +#define EXTMEM_DBUS0_CNT_CLR (BIT(20)) +#define EXTMEM_DBUS0_CNT_CLR_M (BIT(20)) +#define EXTMEM_DBUS0_CNT_CLR_V 0x1 +#define EXTMEM_DBUS0_CNT_CLR_S 20 +/* EXTMEM_DBUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable dbus1 counter in L1-DCache..*/ +#define EXTMEM_DBUS1_CNT_ENA (BIT(5)) +#define EXTMEM_DBUS1_CNT_ENA_M (BIT(5)) +#define EXTMEM_DBUS1_CNT_ENA_V 0x1 +#define EXTMEM_DBUS1_CNT_ENA_S 5 +/* EXTMEM_DBUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable dbus0 counter in L1-DCache..*/ +#define EXTMEM_DBUS0_CNT_ENA (BIT(4)) +#define EXTMEM_DBUS0_CNT_ENA_M (BIT(4)) +#define EXTMEM_DBUS0_CNT_ENA_V 0x1 +#define EXTMEM_DBUS0_CNT_ENA_S 4 + +#define EXTMEM_DBUS0_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) +/* EXTMEM_DBUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_HIT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_HIT_CNT_M ((EXTMEM_DBUS0_HIT_CNT_V)<<(EXTMEM_DBUS0_HIT_CNT_S)) +#define EXTMEM_DBUS0_HIT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_HIT_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) +/* EXTMEM_DBUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_MISS_CNT_M ((EXTMEM_DBUS0_MISS_CNT_V)<<(EXTMEM_DBUS0_MISS_CNT_S)) +#define EXTMEM_DBUS0_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_MISS_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) +/* EXTMEM_DBUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus0 accesses L1-DCache +..*/ +#define EXTMEM_DBUS0_CONFLICT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_CONFLICT_CNT_M ((EXTMEM_DBUS0_CONFLICT_CNT_V)<<(EXTMEM_DBUS0_CONFLICT_CNT_S)) +#define EXTMEM_DBUS0_CONFLICT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_CONFLICT_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) +/* EXTMEM_DBUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-DCache accesses L2-Cache due to + bus0 accessing L1-DCache..*/ +#define EXTMEM_DBUS0_NXTLVL_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_NXTLVL_CNT_M ((EXTMEM_DBUS0_NXTLVL_CNT_V)<<(EXTMEM_DBUS0_NXTLVL_CNT_S)) +#define EXTMEM_DBUS0_NXTLVL_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_NXTLVL_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) +/* EXTMEM_DBUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_HIT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_HIT_CNT_M ((EXTMEM_DBUS1_HIT_CNT_V)<<(EXTMEM_DBUS1_HIT_CNT_S)) +#define EXTMEM_DBUS1_HIT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_HIT_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) +/* EXTMEM_DBUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_MISS_CNT_M ((EXTMEM_DBUS1_MISS_CNT_V)<<(EXTMEM_DBUS1_MISS_CNT_S)) +#define EXTMEM_DBUS1_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_MISS_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) +/* EXTMEM_DBUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus1 accesses L1-DCache +..*/ +#define EXTMEM_DBUS1_CONFLICT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_CONFLICT_CNT_M ((EXTMEM_DBUS1_CONFLICT_CNT_V)<<(EXTMEM_DBUS1_CONFLICT_CNT_S)) +#define EXTMEM_DBUS1_CONFLICT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_CONFLICT_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) +/* EXTMEM_DBUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-DCache accesses L2-Cache due to + bus1 accessing L1-DCache..*/ +#define EXTMEM_DBUS1_NXTLVL_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_NXTLVL_CNT_M ((EXTMEM_DBUS1_NXTLVL_CNT_V)<<(EXTMEM_DBUS1_NXTLVL_CNT_S)) +#define EXTMEM_DBUS1_NXTLVL_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_NXTLVL_CNT_S 0 + +#define EXTMEM_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x1FC) +/* EXTMEM_ICACHE0_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache0 accesses L1-ICac +he..*/ +#define EXTMEM_ICACHE0_FAIL_ATTR 0x0000FFFF +#define EXTMEM_ICACHE0_FAIL_ATTR_M ((EXTMEM_ICACHE0_FAIL_ATTR_V)<<(EXTMEM_ICACHE0_FAIL_ATTR_S)) +#define EXTMEM_ICACHE0_FAIL_ATTR_V 0xFFFF +#define EXTMEM_ICACHE0_FAIL_ATTR_S 16 +/* EXTMEM_ICACHE0_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache0 accesses L1-ICache..*/ +#define EXTMEM_ICACHE0_FAIL_ID 0x0000FFFF +#define EXTMEM_ICACHE0_FAIL_ID_M ((EXTMEM_ICACHE0_FAIL_ID_V)<<(EXTMEM_ICACHE0_FAIL_ID_S)) +#define EXTMEM_ICACHE0_FAIL_ID_V 0xFFFF +#define EXTMEM_ICACHE0_FAIL_ID_S 0 + +#define EXTMEM_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x200) +/* EXTMEM_ICACHE0_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache0 accesses L1-ICache..*/ +#define EXTMEM_ICACHE0_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE0_FAIL_ADDR_M ((EXTMEM_ICACHE0_FAIL_ADDR_V)<<(EXTMEM_ICACHE0_FAIL_ADDR_S)) +#define EXTMEM_ICACHE0_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE0_FAIL_ADDR_S 0 + +#define EXTMEM_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x204) +/* EXTMEM_ICACHE1_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache1 accesses L1-ICac +he..*/ +#define EXTMEM_ICACHE1_FAIL_ATTR 0x0000FFFF +#define EXTMEM_ICACHE1_FAIL_ATTR_M ((EXTMEM_ICACHE1_FAIL_ATTR_V)<<(EXTMEM_ICACHE1_FAIL_ATTR_S)) +#define EXTMEM_ICACHE1_FAIL_ATTR_V 0xFFFF +#define EXTMEM_ICACHE1_FAIL_ATTR_S 16 +/* EXTMEM_ICACHE1_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache1 accesses L1-ICache..*/ +#define EXTMEM_ICACHE1_FAIL_ID 0x0000FFFF +#define EXTMEM_ICACHE1_FAIL_ID_M ((EXTMEM_ICACHE1_FAIL_ID_V)<<(EXTMEM_ICACHE1_FAIL_ID_S)) +#define EXTMEM_ICACHE1_FAIL_ID_V 0xFFFF +#define EXTMEM_ICACHE1_FAIL_ID_S 0 + +#define EXTMEM_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x208) +/* EXTMEM_ICACHE1_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache1 accesses L1-ICache..*/ +#define EXTMEM_ICACHE1_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE1_FAIL_ADDR_M ((EXTMEM_ICACHE1_FAIL_ADDR_V)<<(EXTMEM_ICACHE1_FAIL_ADDR_S)) +#define EXTMEM_ICACHE1_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE1_FAIL_ADDR_S 0 + +#define EXTMEM_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) +/* EXTMEM_DCACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache accesses L1-DCach +e..*/ +#define EXTMEM_DCACHE_FAIL_ATTR 0x0000FFFF +#define EXTMEM_DCACHE_FAIL_ATTR_M ((EXTMEM_DCACHE_FAIL_ATTR_V)<<(EXTMEM_DCACHE_FAIL_ATTR_S)) +#define EXTMEM_DCACHE_FAIL_ATTR_V 0xFFFF +#define EXTMEM_DCACHE_FAIL_ATTR_S 16 +/* EXTMEM_DCACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_ID 0x0000FFFF +#define EXTMEM_DCACHE_FAIL_ID_M ((EXTMEM_DCACHE_FAIL_ID_V)<<(EXTMEM_DCACHE_FAIL_ID_S)) +#define EXTMEM_DCACHE_FAIL_ID_V 0xFFFF +#define EXTMEM_DCACHE_FAIL_ID_S 0 + +#define EXTMEM_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) +/* EXTMEM_DCACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_FAIL_ADDR_M ((EXTMEM_DCACHE_FAIL_ADDR_V)<<(EXTMEM_DCACHE_FAIL_ADDR_S)) +#define EXTMEM_DCACHE_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_FAIL_ADDR_S 0 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) +/* EXTMEM_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of Cache sync-operation error..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-DCache preload-operation error..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of Cache sync-operation done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-DCache preload-operation. If preload o +peration is done, interrupt occurs..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) +/* EXTMEM_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of Cache sync-operation error..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of L1-DCache preload-operation error..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is + done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt that occurs only when L1-DCache preload-opera +tion is done..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) +/* EXTMEM_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc +curs..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation e +rror occurs..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation i +s done..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) +/* EXTMEM_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ST_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_ST_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt of L1-DCache preload-operation err +or..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_ST (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ST_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ST_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_ST_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o +peration is done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ST_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_ST_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt that occurs only when L1-DCache pr +eload-operation is done..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_ST (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ST_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ST_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_ST_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) +/* EXTMEM_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: The values 0-2 are available which means sync map, command conflict and size are + error in Cache System..*/ +#define EXTMEM_CACHE_SYNC_ERR_CODE 0x00000003 +#define EXTMEM_CACHE_SYNC_ERR_CODE_M ((EXTMEM_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_CACHE_SYNC_ERR_CODE_S)) +#define EXTMEM_CACHE_SYNC_ERR_CODE_V 0x3 +#define EXTMEM_CACHE_SYNC_ERR_CODE_S 12 +/* EXTMEM_DCACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The value 2 is Only available which means preload size is error in L1-DCache..*/ +#define EXTMEM_DCACHE_PLD_ERR_CODE 0x00000003 +#define EXTMEM_DCACHE_PLD_ERR_CODE_M ((EXTMEM_DCACHE_PLD_ERR_CODE_V)<<(EXTMEM_DCACHE_PLD_ERR_CODE_S)) +#define EXTMEM_DCACHE_PLD_ERR_CODE_V 0x3 +#define EXTMEM_DCACHE_PLD_ERR_CODE_S 8 + +#define EXTMEM_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) +/* EXTMEM_DCACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset sync-logic inside L1-DCache. Recommend that this should on +ly be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ +#define EXTMEM_DCACHE_SYNC_RST (BIT(4)) +#define EXTMEM_DCACHE_SYNC_RST_M (BIT(4)) +#define EXTMEM_DCACHE_SYNC_RST_V 0x1 +#define EXTMEM_DCACHE_SYNC_RST_S 4 + +#define EXTMEM_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) +/* EXTMEM_DCACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset preload-logic inside L1-DCache. Recommend that this should + only be used to initialize preload-logic when some fatal error of preload-logic + occurs..*/ +#define EXTMEM_DCACHE_PLD_RST (BIT(4)) +#define EXTMEM_DCACHE_PLD_RST_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_RST_V 0x1 +#define EXTMEM_DCACHE_PLD_RST_S 4 + +#define EXTMEM_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) +/* EXTMEM_DCACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, a +utoload will not work in L1-DCache. This bit should not be active when autoload +works in L1-DCache..*/ +#define EXTMEM_DCACHE_ALD_BUF_CLR (BIT(4)) +#define EXTMEM_DCACHE_ALD_BUF_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_ALD_BUF_CLR_V 0x1 +#define EXTMEM_DCACHE_ALD_BUF_CLR_S 4 + +#define EXTMEM_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) +/* EXTMEM_DCACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear the unallocate request buffer of l1 dcache where the un +allocate request is responsed but not completed..*/ +#define EXTMEM_DCACHE_UNALLOC_CLR (BIT(4)) +#define EXTMEM_DCACHE_UNALLOC_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_UNALLOC_CLR_V 0x1 +#define EXTMEM_DCACHE_UNALLOC_CLR_S 4 + +#define EXTMEM_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) +/* EXTMEM_DCACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-DCache data memory as object. This bit should be onehot w +ith the others fields inside this register..*/ +#define EXTMEM_DCACHE_MEM_OBJECT (BIT(10)) +#define EXTMEM_DCACHE_MEM_OBJECT_M (BIT(10)) +#define EXTMEM_DCACHE_MEM_OBJECT_V 0x1 +#define EXTMEM_DCACHE_MEM_OBJECT_S 10 +/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-DCache tag memory as object. This bit should be onehot wi +th the others fields inside this register..*/ +#define EXTMEM_DCACHE_TAG_OBJECT (BIT(4)) +#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(4)) +#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1 +#define EXTMEM_DCACHE_TAG_OBJECT_S 4 + +#define EXTMEM_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) +/* EXTMEM_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 +: way1, 2: way2, 3: way3, ?, 7: way7..*/ +#define EXTMEM_CACHE_WAY_OBJECT 0x00000007 +#define EXTMEM_CACHE_WAY_OBJECT_M ((EXTMEM_CACHE_WAY_OBJECT_V)<<(EXTMEM_CACHE_WAY_OBJECT_S)) +#define EXTMEM_CACHE_WAY_OBJECT_V 0x7 +#define EXTMEM_CACHE_WAY_OBJECT_S 0 + +#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) +/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ +/*description: Those bits stores the virtual address which will decide where inside the specifi +ed tag memory object will be accessed..*/ +#define EXTMEM_CACHE_VADDR 0xFFFFFFFF +#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) +#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_VADDR_S 0 + +#define EXTMEM_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) +/* EXTMEM_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ +/*description: This is a constant place where we can write data to or read data from the tag/da +ta memory on the specified cache..*/ +#define EXTMEM_CACHE_DEBUG_BUS 0xFFFFFFFF +#define EXTMEM_CACHE_DEBUG_BUS_M ((EXTMEM_CACHE_DEBUG_BUS_V)<<(EXTMEM_CACHE_DEBUG_BUS_S)) +#define EXTMEM_CACHE_DEBUG_BUS_V 0xFFFFFFFF +#define EXTMEM_CACHE_DEBUG_BUS_S 0 + +#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) +/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */ +/*description: version control register. Note that this default value stored is the latest date + when the hardware logic was updated..*/ +#define EXTMEM_DATE 0x0FFFFFFF +#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) +#define EXTMEM_DATE_V 0xFFFFFFF +#define EXTMEM_DATE_S 0 + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/extmem_struct.h b/components/soc/esp32h2/include/soc/extmem_struct.h new file mode 100644 index 0000000000..d309e09235 --- /dev/null +++ b/components/soc/esp32h2/include/soc/extmem_struct.h @@ -0,0 +1,5747 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of l1_icache_ctrl register + * L1 instruction Cache(L1-ICache) control register + */ +typedef union { + struct { + /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0; + * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus0:1; + /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0; + * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus1:1; + /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus2:1; + /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus3:1; + /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0; + * Reserved + */ + uint32_t l1_icache_undef_op:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_icache_ctrl_reg_t; + +/** Type of l1_cache_ctrl register + * L1 data Cache(L1-Cache) control register + */ +typedef union { + struct { + /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus0:1; + /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus1:1; + /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus2:1; + /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus3:1; + /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_dma:1; + uint32_t reserved_5:3; + /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0; + * Reserved + */ + uint32_t l1_cache_undef_op:4; + uint32_t reserved_12:20; + }; + uint32_t val; +} extmem_l1_cache_ctrl_reg_t; + +/** Type of l2_cache_ctrl register + * L2 Cache(L2-Cache) control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + */ + uint32_t l2_cache_shut_dma:1; + /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0; + * Reserved + */ + uint32_t l2_cache_undef_op:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} extmem_l2_cache_ctrl_reg_t; + + +/** Group: Bypass Cache Control and configuration registers */ +/** Type of l1_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache0_en:1; + /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache1_en:1; + /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache2_en:1; + /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache3_en:1; + /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_dcache_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_bypass_cache_conf_reg_t; + +/** Type of l2_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; + * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l2_cache_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_bypass_cache_conf_reg_t; + + +/** Group: Cache Atomic Control and configuration registers */ +/** Type of l1_cache_atomic_conf register + * L1 Cache atomic feature configure register + */ +typedef union { + struct { + /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable atomic feature on L1-Cache when multiple cores access + * L1-Cache. 1: disable, 1: enable. + */ + uint32_t l1_cache_atomic_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} extmem_l1_cache_atomic_conf_reg_t; + + +/** Group: Cache Mode Control and configuration registers */ +/** Type of l1_icache_cachesize_conf register + * L1 instruction Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1k:1; + /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2k:1; + /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4k:1; + /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_8k:1; + /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_16k:1; + /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_32k:1; + /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_64k:1; + /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_128k:1; + /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_256k:1; + /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_512k:1; + /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1024k:1; + /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2048k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2048k:1; + /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4096k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l1_icache_cachesize_conf_reg_t; + +/** Type of l1_icache_blocksize_conf register + * L1 instruction Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_8:1; + /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_16:1; + /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_32:1; + /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_64:1; + /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_128:1; + /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache_blocksize_conf_reg_t; + +/** Type of l1_cache_cachesize_conf register + * L1 data Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1k:1; + /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2k:1; + /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4k:1; + /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_8k:1; + /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_16k:1; + /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1; + * The field is used to configure cachesize of L1-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_32k:1; + /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_64k:1; + /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_128k:1; + /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_256k:1; + /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_512k:1; + /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1024k:1; + /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2048k:1; + /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l1_cache_cachesize_conf_reg_t; + +/** Type of l1_cache_blocksize_conf register + * L1 data Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_8:1; + /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_16:1; + /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; + * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_32:1; + /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_64:1; + /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_128:1; + /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_cache_blocksize_conf_reg_t; + +/** Type of l2_cache_cachesize_conf register + * L2 Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1k:1; + /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2k:1; + /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4k:1; + /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_8k:1; + /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_16k:1; + /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_32k:1; + /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_64k:1; + /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_128k:1; + /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_256k:1; + /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_512k:1; + /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1024k:1; + /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2048k:1; + /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_cachesize_conf_reg_t; + +/** Type of l2_cache_blocksize_conf register + * L2 Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_8:1; + /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_16:1; + /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_32:1; + /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_64:1; + /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_128:1; + /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_blocksize_conf_reg_t; + + +/** Group: Wrap Mode Control and configuration registers */ +/** Type of l1_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to enable L1-ICache0 wrap around mode. + */ + uint32_t l1_icache0_wrap:1; + /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to enable L1-ICache1 wrap around mode. + */ + uint32_t l1_icache1_wrap:1; + /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_wrap:1; + /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_wrap:1; + /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ + uint32_t l1_cache_wrap:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_wrap_around_ctrl_reg_t; + +/** Type of l2_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to enable L2-Cache wrap around mode. + */ + uint32_t l2_cache_wrap:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_wrap_around_ctrl_reg_t; + + +/** Group: Cache Tag Memory Power Control registers */ +/** Type of l1_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache0_tag_mem_force_on:1; + /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache0_tag_mem_force_pd:1; + /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache0_tag_mem_force_pu:1; + uint32_t reserved_3:1; + /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache1_tag_mem_force_on:1; + /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache1_tag_mem_force_pd:1; + /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache1_tag_mem_force_pu:1; + uint32_t reserved_7:1; + /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_on:1; + /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_pd:1; + /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_pu:1; + uint32_t reserved_11:1; + /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_on:1; + /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_pd:1; + /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_pu:1; + uint32_t reserved_15:1; + /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_tag_mem_force_on:1; + /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l1_cache_tag_mem_force_pd:1; + /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_tag_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} extmem_l1_cache_tag_mem_power_ctrl_reg_t; + +/** Type of l2_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l2_cache_tag_mem_force_on:1; + /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l2_cache_tag_mem_force_pd:1; + /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l2_cache_tag_mem_force_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} extmem_l2_cache_tag_mem_power_ctrl_reg_t; + + +/** Group: Cache Data Memory Power Control registers */ +/** Type of l1_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache0_data_mem_force_on:1; + /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache0_data_mem_force_pd:1; + /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache0_data_mem_force_pu:1; + uint32_t reserved_3:1; + /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache1_data_mem_force_on:1; + /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache1_data_mem_force_pd:1; + /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache1_data_mem_force_pu:1; + uint32_t reserved_7:1; + /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_on:1; + /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_pd:1; + /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_pu:1; + uint32_t reserved_11:1; + /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_on:1; + /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_pd:1; + /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_pu:1; + uint32_t reserved_15:1; + /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_data_mem_force_on:1; + /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_cache_data_mem_force_pd:1; + /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_data_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} extmem_l1_cache_data_mem_power_ctrl_reg_t; + +/** Type of l2_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l2_cache_data_mem_force_on:1; + /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l2_cache_data_mem_force_pd:1; + /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l2_cache_data_mem_force_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} extmem_l2_cache_data_mem_power_ctrl_reg_t; + + +/** Group: Cache Freeze Control registers */ +/** Type of l1_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by + * software. + */ + uint32_t l1_icache0_freeze_en:1; + /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache0_freeze_mode:1; + /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_freeze_done:1; + uint32_t reserved_3:1; + /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by + * software. + */ + uint32_t l1_icache1_freeze_en:1; + /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache1_freeze_mode:1; + /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_freeze_done:1; + uint32_t reserved_7:1; + /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_en:1; + /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_mode:1; + /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_done:1; + uint32_t reserved_11:1; + /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_en:1; + /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_mode:1; + /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_done:1; + uint32_t reserved_15:1; + /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ + uint32_t l1_cache_freeze_en:1; + /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_cache_freeze_mode:1; + /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_freeze_done:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} extmem_l1_cache_freeze_ctrl_reg_t; + +/** Type of l2_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable freeze operation on L2-Cache. It can be cleared by + * software. + */ + uint32_t l2_cache_freeze_en:1; + /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; + * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l2_cache_freeze_mode:1; + /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; + * The bit is used to indicate whether freeze operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_freeze_done:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} extmem_l2_cache_freeze_ctrl_reg_t; + + +/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Type of l1_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_data_mem_rd_en:1; + /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache0_data_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_data_mem_rd_en:1; + /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache1_data_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_rd_en:1; + /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_rd_en:1; + /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_rd_en:1; + /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} extmem_l1_cache_data_mem_acs_conf_reg_t; + +/** Type of l2_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_rd_en:1; + /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} extmem_l2_cache_data_mem_acs_conf_reg_t; + + +/** Group: Cache Tag Memory Access Control and Configuration registers */ +/** Type of l1_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_rd_en:1; + /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_rd_en:1; + /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_rd_en:1; + /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_rd_en:1; + /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_rd_en:1; + /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} extmem_l1_cache_tag_mem_acs_conf_reg_t; + +/** Type of l2_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_rd_en:1; + /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} extmem_l2_cache_tag_mem_acs_conf_reg_t; + + +/** Group: Prelock Control and configuration registers */ +/** Type of l1_icache0_prelock_conf register + * L1 instruction Cache 0 prelock configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct0_en:1; + /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct1_en:1; + /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache0 prelock. + */ + uint32_t l1_icache0_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache0_prelock_conf_reg_t; + +/** Type of l1_icache0_prelock_sct0_addr register + * L1 instruction Cache 0 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_prelock_sct0_addr_reg_t; + +/** Type of l1_icache0_prelock_sct1_addr register + * L1 instruction Cache 0 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_prelock_sct1_addr_reg_t; + +/** Type of l1_icache0_prelock_sct_size register + * L1 instruction Cache 0 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache0_prelock_sct_size_reg_t; + +/** Type of l1_icache1_prelock_conf register + * L1 instruction Cache 1 prelock configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct0_en:1; + /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct1_en:1; + /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache1 prelock. + */ + uint32_t l1_icache1_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache1_prelock_conf_reg_t; + +/** Type of l1_icache1_prelock_sct0_addr register + * L1 instruction Cache 1 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_prelock_sct0_addr_reg_t; + +/** Type of l1_icache1_prelock_sct1_addr register + * L1 instruction Cache 1 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_prelock_sct1_addr_reg_t; + +/** Type of l1_icache1_prelock_sct_size register + * L1 instruction Cache 1 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache1_prelock_sct_size_reg_t; + +/** Type of l1_icache2_prelock_conf register + * L1 instruction Cache 2 prelock configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct0_en:1; + /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct1_en:1; + /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache2 prelock. + */ + uint32_t l1_icache2_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache2_prelock_conf_reg_t; + +/** Type of l1_icache2_prelock_sct0_addr register + * L1 instruction Cache 2 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_prelock_sct0_addr_reg_t; + +/** Type of l1_icache2_prelock_sct1_addr register + * L1 instruction Cache 2 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_prelock_sct1_addr_reg_t; + +/** Type of l1_icache2_prelock_sct_size register + * L1 instruction Cache 2 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache2_prelock_sct_size_reg_t; + +/** Type of l1_icache3_prelock_conf register + * L1 instruction Cache 3 prelock configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct0_en:1; + /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct1_en:1; + /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache3 prelock. + */ + uint32_t l1_icache3_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache3_prelock_conf_reg_t; + +/** Type of l1_icache3_prelock_sct0_addr register + * L1 instruction Cache 3 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_prelock_sct0_addr_reg_t; + +/** Type of l1_icache3_prelock_sct1_addr register + * L1 instruction Cache 3 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_prelock_sct1_addr_reg_t; + +/** Type of l1_icache3_prelock_sct_size register + * L1 instruction Cache 3 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache3_prelock_sct_size_reg_t; + +/** Type of l1_cache_prelock_conf register + * L1 Cache prelock configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct0_en:1; + /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct1_en:1; + /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ + uint32_t l1_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_cache_prelock_conf_reg_t; + +/** Type of l1_cache_prelock_sct0_addr register + * L1 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_cache_prelock_sct0_addr_reg_t; + +/** Type of l1_dcache_prelock_sct1_addr register + * L1 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_dcache_prelock_sct1_addr_reg_t; + +/** Type of l1_dcache_prelock_sct_size register + * L1 Cache prelock section size configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_cache_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_cache_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_dcache_prelock_sct_size_reg_t; + +/** Type of l2_cache_prelock_conf register + * L2 Cache prelock configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct0_en:1; + /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct1_en:1; + /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l2 cache prelock. + */ + uint32_t l2_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_prelock_conf_reg_t; + +/** Type of l2_cache_prelock_sct0_addr register + * L2 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l2_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l2_cache_prelock_sct0_addr_reg_t; + +/** Type of l2_cache_prelock_sct1_addr register + * L2 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l2_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l2_cache_prelock_sct1_addr_reg_t; + +/** Type of l2_cache_prelock_sct_size register + * L2 Cache prelock section size configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l2_cache_prelock_sct0_size:16; + /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; + * Those bits are used to configure the size of the second section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l2_cache_prelock_sct1_size:16; + }; + uint32_t val; +} extmem_l2_cache_prelock_sct_size_reg_t; + + +/** Group: Lock Control and configuration registers */ +/** Type of cache_lock_ctrl register + * Lock-class (manual lock) operation control register + */ +typedef union { + struct { + /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ + uint32_t cache_lock_ena:1; + /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ + uint32_t cache_unlock_ena:1; + /** cache_lock_done : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ + uint32_t cache_lock_done:1; + /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ + uint32_t cache_lock_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_cache_lock_ctrl_reg_t; + +/** Type of cache_lock_map register + * Lock (manual lock) map configure register + */ +typedef union { + struct { + /** cache_lock_map : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ + uint32_t cache_lock_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_cache_lock_map_reg_t; + +/** Type of cache_lock_addr register + * Lock (manual lock) address configure register + */ +typedef union { + struct { + /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ + uint32_t cache_lock_addr:32; + }; + uint32_t val; +} extmem_cache_lock_addr_reg_t; + +/** Type of cache_lock_size register + * Lock (manual lock) size configure register + */ +typedef union { + struct { + /** cache_lock_size : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ + uint32_t cache_lock_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_cache_lock_size_reg_t; + + +/** Group: Sync Control and configuration registers */ +/** Type of cache_sync_ctrl register + * Sync-class operation control register + */ +typedef union { + struct { + /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t cache_invalidate_ena:1; + /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ + uint32_t cache_clean_ena:1; + /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t cache_writeback_ena:1; + /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ + uint32_t cache_writeback_invalidate_ena:1; + /** cache_sync_done : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ + uint32_t cache_sync_done:1; + /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ + uint32_t cache_sync_rgid:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} extmem_cache_sync_ctrl_reg_t; + +/** Type of cache_sync_map register + * Sync map configure register + */ +typedef union { + struct { + /** cache_sync_map : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ + uint32_t cache_sync_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_cache_sync_map_reg_t; + +/** Type of cache_sync_addr register + * Sync address configure register + */ +typedef union { + struct { + /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ + uint32_t cache_sync_addr:32; + }; + uint32_t val; +} extmem_cache_sync_addr_reg_t; + +/** Type of cache_sync_size register + * Sync size configure register + */ +typedef union { + struct { + /** cache_sync_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ + uint32_t cache_sync_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} extmem_cache_sync_size_reg_t; + + +/** Group: Preload Control and configuration registers */ +/** Type of l1_icache0_preload_ctrl register + * L1 instruction Cache 0 preload-operation control register + */ +typedef union { + struct { + /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache0. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache0_preload_ena:1; + /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache0_preload_done:1; + /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache0_preload_order:1; + /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache0 preload. + */ + uint32_t l1_icache0_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache0_preload_ctrl_reg_t; + +/** Type of l1_icache0_preload_addr register + * L1 instruction Cache 0 preload address configure register + */ +typedef union { + struct { + /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + */ + uint32_t l1_icache0_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_preload_addr_reg_t; + +/** Type of l1_icache0_preload_size register + * L1 instruction Cache 0 preload size configure register + */ +typedef union { + struct { + /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + */ + uint32_t l1_icache0_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache0_preload_size_reg_t; + +/** Type of l1_icache1_preload_ctrl register + * L1 instruction Cache 1 preload-operation control register + */ +typedef union { + struct { + /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache1. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache1_preload_ena:1; + /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache1_preload_done:1; + /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache1_preload_order:1; + /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache1 preload. + */ + uint32_t l1_icache1_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache1_preload_ctrl_reg_t; + +/** Type of l1_icache1_preload_addr register + * L1 instruction Cache 1 preload address configure register + */ +typedef union { + struct { + /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + */ + uint32_t l1_icache1_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_preload_addr_reg_t; + +/** Type of l1_icache1_preload_size register + * L1 instruction Cache 1 preload size configure register + */ +typedef union { + struct { + /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + */ + uint32_t l1_icache1_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache1_preload_size_reg_t; + +/** Type of l1_icache2_preload_ctrl register + * L1 instruction Cache 2 preload-operation control register + */ +typedef union { + struct { + /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache2. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache2_preload_ena:1; + /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache2_preload_done:1; + /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache2_preload_order:1; + /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache2 preload. + */ + uint32_t l1_icache2_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache2_preload_ctrl_reg_t; + +/** Type of l1_icache2_preload_addr register + * L1 instruction Cache 2 preload address configure register + */ +typedef union { + struct { + /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + */ + uint32_t l1_icache2_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_preload_addr_reg_t; + +/** Type of l1_icache2_preload_size register + * L1 instruction Cache 2 preload size configure register + */ +typedef union { + struct { + /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + */ + uint32_t l1_icache2_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache2_preload_size_reg_t; + +/** Type of l1_icache3_preload_ctrl register + * L1 instruction Cache 3 preload-operation control register + */ +typedef union { + struct { + /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache3. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache3_preload_ena:1; + /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache3_preload_done:1; + /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache3_preload_order:1; + /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache3 preload. + */ + uint32_t l1_icache3_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache3_preload_ctrl_reg_t; + +/** Type of l1_icache3_preload_addr register + * L1 instruction Cache 3 preload address configure register + */ +typedef union { + struct { + /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + */ + uint32_t l1_icache3_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_preload_addr_reg_t; + +/** Type of l1_icache3_preload_size register + * L1 instruction Cache 3 preload size configure register + */ +typedef union { + struct { + /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + */ + uint32_t l1_icache3_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache3_preload_size_reg_t; + +/** Type of l1_cache_preload_ctrl register + * L1 Cache preload-operation control register + */ +typedef union { + struct { + /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_cache_preload_ena:1; + /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_cache_preload_done:1; + /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_cache_preload_order:1; + /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ + uint32_t l1_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_cache_preload_ctrl_reg_t; + +/** Type of l1_dcache_preload_addr register + * L1 Cache preload address configure register + */ +typedef union { + struct { + /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l1_cache_preload_addr:32; + }; + uint32_t val; +} extmem_l1_dcache_preload_addr_reg_t; + +/** Type of l1_dcache_preload_size register + * L1 Cache preload size configure register + */ +typedef union { + struct { + /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l1_cache_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_dcache_preload_size_reg_t; + +/** Type of l2_cache_preload_ctrl register + * L2 Cache preload-operation control register + */ +typedef union { + struct { + /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L2-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l2_cache_preload_ena:1; + /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l2_cache_preload_done:1; + /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l2_cache_preload_order:1; + /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l2 cache preload. + */ + uint32_t l2_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l2_cache_preload_ctrl_reg_t; + +/** Type of l2_cache_preload_addr register + * L2 Cache preload address configure register + */ +typedef union { + struct { + /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L2-Cache, + * which should be used together with L2_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l2_cache_preload_addr:32; + }; + uint32_t val; +} extmem_l2_cache_preload_addr_reg_t; + +/** Type of l2_cache_preload_size register + * L2 Cache preload size configure register + */ +typedef union { + struct { + /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l2_cache_preload_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_preload_size_reg_t; + + +/** Group: Autoload Control and configuration registers */ +/** Type of l1_icache0_autoload_ctrl register + * L1 instruction Cache 0 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, + * 0: disable. + */ + uint32_t l1_icache0_autoload_ena:1; + /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_autoload_done:1; + /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache0_autoload_order:1; + /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache0. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache0_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct0_ena:1; + /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct1_ena:1; + /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache0 autoload. + */ + uint32_t l1_icache0_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache0_autoload_ctrl_reg_t; + +/** Type of l1_icache0_autoload_sct0_addr register + * L1 instruction Cache 0 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct0_addr_reg_t; + +/** Type of l1_icache0_autoload_sct0_size register + * L1 instruction Cache 0 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct0_size_reg_t; + +/** Type of l1_icache0_autoload_sct1_addr register + * L1 instruction Cache 0 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct1_addr_reg_t; + +/** Type of l1_icache0_autoload_sct1_size register + * L1 instruction Cache 0 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct1_size_reg_t; + +/** Type of l1_icache1_autoload_ctrl register + * L1 instruction Cache 1 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, + * 0: disable. + */ + uint32_t l1_icache1_autoload_ena:1; + /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_autoload_done:1; + /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache1_autoload_order:1; + /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache1. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache1_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct0_ena:1; + /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct1_ena:1; + /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache1 autoload. + */ + uint32_t l1_icache1_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache1_autoload_ctrl_reg_t; + +/** Type of l1_icache1_autoload_sct0_addr register + * L1 instruction Cache 1 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct0_addr_reg_t; + +/** Type of l1_icache1_autoload_sct0_size register + * L1 instruction Cache 1 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct0_size_reg_t; + +/** Type of l1_icache1_autoload_sct1_addr register + * L1 instruction Cache 1 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct1_addr_reg_t; + +/** Type of l1_icache1_autoload_sct1_size register + * L1 instruction Cache 1 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct1_size_reg_t; + +/** Type of l1_icache2_autoload_ctrl register + * L1 instruction Cache 2 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, + * 0: disable. + */ + uint32_t l1_icache2_autoload_ena:1; + /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache2_autoload_done:1; + /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache2_autoload_order:1; + /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache2. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache2_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct0_ena:1; + /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct1_ena:1; + /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache2 autoload. + */ + uint32_t l1_icache2_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache2_autoload_ctrl_reg_t; + +/** Type of l1_icache2_autoload_sct0_addr register + * L1 instruction Cache 2 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct0_addr_reg_t; + +/** Type of l1_icache2_autoload_sct0_size register + * L1 instruction Cache 2 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct0_size_reg_t; + +/** Type of l1_icache2_autoload_sct1_addr register + * L1 instruction Cache 2 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct1_addr_reg_t; + +/** Type of l1_icache2_autoload_sct1_size register + * L1 instruction Cache 2 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct1_size_reg_t; + +/** Type of l1_icache3_autoload_ctrl register + * L1 instruction Cache 3 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, + * 0: disable. + */ + uint32_t l1_icache3_autoload_ena:1; + /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache3_autoload_done:1; + /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache3_autoload_order:1; + /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache3. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache3_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct0_ena:1; + /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct1_ena:1; + /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache3 autoload. + */ + uint32_t l1_icache3_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache3_autoload_ctrl_reg_t; + +/** Type of l1_icache3_autoload_sct0_addr register + * L1 instruction Cache 3 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct0_addr_reg_t; + +/** Type of l1_icache3_autoload_sct0_size register + * L1 instruction Cache 3 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct0_size_reg_t; + +/** Type of l1_icache3_autoload_sct1_addr register + * L1 instruction Cache 3 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache3_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct1_addr_reg_t; + +/** Type of l1_icache3_autoload_sct1_size register + * L1 instruction Cache 3 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Reserved + */ + uint32_t l1_icache3_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_ctrl register + * L1 Cache autoload-operation control register + */ +typedef union { + struct { + /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ + uint32_t l1_cache_autoload_ena:1; + /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_autoload_done:1; + /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l1_cache_autoload_order:1; + /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct0_ena:1; + /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct1_ena:1; + /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct2_ena:1; + /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct3_ena:1; + /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l1 cache autoload. + */ + uint32_t l1_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l1_cache_autoload_ctrl_reg_t; + +/** Type of l1_cache_autoload_sct0_addr register + * L1 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct0_addr_reg_t; + +/** Type of l1_cache_autoload_sct0_size register + * L1 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct0_size_reg_t; + +/** Type of l1_cache_autoload_sct1_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct1_addr_reg_t; + +/** Type of l1_cache_autoload_sct1_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_sct2_addr register + * L1 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct2_addr_reg_t; + +/** Type of l1_cache_autoload_sct2_size register + * L1 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct2_size_reg_t; + +/** Type of l1_cache_autoload_sct3_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct3_addr_reg_t; + +/** Type of l1_cache_autoload_sct3_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct3_size_reg_t; + +/** Type of l2_cache_autoload_ctrl register + * L2 Cache autoload-operation control register + */ +typedef union { + struct { + /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, + * 0: disable. + */ + uint32_t l2_cache_autoload_ena:1; + /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_autoload_done:1; + /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L2-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l2_cache_autoload_order:1; + /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l2_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct0_ena:1; + /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct1_ena:1; + /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct2_ena:1; + /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct3_ena:1; + /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l2 cache autoload. + */ + uint32_t l2_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_autoload_ctrl_reg_t; + +/** Type of l2_cache_autoload_sct0_addr register + * L2 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct0_addr_reg_t; + +/** Type of l2_cache_autoload_sct0_size register + * L2 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct0_size_reg_t; + +/** Type of l2_cache_autoload_sct1_addr register + * L2 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct1_addr_reg_t; + +/** Type of l2_cache_autoload_sct1_size register + * L2 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct1_size_reg_t; + +/** Type of l2_cache_autoload_sct2_addr register + * L2 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct2_addr_reg_t; + +/** Type of l2_cache_autoload_sct2_size register + * L2 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct2_size_reg_t; + +/** Type of l2_cache_autoload_sct3_addr register + * L2 Cache autoload section 3 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct3_addr_reg_t; + +/** Type of l2_cache_autoload_sct3_size register + * L2 Cache autoload section 3 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct3_size_reg_t; + + +/** Group: Interrupt registers */ +/** Type of l1_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_ena:1; + /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_ena:1; + /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_ena:1; + /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_ena:1; + /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_ena:1; + /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_ena:1; + /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_ena:1; + /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_ena_reg_t; + +/** Type of l1_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due + * to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_clr:1; + /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due + * to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_clr:1; + /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_clr:1; + /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_clr:1; + /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_clr:1; + /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_clr:1; + /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_clr:1; + /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_clr_reg_t; + +/** Type of l1_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 + * due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_raw:1; + /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 + * due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_raw:1; + /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 + * due to bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_ovf_int_raw:1; + /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 + * due to bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_ovf_int_raw:1; + /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_raw:1; + /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_raw:1; + /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_ovf_int_raw:1; + /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_ovf_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_raw_reg_t; + +/** Type of l1_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_st:1; + /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_st:1; + /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_st:1; + /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_st:1; + /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_st:1; + /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_st:1; + /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_st:1; + /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_st_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_ena:1; + /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_ena:1; + /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_ena:1; + /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_ena:1; + /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_ena_reg_t; + +/** Type of l1_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_clr:1; + /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_clr:1; + /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_clr:1; + /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_clr:1; + /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_clr_reg_t; + +/** Type of l1_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache0. + */ + uint32_t l1_icache0_fail_int_raw:1; + /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache1. + */ + uint32_t l1_icache1_fail_int_raw:1; + /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache2. + */ + uint32_t l1_icache2_fail_int_raw:1; + /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache3. + */ + uint32_t l1_icache3_fail_int_raw:1; + /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ + uint32_t l1_cache_fail_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_raw_reg_t; + +/** Type of l1_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache0_fail_int_st:1; + /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache1_fail_int_st:1; + /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_st:1; + /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_st:1; + /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_st_reg_t; + +/** Type of l1_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache0_pld_done_int_ena:1; + /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache1_pld_done_int_ena:1; + /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_ena:1; + /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_ena:1; + /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_cache_pld_done_int_ena:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ + uint32_t cache_sync_done_int_ena:1; + /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_ena:1; + /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_ena:1; + /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_ena:1; + /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_ena:1; + /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_ena:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ + uint32_t cache_sync_err_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_ena_reg_t; + +/** Type of l1_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_clr:1; + /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_clr:1; + /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_clr:1; + /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_clr:1; + /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ + uint32_t l1_cache_pld_done_int_clr:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ + uint32_t cache_sync_done_int_clr:1; + /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; + * The bit is used to clear interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_clr:1; + /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_clr:1; + /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_clr:1; + /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_clr:1; + /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_clr:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ + uint32_t cache_sync_err_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_clr_reg_t; + +/** Type of l1_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is + * done. + */ + uint32_t l1_icache0_pld_done_int_raw:1; + /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is + * done. + */ + uint32_t l1_icache1_pld_done_int_raw:1; + /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_raw:1; + /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_raw:1; + /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ + uint32_t l1_cache_pld_done_int_raw:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ + uint32_t cache_sync_done_int_raw:1; + /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation + * error occurs. + */ + uint32_t l1_icache0_pld_err_int_raw:1; + /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation + * error occurs. + */ + uint32_t l1_icache1_pld_err_int_raw:1; + /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_raw:1; + /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_raw:1; + /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ + uint32_t l1_cache_pld_err_int_raw:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ + uint32_t cache_sync_err_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_raw_reg_t; + +/** Type of l1_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_st:1; + /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_st:1; + /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_st:1; + /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_st:1; + /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ + uint32_t l1_cache_pld_done_int_st:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ + uint32_t cache_sync_done_int_st:1; + /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_st:1; + /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_st:1; + /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_st:1; + /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_st:1; + /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_st:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ + uint32_t cache_sync_err_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_st_reg_t; + +/** Type of l2_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_ena:1; + /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_ena:1; + /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_ena:1; + /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_ena:1; + /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_ena:1; + /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_ena:1; + /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_ena:1; + /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_ena_reg_t; + +/** Type of l2_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_clr:1; + /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_clr:1; + /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_clr:1; + /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_clr:1; + /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_clr:1; + /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_clr:1; + /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_clr:1; + /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_clr_reg_t; + +/** Type of l2_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-ICache0. + */ + uint32_t l2_ibus0_ovf_int_raw:1; + /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-ICache1. + */ + uint32_t l2_ibus1_ovf_int_raw:1; + /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-ICache2. + */ + uint32_t l2_ibus2_ovf_int_raw:1; + /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-ICache3. + */ + uint32_t l2_ibus3_ovf_int_raw:1; + /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-DCache. + */ + uint32_t l2_dbus0_ovf_int_raw:1; + /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-DCache. + */ + uint32_t l2_dbus1_ovf_int_raw:1; + /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-DCache. + */ + uint32_t l2_dbus2_ovf_int_raw:1; + /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-DCache. + */ + uint32_t l2_dbus3_ovf_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_raw_reg_t; + +/** Type of l2_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_st:1; + /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_st:1; + /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_st:1; + /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_st:1; + /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_st:1; + /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_st:1; + /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_st:1; + /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_st_reg_t; + +/** Type of l2_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to + * l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_ena_reg_t; + +/** Type of l2_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 + * cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_clr_reg_t; + +/** Type of l2_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L2-Cache. + */ + uint32_t l2_cache_fail_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_raw_reg_t; + +/** Type of l2_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L2-Cache due + * to l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_st_reg_t; + +/** Type of l2_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation done. + */ + uint32_t l2_cache_pld_done_int_ena:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_ena:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_ena_reg_t; + +/** Type of l2_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation + * is done. + */ + uint32_t l2_cache_pld_done_int_clr:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_clr:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_clr_reg_t; + +/** Type of l2_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is + * done. + */ + uint32_t l2_cache_pld_done_int_raw:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error + * occurs. + */ + uint32_t l2_cache_pld_err_int_raw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_raw_reg_t; + +/** Type of l2_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L2-Cache + * preload-operation is done. + */ + uint32_t l2_cache_pld_done_int_st:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the status of the interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_st:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_st_reg_t; + + +/** Group: Access Statistics registers */ +/** Type of l1_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_ena:1; + /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_ena:1; + /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_ena:1; + /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_ena:1; + /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_ena:1; + /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_ena:1; + /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_ena:1; + /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_ena:1; + uint32_t reserved_8:8; + /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0; + * The bit is used to clear ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_clr:1; + /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0; + * The bit is used to clear ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_clr:1; + /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_clr:1; + /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_clr:1; + /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_clr:1; + /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_clr:1; + /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_clr:1; + /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_clr:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_ctrl_reg_t; + +/** Type of l1_ibus0_acs_hit_cnt register + * L1-ICache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_hit_cnt_reg_t; + +/** Type of l1_ibus0_acs_miss_cnt register + * L1-ICache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_miss_cnt_reg_t; + +/** Type of l1_ibus0_acs_conflict_cnt register + * L1-ICache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus0_acs_nxtlvl_cnt register + * L1-ICache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l1_ibus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus1_acs_hit_cnt register + * L1-ICache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_hit_cnt_reg_t; + +/** Type of l1_ibus1_acs_miss_cnt register + * L1-ICache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_miss_cnt_reg_t; + +/** Type of l1_ibus1_acs_conflict_cnt register + * L1-ICache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus1_acs_nxtlvl_cnt register + * L1-ICache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l1_ibus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus2_acs_hit_cnt register + * L1-ICache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_hit_cnt_reg_t; + +/** Type of l1_ibus2_acs_miss_cnt register + * L1-ICache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_miss_cnt_reg_t; + +/** Type of l1_ibus2_acs_conflict_cnt register + * L1-ICache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus2_acs_nxtlvl_cnt register + * L1-ICache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l1_ibus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus3_acs_hit_cnt register + * L1-ICache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_hit_cnt_reg_t; + +/** Type of l1_ibus3_acs_miss_cnt register + * L1-ICache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_miss_cnt_reg_t; + +/** Type of l1_ibus3_acs_conflict_cnt register + * L1-ICache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus3_acs_nxtlvl_cnt register + * L1-ICache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l1_ibus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_bus0_acs_hit_cnt register + * L1-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_hit_cnt_reg_t; + +/** Type of l1_bus0_acs_miss_cnt register + * L1-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_miss_cnt_reg_t; + +/** Type of l1_bus0_acs_conflict_cnt register + * L1-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_conflict_cnt_reg_t; + +/** Type of l1_bus0_acs_nxtlvl_cnt register + * L1-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_bus1_acs_hit_cnt register + * L1-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_hit_cnt_reg_t; + +/** Type of l1_bus1_acs_miss_cnt register + * L1-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_miss_cnt_reg_t; + +/** Type of l1_bus1_acs_conflict_cnt register + * L1-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_conflict_cnt_reg_t; + +/** Type of l1_bus1_acs_nxtlvl_cnt register + * L1-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ + uint32_t l1_bus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_dbus2_acs_hit_cnt register + * L1-DCache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_hit_cnt_reg_t; + +/** Type of l1_dbus2_acs_miss_cnt register + * L1-DCache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_miss_cnt_reg_t; + +/** Type of l1_dbus2_acs_conflict_cnt register + * L1-DCache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus2_acs_nxtlvl_cnt register + * L1-DCache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l1_dbus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_dbus3_acs_hit_cnt register + * L1-DCache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_hit_cnt_reg_t; + +/** Type of l1_dbus3_acs_miss_cnt register + * L1-DCache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_miss_cnt_reg_t; + +/** Type of l1_dbus3_acs_conflict_cnt register + * L1-DCache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus3_acs_nxtlvl_cnt register + * L1-DCache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l1_dbus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_ena:1; + /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_ena:1; + /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_ena:1; + /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_ena:1; + /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_ena:1; + /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_ena:1; + /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_ena:1; + /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_ena:1; + uint32_t reserved_16:8; + /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; + * The bit is used to clear ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_clr:1; + /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; + * The bit is used to clear ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_clr:1; + /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_clr:1; + /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_clr:1; + /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; + * The bit is used to clear dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_clr:1; + /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; + * The bit is used to clear dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_clr:1; + /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_clr:1; + /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_clr:1; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_ctrl_reg_t; + +/** Type of l2_ibus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_hit_cnt_reg_t; + +/** Type of l2_ibus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_miss_cnt_reg_t; + +/** Type of l2_ibus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache0 accesses + * L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus0_acs_nxtlvl_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_hit_cnt_reg_t; + +/** Type of l2_ibus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_miss_cnt_reg_t; + +/** Type of l2_ibus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache1 accesses + * L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus1_acs_nxtlvl_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_hit_cnt_reg_t; + +/** Type of l2_ibus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_miss_cnt_reg_t; + +/** Type of l2_ibus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache2 accesses + * L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus2_acs_nxtlvl_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_hit_cnt_reg_t; + +/** Type of l2_ibus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_miss_cnt_reg_t; + +/** Type of l2_ibus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache3 accesses + * L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus3_acs_nxtlvl_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_hit_cnt_reg_t; + +/** Type of l2_dbus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_miss_cnt_reg_t; + +/** Type of l2_dbus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus0_acs_nxtlvl_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_hit_cnt_reg_t; + +/** Type of l2_dbus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_miss_cnt_reg_t; + +/** Type of l2_dbus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus1_acs_nxtlvl_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_hit_cnt_reg_t; + +/** Type of l2_dbus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_miss_cnt_reg_t; + +/** Type of l2_dbus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus2_acs_nxtlvl_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_hit_cnt_reg_t; + +/** Type of l2_dbus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_miss_cnt_reg_t; + +/** Type of l2_dbus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus3_acs_nxtlvl_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t; + + +/** Group: Access Fail Debug registers */ +/** Type of l1_icache0_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_id:16; + /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache0_acs_fail_id_attr_reg_t; + +/** Type of l1_icache0_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_acs_fail_addr_reg_t; + +/** Type of l1_icache1_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_id:16; + /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache1_acs_fail_id_attr_reg_t; + +/** Type of l1_icache1_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_acs_fail_addr_reg_t; + +/** Type of l1_icache2_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_id:16; + /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache2_acs_fail_id_attr_reg_t; + +/** Type of l1_icache2_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_acs_fail_addr_reg_t; + +/** Type of l1_icache3_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_id:16; + /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache3_acs_fail_id_attr_reg_t; + +/** Type of l1_icache3_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_acs_fail_addr_reg_t; + +/** Type of l1_cache_acs_fail_id_attr register + * L1-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_id:16; + /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_attr:16; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_id_attr_reg_t; + +/** Type of l1_dcache_acs_fail_addr register + * L1-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_addr:32; + }; + uint32_t val; +} extmem_l1_dcache_acs_fail_addr_reg_t; + +/** Type of l2_cache_acs_fail_id_attr register + * L2-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_id:16; + /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when L1-Cache accesses L2-Cache + * due to cache accessing L1-Cache. + */ + uint32_t l2_cache_fail_attr:16; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_id_attr_reg_t; + +/** Type of l2_cache_acs_fail_addr register + * L2-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_addr:32; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_addr_reg_t; + + +/** Group: Operation Exception registers */ +/** Type of l1_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache0. + */ + uint32_t l1_icache0_pld_err_code:2; + /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache1. + */ + uint32_t l1_icache1_pld_err_code:2; + /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_code:2; + /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_code:2; + /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ + uint32_t l1_cache_pld_err_code:2; + uint32_t reserved_10:2; + /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ + uint32_t cache_sync_err_code:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_exception_reg_t; + +/** Type of l2_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; + * The value 2 is Only available which means preload size is error in L2-Cache. + */ + uint32_t l2_cache_pld_err_code:2; + uint32_t reserved_12:20; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_exception_reg_t; + + +/** Group: Sync Reset control and configuration registers */ +/** Type of l1_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache0_sync_rst:1; + /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache1_sync_rst:1; + /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_sync_rst:1; + /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_sync_rst:1; + /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_cache_sync_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_sync_rst_ctrl_reg_t; + +/** Type of l2_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l2_cache_sync_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_sync_rst_ctrl_reg_t; + + +/** Group: Preload Reset control and configuration registers */ +/** Type of l1_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache0_pld_rst:1; + /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache1_pld_rst:1; + /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_rst:1; + /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_rst:1; + /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_cache_pld_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_preload_rst_ctrl_reg_t; + +/** Type of l2_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset preload-logic inside L2-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l2_cache_pld_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_preload_rst_ctrl_reg_t; + + +/** Group: Autoload buffer clear control and configuration registers */ +/** Type of l1_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, + * autoload will not work in L1-ICache0. This bit should not be active when autoload + * works in L1-ICache0. + */ + uint32_t l1_icache0_ald_buf_clr:1; + /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, + * autoload will not work in L1-ICache1. This bit should not be active when autoload + * works in L1-ICache1. + */ + uint32_t l1_icache1_ald_buf_clr:1; + /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_ald_buf_clr:1; + /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_ald_buf_clr:1; + /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ + uint32_t l1_cache_ald_buf_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t; + +/** Type of l2_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; + * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, + * autoload will not work in L2-Cache. This bit should not be active when autoload + * works in L2-Cache. + */ + uint32_t l2_cache_ald_buf_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t; + + +/** Group: Unallocate request buffer clear registers */ +/** Type of l1_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache0 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache0_unalloc_clr:1; + /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache1 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache1_unalloc_clr:1; + /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_unalloc_clr:1; + /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_unalloc_clr:1; + /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_cache_unalloc_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_unallocate_buffer_clear_reg_t; + +/** Type of l2_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear the unallocate request buffer of l2 icache where the + * unallocate request is responsed but not completed. + */ + uint32_t l2_cache_unalloc_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_unallocate_buffer_clear_reg_t; + + +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0; + * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache0_tag_object:1; + /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0; + * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache1_tag_object:1; + /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_object:1; + /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_object:1; + /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_tag_object:1; + uint32_t reserved_5:1; + /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0; + * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache0_mem_object:1; + /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0; + * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache1_mem_object:1; + /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_mem_object:1; + /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache3_mem_object:1; + /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_mem_object:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} extmem_l1_cache_object_ctrl_reg_t; + +/** Type of l1_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l1_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} extmem_l1_cache_way_object_reg_t; + +/** Type of l1_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l1_cache_vaddr:32; + }; + uint32_t val; +} extmem_l1_cache_vaddr_reg_t; + +/** Type of l1_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l1_cache_debug_bus:32; + }; + uint32_t val; +} extmem_l1_cache_debug_bus_reg_t; + +/** Type of l2_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; + * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_tag_object:1; + uint32_t reserved_6:5; + /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; + * Set this bit to set L2-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_mem_object:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} extmem_l2_cache_object_ctrl_reg_t; + +/** Type of l2_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l2_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} extmem_l2_cache_way_object_reg_t; + +/** Type of l2_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l2_cache_vaddr:32; + }; + uint32_t val; +} extmem_l2_cache_vaddr_reg_t; + +/** Type of l2_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l2_cache_debug_bus:32; + }; + uint32_t val; +} extmem_l2_cache_debug_bus_reg_t; + + +/** Group: Split L1 and L2 registers */ +/** Type of level_split0 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split0 : HRO; bitpos: [31:0]; default: 600; + * Reserved + */ + uint32_t level_split0:32; + }; + uint32_t val; +} extmem_level_split0_reg_t; + +/** Type of level_split1 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split1 : HRO; bitpos: [31:0]; default: 936; + * Reserved + */ + uint32_t level_split1:32; + }; + uint32_t val; +} extmem_level_split1_reg_t; + + +/** Group: L2 cache access attribute control register */ +/** Type of l2_cache_access_attr_ctrl register + * L1 Cache access Attribute propagation control register + */ +typedef union { + struct { + /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; + * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and + * non-cacheable. + */ + uint32_t l2_cache_access_force_cc:1; + /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; + * Set this bit to force the request to l2 cache with write-back attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of write-back and + * write-through. + */ + uint32_t l2_cache_access_force_wb:1; + /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; + * Set this bit to force the request to l2 cache with write-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * write-miss-allocate and write-miss-no-allocate. + */ + uint32_t l2_cache_access_force_wma:1; + /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; + * Set this bit to force the request to l2 cache with read-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * read-miss-allocate and read-miss-no-allocate. + */ + uint32_t l2_cache_access_force_rma:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} extmem_l2_cache_access_attr_ctrl_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} extmem_clock_gate_reg_t; + + +/** Group: Redundancy register (Prepare for ECO) */ +/** Type of redundancy_sig0 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig0:32; + }; + uint32_t val; +} extmem_redundancy_sig0_reg_t; + +/** Type of redundancy_sig1 register + * Cache redundancy signal 1 register + */ +typedef union { + struct { + /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig1:32; + }; + uint32_t val; +} extmem_redundancy_sig1_reg_t; + +/** Type of redundancy_sig2 register + * Cache redundancy signal 2 register + */ +typedef union { + struct { + /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig2:32; + }; + uint32_t val; +} extmem_redundancy_sig2_reg_t; + +/** Type of redundancy_sig3 register + * Cache redundancy signal 3 register + */ +typedef union { + struct { + /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig3:32; + }; + uint32_t val; +} extmem_redundancy_sig3_reg_t; + +/** Type of redundancy_sig4 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig4:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} extmem_redundancy_sig4_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35659904; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_date_reg_t; + + +typedef struct extmem_dev_s { + volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl; + volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl; + volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; + volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; + volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; + volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; + volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; + volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; + volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; + volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl; + volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl; + volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; + volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; + volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; + volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; + volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; + volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; + volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; + volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; + volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; + volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; + volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; + volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; + volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; + volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; + volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; + volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; + volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; + volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; + volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; + volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; + volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; + volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; + volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl; + volatile extmem_cache_lock_map_reg_t cache_lock_map; + volatile extmem_cache_lock_addr_reg_t cache_lock_addr; + volatile extmem_cache_lock_size_reg_t cache_lock_size; + volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl; + volatile extmem_cache_sync_map_reg_t cache_sync_map; + volatile extmem_cache_sync_addr_reg_t cache_sync_addr; + volatile extmem_cache_sync_size_reg_t cache_sync_size; + volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; + volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; + volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size; + volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; + volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; + volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size; + volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; + volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; + volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size; + volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; + volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; + volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size; + volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; + volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; + volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size; + volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; + volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; + volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; + volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; + volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; + volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; + volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; + volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; + volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; + volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; + volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; + volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; + volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; + volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; + volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; + volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; + volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; + volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; + volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; + volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; + volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; + volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; + volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; + volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; + volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; + volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; + volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; + volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; + volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; + volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; + volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; + volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; + volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; + volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; + volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; + volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; + volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; + volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; + volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; + volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; + volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; + volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt; + volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; + volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; + volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; + volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt; + volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; + volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; + volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; + volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt; + volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; + volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; + volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; + volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt; + volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; + volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; + volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; + volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt; + volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; + volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; + volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; + volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt; + volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; + volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; + volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; + volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt; + volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; + volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; + volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; + volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt; + volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; + volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; + volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; + volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; + volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; + volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; + volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; + volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; + volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr; + volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; + volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; + volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; + volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st; + volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception; + volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; + volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; + volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; + volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; + volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object; + volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr; + volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus; + volatile extmem_level_split0_reg_t level_split0; + volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl; + volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; + volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; + volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; + volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; + volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl; + volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl; + volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; + volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; + volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; + volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; + volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; + volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; + volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; + volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; + volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr; + volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size; + volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; + volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; + volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; + volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; + volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; + volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; + volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; + volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; + volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; + volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; + volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; + volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; + volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; + volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; + volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; + volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; + volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; + volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; + volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; + volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; + volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; + volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt; + volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; + volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; + volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; + volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt; + volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; + volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; + volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; + volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt; + volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; + volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; + volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; + volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt; + volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; + volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; + volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; + volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt; + volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; + volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; + volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; + volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt; + volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; + volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; + volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; + volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt; + volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; + volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; + volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; + volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt; + volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; + volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; + volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; + volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; + volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; + volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; + volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; + volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; + volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; + volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; + volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; + volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; + volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; + volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object; + volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr; + volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus; + volatile extmem_level_split1_reg_t level_split1; + volatile extmem_clock_gate_reg_t clock_gate; + volatile extmem_redundancy_sig0_reg_t redundancy_sig0; + volatile extmem_redundancy_sig1_reg_t redundancy_sig1; + volatile extmem_redundancy_sig2_reg_t redundancy_sig2; + volatile extmem_redundancy_sig3_reg_t redundancy_sig3; + volatile extmem_redundancy_sig4_reg_t redundancy_sig4; + uint32_t reserved_3c4[14]; + volatile extmem_date_reg_t date; +} extmem_dev_t; + +extern extmem_dev_t EXTMEM; + +#ifndef __cplusplus +_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gdma_channel.h b/components/soc/esp32h2/include/soc/gdma_channel.h new file mode 100644 index 0000000000..de9e2dd659 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gdma_channel.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) +#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_AES0 (6) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) diff --git a/components/soc/esp32h2/include/soc/gdma_reg.h b/components/soc/esp32h2/include/soc/gdma_reg.h new file mode 100644 index 0000000000..885de86e4f --- /dev/null +++ b/components/soc/esp32h2/include/soc/gdma_reg.h @@ -0,0 +1,3161 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw status interrupt of channel 1 + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 1. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 1. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 1. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 1. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt of channel 1 + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 1 + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 1 + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH2_REG register + * Raw status interrupt of channel 2 + */ +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) +/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 2. + */ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 2. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 2. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 2. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_M (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_M (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH2_REG register + * Masked interrupt of channel 2 + */ +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) +/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ST_M (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S) +#define GDMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ST_M (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S) +#define GDMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 2 + */ +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) +/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_M (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_M (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 2 + */ +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) +/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_M (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_M (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw status interrupt of channel 1 + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 1. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 1. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 1. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 1. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt of channel 1 + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 1 + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 1 + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH2_REG register + * Raw status interrupt of channel 2 + */ +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50) +/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 2. + */ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 2. + */ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 2. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 2. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH2_REG register + * Masked interrupt of channel 2 + */ +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54) +/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 +/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 2 + */ +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58) +/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 2 + */ +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c) +/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * MISC register + */ +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configure 0 register of Rx channel 0 + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 + +/** GDMA_IN_CONF1_CH0_REG register + * Configure 1 register of Rx channel 0 + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of Rx channel 0 + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of Rx channel 0 + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Link descriptor configure and control register of Rx channel 0 + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 21 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 22 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 23 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 24 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of Rx channel 0 + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of Rx channel 0 + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection of Rx channel 0 + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configure 0 register of Tx channel 0 + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 0 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configure 1 register of Tx channel 0 + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of Tx channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of Rx channel 0 + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Link descriptor configure and control register of Tx channel 0 + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 20 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 21 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 23 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of Tx channel 0 + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection of Tx channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configure 0 register of Rx channel 1 + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 1 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 1 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 + +/** GDMA_IN_CONF1_CH1_REG register + * Configure 1 register of Rx channel 1 + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of Rx channel 1 + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of Rx channel 1 + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Link descriptor configure and control register of Rx channel 1 + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 21 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 22 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 23 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 24 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of Rx channel 1 + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when EOF occurs of Rx channel 1 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when errors occur of Rx channel 1 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of Rx channel 1 + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection of Rx channel 1 + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configure 0 register of Tx channel 1 + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configure 1 register of Tx channel 1 + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of Tx channel 1 + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of Rx channel 1 + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Link descriptor configure and control register of Tx channel 1 + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 20 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 21 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 23 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of Tx channel 1 + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Outlink descriptor address when EOF occurs of Tx channel 1 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of Tx channel 1 + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection of Tx channel 1 + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_IN_CONF0_CH2_REG register + * Configure 0 register of Rx channel 2 + */ +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) +/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 2 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S) +#define GDMA_IN_RST_CH2_V 0x00000001U +#define GDMA_IN_RST_CH2_S 0 +/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S) +#define GDMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S) +#define GDMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 2 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH2 (BIT(5)) +#define GDMA_IN_ETM_EN_CH2_M (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S) +#define GDMA_IN_ETM_EN_CH2_V 0x00000001U +#define GDMA_IN_ETM_EN_CH2_S 5 + +/** GDMA_IN_CONF1_CH2_REG register + * Configure 1 register of Rx channel 2 + */ +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) +/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH2_S 12 + +/** GDMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of Rx channel 2 + */ +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) +/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ +#define GDMA_INFIFO_FULL_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_CH2_M (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S) +#define GDMA_INFIFO_FULL_CH2_V 0x00000001U +#define GDMA_INFIFO_FULL_CH2_S 0 +/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ +#define GDMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH2_M (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S) +#define GDMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH2_S 1 +/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ +#define GDMA_INFIFO_CNT_CH2 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_M (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S) +#define GDMA_INFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_M (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_M (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_M (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_M (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH2_S 27 + +/** GDMA_IN_POP_CH2_REG register + * Pop control register of Rx channel 2 + */ +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) +/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_M (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S) +#define GDMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_S 0 +/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S) +#define GDMA_INFIFO_POP_CH2_V 0x00000001U +#define GDMA_INFIFO_POP_CH2_S 12 + +/** GDMA_IN_LINK_CH2_REG register + * Link descriptor configure and control register of Rx channel 2 + */ +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_M (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S) +#define GDMA_INLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_S 0 +/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S) +#define GDMA_INLINK_STOP_CH2_V 0x00000001U +#define GDMA_INLINK_STOP_CH2_S 21 +/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S) +#define GDMA_INLINK_START_CH2_V 0x00000001U +#define GDMA_INLINK_START_CH2_S 22 +/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S) +#define GDMA_INLINK_RESTART_CH2_V 0x00000001U +#define GDMA_INLINK_RESTART_CH2_S 23 +/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S) +#define GDMA_INLINK_PARK_CH2_V 0x00000001U +#define GDMA_INLINK_PARK_CH2_S 24 + +/** GDMA_IN_STATE_CH2_REG register + * Receive status of Rx channel 2 + */ +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_M (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_M (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S) +#define GDMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH2 0x00000007U +#define GDMA_IN_STATE_CH2_M (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S) +#define GDMA_IN_STATE_CH2_V 0x00000007U +#define GDMA_IN_STATE_CH2_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when EOF occurs of Rx channel 2 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when errors occur of Rx channel 2 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_DSCR_CH2_REG register + * Current inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_M (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_S 0 + +/** GDMA_IN_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_M (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_M (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_IN_PRI_CH2_REG register + * Priority register of Rx channel 2 + */ +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) +/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH2 0x0000000FU +#define GDMA_RX_PRI_CH2_M (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S) +#define GDMA_RX_PRI_CH2_V 0x0000000FU +#define GDMA_RX_PRI_CH2_S 0 + +/** GDMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection of Rx channel 2 + */ +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH2 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_M (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S) +#define GDMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_S 0 + +/** GDMA_OUT_CONF0_CH2_REG register + * Configure 0 register of Tx channel 2 + */ +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 2 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S) +#define GDMA_OUT_RST_CH2_V 0x00000001U +#define GDMA_OUT_RST_CH2_S 0 +/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S) +#define GDMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 2 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH2 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH2_M (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S) +#define GDMA_OUT_ETM_EN_CH2_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH2_S 6 + +/** GDMA_OUT_CONF1_CH2_REG register + * Configure 1 register of Tx channel 2 + */ +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +/** GDMA_OUTFIFO_STATUS_CH2_REG register + * Transmit FIFO status of Tx channel 2 + */ +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH2_M (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S) +#define GDMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH2_S 0 +/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH2_M (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S) +#define GDMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH2_S 1 +/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ +#define GDMA_OUTFIFO_CNT_CH2 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_M (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S) +#define GDMA_OUTFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** GDMA_OUT_PUSH_CH2_REG register + * Push control register of Rx channel 2 + */ +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) +/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_M (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_S 0 +/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH2_S 9 + +/** GDMA_OUT_LINK_CH2_REG register + * Link descriptor configure and control register of Tx channel 2 + */ +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_M (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S) +#define GDMA_OUTLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_S 0 +/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S) +#define GDMA_OUTLINK_STOP_CH2_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH2_S 20 +/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S) +#define GDMA_OUTLINK_START_CH2_V 0x00000001U +#define GDMA_OUTLINK_START_CH2_S 21 +/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S) +#define GDMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S) +#define GDMA_OUTLINK_PARK_CH2_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH2_S 23 + +/** GDMA_OUT_STATE_CH2_REG register + * Transmit status of Tx channel 2 + */ +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_M (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH2 0x00000007U +#define GDMA_OUT_STATE_CH2_M (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S) +#define GDMA_OUT_STATE_CH2_V 0x00000007U +#define GDMA_OUT_STATE_CH2_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register + * Outlink descriptor address when EOF occurs of Tx channel 2 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_M (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 2 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_DSCR_CH2_REG register + * Current inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_M (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +/** GDMA_OUT_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_M (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_M (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_OUT_PRI_CH2_REG register + * Priority register of Tx channel 2 + */ +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) +/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH2 0x0000000FU +#define GDMA_TX_PRI_CH2_M (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S) +#define GDMA_TX_PRI_CH2_V 0x0000000FU +#define GDMA_TX_PRI_CH2_S 0 + +/** GDMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection of Tx channel 2 + */ +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_M (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S) +#define GDMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gdma_struct.h b/components/soc/esp32h2/include/soc/gdma_struct.h new file mode 100644 index 0000000000..7e4e641686 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gdma_struct.h @@ -0,0 +1,995 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of in_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ + uint32_t in_done_int_raw:1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ + uint32_t in_suc_eof_int_raw:1; + /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ + uint32_t in_err_eof_int_raw:1; + /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ + uint32_t in_dscr_err_int_raw:1; + /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ + uint32_t in_dscr_empty_int_raw:1; + /** infifo_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ + uint32_t infifo_ovf_int_raw:1; + /** infifo_udf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ + uint32_t infifo_udf_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_st:1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_st:1; + /** in_err_eof_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_int_st:1; + /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_int_st:1; + /** in_dscr_empty_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_st:1; + /** infifo_ovf_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_int_st:1; + /** infifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_ena:1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_ena:1; + /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_int_ena:1; + /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_int_ena:1; + /** in_dscr_empty_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_ena:1; + /** infifo_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_int_ena:1; + /** infifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** in_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_clr:1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_clr:1; + /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_int_clr:1; + /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_int_clr:1; + /** in_dscr_empty_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_clr:1; + /** infifo_ovf_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_int_clr:1; + /** infifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + +/** Type of out_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ + uint32_t out_done_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ + uint32_t out_eof_int_raw:1; + /** out_dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ + uint32_t out_dscr_err_int_raw:1; + /** out_total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ + uint32_t out_total_eof_int_raw:1; + /** outfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ + uint32_t outfifo_ovf_int_raw:1; + /** outfifo_udf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ + uint32_t outfifo_udf_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_int_st:1; + /** out_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_int_st:1; + /** out_dscr_err_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_int_st:1; + /** out_total_eof_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_int_st:1; + /** outfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_int_st:1; + /** outfifo_udf_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** out_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_int_ena:1; + /** out_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_int_ena:1; + /** out_dscr_err_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_int_ena:1; + /** out_total_eof_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_int_ena:1; + /** outfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_int_ena:1; + /** outfifo_udf_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** out_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_int_clr:1; + /** out_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_int_clr:1; + /** out_dscr_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_int_clr:1; + /** out_total_eof_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_int_clr:1; + /** outfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_int_clr:1; + /** outfifo_udf_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * MISC register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 0 + */ +typedef union { + struct { + /** in_rst : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst:1; + /** in_loop_test : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test:1; + /** indscr_burst_en : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en:1; + /** in_data_burst_en : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en:1; + /** mem_trans_en : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en:1; + /** in_etm_en : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * task. + */ + uint32_t in_etm_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 0 + */ +typedef union { + struct { + /** infifo_rdata : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata:12; + /** infifo_pop : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 0 + */ +typedef union { + struct { + /** inlink_addr : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr:20; + /** inlink_auto_ret : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret:1; + /** inlink_stop : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop:1; + /** inlink_start : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start:1; + /** inlink_restart : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart:1; + /** inlink_park : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel 0 + */ +typedef union { + struct { + /** out_rst : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst:1; + /** out_loop_test : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test:1; + /** out_auto_wrback : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback:1; + /** out_eof_mode : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode:1; + /** outdscr_burst_en : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en:1; + /** out_data_burst_en : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en:1; + /** out_etm_en : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ + uint32_t out_etm_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 0 + */ +typedef union { + struct { + /** outfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata:9; + /** outfifo_push : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 0 + */ +typedef union { + struct { + /** outlink_addr : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr:20; + /** outlink_stop : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop:1; + /** outlink_start : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start:1; + /** outlink_restart : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart:1; + /** outlink_park : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Status Registers */ +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 0 + */ +typedef union { + struct { + /** infifo_full : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ + uint32_t infifo_full:1; + /** infifo_empty : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ + uint32_t infifo_empty:1; + /** infifo_cnt : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ + uint32_t infifo_cnt:6; + uint32_t reserved_8:15; + /** in_remain_under_1b : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b:1; + /** in_remain_under_2b : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b:1; + /** in_remain_under_3b : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b:1; + /** in_remain_under_4b : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b:1; + /** in_buf_hungry : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr:18; + /** in_dscr_state : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state:2; + /** in_state : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 0 + */ +typedef union { + struct { + /** outfifo_full : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ + uint32_t outfifo_full:1; + /** outfifo_empty : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ + uint32_t outfifo_empty:1; + /** outfifo_cnt : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ + uint32_t outfifo_cnt:6; + uint32_t reserved_8:15; + /** out_remain_under_1b : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b:1; + /** out_remain_under_2b : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b:1; + /** out_remain_under_3b : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b:1; + /** out_remain_under_4b : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr:18; + /** out_dscr_state : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state:2; + /** out_state : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + + +/** Group: Priority Registers */ +/** Type of in_pri_chn register + * Priority register of Rx channel 0 + */ +typedef union { + struct { + /** rx_pri : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ + uint32_t rx_pri:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 0. + */ +typedef union { + struct { + /** tx_pri : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ + uint32_t tx_pri:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 0 + */ +typedef union { + struct { + /** peri_in_sel : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ + uint32_t peri_in_sel:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 0 + */ +typedef union { + struct { + /** peri_out_sel : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ + uint32_t peri_out_sel:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + +typedef struct { + volatile gdma_in_int_raw_chn_reg_t raw; + volatile gdma_in_int_st_chn_reg_t st; + volatile gdma_in_int_ena_chn_reg_t ena; + volatile gdma_in_int_clr_chn_reg_t clr; +} gdma_in_int_chn_reg_t; + +typedef struct { + volatile gdma_out_int_raw_chn_reg_t raw; + volatile gdma_out_int_st_chn_reg_t st; + volatile gdma_out_int_ena_chn_reg_t ena; + volatile gdma_out_int_clr_chn_reg_t clr; +} gdma_out_int_chn_reg_t; + +typedef struct { + volatile gdma_in_conf0_chn_reg_t in_conf0; + volatile gdma_in_conf1_chn_reg_t in_conf1; + volatile gdma_infifo_status_chn_reg_t infifo_status; + volatile gdma_in_pop_chn_reg_t in_pop; + volatile gdma_in_link_chn_reg_t in_link; + volatile gdma_in_state_chn_reg_t in_state; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; + volatile gdma_in_dscr_chn_reg_t in_dscr; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1; + volatile gdma_in_pri_chn_reg_t in_pri; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel; +} gdma_in_chn_reg_t; + +typedef struct { + volatile gdma_out_conf0_chn_reg_t out_conf0; + volatile gdma_out_conf1_chn_reg_t out_conf1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status; + volatile gdma_out_push_chn_reg_t out_push; + volatile gdma_out_link_chn_reg_t out_link; + volatile gdma_out_state_chn_reg_t out_state; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; + volatile gdma_out_dscr_chn_reg_t out_dscr; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1; + volatile gdma_out_pri_chn_reg_t out_pri; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel; +} gdma_out_chn_reg_t; + +typedef struct { + volatile gdma_in_chn_reg_t in; + uint32_t reserved_in[11]; + volatile gdma_out_chn_reg_t out; + uint32_t reserved_out[11]; +} gdma_chn_reg_t; + + +typedef struct gdma_dev_s { + volatile gdma_in_int_chn_reg_t in_intr[3]; + volatile gdma_out_int_chn_reg_t out_intr[3]; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_chn_reg_t channel[3]; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x2B0, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_ext_reg.h b/components/soc/esp32h2/include/soc/gpio_ext_reg.h new file mode 100644 index 0000000000..22143537fc --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_ext_reg.h @@ -0,0 +1,1072 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_SIGMADELTA0_REG register + * Duty Cycle Configure Register of SDM0 + */ +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) +/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD0_IN 0x000000FFU +#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S) +#define GPIO_SD0_IN_V 0x000000FFU +#define GPIO_SD0_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_SIGMADELTA1_REG register + * Duty Cycle Configure Register of SDM1 + */ +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) +/** GPIO_SD1_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD1_IN 0x000000FFU +#define GPIO_SD1_IN_M (GPIO_SD1_IN_V << GPIO_SD1_IN_S) +#define GPIO_SD1_IN_V 0x000000FFU +#define GPIO_SD1_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_SIGMADELTA2_REG register + * Duty Cycle Configure Register of SDM2 + */ +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) +/** GPIO_SD2_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD2_IN 0x000000FFU +#define GPIO_SD2_IN_M (GPIO_SD2_IN_V << GPIO_SD2_IN_S) +#define GPIO_SD2_IN_V 0x000000FFU +#define GPIO_SD2_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_SIGMADELTA3_REG register + * Duty Cycle Configure Register of SDM3 + */ +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) +/** GPIO_SD3_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD3_IN 0x000000FFU +#define GPIO_SD3_IN_M (GPIO_SD3_IN_V << GPIO_SD3_IN_S) +#define GPIO_SD3_IN_V 0x000000FFU +#define GPIO_SD3_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_CLOCK_GATE_REG register + * Clock Gating Configure Register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x20) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 0; + * Clock enable bit of configuration registers for sigma delta modulation. + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_SIGMADELTA_MISC_REG register + * MISC Register + */ +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) +/** GPIO_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ +#define GPIO_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_M (GPIO_FUNCTION_CLK_EN_V << GPIO_FUNCTION_CLK_EN_S) +#define GPIO_FUNCTION_CLK_EN_V 0x00000001U +#define GPIO_FUNCTION_CLK_EN_S 30 +/** GPIO_SPI_SWAP : R/W; bitpos: [31]; default: 0; + * Reserved. + */ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (GPIO_SPI_SWAP_V << GPIO_SPI_SWAP_S) +#define GPIO_SPI_SWAP_V 0x00000001U +#define GPIO_SPI_SWAP_S 31 + +/** GPIO_PAD_COMP_CONFIG_REG register + * PAD Compare configure Register + */ +#define GPIO_PAD_COMP_CONFIG_REG (DR_REG_GPIO_EXT_BASE + 0x28) +/** GPIO_XPD_COMP : R/W; bitpos: [0]; default: 0; + * Pad compare enable bit. + */ +#define GPIO_XPD_COMP (BIT(0)) +#define GPIO_XPD_COMP_M (GPIO_XPD_COMP_V << GPIO_XPD_COMP_S) +#define GPIO_XPD_COMP_V 0x00000001U +#define GPIO_XPD_COMP_S 0 +/** GPIO_MODE_COMP : R/W; bitpos: [1]; default: 0; + * 1 to enable external reference from PAD[0]. 0 to enable internal reference, + * meanwhile PAD[0] can be used as a regular GPIO. + */ +#define GPIO_MODE_COMP (BIT(1)) +#define GPIO_MODE_COMP_M (GPIO_MODE_COMP_V << GPIO_MODE_COMP_S) +#define GPIO_MODE_COMP_V 0x00000001U +#define GPIO_MODE_COMP_S 1 +/** GPIO_DREF_COMP : R/W; bitpos: [4:2]; default: 0; + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + */ +#define GPIO_DREF_COMP 0x00000007U +#define GPIO_DREF_COMP_M (GPIO_DREF_COMP_V << GPIO_DREF_COMP_S) +#define GPIO_DREF_COMP_V 0x00000007U +#define GPIO_DREF_COMP_S 2 +/** GPIO_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0; + * Zero Detect mode select. + */ +#define GPIO_ZERO_DET_MODE 0x00000003U +#define GPIO_ZERO_DET_MODE_M (GPIO_ZERO_DET_MODE_V << GPIO_ZERO_DET_MODE_S) +#define GPIO_ZERO_DET_MODE_V 0x00000003U +#define GPIO_ZERO_DET_MODE_S 5 + +/** GPIO_PAD_COMP_FILTER_REG register + * Zero Detect filter Register + */ +#define GPIO_PAD_COMP_FILTER_REG (DR_REG_GPIO_EXT_BASE + 0x2c) +/** GPIO_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0; + * Zero Detect filter cycle length + */ +#define GPIO_ZERO_DET_FILTER_CNT 0xFFFFFFFFU +#define GPIO_ZERO_DET_FILTER_CNT_M (GPIO_ZERO_DET_FILTER_CNT_V << GPIO_ZERO_DET_FILTER_CNT_S) +#define GPIO_ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU +#define GPIO_ZERO_DET_FILTER_CNT_S 0 + +/** GPIO_GLITCH_FILTER_CH0_REG register + * Glitch Filter Configure Register of Channel0 + */ +#define GPIO_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) +/** GPIO_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH0_EN (BIT(0)) +#define GPIO_FILTER_CH0_EN_M (GPIO_FILTER_CH0_EN_V << GPIO_FILTER_CH0_EN_S) +#define GPIO_FILTER_CH0_EN_V 0x00000001U +#define GPIO_FILTER_CH0_EN_S 0 +/** GPIO_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH0_INPUT_IO_NUM_M (GPIO_FILTER_CH0_INPUT_IO_NUM_V << GPIO_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_THRES_M (GPIO_FILTER_CH0_WINDOW_THRES_V << GPIO_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_WIDTH_M (GPIO_FILTER_CH0_WINDOW_WIDTH_V << GPIO_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH1_REG register + * Glitch Filter Configure Register of Channel1 + */ +#define GPIO_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) +/** GPIO_FILTER_CH1_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH1_EN (BIT(0)) +#define GPIO_FILTER_CH1_EN_M (GPIO_FILTER_CH1_EN_V << GPIO_FILTER_CH1_EN_S) +#define GPIO_FILTER_CH1_EN_V 0x00000001U +#define GPIO_FILTER_CH1_EN_S 0 +/** GPIO_FILTER_CH1_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH1_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH1_INPUT_IO_NUM_M (GPIO_FILTER_CH1_INPUT_IO_NUM_V << GPIO_FILTER_CH1_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH1_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH1_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH1_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH1_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_THRES_M (GPIO_FILTER_CH1_WINDOW_THRES_V << GPIO_FILTER_CH1_WINDOW_THRES_S) +#define GPIO_FILTER_CH1_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH1_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH1_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_WIDTH_M (GPIO_FILTER_CH1_WINDOW_WIDTH_V << GPIO_FILTER_CH1_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH1_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH2_REG register + * Glitch Filter Configure Register of Channel2 + */ +#define GPIO_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) +/** GPIO_FILTER_CH2_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH2_EN (BIT(0)) +#define GPIO_FILTER_CH2_EN_M (GPIO_FILTER_CH2_EN_V << GPIO_FILTER_CH2_EN_S) +#define GPIO_FILTER_CH2_EN_V 0x00000001U +#define GPIO_FILTER_CH2_EN_S 0 +/** GPIO_FILTER_CH2_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH2_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH2_INPUT_IO_NUM_M (GPIO_FILTER_CH2_INPUT_IO_NUM_V << GPIO_FILTER_CH2_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH2_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH2_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH2_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH2_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_THRES_M (GPIO_FILTER_CH2_WINDOW_THRES_V << GPIO_FILTER_CH2_WINDOW_THRES_S) +#define GPIO_FILTER_CH2_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH2_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH2_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_WIDTH_M (GPIO_FILTER_CH2_WINDOW_WIDTH_V << GPIO_FILTER_CH2_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH2_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH3_REG register + * Glitch Filter Configure Register of Channel3 + */ +#define GPIO_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) +/** GPIO_FILTER_CH3_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH3_EN (BIT(0)) +#define GPIO_FILTER_CH3_EN_M (GPIO_FILTER_CH3_EN_V << GPIO_FILTER_CH3_EN_S) +#define GPIO_FILTER_CH3_EN_V 0x00000001U +#define GPIO_FILTER_CH3_EN_S 0 +/** GPIO_FILTER_CH3_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH3_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH3_INPUT_IO_NUM_M (GPIO_FILTER_CH3_INPUT_IO_NUM_V << GPIO_FILTER_CH3_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH3_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH3_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH3_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH3_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_THRES_M (GPIO_FILTER_CH3_WINDOW_THRES_V << GPIO_FILTER_CH3_WINDOW_THRES_S) +#define GPIO_FILTER_CH3_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH3_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH3_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_WIDTH_M (GPIO_FILTER_CH3_WINDOW_WIDTH_V << GPIO_FILTER_CH3_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH3_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH4_REG register + * Glitch Filter Configure Register of Channel4 + */ +#define GPIO_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) +/** GPIO_FILTER_CH4_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH4_EN (BIT(0)) +#define GPIO_FILTER_CH4_EN_M (GPIO_FILTER_CH4_EN_V << GPIO_FILTER_CH4_EN_S) +#define GPIO_FILTER_CH4_EN_V 0x00000001U +#define GPIO_FILTER_CH4_EN_S 0 +/** GPIO_FILTER_CH4_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH4_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH4_INPUT_IO_NUM_M (GPIO_FILTER_CH4_INPUT_IO_NUM_V << GPIO_FILTER_CH4_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH4_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH4_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH4_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH4_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_THRES_M (GPIO_FILTER_CH4_WINDOW_THRES_V << GPIO_FILTER_CH4_WINDOW_THRES_S) +#define GPIO_FILTER_CH4_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH4_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH4_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_WIDTH_M (GPIO_FILTER_CH4_WINDOW_WIDTH_V << GPIO_FILTER_CH4_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH4_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH5_REG register + * Glitch Filter Configure Register of Channel5 + */ +#define GPIO_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) +/** GPIO_FILTER_CH5_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH5_EN (BIT(0)) +#define GPIO_FILTER_CH5_EN_M (GPIO_FILTER_CH5_EN_V << GPIO_FILTER_CH5_EN_S) +#define GPIO_FILTER_CH5_EN_V 0x00000001U +#define GPIO_FILTER_CH5_EN_S 0 +/** GPIO_FILTER_CH5_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH5_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH5_INPUT_IO_NUM_M (GPIO_FILTER_CH5_INPUT_IO_NUM_V << GPIO_FILTER_CH5_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH5_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH5_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH5_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH5_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_THRES_M (GPIO_FILTER_CH5_WINDOW_THRES_V << GPIO_FILTER_CH5_WINDOW_THRES_S) +#define GPIO_FILTER_CH5_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH5_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH5_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_WIDTH_M (GPIO_FILTER_CH5_WINDOW_WIDTH_V << GPIO_FILTER_CH5_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH5_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH6_REG register + * Glitch Filter Configure Register of Channel6 + */ +#define GPIO_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) +/** GPIO_FILTER_CH6_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH6_EN (BIT(0)) +#define GPIO_FILTER_CH6_EN_M (GPIO_FILTER_CH6_EN_V << GPIO_FILTER_CH6_EN_S) +#define GPIO_FILTER_CH6_EN_V 0x00000001U +#define GPIO_FILTER_CH6_EN_S 0 +/** GPIO_FILTER_CH6_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH6_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH6_INPUT_IO_NUM_M (GPIO_FILTER_CH6_INPUT_IO_NUM_V << GPIO_FILTER_CH6_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH6_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH6_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH6_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH6_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_THRES_M (GPIO_FILTER_CH6_WINDOW_THRES_V << GPIO_FILTER_CH6_WINDOW_THRES_S) +#define GPIO_FILTER_CH6_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH6_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH6_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_WIDTH_M (GPIO_FILTER_CH6_WINDOW_WIDTH_V << GPIO_FILTER_CH6_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH6_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH7_REG register + * Glitch Filter Configure Register of Channel7 + */ +#define GPIO_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) +/** GPIO_FILTER_CH7_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH7_EN (BIT(0)) +#define GPIO_FILTER_CH7_EN_M (GPIO_FILTER_CH7_EN_V << GPIO_FILTER_CH7_EN_S) +#define GPIO_FILTER_CH7_EN_V 0x00000001U +#define GPIO_FILTER_CH7_EN_S 0 +/** GPIO_FILTER_CH7_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH7_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH7_INPUT_IO_NUM_M (GPIO_FILTER_CH7_INPUT_IO_NUM_V << GPIO_FILTER_CH7_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH7_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH7_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH7_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH7_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_THRES_M (GPIO_FILTER_CH7_WINDOW_THRES_V << GPIO_FILTER_CH7_WINDOW_THRES_S) +#define GPIO_FILTER_CH7_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH7_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH7_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_WIDTH_M (GPIO_FILTER_CH7_WINDOW_WIDTH_V << GPIO_FILTER_CH7_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH7_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_WIDTH_S 13 + +/** GPIO_ETM_EVENT_CH0_CFG_REG register + * Etm Config register of Channel0 + */ +#define GPIO_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) +/** GPIO_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH0_EVENT_SEL_M (GPIO_ETM_CH0_EVENT_SEL_V << GPIO_ETM_CH0_EVENT_SEL_S) +#define GPIO_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH0_EVENT_EN_M (GPIO_ETM_CH0_EVENT_EN_V << GPIO_ETM_CH0_EVENT_EN_S) +#define GPIO_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH1_CFG_REG register + * Etm Config register of Channel1 + */ +#define GPIO_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) +/** GPIO_ETM_CH1_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH1_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH1_EVENT_SEL_M (GPIO_ETM_CH1_EVENT_SEL_V << GPIO_ETM_CH1_EVENT_SEL_S) +#define GPIO_ETM_CH1_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH1_EVENT_SEL_S 0 +/** GPIO_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH1_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH1_EVENT_EN_M (GPIO_ETM_CH1_EVENT_EN_V << GPIO_ETM_CH1_EVENT_EN_S) +#define GPIO_ETM_CH1_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH1_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH2_CFG_REG register + * Etm Config register of Channel2 + */ +#define GPIO_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) +/** GPIO_ETM_CH2_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH2_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH2_EVENT_SEL_M (GPIO_ETM_CH2_EVENT_SEL_V << GPIO_ETM_CH2_EVENT_SEL_S) +#define GPIO_ETM_CH2_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH2_EVENT_SEL_S 0 +/** GPIO_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH2_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH2_EVENT_EN_M (GPIO_ETM_CH2_EVENT_EN_V << GPIO_ETM_CH2_EVENT_EN_S) +#define GPIO_ETM_CH2_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH2_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH3_CFG_REG register + * Etm Config register of Channel3 + */ +#define GPIO_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) +/** GPIO_ETM_CH3_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH3_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH3_EVENT_SEL_M (GPIO_ETM_CH3_EVENT_SEL_V << GPIO_ETM_CH3_EVENT_SEL_S) +#define GPIO_ETM_CH3_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH3_EVENT_SEL_S 0 +/** GPIO_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH3_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH3_EVENT_EN_M (GPIO_ETM_CH3_EVENT_EN_V << GPIO_ETM_CH3_EVENT_EN_S) +#define GPIO_ETM_CH3_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH3_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH4_CFG_REG register + * Etm Config register of Channel4 + */ +#define GPIO_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) +/** GPIO_ETM_CH4_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH4_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH4_EVENT_SEL_M (GPIO_ETM_CH4_EVENT_SEL_V << GPIO_ETM_CH4_EVENT_SEL_S) +#define GPIO_ETM_CH4_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH4_EVENT_SEL_S 0 +/** GPIO_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH4_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH4_EVENT_EN_M (GPIO_ETM_CH4_EVENT_EN_V << GPIO_ETM_CH4_EVENT_EN_S) +#define GPIO_ETM_CH4_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH4_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH5_CFG_REG register + * Etm Config register of Channel5 + */ +#define GPIO_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) +/** GPIO_ETM_CH5_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH5_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH5_EVENT_SEL_M (GPIO_ETM_CH5_EVENT_SEL_V << GPIO_ETM_CH5_EVENT_SEL_S) +#define GPIO_ETM_CH5_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH5_EVENT_SEL_S 0 +/** GPIO_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH5_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH5_EVENT_EN_M (GPIO_ETM_CH5_EVENT_EN_V << GPIO_ETM_CH5_EVENT_EN_S) +#define GPIO_ETM_CH5_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH5_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH6_CFG_REG register + * Etm Config register of Channel6 + */ +#define GPIO_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) +/** GPIO_ETM_CH6_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH6_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH6_EVENT_SEL_M (GPIO_ETM_CH6_EVENT_SEL_V << GPIO_ETM_CH6_EVENT_SEL_S) +#define GPIO_ETM_CH6_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH6_EVENT_SEL_S 0 +/** GPIO_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH6_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH6_EVENT_EN_M (GPIO_ETM_CH6_EVENT_EN_V << GPIO_ETM_CH6_EVENT_EN_S) +#define GPIO_ETM_CH6_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH6_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH7_CFG_REG register + * Etm Config register of Channel7 + */ +#define GPIO_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) +/** GPIO_ETM_CH7_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH7_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH7_EVENT_SEL_M (GPIO_ETM_CH7_EVENT_SEL_V << GPIO_ETM_CH7_EVENT_SEL_S) +#define GPIO_ETM_CH7_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH7_EVENT_SEL_S 0 +/** GPIO_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH7_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH7_EVENT_EN_M (GPIO_ETM_CH7_EVENT_EN_V << GPIO_ETM_CH7_EVENT_EN_S) +#define GPIO_ETM_CH7_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH7_EVENT_EN_S 7 + +/** GPIO_ETM_TASK_P0_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) +/** GPIO_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO0_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO0_EN_M (GPIO_ETM_TASK_GPIO0_EN_V << GPIO_ETM_TASK_GPIO0_EN_S) +#define GPIO_ETM_TASK_GPIO0_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO0_EN_S 0 +/** GPIO_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO0_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO0_SEL_M (GPIO_ETM_TASK_GPIO0_SEL_V << GPIO_ETM_TASK_GPIO0_SEL_S) +#define GPIO_ETM_TASK_GPIO0_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO0_SEL_S 1 +/** GPIO_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO1_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO1_EN_M (GPIO_ETM_TASK_GPIO1_EN_V << GPIO_ETM_TASK_GPIO1_EN_S) +#define GPIO_ETM_TASK_GPIO1_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO1_EN_S 8 +/** GPIO_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO1_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO1_SEL_M (GPIO_ETM_TASK_GPIO1_SEL_V << GPIO_ETM_TASK_GPIO1_SEL_S) +#define GPIO_ETM_TASK_GPIO1_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO1_SEL_S 9 +/** GPIO_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO2_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO2_EN_M (GPIO_ETM_TASK_GPIO2_EN_V << GPIO_ETM_TASK_GPIO2_EN_S) +#define GPIO_ETM_TASK_GPIO2_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO2_EN_S 16 +/** GPIO_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO2_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO2_SEL_M (GPIO_ETM_TASK_GPIO2_SEL_V << GPIO_ETM_TASK_GPIO2_SEL_S) +#define GPIO_ETM_TASK_GPIO2_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO2_SEL_S 17 +/** GPIO_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO3_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO3_EN_M (GPIO_ETM_TASK_GPIO3_EN_V << GPIO_ETM_TASK_GPIO3_EN_S) +#define GPIO_ETM_TASK_GPIO3_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO3_EN_S 24 +/** GPIO_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO3_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO3_SEL_M (GPIO_ETM_TASK_GPIO3_SEL_V << GPIO_ETM_TASK_GPIO3_SEL_S) +#define GPIO_ETM_TASK_GPIO3_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO3_SEL_S 25 + +/** GPIO_ETM_TASK_P1_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) +/** GPIO_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO4_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO4_EN_M (GPIO_ETM_TASK_GPIO4_EN_V << GPIO_ETM_TASK_GPIO4_EN_S) +#define GPIO_ETM_TASK_GPIO4_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO4_EN_S 0 +/** GPIO_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO4_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO4_SEL_M (GPIO_ETM_TASK_GPIO4_SEL_V << GPIO_ETM_TASK_GPIO4_SEL_S) +#define GPIO_ETM_TASK_GPIO4_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO4_SEL_S 1 +/** GPIO_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO5_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO5_EN_M (GPIO_ETM_TASK_GPIO5_EN_V << GPIO_ETM_TASK_GPIO5_EN_S) +#define GPIO_ETM_TASK_GPIO5_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO5_EN_S 8 +/** GPIO_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO5_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO5_SEL_M (GPIO_ETM_TASK_GPIO5_SEL_V << GPIO_ETM_TASK_GPIO5_SEL_S) +#define GPIO_ETM_TASK_GPIO5_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO5_SEL_S 9 +/** GPIO_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO6_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO6_EN_M (GPIO_ETM_TASK_GPIO6_EN_V << GPIO_ETM_TASK_GPIO6_EN_S) +#define GPIO_ETM_TASK_GPIO6_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO6_EN_S 16 +/** GPIO_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO6_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO6_SEL_M (GPIO_ETM_TASK_GPIO6_SEL_V << GPIO_ETM_TASK_GPIO6_SEL_S) +#define GPIO_ETM_TASK_GPIO6_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO6_SEL_S 17 +/** GPIO_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO7_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO7_EN_M (GPIO_ETM_TASK_GPIO7_EN_V << GPIO_ETM_TASK_GPIO7_EN_S) +#define GPIO_ETM_TASK_GPIO7_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO7_EN_S 24 +/** GPIO_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO7_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO7_SEL_M (GPIO_ETM_TASK_GPIO7_SEL_V << GPIO_ETM_TASK_GPIO7_SEL_S) +#define GPIO_ETM_TASK_GPIO7_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO7_SEL_S 25 + +/** GPIO_ETM_TASK_P2_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) +/** GPIO_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO8_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO8_EN_M (GPIO_ETM_TASK_GPIO8_EN_V << GPIO_ETM_TASK_GPIO8_EN_S) +#define GPIO_ETM_TASK_GPIO8_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO8_EN_S 0 +/** GPIO_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO8_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO8_SEL_M (GPIO_ETM_TASK_GPIO8_SEL_V << GPIO_ETM_TASK_GPIO8_SEL_S) +#define GPIO_ETM_TASK_GPIO8_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO8_SEL_S 1 +/** GPIO_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO9_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO9_EN_M (GPIO_ETM_TASK_GPIO9_EN_V << GPIO_ETM_TASK_GPIO9_EN_S) +#define GPIO_ETM_TASK_GPIO9_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO9_EN_S 8 +/** GPIO_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO9_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO9_SEL_M (GPIO_ETM_TASK_GPIO9_SEL_V << GPIO_ETM_TASK_GPIO9_SEL_S) +#define GPIO_ETM_TASK_GPIO9_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO9_SEL_S 9 +/** GPIO_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO10_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO10_EN_M (GPIO_ETM_TASK_GPIO10_EN_V << GPIO_ETM_TASK_GPIO10_EN_S) +#define GPIO_ETM_TASK_GPIO10_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO10_EN_S 16 +/** GPIO_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO10_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO10_SEL_M (GPIO_ETM_TASK_GPIO10_SEL_V << GPIO_ETM_TASK_GPIO10_SEL_S) +#define GPIO_ETM_TASK_GPIO10_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO10_SEL_S 17 +/** GPIO_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO11_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO11_EN_M (GPIO_ETM_TASK_GPIO11_EN_V << GPIO_ETM_TASK_GPIO11_EN_S) +#define GPIO_ETM_TASK_GPIO11_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO11_EN_S 24 +/** GPIO_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO11_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO11_SEL_M (GPIO_ETM_TASK_GPIO11_SEL_V << GPIO_ETM_TASK_GPIO11_SEL_S) +#define GPIO_ETM_TASK_GPIO11_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO11_SEL_S 25 + +/** GPIO_ETM_TASK_P3_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) +/** GPIO_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO12_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO12_EN_M (GPIO_ETM_TASK_GPIO12_EN_V << GPIO_ETM_TASK_GPIO12_EN_S) +#define GPIO_ETM_TASK_GPIO12_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO12_EN_S 0 +/** GPIO_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO12_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO12_SEL_M (GPIO_ETM_TASK_GPIO12_SEL_V << GPIO_ETM_TASK_GPIO12_SEL_S) +#define GPIO_ETM_TASK_GPIO12_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO12_SEL_S 1 +/** GPIO_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO13_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO13_EN_M (GPIO_ETM_TASK_GPIO13_EN_V << GPIO_ETM_TASK_GPIO13_EN_S) +#define GPIO_ETM_TASK_GPIO13_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO13_EN_S 8 +/** GPIO_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO13_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO13_SEL_M (GPIO_ETM_TASK_GPIO13_SEL_V << GPIO_ETM_TASK_GPIO13_SEL_S) +#define GPIO_ETM_TASK_GPIO13_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO13_SEL_S 9 +/** GPIO_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO14_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO14_EN_M (GPIO_ETM_TASK_GPIO14_EN_V << GPIO_ETM_TASK_GPIO14_EN_S) +#define GPIO_ETM_TASK_GPIO14_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO14_EN_S 16 +/** GPIO_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO14_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO14_SEL_M (GPIO_ETM_TASK_GPIO14_SEL_V << GPIO_ETM_TASK_GPIO14_SEL_S) +#define GPIO_ETM_TASK_GPIO14_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO14_SEL_S 17 +/** GPIO_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO15_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO15_EN_M (GPIO_ETM_TASK_GPIO15_EN_V << GPIO_ETM_TASK_GPIO15_EN_S) +#define GPIO_ETM_TASK_GPIO15_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO15_EN_S 24 +/** GPIO_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO15_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO15_SEL_M (GPIO_ETM_TASK_GPIO15_SEL_V << GPIO_ETM_TASK_GPIO15_SEL_S) +#define GPIO_ETM_TASK_GPIO15_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO15_SEL_S 25 + +/** GPIO_ETM_TASK_P4_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) +/** GPIO_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO16_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO16_EN_M (GPIO_ETM_TASK_GPIO16_EN_V << GPIO_ETM_TASK_GPIO16_EN_S) +#define GPIO_ETM_TASK_GPIO16_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO16_EN_S 0 +/** GPIO_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO16_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO16_SEL_M (GPIO_ETM_TASK_GPIO16_SEL_V << GPIO_ETM_TASK_GPIO16_SEL_S) +#define GPIO_ETM_TASK_GPIO16_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO16_SEL_S 1 +/** GPIO_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO17_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO17_EN_M (GPIO_ETM_TASK_GPIO17_EN_V << GPIO_ETM_TASK_GPIO17_EN_S) +#define GPIO_ETM_TASK_GPIO17_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO17_EN_S 8 +/** GPIO_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO17_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO17_SEL_M (GPIO_ETM_TASK_GPIO17_SEL_V << GPIO_ETM_TASK_GPIO17_SEL_S) +#define GPIO_ETM_TASK_GPIO17_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO17_SEL_S 9 +/** GPIO_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO18_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO18_EN_M (GPIO_ETM_TASK_GPIO18_EN_V << GPIO_ETM_TASK_GPIO18_EN_S) +#define GPIO_ETM_TASK_GPIO18_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO18_EN_S 16 +/** GPIO_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO18_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO18_SEL_M (GPIO_ETM_TASK_GPIO18_SEL_V << GPIO_ETM_TASK_GPIO18_SEL_S) +#define GPIO_ETM_TASK_GPIO18_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO18_SEL_S 17 +/** GPIO_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO19_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO19_EN_M (GPIO_ETM_TASK_GPIO19_EN_V << GPIO_ETM_TASK_GPIO19_EN_S) +#define GPIO_ETM_TASK_GPIO19_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO19_EN_S 24 +/** GPIO_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO19_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO19_SEL_M (GPIO_ETM_TASK_GPIO19_SEL_V << GPIO_ETM_TASK_GPIO19_SEL_S) +#define GPIO_ETM_TASK_GPIO19_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO19_SEL_S 25 + +/** GPIO_ETM_TASK_P5_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) +/** GPIO_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO20_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO20_EN_M (GPIO_ETM_TASK_GPIO20_EN_V << GPIO_ETM_TASK_GPIO20_EN_S) +#define GPIO_ETM_TASK_GPIO20_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO20_EN_S 0 +/** GPIO_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO20_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO20_SEL_M (GPIO_ETM_TASK_GPIO20_SEL_V << GPIO_ETM_TASK_GPIO20_SEL_S) +#define GPIO_ETM_TASK_GPIO20_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO20_SEL_S 1 +/** GPIO_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO21_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO21_EN_M (GPIO_ETM_TASK_GPIO21_EN_V << GPIO_ETM_TASK_GPIO21_EN_S) +#define GPIO_ETM_TASK_GPIO21_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO21_EN_S 8 +/** GPIO_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO21_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO21_SEL_M (GPIO_ETM_TASK_GPIO21_SEL_V << GPIO_ETM_TASK_GPIO21_SEL_S) +#define GPIO_ETM_TASK_GPIO21_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO21_SEL_S 9 +/** GPIO_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO22_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO22_EN_M (GPIO_ETM_TASK_GPIO22_EN_V << GPIO_ETM_TASK_GPIO22_EN_S) +#define GPIO_ETM_TASK_GPIO22_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO22_EN_S 16 +/** GPIO_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO22_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO22_SEL_M (GPIO_ETM_TASK_GPIO22_SEL_V << GPIO_ETM_TASK_GPIO22_SEL_S) +#define GPIO_ETM_TASK_GPIO22_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO22_SEL_S 17 +/** GPIO_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO23_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO23_EN_M (GPIO_ETM_TASK_GPIO23_EN_V << GPIO_ETM_TASK_GPIO23_EN_S) +#define GPIO_ETM_TASK_GPIO23_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO23_EN_S 24 +/** GPIO_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO23_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO23_SEL_M (GPIO_ETM_TASK_GPIO23_SEL_V << GPIO_ETM_TASK_GPIO23_SEL_S) +#define GPIO_ETM_TASK_GPIO23_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO23_SEL_S 25 + +/** GPIO_ETM_TASK_P6_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) +/** GPIO_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO24_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO24_EN_M (GPIO_ETM_TASK_GPIO24_EN_V << GPIO_ETM_TASK_GPIO24_EN_S) +#define GPIO_ETM_TASK_GPIO24_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO24_EN_S 0 +/** GPIO_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO24_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO24_SEL_M (GPIO_ETM_TASK_GPIO24_SEL_V << GPIO_ETM_TASK_GPIO24_SEL_S) +#define GPIO_ETM_TASK_GPIO24_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO24_SEL_S 1 +/** GPIO_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO25_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO25_EN_M (GPIO_ETM_TASK_GPIO25_EN_V << GPIO_ETM_TASK_GPIO25_EN_S) +#define GPIO_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO25_EN_S 8 +/** GPIO_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO25_SEL_M (GPIO_ETM_TASK_GPIO25_SEL_V << GPIO_ETM_TASK_GPIO25_SEL_S) +#define GPIO_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO25_SEL_S 9 +/** GPIO_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO26_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO26_EN_M (GPIO_ETM_TASK_GPIO26_EN_V << GPIO_ETM_TASK_GPIO26_EN_S) +#define GPIO_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO26_EN_S 16 +/** GPIO_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO26_SEL_M (GPIO_ETM_TASK_GPIO26_SEL_V << GPIO_ETM_TASK_GPIO26_SEL_S) +#define GPIO_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO26_SEL_S 17 +/** GPIO_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO27_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO27_EN_M (GPIO_ETM_TASK_GPIO27_EN_V << GPIO_ETM_TASK_GPIO27_EN_S) +#define GPIO_ETM_TASK_GPIO27_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO27_EN_S 24 +/** GPIO_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO27_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO27_SEL_M (GPIO_ETM_TASK_GPIO27_SEL_V << GPIO_ETM_TASK_GPIO27_SEL_S) +#define GPIO_ETM_TASK_GPIO27_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO27_SEL_S 25 + +/** GPIO_INT_RAW_REG register + * GPIO interrupt raw register + */ +#define GPIO_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0xe0) +/** GPIO_PAD_COMP_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * Pad compare raw interrupt + */ +#define GPIO_PAD_COMP_INT_RAW (BIT(0)) +#define GPIO_PAD_COMP_INT_RAW_M (GPIO_PAD_COMP_INT_RAW_V << GPIO_PAD_COMP_INT_RAW_S) +#define GPIO_PAD_COMP_INT_RAW_V 0x00000001U +#define GPIO_PAD_COMP_INT_RAW_S 0 + +/** GPIO_INT_ST_REG register + * GPIO interrupt masked register + */ +#define GPIO_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0xe4) +/** GPIO_PAD_COMP_INT_ST : RO; bitpos: [0]; default: 0; + * Pad compare masked interrupt + */ +#define GPIO_PAD_COMP_INT_ST (BIT(0)) +#define GPIO_PAD_COMP_INT_ST_M (GPIO_PAD_COMP_INT_ST_V << GPIO_PAD_COMP_INT_ST_S) +#define GPIO_PAD_COMP_INT_ST_V 0x00000001U +#define GPIO_PAD_COMP_INT_ST_S 0 + +/** GPIO_INT_ENA_REG register + * GPIO interrupt enable register + */ +#define GPIO_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0xe8) +/** GPIO_PAD_COMP_INT_ENA : R/W; bitpos: [0]; default: 0; + * Pad compare interrupt enable + */ +#define GPIO_PAD_COMP_INT_ENA (BIT(0)) +#define GPIO_PAD_COMP_INT_ENA_M (GPIO_PAD_COMP_INT_ENA_V << GPIO_PAD_COMP_INT_ENA_S) +#define GPIO_PAD_COMP_INT_ENA_V 0x00000001U +#define GPIO_PAD_COMP_INT_ENA_S 0 + +/** GPIO_INT_CLR_REG register + * GPIO interrupt clear register + */ +#define GPIO_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0xec) +/** GPIO_PAD_COMP_INT_CLR : WT; bitpos: [0]; default: 0; + * Pad compare interrupt clear + */ +#define GPIO_PAD_COMP_INT_CLR (BIT(0)) +#define GPIO_PAD_COMP_INT_CLR_M (GPIO_PAD_COMP_INT_CLR_V << GPIO_PAD_COMP_INT_CLR_S) +#define GPIO_PAD_COMP_INT_CLR_V 0x00000001U +#define GPIO_PAD_COMP_INT_CLR_S 0 + +/** GPIO_VERSION_REG register + * Version Control Register + */ +#define GPIO_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) +/** GPIO_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35684640; + * Version control register. + */ +#define GPIO_GPIO_SD_DATE 0x0FFFFFFFU +#define GPIO_GPIO_SD_DATE_M (GPIO_GPIO_SD_DATE_V << GPIO_GPIO_SD_DATE_S) +#define GPIO_GPIO_SD_DATE_V 0x0FFFFFFFU +#define GPIO_GPIO_SD_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_ext_struct.h b/components/soc/esp32h2/include/soc/gpio_ext_struct.h new file mode 100644 index 0000000000..df1cc89370 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_ext_struct.h @@ -0,0 +1,319 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SDM Configure Registers */ +/** Type of sigmadeltan register + * Duty Cycle Configure Register of SDMn + */ +typedef union { + struct { + /** sd0_in : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ + uint32_t duty:8; + /** sd0_prescale : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ + uint32_t prescale:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_sigmadelta_chn_reg_t; + +/** Type of sigmadelta_misc register + * MISC Register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** function_clk_en : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ + uint32_t function_clk_en:1; + /** spi_swap : R/W; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t spi_swap:1; + }; + uint32_t val; +} gpio_sigmadelta_misc_reg_t; + + +/** Group: Clock gate Register */ +/** Type of clock_gate register + * Clock Gating Configure Register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Clock enable bit of configuration registers for sigma delta modulation. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_sigmadelta_clock_gate_reg_t; + + +/** Group: Configure Registers */ +/** Type of pad_comp_config register + * PAD Compare configure Register + */ +typedef union { + struct { + /** xpd_comp : R/W; bitpos: [0]; default: 0; + * Pad compare enable bit. + */ + uint32_t xpd_comp:1; + /** mode_comp : R/W; bitpos: [1]; default: 0; + * 1 to enable external reference from PAD[0]. 0 to enable internal reference, + * meanwhile PAD[0] can be used as a regular GPIO. + */ + uint32_t mode_comp:1; + /** dref_comp : R/W; bitpos: [4:2]; default: 0; + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + */ + uint32_t dref_comp:3; + /** zero_det_mode : R/W; bitpos: [6:5]; default: 0; + * Zero Detect mode select. + */ + uint32_t zero_det_mode:2; + uint32_t reserved_7:25; + }; + uint32_t val; +} gpio_pad_comp_config_reg_t; + +/** Type of pad_comp_filter register + * Zero Detect filter Register + */ +typedef union { + struct { + /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0; + * Zero Detect filter cycle length + */ + uint32_t zero_det_filter_cnt:32; + }; + uint32_t val; +} gpio_pad_comp_filter_reg_t; + + +/** Group: Glitch filter Configure Registers */ +/** Type of glitch_filter_chn register + * Glitch Filter Configure Register of Channeln + */ +typedef union { + struct { + /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ + uint32_t filter_ch0_en:1; + /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ + uint32_t filter_ch0_input_io_num:6; + /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ + uint32_t filter_ch0_window_thres:6; + /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ + uint32_t filter_ch0_window_width:6; + uint32_t reserved_19:13; + }; + uint32_t val; +} gpio_glitch_filter_chn_reg_t; + + +/** Group: Etm Configure Registers */ +/** Type of etm_event_chn_cfg register + * Etm Config register of Channeln + */ +typedef union { + struct { + /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ + uint32_t etm_ch0_event_sel:5; + uint32_t reserved_5:2; + /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ + uint32_t etm_ch0_event_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_etm_event_chn_cfg_reg_t; + +/** Type of etm_task_p0_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio0_en:1; + /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio0_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio1_en:1; + /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio1_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio2_en:1; + /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio2_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio3_en:1; + /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio3_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_pn_cfg_reg_t; + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * GPIOSD interrupt raw register + */ +typedef union { + struct { + /** pad_comp_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * Pad compare raw interrupt + */ + uint32_t pad_comp_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_ext_int_raw_reg_t; + +/** Type of int_st register + * GPIOSD interrupt masked register + */ +typedef union { + struct { + /** pad_comp_int_st : RO; bitpos: [0]; default: 0; + * Pad compare masked interrupt + */ + uint32_t pad_comp_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_ext_int_st_reg_t; + +/** Type of int_ena register + * GPIOSD interrupt enable register + */ +typedef union { + struct { + /** pad_comp_int_ena : R/W; bitpos: [0]; default: 0; + * Pad compare interrupt enable + */ + uint32_t pad_comp_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_ext_int_ena_reg_t; + +/** Type of int_clr register + * GPIOSD interrupt clear register + */ +typedef union { + struct { + /** pad_comp_int_clr : WT; bitpos: [0]; default: 0; + * Pad compare interrupt clear + */ + uint32_t pad_comp_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_ext_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version Control Register + */ +typedef union { + struct { + /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35684640; + * Version control register. + */ + uint32_t gpio_sd_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_version_reg_t; + +typedef struct { + volatile gpio_sigmadelta_chn_reg_t channel[4]; + uint32_t reserved_010[4]; + volatile gpio_sigmadelta_misc_reg_t misc; + volatile gpio_sigmadelta_clock_gate_reg_t clock_gate; +} gpio_sd_dev_t; + +typedef struct { + volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + +typedef struct { + volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7]; +} gpio_etm_dev_t; + +typedef struct { + volatile gpio_sd_dev_t sigma_delta; + volatile gpio_pad_comp_config_reg_t pad_comp_config; + volatile gpio_pad_comp_filter_reg_t pad_comp_filter; + volatile gpio_glitch_filter_dev_t glitch_filter; + uint32_t reserved_050[4]; + volatile gpio_etm_dev_t etm; + uint32_t reserved_0bc[9]; + volatile gpio_ext_int_raw_reg_t int_raw; + volatile gpio_ext_int_st_reg_t int_st; + volatile gpio_ext_int_ena_reg_t int_ena; + volatile gpio_ext_int_clr_reg_t int_clr; + uint32_t reserved_0f0[3]; + volatile gpio_ext_version_reg_t version; +} gpio_ext_dev_t; + +extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_pins.h b/components/soc/esp32h2/include/soc/gpio_pins.h new file mode 100644 index 0000000000..7ff04cf5dc --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_pins.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_reg.h b/components/soc/esp32h2/include/soc/gpio_reg.h new file mode 100644 index 0000000000..81f9b061ce --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_reg.h @@ -0,0 +1,5633 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_BT_SELECT_REG register + * GPIO bit select register + */ +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ +#define GPIO_BT_SEL 0xFFFFFFFFU +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFFU +#define GPIO_BT_SEL_S 0 + +/** GPIO_OUT_REG register + * GPIO output register for GPIO0-31 + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 + */ +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 + +/** GPIO_OUT_W1TS_REG register + * GPIO output set register for GPIO0-31 + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 + */ +#define GPIO_OUT_W1TS 0xFFFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0xFFFFFFFFU +#define GPIO_OUT_W1TS_S 0 + +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register for GPIO0-31 + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 + */ +#define GPIO_OUT_W1TC 0xFFFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0xFFFFFFFFU +#define GPIO_OUT_W1TC_S 0 + +/** GPIO_SDIO_SELECT_REG register + * GPIO sdio select register + */ +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) +/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ +#define GPIO_SDIO_SEL 0x000000FFU +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FFU +#define GPIO_SDIO_SEL_S 0 + +/** GPIO_ENABLE_REG register + * GPIO output enable register for GPIO0-31 + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ +#define GPIO_ENABLE_DATA 0xFFFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFFU +#define GPIO_ENABLE_DATA_S 0 + +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TS 0xFFFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU +#define GPIO_ENABLE_W1TS_S 0 + +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TC 0xFFFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU +#define GPIO_ENABLE_W1TC_S 0 + +/** GPIO_STRAP_REG register + * pad strapping register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU +#define GPIO_STRAPPING_S 0 + +/** GPIO_IN_REG register + * GPIO input register for GPIO0-31 + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ +#define GPIO_IN_DATA_NEXT 0xFFFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 + +/** GPIO_STATUS_REG register + * GPIO interrupt status register for GPIO0-31 + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 + +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register for GPIO0-31 + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 + */ +#define GPIO_STATUS_W1TS 0xFFFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0xFFFFFFFFU +#define GPIO_STATUS_W1TS_S 0 + +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register for GPIO0-31 + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) +/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 + */ +#define GPIO_STATUS_W1TC 0xFFFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0xFFFFFFFFU +#define GPIO_STATUS_W1TC_S 0 + +/** GPIO_PCPU_INT_REG register + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) +/** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +#define GPIO_PROCPU_INT 0xFFFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0xFFFFFFFFU +#define GPIO_PROCPU_INT_S 0 + +/** GPIO_PCPU_NMI_INT_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/** GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFFU +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFFU +#define GPIO_PROCPU_NMI_INT_S 0 + +/** GPIO_CPUSDIO_INT_REG register + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT 0xFFFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN0_CONFIG 0x00000003U +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003U +#define GPIO_PIN0_CONFIG_S 11 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 + +/** GPIO_PIN1_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN1_CONFIG 0x00000003U +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003U +#define GPIO_PIN1_CONFIG_S 11 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 + +/** GPIO_PIN2_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN2_CONFIG 0x00000003U +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003U +#define GPIO_PIN2_CONFIG_S 11 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 + +/** GPIO_PIN3_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN3_CONFIG 0x00000003U +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003U +#define GPIO_PIN3_CONFIG_S 11 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 + +/** GPIO_PIN4_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN4_CONFIG 0x00000003U +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003U +#define GPIO_PIN4_CONFIG_S 11 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 + +/** GPIO_PIN5_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN5_CONFIG 0x00000003U +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003U +#define GPIO_PIN5_CONFIG_S 11 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 + +/** GPIO_PIN6_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN6_CONFIG 0x00000003U +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003U +#define GPIO_PIN6_CONFIG_S 11 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 + +/** GPIO_PIN7_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN7_CONFIG 0x00000003U +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003U +#define GPIO_PIN7_CONFIG_S 11 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 + +/** GPIO_PIN8_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN8_CONFIG 0x00000003U +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003U +#define GPIO_PIN8_CONFIG_S 11 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 + +/** GPIO_PIN9_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN9_CONFIG 0x00000003U +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003U +#define GPIO_PIN9_CONFIG_S 11 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 + +/** GPIO_PIN10_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN10_CONFIG 0x00000003U +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003U +#define GPIO_PIN10_CONFIG_S 11 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 + +/** GPIO_PIN11_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN11_CONFIG 0x00000003U +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003U +#define GPIO_PIN11_CONFIG_S 11 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 + +/** GPIO_PIN12_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN12_CONFIG 0x00000003U +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003U +#define GPIO_PIN12_CONFIG_S 11 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 + +/** GPIO_PIN13_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN13_CONFIG 0x00000003U +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003U +#define GPIO_PIN13_CONFIG_S 11 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 + +/** GPIO_PIN14_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN14_CONFIG 0x00000003U +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003U +#define GPIO_PIN14_CONFIG_S 11 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 + +/** GPIO_PIN15_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN15_CONFIG 0x00000003U +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003U +#define GPIO_PIN15_CONFIG_S 11 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 + +/** GPIO_PIN16_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN16_CONFIG 0x00000003U +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003U +#define GPIO_PIN16_CONFIG_S 11 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 + +/** GPIO_PIN17_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN17_CONFIG 0x00000003U +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003U +#define GPIO_PIN17_CONFIG_S 11 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 + +/** GPIO_PIN18_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN18_CONFIG 0x00000003U +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003U +#define GPIO_PIN18_CONFIG_S 11 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 + +/** GPIO_PIN19_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN19_CONFIG 0x00000003U +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003U +#define GPIO_PIN19_CONFIG_S 11 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 + +/** GPIO_PIN20_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN20_CONFIG 0x00000003U +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003U +#define GPIO_PIN20_CONFIG_S 11 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 + +/** GPIO_PIN21_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN21_CONFIG 0x00000003U +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003U +#define GPIO_PIN21_CONFIG_S 11 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 + +/** GPIO_PIN22_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN22_CONFIG 0x00000003U +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003U +#define GPIO_PIN22_CONFIG_S 11 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 + +/** GPIO_PIN23_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN23_CONFIG 0x00000003U +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003U +#define GPIO_PIN23_CONFIG_S 11 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 + +/** GPIO_PIN24_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN24_CONFIG 0x00000003U +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003U +#define GPIO_PIN24_CONFIG_S 11 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 + +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN25_CONFIG 0x00000003U +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003U +#define GPIO_PIN25_CONFIG_S 11 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN26_CONFIG 0x00000003U +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003U +#define GPIO_PIN26_CONFIG_S 11 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN27_CONFIG 0x00000003U +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003U +#define GPIO_PIN27_CONFIG_S 11 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN28_CONFIG 0x00000003U +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003U +#define GPIO_PIN28_CONFIG_S 11 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN29_CONFIG 0x00000003U +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003U +#define GPIO_PIN29_CONFIG_S 11 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 + +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN30_CONFIG 0x00000003U +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003U +#define GPIO_PIN30_CONFIG_S 11 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 + +/** GPIO_PIN31_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) +/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_S 0 +/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN31_PAD_DRIVER_S 2 +/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN31_INT_TYPE 0x00000007U +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007U +#define GPIO_PIN31_INT_TYPE_S 7 +/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN31_CONFIG 0x00000003U +#define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) +#define GPIO_PIN31_CONFIG_V 0x00000003U +#define GPIO_PIN31_CONFIG_S 11 +/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN31_INT_ENA 0x0000001FU +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001FU +#define GPIO_PIN31_INT_ENA_S 13 + +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 7 + +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 7 + +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 7 + +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 7 + +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 7 + +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 7 + +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 7 + +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 7 + +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 7 + +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 7 + +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 7 + +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 7 + +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 7 + +/** GPIO_FUNC19_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) +/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC19_IN_SEL 0x0000003FU +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003FU +#define GPIO_FUNC19_IN_SEL_S 0 +/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001U +#define GPIO_SIG19_IN_SEL_S 7 + +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 7 + +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 7 + +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 7 + +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 7 + +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 7 + +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 7 + +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 7 + +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 7 + +/** GPIO_FUNC40_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) +/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC40_IN_SEL 0x0000003FU +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003FU +#define GPIO_FUNC40_IN_SEL_S 0 +/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001U +#define GPIO_SIG40_IN_SEL_S 7 + +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 7 + +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 7 + +/** GPIO_FUNC45_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC45_IN_SEL 0x0000003FU +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003FU +#define GPIO_FUNC45_IN_SEL_S 0 +/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001U +#define GPIO_SIG45_IN_SEL_S 7 + +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 7 + +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 7 + +/** GPIO_FUNC48_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC48_IN_SEL 0x0000003FU +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003FU +#define GPIO_FUNC48_IN_SEL_S 0 +/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001U +#define GPIO_SIG48_IN_SEL_S 7 + +/** GPIO_FUNC49_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC49_IN_SEL 0x0000003FU +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003FU +#define GPIO_FUNC49_IN_SEL_S 0 +/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001U +#define GPIO_SIG49_IN_SEL_S 7 + +/** GPIO_FUNC50_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) +/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC50_IN_SEL 0x0000003FU +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003FU +#define GPIO_FUNC50_IN_SEL_S 0 +/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001U +#define GPIO_SIG50_IN_SEL_S 7 + +/** GPIO_FUNC51_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC51_IN_SEL 0x0000003FU +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003FU +#define GPIO_FUNC51_IN_SEL_S 0 +/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001U +#define GPIO_SIG51_IN_SEL_S 7 + +/** GPIO_FUNC52_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC52_IN_SEL 0x0000003FU +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003FU +#define GPIO_FUNC52_IN_SEL_S 0 +/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001U +#define GPIO_SIG52_IN_SEL_S 7 + +/** GPIO_FUNC53_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC53_IN_SEL 0x0000003FU +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003FU +#define GPIO_FUNC53_IN_SEL_S 0 +/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001U +#define GPIO_SIG53_IN_SEL_S 7 + +/** GPIO_FUNC54_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) +/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC54_IN_SEL 0x0000003FU +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003FU +#define GPIO_FUNC54_IN_SEL_S 0 +/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001U +#define GPIO_SIG54_IN_SEL_S 7 + +/** GPIO_FUNC55_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC55_IN_SEL 0x0000003FU +#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) +#define GPIO_FUNC55_IN_SEL_V 0x0000003FU +#define GPIO_FUNC55_IN_SEL_S 0 +/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) +#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) +#define GPIO_SIG55_IN_SEL_V 0x00000001U +#define GPIO_SIG55_IN_SEL_S 7 + +/** GPIO_FUNC56_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC56_IN_SEL 0x0000003FU +#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) +#define GPIO_FUNC56_IN_SEL_V 0x0000003FU +#define GPIO_FUNC56_IN_SEL_S 0 +/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) +#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) +#define GPIO_SIG56_IN_SEL_V 0x00000001U +#define GPIO_SIG56_IN_SEL_S 7 + +/** GPIO_FUNC63_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC63_IN_SEL 0x0000003FU +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003FU +#define GPIO_FUNC63_IN_SEL_S 0 +/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001U +#define GPIO_SIG63_IN_SEL_S 7 + +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 7 + +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 7 + +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 7 + +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 7 + +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 7 + +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 7 + +/** GPIO_FUNC70_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) +/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC70_IN_SEL 0x0000003FU +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003FU +#define GPIO_FUNC70_IN_SEL_S 0 +/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001U +#define GPIO_SIG70_IN_SEL_S 7 + +/** GPIO_FUNC71_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC71_IN_SEL 0x0000003FU +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003FU +#define GPIO_FUNC71_IN_SEL_S 0 +/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001U +#define GPIO_SIG71_IN_SEL_S 7 + +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 7 + +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 7 + +/** GPIO_FUNC81_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC81_IN_SEL 0x0000003FU +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003FU +#define GPIO_FUNC81_IN_SEL_S 0 +/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001U +#define GPIO_SIG81_IN_SEL_S 7 + +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 7 + +/** GPIO_FUNC87_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) +/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC87_IN_SEL 0x0000003FU +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003FU +#define GPIO_FUNC87_IN_SEL_S 0 +/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001U +#define GPIO_SIG87_IN_SEL_S 7 + +/** GPIO_FUNC88_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) +/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC88_IN_SEL 0x0000003FU +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003FU +#define GPIO_FUNC88_IN_SEL_S 0 +/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001U +#define GPIO_SIG88_IN_SEL_S 7 + +/** GPIO_FUNC89_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) +/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC89_IN_SEL 0x0000003FU +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003FU +#define GPIO_FUNC89_IN_SEL_S 0 +/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001U +#define GPIO_SIG89_IN_SEL_S 7 + +/** GPIO_FUNC90_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) +/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC90_IN_SEL 0x0000003FU +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003FU +#define GPIO_FUNC90_IN_SEL_S 0 +/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001U +#define GPIO_SIG90_IN_SEL_S 7 + +/** GPIO_FUNC91_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) +/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC91_IN_SEL 0x0000003FU +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003FU +#define GPIO_FUNC91_IN_SEL_S 0 +/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001U +#define GPIO_SIG91_IN_SEL_S 7 + +/** GPIO_FUNC92_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC92_IN_SEL 0x0000003FU +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003FU +#define GPIO_FUNC92_IN_SEL_S 0 +/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001U +#define GPIO_SIG92_IN_SEL_S 7 + +/** GPIO_FUNC93_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) +/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC93_IN_SEL 0x0000003FU +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003FU +#define GPIO_FUNC93_IN_SEL_S 0 +/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001U +#define GPIO_SIG93_IN_SEL_S 7 + +/** GPIO_FUNC94_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) +/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC94_IN_SEL 0x0000003FU +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003FU +#define GPIO_FUNC94_IN_SEL_S 0 +/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001U +#define GPIO_SIG94_IN_SEL_S 7 + +/** GPIO_FUNC95_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) +/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC95_IN_SEL 0x0000003FU +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003FU +#define GPIO_FUNC95_IN_SEL_S 0 +/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001U +#define GPIO_SIG95_IN_SEL_S 7 + +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 7 + +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 7 + +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 7 + +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 7 + +/** GPIO_FUNC101_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC101_IN_SEL 0x0000003FU +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003FU +#define GPIO_FUNC101_IN_SEL_S 0 +/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001U +#define GPIO_SIG101_IN_SEL_S 7 + +/** GPIO_FUNC102_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC102_IN_SEL 0x0000003FU +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003FU +#define GPIO_FUNC102_IN_SEL_S 0 +/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001U +#define GPIO_SIG102_IN_SEL_S 7 + +/** GPIO_FUNC103_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC103_IN_SEL 0x0000003FU +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003FU +#define GPIO_FUNC103_IN_SEL_S 0 +/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001U +#define GPIO_SIG103_IN_SEL_S 7 + +/** GPIO_FUNC104_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC104_IN_SEL 0x0000003FU +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003FU +#define GPIO_FUNC104_IN_SEL_S 0 +/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001U +#define GPIO_SIG104_IN_SEL_S 7 + +/** GPIO_FUNC105_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC105_IN_SEL 0x0000003FU +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003FU +#define GPIO_FUNC105_IN_SEL_S 0 +/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001U +#define GPIO_SIG105_IN_SEL_S 7 + +/** GPIO_FUNC106_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC106_IN_SEL 0x0000003FU +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003FU +#define GPIO_FUNC106_IN_SEL_S 0 +/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001U +#define GPIO_SIG106_IN_SEL_S 7 + +/** GPIO_FUNC107_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC107_IN_SEL 0x0000003FU +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003FU +#define GPIO_FUNC107_IN_SEL_S 0 +/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001U +#define GPIO_SIG107_IN_SEL_S 7 + +/** GPIO_FUNC108_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC108_IN_SEL 0x0000003FU +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003FU +#define GPIO_FUNC108_IN_SEL_S 0 +/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001U +#define GPIO_SIG108_IN_SEL_S 7 + +/** GPIO_FUNC109_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC109_IN_SEL 0x0000003FU +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003FU +#define GPIO_FUNC109_IN_SEL_S 0 +/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001U +#define GPIO_SIG109_IN_SEL_S 7 + +/** GPIO_FUNC110_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC110_IN_SEL 0x0000003FU +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003FU +#define GPIO_FUNC110_IN_SEL_S 0 +/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001U +#define GPIO_SIG110_IN_SEL_S 7 + +/** GPIO_FUNC111_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC111_IN_SEL 0x0000003FU +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003FU +#define GPIO_FUNC111_IN_SEL_S 0 +/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001U +#define GPIO_SIG111_IN_SEL_S 7 + +/** GPIO_FUNC112_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC112_IN_SEL 0x0000003FU +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003FU +#define GPIO_FUNC112_IN_SEL_S 0 +/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001U +#define GPIO_SIG112_IN_SEL_S 7 + +/** GPIO_FUNC113_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC113_IN_SEL 0x0000003FU +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003FU +#define GPIO_FUNC113_IN_SEL_S 0 +/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001U +#define GPIO_SIG113_IN_SEL_S 7 + +/** GPIO_FUNC114_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) +/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC114_IN_SEL 0x0000003FU +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003FU +#define GPIO_FUNC114_IN_SEL_S 0 +/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001U +#define GPIO_SIG114_IN_SEL_S 7 + +/** GPIO_FUNC115_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC115_IN_SEL 0x0000003FU +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003FU +#define GPIO_FUNC115_IN_SEL_S 0 +/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001U +#define GPIO_SIG115_IN_SEL_S 7 + +/** GPIO_FUNC116_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC116_IN_SEL 0x0000003FU +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003FU +#define GPIO_FUNC116_IN_SEL_S 0 +/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001U +#define GPIO_SIG116_IN_SEL_S 7 + +/** GPIO_FUNC117_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC117_IN_SEL 0x0000003FU +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003FU +#define GPIO_FUNC117_IN_SEL_S 0 +/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001U +#define GPIO_SIG117_IN_SEL_S 7 + +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 7 + +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 7 + +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 7 + +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 7 + +/** GPIO_FUNC122_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC122_IN_SEL 0x0000003FU +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003FU +#define GPIO_FUNC122_IN_SEL_S 0 +/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001U +#define GPIO_SIG122_IN_SEL_S 7 + +/** GPIO_FUNC123_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC123_IN_SEL 0x0000003FU +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003FU +#define GPIO_FUNC123_IN_SEL_S 0 +/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001U +#define GPIO_SIG123_IN_SEL_S 7 + +/** GPIO_FUNC124_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC124_IN_SEL 0x0000003FU +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003FU +#define GPIO_FUNC124_IN_SEL_S 0 +/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001U +#define GPIO_SIG124_IN_SEL_S 7 + +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC0_OUT_SEL 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_SEL_S 9 +/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_INV_SEL_S 10 + +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC1_OUT_SEL 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_SEL_S 9 +/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_INV_SEL_S 10 + +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) +/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC2_OUT_SEL 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_SEL_S 9 +/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_INV_SEL_S 10 + +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC3_OUT_SEL 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_SEL_S 9 +/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_INV_SEL_S 10 + +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC4_OUT_SEL 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_SEL_S 9 +/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_INV_SEL_S 10 + +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC5_OUT_SEL 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_SEL_S 9 +/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_INV_SEL_S 10 + +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) +/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC6_OUT_SEL 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_SEL_S 9 +/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_INV_SEL_S 10 + +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC7_OUT_SEL 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_SEL_S 9 +/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_INV_SEL_S 10 + +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC8_OUT_SEL 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_SEL_S 9 +/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_INV_SEL_S 10 + +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC9_OUT_SEL 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_SEL_S 9 +/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_INV_SEL_S 10 + +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) +/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC10_OUT_SEL 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_SEL_S 9 +/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_INV_SEL_S 10 + +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC11_OUT_SEL 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_SEL_S 9 +/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_INV_SEL_S 10 + +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC12_OUT_SEL 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_SEL_S 9 +/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_INV_SEL_S 10 + +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC13_OUT_SEL 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_SEL_S 9 +/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_INV_SEL_S 10 + +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) +/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC14_OUT_SEL 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_SEL_S 9 +/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_INV_SEL_S 10 + +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC15_OUT_SEL 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_SEL_S 9 +/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_INV_SEL_S 10 + +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC16_OUT_SEL 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_SEL_S 9 +/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_INV_SEL_S 10 + +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC17_OUT_SEL 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_SEL_S 9 +/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_INV_SEL_S 10 + +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) +/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC18_OUT_SEL 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_SEL_S 9 +/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_INV_SEL_S 10 + +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) +/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC19_OUT_SEL 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_SEL_S 9 +/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_INV_SEL_S 10 + +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) +/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC20_OUT_SEL 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_SEL_S 9 +/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_INV_SEL_S 10 + +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) +/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC21_OUT_SEL 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_SEL_S 9 +/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_INV_SEL_S 10 + +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) +/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC22_OUT_SEL 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_SEL_S 9 +/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_INV_SEL_S 10 + +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) +/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC23_OUT_SEL 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_SEL_S 9 +/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_INV_SEL_S 10 + +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) +/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC24_OUT_SEL 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_SEL_S 9 +/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_INV_SEL_S 10 + +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_SEL_S 9 +/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_INV_SEL_S 10 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_SEL_S 9 +/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_INV_SEL_S 10 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_SEL_S 9 +/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_INV_SEL_S 10 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_SEL_S 9 +/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_INV_SEL_S 10 + +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) +/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_SEL_S 9 +/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_INV_SEL_S 10 + +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) +/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 8 +/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OEN_SEL (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_SEL_S 9 +/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_INV_SEL_S 10 + +/** GPIO_FUNC31_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) +/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC31_OUT_SEL 0x000000FFU +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC31_OUT_SEL_S 0 +/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OUT_INV_SEL_S 8 +/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC31_OEN_SEL (BIT(9)) +#define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) +#define GPIO_FUNC31_OEN_SEL_V 0x00000001U +#define GPIO_FUNC31_OEN_SEL_S 9 +/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OEN_INV_SEL_S 10 + +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_DATE_REG register + * GPIO version register + */ +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 35655968; + * version register + */ +#define GPIO_DATE 0x0FFFFFFFU +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFFU +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/gpio_sig_map.h b/components/soc/esp32h2/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..baa9a4f6d3 --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_sig_map.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define MODEM_DIAG0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define MODEM_DIAG1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define MODEM_DIAG2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define MODEM_DIAG3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define MODEM_DIAG4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define MODEM_DIAG5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define MODEM_DIAG6_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define USB_JTAG_TDO_BRIDGE_IDX 19 +#define USB_JTAG_TRST_IDX 19 +#define CPU_TESTBUS0_IDX 20 +#define CPU_TESTBUS1_IDX 21 +#define CPU_TESTBUS2_IDX 22 +#define CPU_TESTBUS3_IDX 23 +#define CPU_TESTBUS4_IDX 24 +#define CPU_TESTBUS5_IDX 25 +#define CPU_TESTBUS6_IDX 26 +#define CPU_TESTBUS7_IDX 27 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define USB_JTAG_TCK_IDX 36 +#define USB_JTAG_TMS_IDX 37 +#define USB_JTAG_TDI_IDX 38 +#define USB_JTAG_TDO_IDX 39 +#define USB_EXTPHY_VP_IDX 40 +#define USB_EXTPHY_OEN_IDX 40 +#define USB_EXTPHY_VM_IDX 41 +#define USB_EXTPHY_SPEED_IDX 41 +#define USB_EXTPHY_RCV_IDX 42 +#define USB_EXTPHY_VPO_IDX 42 +#define USB_EXTPHY_VMO_IDX 43 +#define USB_EXTPHY_SUSPND_IDX 44 +#define I2CEXT0_SCL_IN_IDX 45 +#define I2CEXT0_SCL_OUT_IDX 45 +#define I2CEXT0_SDA_IN_IDX 46 +#define I2CEXT0_SDA_OUT_IDX 46 +#define PARL_RX_DATA0_IDX 47 +#define PARL_TX_DATA0_IDX 47 +#define PARL_RX_DATA1_IDX 48 +#define PARL_TX_DATA1_IDX 48 +#define PARL_RX_DATA2_IDX 49 +#define PARL_TX_DATA2_IDX 49 +#define PARL_RX_DATA3_IDX 50 +#define PARL_TX_DATA3_IDX 50 +#define PARL_RX_DATA4_IDX 51 +#define PARL_TX_DATA4_IDX 51 +#define PARL_RX_DATA5_IDX 52 +#define PARL_TX_DATA5_IDX 52 +#define PARL_RX_DATA6_IDX 53 +#define PARL_TX_DATA6_IDX 53 +#define PARL_RX_DATA7_IDX 54 +#define PARL_TX_DATA7_IDX 54 +#define I2CEXT1_SCL_IN_IDX 55 +#define I2CEXT1_SCL_OUT_IDX 55 +#define I2CEXT1_SDA_IN_IDX 56 +#define I2CEXT1_SDA_OUT_IDX 56 +#define CTE_ANT0_IDX 57 +#define CTE_ANT1_IDX 58 +#define CTE_ANT2_IDX 59 +#define CTE_ANT3_IDX 60 +#define CTE_ANT4_IDX 61 +#define CTE_ANT5_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define MODEM_DIAG7_IDX 68 +#define PARL_RX_CLK_IN_IDX 69 +#define PARL_RX_CLK_OUT_IDX 69 +#define PARL_TX_CLK_IN_IDX 70 +#define PARL_TX_CLK_OUT_IDX 70 +#define RMT_SIG_IN0_IDX 71 +#define RMT_SIG_OUT0_IDX 71 +#define MODEM_DIAG8_IDX 71 +#define RMT_SIG_IN1_IDX 72 +#define RMT_SIG_OUT1_IDX 72 +#define MODEM_DIAG9_IDX 72 +#define CAN0_RX_IDX 73 +#define CAN0_TX_IDX 73 +#define MODEM_DIAG10_IDX 73 +#define CAN0_BUS_OFF_ON_IDX 74 +#define MODEM_DIAG11_IDX 74 +#define CAN0_CLKOUT_IDX 75 +#define MODEM_DIAG12_IDX 75 +#define CAN0_STANDBY_IDX 76 +#define MODEM_DIAG13_IDX 76 +#define CTE_ANT6_IDX 77 +#define CTE_ANT7_IDX 78 +#define CTE_ANT8_IDX 79 +#define CTE_ANT9_IDX 80 +#define EXTERN_PRIORITY_I_IDX 81 +#define EXTERN_PRIORITY_O_IDX 81 +#define EXTERN_ACTIVE_I_IDX 82 +#define EXTERN_ACTIVE_O_IDX 82 +#define GPIO_SD0_OUT_IDX 83 +#define GPIO_SD1_OUT_IDX 84 +#define GPIO_SD2_OUT_IDX 85 +#define GPIO_SD3_OUT_IDX 86 +#define PWM0_SYNC0_IN_IDX 87 +#define PWM0_OUT0A_IDX 87 +#define MODEM_DIAG14_IDX 87 +#define PWM0_SYNC1_IN_IDX 88 +#define PWM0_OUT0B_IDX 88 +#define MODEM_DIAG15_IDX 88 +#define PWM0_SYNC2_IN_IDX 89 +#define PWM0_OUT1A_IDX 89 +#define MODEM_DIAG16_IDX 89 +#define PWM0_F0_IN_IDX 90 +#define PWM0_OUT1B_IDX 90 +#define MODEM_DIAG17_IDX 90 +#define PWM0_F1_IN_IDX 91 +#define PWM0_OUT2A_IDX 91 +#define MODEM_DIAG18_IDX 91 +#define PWM0_F2_IN_IDX 92 +#define PWM0_OUT2B_IDX 92 +#define MODEM_DIAG19_IDX 92 +#define PWM0_CAP0_IN_IDX 93 +#define ANT_SEL0_IDX 93 +#define PWM0_CAP1_IN_IDX 94 +#define ANT_SEL1_IDX 94 +#define PWM0_CAP2_IN_IDX 95 +#define ANT_SEL2_IDX 95 +#define ANT_SEL3_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 101 +#define FSPICS1_OUT_IDX 101 +#define MODEM_DIAG20_IDX 101 +#define PCNT_SIG_CH1_IN0_IDX 102 +#define FSPICS2_OUT_IDX 102 +#define MODEM_DIAG21_IDX 102 +#define PCNT_CTRL_CH0_IN0_IDX 103 +#define FSPICS3_OUT_IDX 103 +#define MODEM_DIAG22_IDX 103 +#define PCNT_CTRL_CH1_IN0_IDX 104 +#define FSPICS4_OUT_IDX 104 +#define MODEM_DIAG23_IDX 104 +#define PCNT_SIG_CH0_IN1_IDX 105 +#define FSPICS5_OUT_IDX 105 +#define MODEM_DIAG24_IDX 105 +#define PCNT_SIG_CH1_IN1_IDX 106 +#define CTE_ANT10_IDX 106 +#define PCNT_CTRL_CH0_IN1_IDX 107 +#define CTE_ANT11_IDX 107 +#define PCNT_CTRL_CH1_IN1_IDX 108 +#define CTE_ANT12_IDX 108 +#define PCNT_SIG_CH0_IN2_IDX 109 +#define CTE_ANT13_IDX 109 +#define PCNT_SIG_CH1_IN2_IDX 110 +#define CTE_ANT14_IDX 110 +#define PCNT_CTRL_CH0_IN2_IDX 111 +#define CTE_ANT15_IDX 111 +#define PCNT_CTRL_CH1_IN2_IDX 112 +#define MODEM_DIAG25_IDX 112 +#define PCNT_SIG_CH0_IN3_IDX 113 +#define MODEM_DIAG26_IDX 113 +#define PCNT_SIG_CH1_IN3_IDX 114 +#define SPICLK_OUT_IDX 114 +#define PCNT_CTRL_CH0_IN3_IDX 115 +#define SPICS0_OUT_IDX 115 +#define MODEM_DIAG27_IDX 115 +#define PCNT_CTRL_CH1_IN3_IDX 116 +#define SPICS1_OUT_IDX 116 +#define MODEM_DIAG28_IDX 116 +#define GPIO_EVENT_MATRIX_IN0_IDX 117 +#define GPIO_TASK_MATRIX_OUT0_IDX 117 +#define GPIO_EVENT_MATRIX_IN1_IDX 118 +#define GPIO_TASK_MATRIX_OUT1_IDX 118 +#define GPIO_EVENT_MATRIX_IN2_IDX 119 +#define GPIO_TASK_MATRIX_OUT2_IDX 119 +#define GPIO_EVENT_MATRIX_IN3_IDX 120 +#define GPIO_TASK_MATRIX_OUT3_IDX 120 +#define SPIQ_IN_IDX 121 +#define SPIQ_OUT_IDX 121 +#define SPID_IN_IDX 122 +#define SPID_OUT_IDX 122 +#define SPIHD_IN_IDX 123 +#define SPIHD_OUT_IDX 123 +#define SPIWP_IN_IDX 124 +#define SPIWP_OUT_IDX 124 +#define CLK_OUT_OUT1_IDX 125 +#define MODEM_DIAG29_IDX 125 +#define CLK_OUT_OUT2_IDX 126 +#define MODEM_DIAG30_IDX 126 +#define CLK_OUT_OUT3_IDX 127 +#define MODEM_DIAG31_IDX 127 +#define SIG_GPIO_OUT_IDX 128 +#define GPIO_MAP_DATE_IDX 0x2201120 diff --git a/components/soc/esp32h2/include/soc/gpio_struct.h b/components/soc/esp32h2/include/soc/gpio_struct.h new file mode 100644 index 0000000000..f1e8327deb --- /dev/null +++ b/components/soc/esp32h2/include/soc/gpio_struct.h @@ -0,0 +1,405 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration register */ +/** Type of bt_select register + * GPIO bit select register + */ +typedef union { + struct { + /** bt_sel : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ + uint32_t bt_sel:32; + }; + uint32_t val; +} gpio_bt_select_reg_t; + +/** Type of out register + * GPIO output register for GPIO0-31 + */ +typedef union { + struct { + /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 + */ + uint32_t out_data_orig:32; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register for GPIO0-31 + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 + */ + uint32_t out_w1ts:32; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register for GPIO0-31 + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 + */ + uint32_t out_w1tc:32; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of sdio_select register + * GPIO sdio select register + */ +typedef union { + struct { + /** sdio_sel : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ + uint32_t sdio_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_sdio_select_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-31 + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ + uint32_t enable_data:32; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register for GPIO0-31 + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 + */ + uint32_t enable_w1ts:32; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register for GPIO0-31 + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 + */ + uint32_t enable_w1tc:32; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of strap register + * pad strapping register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-31 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ + uint32_t in_data_next:32; + }; + uint32_t val; +} gpio_in_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ + uint32_t status_interrupt:32; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register for GPIO0-31 + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 + */ + uint32_t status_w1ts:32; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register for GPIO0-31 + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 + */ + uint32_t status_w1tc:32; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of pcpu_int register + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ + uint32_t procpu_int:32; + }; + uint32_t val; +} gpio_pcpu_int_reg_t; + +/** Type of pcpu_nmi_int register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_nmi_int : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ + uint32_t procpu_nmi_int:32; + }; + uint32_t val; +} gpio_pcpu_nmi_int_reg_t; + +/** Type of cpusdio_int register + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [31:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ + uint32_t sdio_int:32; + }; + uint32_t val; +} gpio_cpusdio_int_reg_t; + +/** Type of pinn register + * GPIO pin configuration register + */ +typedef union { + struct { + /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t sync2_bypass:2; + /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ + uint32_t pad_driver:1; + /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t sync1_bypass:2; + uint32_t reserved_5:2; + /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ + uint32_t int_type:3; + /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ + uint32_t wakeup_enable:1; + /** pinn_config : R/W; bitpos: [12:11]; default: 0; + * reserved + */ + uint32_t config:2; + /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ + uint32_t int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:32; + }; + uint32_t val; +} gpio_status_next_reg_t; + +/** Type of func0_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func0_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t in_sel:6; + /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t in_inv_sel:1; + /** sig0_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func_in_sel_cfg_reg_t; + +/** Type of funcn_out_sel_cfg register + * GPIO output function select register + */ +typedef union { + struct { + /** funcn_out_sel : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ + uint32_t out_sel:8; + /** funcn_out_inv_sel : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ + uint32_t out_inv_sel:1; + /** funcn_oen_sel : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ + uint32_t oen_sel:1; + /** funcn_oen_inv_sel : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ + uint32_t oen_inv_sel:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} gpio_func_out_sel_cfg_reg_t; + +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + +/** Type of date register + * GPIO version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655968; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_date_reg_t; + + +typedef struct { + volatile gpio_bt_select_reg_t bt_select; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + uint32_t reserved_010[3]; + volatile gpio_sdio_select_reg_t sdio_select; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + uint32_t reserved_02c[3]; + volatile gpio_strap_reg_t strap; + volatile gpio_in_reg_t in; + uint32_t reserved_040; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + uint32_t reserved_050[3]; + volatile gpio_pcpu_int_reg_t pcpu_int; + volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; + volatile gpio_cpusdio_int_reg_t cpusdio_int; + uint32_t reserved_068[3]; + volatile gpio_pin_reg_t pin[32]; + uint32_t reserved_0f4[22]; + volatile gpio_status_next_reg_t status_next; + uint32_t reserved_150; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[125]; + uint32_t reserved_348[131]; + volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[32]; + uint32_t reserved_5d4[22]; + volatile gpio_clock_gate_reg_t clock_gate; + uint32_t reserved_630[51]; + volatile gpio_date_reg_t date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hmac_reg.h b/components/soc/esp32h2/include/soc/hmac_reg.h new file mode 100644 index 0000000000..16d527ba0e --- /dev/null +++ b/components/soc/esp32h2/include/soc/hmac_reg.h @@ -0,0 +1,232 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HMAC_SET_START_REG register + * Process control register 0. + */ +#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40) +/** HMAC_SET_START : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ +#define HMAC_SET_START (BIT(0)) +#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S) +#define HMAC_SET_START_V 0x00000001U +#define HMAC_SET_START_S 0 + +/** HMAC_SET_PARA_PURPOSE_REG register + * Configure purpose. + */ +#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44) +/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ +#define HMAC_PURPOSE_SET 0x0000000FU +#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S) +#define HMAC_PURPOSE_SET_V 0x0000000FU +#define HMAC_PURPOSE_SET_S 0 + +/** HMAC_SET_PARA_KEY_REG register + * Configure key. + */ +#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48) +/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ +#define HMAC_KEY_SET 0x00000007U +#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S) +#define HMAC_KEY_SET_V 0x00000007U +#define HMAC_KEY_SET_S 0 + +/** HMAC_SET_PARA_FINISH_REG register + * Finish initial configuration. + */ +#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c) +/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ +#define HMAC_SET_PARA_END (BIT(0)) +#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S) +#define HMAC_SET_PARA_END_V 0x00000001U +#define HMAC_SET_PARA_END_S 0 + +/** HMAC_SET_MESSAGE_ONE_REG register + * Process control register 1. + */ +#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50) +/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ +#define HMAC_SET_TEXT_ONE (BIT(0)) +#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S) +#define HMAC_SET_TEXT_ONE_V 0x00000001U +#define HMAC_SET_TEXT_ONE_S 0 + +/** HMAC_SET_MESSAGE_ING_REG register + * Process control register 2. + */ +#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54) +/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ +#define HMAC_SET_TEXT_ING (BIT(0)) +#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S) +#define HMAC_SET_TEXT_ING_V 0x00000001U +#define HMAC_SET_TEXT_ING_S 0 + +/** HMAC_SET_MESSAGE_END_REG register + * Process control register 3. + */ +#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58) +/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ +#define HMAC_SET_TEXT_END (BIT(0)) +#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S) +#define HMAC_SET_TEXT_END_V 0x00000001U +#define HMAC_SET_TEXT_END_S 0 + +/** HMAC_SET_RESULT_FINISH_REG register + * Process control register 4. + */ +#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c) +/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ +#define HMAC_SET_RESULT_END (BIT(0)) +#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S) +#define HMAC_SET_RESULT_END_V 0x00000001U +#define HMAC_SET_RESULT_END_S 0 + +/** HMAC_SET_INVALIDATE_JTAG_REG register + * Invalidate register 0. + */ +#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60) +/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ +#define HMAC_SET_INVALIDATE_JTAG (BIT(0)) +#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S) +#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U +#define HMAC_SET_INVALIDATE_JTAG_S 0 + +/** HMAC_SET_INVALIDATE_DS_REG register + * Invalidate register 1. + */ +#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64) +/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ +#define HMAC_SET_INVALIDATE_DS (BIT(0)) +#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S) +#define HMAC_SET_INVALIDATE_DS_V 0x00000001U +#define HMAC_SET_INVALIDATE_DS_S 0 + +/** HMAC_QUERY_ERROR_REG register + * Error register. + */ +#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68) +/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ +#define HMAC_QUREY_CHECK (BIT(0)) +#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S) +#define HMAC_QUREY_CHECK_V 0x00000001U +#define HMAC_QUREY_CHECK_S 0 + +/** HMAC_QUERY_BUSY_REG register + * Busy register. + */ +#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c) +/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ +#define HMAC_BUSY_STATE (BIT(0)) +#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S) +#define HMAC_BUSY_STATE_V 0x00000001U +#define HMAC_BUSY_STATE_S 0 + +/** HMAC_WR_MESSAGE_MEM register + * Message block memory. + */ +#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80) +#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64 + +/** HMAC_RD_RESULT_MEM register + * Result from upstream. + */ +#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0) +#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32 + +/** HMAC_SET_MESSAGE_PAD_REG register + * Process control register 5. + */ +#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0) +/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0; + * Start software padding. + */ +#define HMAC_SET_TEXT_PAD (BIT(0)) +#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S) +#define HMAC_SET_TEXT_PAD_V 0x00000001U +#define HMAC_SET_TEXT_PAD_S 0 + +/** HMAC_ONE_BLOCK_REG register + * Process control register 6. + */ +#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4) +/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ +#define HMAC_SET_ONE_BLOCK (BIT(0)) +#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S) +#define HMAC_SET_ONE_BLOCK_V 0x00000001U +#define HMAC_SET_ONE_BLOCK_S 0 + +/** HMAC_SOFT_JTAG_CTRL_REG register + * Jtag register 0. + */ +#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8) +/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ +#define HMAC_SOFT_JTAG_CTRL (BIT(0)) +#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S) +#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U +#define HMAC_SOFT_JTAG_CTRL_S 0 + +/** HMAC_WR_JTAG_REG register + * Jtag register 1. + */ +#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc) +/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ +#define HMAC_WR_JTAG 0xFFFFFFFFU +#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S) +#define HMAC_WR_JTAG_V 0xFFFFFFFFU +#define HMAC_WR_JTAG_S 0 + +/** HMAC_DATE_REG register + * Date register. + */ +#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc) +/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ +#define HMAC_DATE 0x3FFFFFFFU +#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S) +#define HMAC_DATE_V 0x3FFFFFFFU +#define HMAC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hmac_struct.h b/components/soc/esp32h2/include/soc/hmac_struct.h new file mode 100644 index 0000000000..45df1b24b8 --- /dev/null +++ b/components/soc/esp32h2/include/soc/hmac_struct.h @@ -0,0 +1,292 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of set_start register + * Process control register 0. + */ +typedef union { + struct { + /** set_start : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_start_reg_t; + +/** Type of set_para_purpose register + * Configure purpose. + */ +typedef union { + struct { + /** purpose_set : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ + uint32_t purpose_set:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} hmac_set_para_purpose_reg_t; + +/** Type of set_para_key register + * Configure key. + */ +typedef union { + struct { + /** key_set : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ + uint32_t key_set:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} hmac_set_para_key_reg_t; + +/** Type of set_para_finish register + * Finish initial configuration. + */ +typedef union { + struct { + /** set_para_end : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ + uint32_t set_para_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_para_finish_reg_t; + +/** Type of set_message_one register + * Process control register 1. + */ +typedef union { + struct { + /** set_text_one : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ + uint32_t set_text_one:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_one_reg_t; + +/** Type of set_message_ing register + * Process control register 2. + */ +typedef union { + struct { + /** set_text_ing : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ + uint32_t set_text_ing:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_ing_reg_t; + +/** Type of set_message_end register + * Process control register 3. + */ +typedef union { + struct { + /** set_text_end : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ + uint32_t set_text_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_end_reg_t; + +/** Type of set_result_finish register + * Process control register 4. + */ +typedef union { + struct { + /** set_result_end : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ + uint32_t set_result_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_result_finish_reg_t; + +/** Type of set_invalidate_jtag register + * Invalidate register 0. + */ +typedef union { + struct { + /** set_invalidate_jtag : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ + uint32_t set_invalidate_jtag:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_jtag_reg_t; + +/** Type of set_invalidate_ds register + * Invalidate register 1. + */ +typedef union { + struct { + /** set_invalidate_ds : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ + uint32_t set_invalidate_ds:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_ds_reg_t; + +/** Type of set_message_pad register + * Process control register 5. + */ +typedef union { + struct { + /** set_text_pad : WO; bitpos: [0]; default: 0; + * Start software padding. + */ + uint32_t set_text_pad:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_pad_reg_t; + +/** Type of one_block register + * Process control register 6. + */ +typedef union { + struct { + /** set_one_block : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ + uint32_t set_one_block:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_one_block_reg_t; + +/** Type of soft_jtag_ctrl register + * Jtag register 0. + */ +typedef union { + struct { + /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ + uint32_t soft_jtag_ctrl:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_soft_jtag_ctrl_reg_t; + +/** Type of wr_jtag register + * Jtag register 1. + */ +typedef union { + struct { + /** wr_jtag : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ + uint32_t wr_jtag:32; + }; + uint32_t val; +} hmac_wr_jtag_reg_t; + + +/** Group: Status Register */ +/** Type of query_error register + * Error register. + */ +typedef union { + struct { + /** qurey_check : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ + uint32_t qurey_check:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_error_reg_t; + +/** Type of query_busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_busy_reg_t; + + +/** Group: Memory Type */ + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} hmac_date_reg_t; + + +typedef struct { + uint32_t reserved_000[16]; + volatile hmac_set_start_reg_t set_start; + volatile hmac_set_para_purpose_reg_t set_para_purpose; + volatile hmac_set_para_key_reg_t set_para_key; + volatile hmac_set_para_finish_reg_t set_para_finish; + volatile hmac_set_message_one_reg_t set_message_one; + volatile hmac_set_message_ing_reg_t set_message_ing; + volatile hmac_set_message_end_reg_t set_message_end; + volatile hmac_set_result_finish_reg_t set_result_finish; + volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag; + volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds; + volatile hmac_query_error_reg_t query_error; + volatile hmac_query_busy_reg_t query_busy; + uint32_t reserved_070[4]; + volatile uint32_t wr_message[16]; + volatile uint32_t rd_result[8]; + uint32_t reserved_0e0[4]; + volatile hmac_set_message_pad_reg_t set_message_pad; + volatile hmac_one_block_reg_t one_block; + volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl; + volatile hmac_wr_jtag_reg_t wr_jtag; + uint32_t reserved_100[63]; + volatile hmac_date_reg_t date; +} hmac_dev_t; + +extern hmac_dev_t HMAC; + +#ifndef __cplusplus +_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hp_apm_reg.h b/components/soc/esp32h2/include/soc/hp_apm_reg.h new file mode 100644 index 0000000000..fb7cc66c15 --- /dev/null +++ b/components/soc/esp32h2/include/soc/hp_apm_reg.h @@ -0,0 +1,1838 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) +/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ +#define HP_APM_REGION_FILTER_EN 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) +#define HP_APM_REGION_FILTER_EN_V 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_S 0 + +/** HP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) +/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) +#define HP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_S 0 + +/** HP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) +/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) +#define HP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_S 0 + +/** HP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) +/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_X (BIT(0)) +#define HP_APM_REGION0_R0_PMS_X_M (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S) +#define HP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_X_S 0 +/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_W (BIT(1)) +#define HP_APM_REGION0_R0_PMS_W_M (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S) +#define HP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_W_S 1 +/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_R (BIT(2)) +#define HP_APM_REGION0_R0_PMS_R_M (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S) +#define HP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_R_S 2 +/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_X (BIT(4)) +#define HP_APM_REGION0_R1_PMS_X_M (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S) +#define HP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_X_S 4 +/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_W (BIT(5)) +#define HP_APM_REGION0_R1_PMS_W_M (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S) +#define HP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_W_S 5 +/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_R (BIT(6)) +#define HP_APM_REGION0_R1_PMS_R_M (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S) +#define HP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_R_S 6 +/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_X (BIT(8)) +#define HP_APM_REGION0_R2_PMS_X_M (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S) +#define HP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_X_S 8 +/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_W (BIT(9)) +#define HP_APM_REGION0_R2_PMS_W_M (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S) +#define HP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_W_S 9 +/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_R (BIT(10)) +#define HP_APM_REGION0_R2_PMS_R_M (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S) +#define HP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_R_S 10 + +/** HP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) +/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) +#define HP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_S 0 + +/** HP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) +/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) +#define HP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_S 0 + +/** HP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) +/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_X (BIT(0)) +#define HP_APM_REGION1_R0_PMS_X_M (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S) +#define HP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_X_S 0 +/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_W (BIT(1)) +#define HP_APM_REGION1_R0_PMS_W_M (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S) +#define HP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_W_S 1 +/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_R (BIT(2)) +#define HP_APM_REGION1_R0_PMS_R_M (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S) +#define HP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_R_S 2 +/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_X (BIT(4)) +#define HP_APM_REGION1_R1_PMS_X_M (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S) +#define HP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_X_S 4 +/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_W (BIT(5)) +#define HP_APM_REGION1_R1_PMS_W_M (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S) +#define HP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_W_S 5 +/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_R (BIT(6)) +#define HP_APM_REGION1_R1_PMS_R_M (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S) +#define HP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_R_S 6 +/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_X (BIT(8)) +#define HP_APM_REGION1_R2_PMS_X_M (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S) +#define HP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_X_S 8 +/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_W (BIT(9)) +#define HP_APM_REGION1_R2_PMS_W_M (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S) +#define HP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_W_S 9 +/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_R (BIT(10)) +#define HP_APM_REGION1_R2_PMS_R_M (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S) +#define HP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_R_S 10 + +/** HP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) +/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) +#define HP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_S 0 + +/** HP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) +/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) +#define HP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_S 0 + +/** HP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) +/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_X (BIT(0)) +#define HP_APM_REGION2_R0_PMS_X_M (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S) +#define HP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_X_S 0 +/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_W (BIT(1)) +#define HP_APM_REGION2_R0_PMS_W_M (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S) +#define HP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_W_S 1 +/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_R (BIT(2)) +#define HP_APM_REGION2_R0_PMS_R_M (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S) +#define HP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_R_S 2 +/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_X (BIT(4)) +#define HP_APM_REGION2_R1_PMS_X_M (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S) +#define HP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_X_S 4 +/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_W (BIT(5)) +#define HP_APM_REGION2_R1_PMS_W_M (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S) +#define HP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_W_S 5 +/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_R (BIT(6)) +#define HP_APM_REGION2_R1_PMS_R_M (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S) +#define HP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_R_S 6 +/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_X (BIT(8)) +#define HP_APM_REGION2_R2_PMS_X_M (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S) +#define HP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_X_S 8 +/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_W (BIT(9)) +#define HP_APM_REGION2_R2_PMS_W_M (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S) +#define HP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_W_S 9 +/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_R (BIT(10)) +#define HP_APM_REGION2_R2_PMS_R_M (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S) +#define HP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_R_S 10 + +/** HP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) +/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) +#define HP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_S 0 + +/** HP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) +/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) +#define HP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_S 0 + +/** HP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) +/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_X (BIT(0)) +#define HP_APM_REGION3_R0_PMS_X_M (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S) +#define HP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_X_S 0 +/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_W (BIT(1)) +#define HP_APM_REGION3_R0_PMS_W_M (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S) +#define HP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_W_S 1 +/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_R (BIT(2)) +#define HP_APM_REGION3_R0_PMS_R_M (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S) +#define HP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_R_S 2 +/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_X (BIT(4)) +#define HP_APM_REGION3_R1_PMS_X_M (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S) +#define HP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_X_S 4 +/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_W (BIT(5)) +#define HP_APM_REGION3_R1_PMS_W_M (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S) +#define HP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_W_S 5 +/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_R (BIT(6)) +#define HP_APM_REGION3_R1_PMS_R_M (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S) +#define HP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_R_S 6 +/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_X (BIT(8)) +#define HP_APM_REGION3_R2_PMS_X_M (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S) +#define HP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_X_S 8 +/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_W (BIT(9)) +#define HP_APM_REGION3_R2_PMS_W_M (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S) +#define HP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_W_S 9 +/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_R (BIT(10)) +#define HP_APM_REGION3_R2_PMS_R_M (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S) +#define HP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_R_S 10 + +/** HP_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) +/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ +#define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) +#define HP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_S 0 + +/** HP_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) +/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ +#define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) +#define HP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_S 0 + +/** HP_APM_REGION4_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) +/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_X (BIT(0)) +#define HP_APM_REGION4_R0_PMS_X_M (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S) +#define HP_APM_REGION4_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_X_S 0 +/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_W (BIT(1)) +#define HP_APM_REGION4_R0_PMS_W_M (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S) +#define HP_APM_REGION4_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_W_S 1 +/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_R (BIT(2)) +#define HP_APM_REGION4_R0_PMS_R_M (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S) +#define HP_APM_REGION4_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_R_S 2 +/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_X (BIT(4)) +#define HP_APM_REGION4_R1_PMS_X_M (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S) +#define HP_APM_REGION4_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_X_S 4 +/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_W (BIT(5)) +#define HP_APM_REGION4_R1_PMS_W_M (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S) +#define HP_APM_REGION4_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_W_S 5 +/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_R (BIT(6)) +#define HP_APM_REGION4_R1_PMS_R_M (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S) +#define HP_APM_REGION4_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_R_S 6 +/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_X (BIT(8)) +#define HP_APM_REGION4_R2_PMS_X_M (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S) +#define HP_APM_REGION4_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_X_S 8 +/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_W (BIT(9)) +#define HP_APM_REGION4_R2_PMS_W_M (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S) +#define HP_APM_REGION4_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_W_S 9 +/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_R (BIT(10)) +#define HP_APM_REGION4_R2_PMS_R_M (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S) +#define HP_APM_REGION4_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_R_S 10 + +/** HP_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) +/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ +#define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) +#define HP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_S 0 + +/** HP_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) +/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ +#define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) +#define HP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_S 0 + +/** HP_APM_REGION5_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) +/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_X (BIT(0)) +#define HP_APM_REGION5_R0_PMS_X_M (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S) +#define HP_APM_REGION5_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_X_S 0 +/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_W (BIT(1)) +#define HP_APM_REGION5_R0_PMS_W_M (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S) +#define HP_APM_REGION5_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_W_S 1 +/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_R (BIT(2)) +#define HP_APM_REGION5_R0_PMS_R_M (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S) +#define HP_APM_REGION5_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_R_S 2 +/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_X (BIT(4)) +#define HP_APM_REGION5_R1_PMS_X_M (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S) +#define HP_APM_REGION5_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_X_S 4 +/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_W (BIT(5)) +#define HP_APM_REGION5_R1_PMS_W_M (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S) +#define HP_APM_REGION5_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_W_S 5 +/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_R (BIT(6)) +#define HP_APM_REGION5_R1_PMS_R_M (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S) +#define HP_APM_REGION5_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_R_S 6 +/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_X (BIT(8)) +#define HP_APM_REGION5_R2_PMS_X_M (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S) +#define HP_APM_REGION5_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_X_S 8 +/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_W (BIT(9)) +#define HP_APM_REGION5_R2_PMS_W_M (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S) +#define HP_APM_REGION5_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_W_S 9 +/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_R (BIT(10)) +#define HP_APM_REGION5_R2_PMS_R_M (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S) +#define HP_APM_REGION5_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_R_S 10 + +/** HP_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) +/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ +#define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) +#define HP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_S 0 + +/** HP_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) +/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ +#define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) +#define HP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_S 0 + +/** HP_APM_REGION6_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) +/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_X (BIT(0)) +#define HP_APM_REGION6_R0_PMS_X_M (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S) +#define HP_APM_REGION6_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_X_S 0 +/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_W (BIT(1)) +#define HP_APM_REGION6_R0_PMS_W_M (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S) +#define HP_APM_REGION6_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_W_S 1 +/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_R (BIT(2)) +#define HP_APM_REGION6_R0_PMS_R_M (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S) +#define HP_APM_REGION6_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_R_S 2 +/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_X (BIT(4)) +#define HP_APM_REGION6_R1_PMS_X_M (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S) +#define HP_APM_REGION6_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_X_S 4 +/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_W (BIT(5)) +#define HP_APM_REGION6_R1_PMS_W_M (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S) +#define HP_APM_REGION6_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_W_S 5 +/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_R (BIT(6)) +#define HP_APM_REGION6_R1_PMS_R_M (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S) +#define HP_APM_REGION6_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_R_S 6 +/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_X (BIT(8)) +#define HP_APM_REGION6_R2_PMS_X_M (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S) +#define HP_APM_REGION6_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_X_S 8 +/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_W (BIT(9)) +#define HP_APM_REGION6_R2_PMS_W_M (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S) +#define HP_APM_REGION6_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_W_S 9 +/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_R (BIT(10)) +#define HP_APM_REGION6_R2_PMS_R_M (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S) +#define HP_APM_REGION6_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_R_S 10 + +/** HP_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) +/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ +#define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) +#define HP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_S 0 + +/** HP_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) +/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ +#define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) +#define HP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_S 0 + +/** HP_APM_REGION7_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) +/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_X (BIT(0)) +#define HP_APM_REGION7_R0_PMS_X_M (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S) +#define HP_APM_REGION7_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_X_S 0 +/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_W (BIT(1)) +#define HP_APM_REGION7_R0_PMS_W_M (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S) +#define HP_APM_REGION7_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_W_S 1 +/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_R (BIT(2)) +#define HP_APM_REGION7_R0_PMS_R_M (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S) +#define HP_APM_REGION7_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_R_S 2 +/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_X (BIT(4)) +#define HP_APM_REGION7_R1_PMS_X_M (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S) +#define HP_APM_REGION7_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_X_S 4 +/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_W (BIT(5)) +#define HP_APM_REGION7_R1_PMS_W_M (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S) +#define HP_APM_REGION7_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_W_S 5 +/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_R (BIT(6)) +#define HP_APM_REGION7_R1_PMS_R_M (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S) +#define HP_APM_REGION7_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_R_S 6 +/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_X (BIT(8)) +#define HP_APM_REGION7_R2_PMS_X_M (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S) +#define HP_APM_REGION7_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_X_S 8 +/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_W (BIT(9)) +#define HP_APM_REGION7_R2_PMS_W_M (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S) +#define HP_APM_REGION7_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_W_S 9 +/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_R (BIT(10)) +#define HP_APM_REGION7_R2_PMS_R_M (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S) +#define HP_APM_REGION7_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_R_S 10 + +/** HP_APM_REGION8_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) +/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ +#define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) +#define HP_APM_REGION8_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_S 0 + +/** HP_APM_REGION8_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) +/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ +#define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) +#define HP_APM_REGION8_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_S 0 + +/** HP_APM_REGION8_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) +/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_X (BIT(0)) +#define HP_APM_REGION8_R0_PMS_X_M (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S) +#define HP_APM_REGION8_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_X_S 0 +/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_W (BIT(1)) +#define HP_APM_REGION8_R0_PMS_W_M (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S) +#define HP_APM_REGION8_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_W_S 1 +/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_R (BIT(2)) +#define HP_APM_REGION8_R0_PMS_R_M (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S) +#define HP_APM_REGION8_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_R_S 2 +/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_X (BIT(4)) +#define HP_APM_REGION8_R1_PMS_X_M (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S) +#define HP_APM_REGION8_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_X_S 4 +/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_W (BIT(5)) +#define HP_APM_REGION8_R1_PMS_W_M (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S) +#define HP_APM_REGION8_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_W_S 5 +/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_R (BIT(6)) +#define HP_APM_REGION8_R1_PMS_R_M (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S) +#define HP_APM_REGION8_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_R_S 6 +/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_X (BIT(8)) +#define HP_APM_REGION8_R2_PMS_X_M (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S) +#define HP_APM_REGION8_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_X_S 8 +/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_W (BIT(9)) +#define HP_APM_REGION8_R2_PMS_W_M (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S) +#define HP_APM_REGION8_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_W_S 9 +/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_R (BIT(10)) +#define HP_APM_REGION8_R2_PMS_R_M (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S) +#define HP_APM_REGION8_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_R_S 10 + +/** HP_APM_REGION9_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) +/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ +#define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) +#define HP_APM_REGION9_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_S 0 + +/** HP_APM_REGION9_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) +/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ +#define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) +#define HP_APM_REGION9_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_S 0 + +/** HP_APM_REGION9_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) +/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_X (BIT(0)) +#define HP_APM_REGION9_R0_PMS_X_M (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S) +#define HP_APM_REGION9_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_X_S 0 +/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_W (BIT(1)) +#define HP_APM_REGION9_R0_PMS_W_M (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S) +#define HP_APM_REGION9_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_W_S 1 +/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_R (BIT(2)) +#define HP_APM_REGION9_R0_PMS_R_M (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S) +#define HP_APM_REGION9_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_R_S 2 +/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_X (BIT(4)) +#define HP_APM_REGION9_R1_PMS_X_M (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S) +#define HP_APM_REGION9_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_X_S 4 +/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_W (BIT(5)) +#define HP_APM_REGION9_R1_PMS_W_M (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S) +#define HP_APM_REGION9_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_W_S 5 +/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_R (BIT(6)) +#define HP_APM_REGION9_R1_PMS_R_M (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S) +#define HP_APM_REGION9_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_R_S 6 +/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_X (BIT(8)) +#define HP_APM_REGION9_R2_PMS_X_M (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S) +#define HP_APM_REGION9_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_X_S 8 +/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_W (BIT(9)) +#define HP_APM_REGION9_R2_PMS_W_M (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S) +#define HP_APM_REGION9_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_W_S 9 +/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_R (BIT(10)) +#define HP_APM_REGION9_R2_PMS_R_M (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S) +#define HP_APM_REGION9_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_R_S 10 + +/** HP_APM_REGION10_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) +/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ +#define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) +#define HP_APM_REGION10_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_S 0 + +/** HP_APM_REGION10_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) +/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ +#define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) +#define HP_APM_REGION10_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_S 0 + +/** HP_APM_REGION10_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) +/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_X (BIT(0)) +#define HP_APM_REGION10_R0_PMS_X_M (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S) +#define HP_APM_REGION10_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_X_S 0 +/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_W (BIT(1)) +#define HP_APM_REGION10_R0_PMS_W_M (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S) +#define HP_APM_REGION10_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_W_S 1 +/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_R (BIT(2)) +#define HP_APM_REGION10_R0_PMS_R_M (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S) +#define HP_APM_REGION10_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_R_S 2 +/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_X (BIT(4)) +#define HP_APM_REGION10_R1_PMS_X_M (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S) +#define HP_APM_REGION10_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_X_S 4 +/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_W (BIT(5)) +#define HP_APM_REGION10_R1_PMS_W_M (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S) +#define HP_APM_REGION10_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_W_S 5 +/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_R (BIT(6)) +#define HP_APM_REGION10_R1_PMS_R_M (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S) +#define HP_APM_REGION10_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_R_S 6 +/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_X (BIT(8)) +#define HP_APM_REGION10_R2_PMS_X_M (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S) +#define HP_APM_REGION10_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_X_S 8 +/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_W (BIT(9)) +#define HP_APM_REGION10_R2_PMS_W_M (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S) +#define HP_APM_REGION10_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_W_S 9 +/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_R (BIT(10)) +#define HP_APM_REGION10_R2_PMS_R_M (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S) +#define HP_APM_REGION10_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_R_S 10 + +/** HP_APM_REGION11_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) +/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ +#define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) +#define HP_APM_REGION11_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_S 0 + +/** HP_APM_REGION11_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) +/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ +#define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) +#define HP_APM_REGION11_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_S 0 + +/** HP_APM_REGION11_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) +/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_X (BIT(0)) +#define HP_APM_REGION11_R0_PMS_X_M (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S) +#define HP_APM_REGION11_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_X_S 0 +/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_W (BIT(1)) +#define HP_APM_REGION11_R0_PMS_W_M (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S) +#define HP_APM_REGION11_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_W_S 1 +/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_R (BIT(2)) +#define HP_APM_REGION11_R0_PMS_R_M (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S) +#define HP_APM_REGION11_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_R_S 2 +/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_X (BIT(4)) +#define HP_APM_REGION11_R1_PMS_X_M (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S) +#define HP_APM_REGION11_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_X_S 4 +/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_W (BIT(5)) +#define HP_APM_REGION11_R1_PMS_W_M (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S) +#define HP_APM_REGION11_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_W_S 5 +/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_R (BIT(6)) +#define HP_APM_REGION11_R1_PMS_R_M (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S) +#define HP_APM_REGION11_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_R_S 6 +/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_X (BIT(8)) +#define HP_APM_REGION11_R2_PMS_X_M (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S) +#define HP_APM_REGION11_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_X_S 8 +/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_W (BIT(9)) +#define HP_APM_REGION11_R2_PMS_W_M (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S) +#define HP_APM_REGION11_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_W_S 9 +/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_R (BIT(10)) +#define HP_APM_REGION11_R2_PMS_R_M (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S) +#define HP_APM_REGION11_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_R_S 10 + +/** HP_APM_REGION12_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) +/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ +#define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) +#define HP_APM_REGION12_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_S 0 + +/** HP_APM_REGION12_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) +/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ +#define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) +#define HP_APM_REGION12_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_S 0 + +/** HP_APM_REGION12_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) +/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_X (BIT(0)) +#define HP_APM_REGION12_R0_PMS_X_M (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S) +#define HP_APM_REGION12_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_X_S 0 +/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_W (BIT(1)) +#define HP_APM_REGION12_R0_PMS_W_M (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S) +#define HP_APM_REGION12_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_W_S 1 +/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_R (BIT(2)) +#define HP_APM_REGION12_R0_PMS_R_M (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S) +#define HP_APM_REGION12_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_R_S 2 +/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_X (BIT(4)) +#define HP_APM_REGION12_R1_PMS_X_M (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S) +#define HP_APM_REGION12_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_X_S 4 +/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_W (BIT(5)) +#define HP_APM_REGION12_R1_PMS_W_M (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S) +#define HP_APM_REGION12_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_W_S 5 +/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_R (BIT(6)) +#define HP_APM_REGION12_R1_PMS_R_M (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S) +#define HP_APM_REGION12_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_R_S 6 +/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_X (BIT(8)) +#define HP_APM_REGION12_R2_PMS_X_M (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S) +#define HP_APM_REGION12_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_X_S 8 +/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_W (BIT(9)) +#define HP_APM_REGION12_R2_PMS_W_M (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S) +#define HP_APM_REGION12_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_W_S 9 +/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_R (BIT(10)) +#define HP_APM_REGION12_R2_PMS_R_M (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S) +#define HP_APM_REGION12_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_R_S 10 + +/** HP_APM_REGION13_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) +/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ +#define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) +#define HP_APM_REGION13_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_S 0 + +/** HP_APM_REGION13_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) +/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ +#define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) +#define HP_APM_REGION13_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_S 0 + +/** HP_APM_REGION13_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) +/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_X (BIT(0)) +#define HP_APM_REGION13_R0_PMS_X_M (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S) +#define HP_APM_REGION13_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_X_S 0 +/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_W (BIT(1)) +#define HP_APM_REGION13_R0_PMS_W_M (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S) +#define HP_APM_REGION13_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_W_S 1 +/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_R (BIT(2)) +#define HP_APM_REGION13_R0_PMS_R_M (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S) +#define HP_APM_REGION13_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_R_S 2 +/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_X (BIT(4)) +#define HP_APM_REGION13_R1_PMS_X_M (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S) +#define HP_APM_REGION13_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_X_S 4 +/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_W (BIT(5)) +#define HP_APM_REGION13_R1_PMS_W_M (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S) +#define HP_APM_REGION13_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_W_S 5 +/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_R (BIT(6)) +#define HP_APM_REGION13_R1_PMS_R_M (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S) +#define HP_APM_REGION13_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_R_S 6 +/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_X (BIT(8)) +#define HP_APM_REGION13_R2_PMS_X_M (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S) +#define HP_APM_REGION13_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_X_S 8 +/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_W (BIT(9)) +#define HP_APM_REGION13_R2_PMS_W_M (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S) +#define HP_APM_REGION13_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_W_S 9 +/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_R (BIT(10)) +#define HP_APM_REGION13_R2_PMS_R_M (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S) +#define HP_APM_REGION13_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_R_S 10 + +/** HP_APM_REGION14_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) +/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ +#define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) +#define HP_APM_REGION14_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_S 0 + +/** HP_APM_REGION14_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) +/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ +#define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) +#define HP_APM_REGION14_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_S 0 + +/** HP_APM_REGION14_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) +/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_X (BIT(0)) +#define HP_APM_REGION14_R0_PMS_X_M (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S) +#define HP_APM_REGION14_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_X_S 0 +/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_W (BIT(1)) +#define HP_APM_REGION14_R0_PMS_W_M (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S) +#define HP_APM_REGION14_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_W_S 1 +/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_R (BIT(2)) +#define HP_APM_REGION14_R0_PMS_R_M (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S) +#define HP_APM_REGION14_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_R_S 2 +/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_X (BIT(4)) +#define HP_APM_REGION14_R1_PMS_X_M (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S) +#define HP_APM_REGION14_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_X_S 4 +/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_W (BIT(5)) +#define HP_APM_REGION14_R1_PMS_W_M (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S) +#define HP_APM_REGION14_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_W_S 5 +/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_R (BIT(6)) +#define HP_APM_REGION14_R1_PMS_R_M (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S) +#define HP_APM_REGION14_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_R_S 6 +/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_X (BIT(8)) +#define HP_APM_REGION14_R2_PMS_X_M (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S) +#define HP_APM_REGION14_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_X_S 8 +/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_W (BIT(9)) +#define HP_APM_REGION14_R2_PMS_W_M (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S) +#define HP_APM_REGION14_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_W_S 9 +/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_R (BIT(10)) +#define HP_APM_REGION14_R2_PMS_R_M (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S) +#define HP_APM_REGION14_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_R_S 10 + +/** HP_APM_REGION15_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) +/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ +#define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) +#define HP_APM_REGION15_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_S 0 + +/** HP_APM_REGION15_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) +/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ +#define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) +#define HP_APM_REGION15_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_S 0 + +/** HP_APM_REGION15_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) +/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_X (BIT(0)) +#define HP_APM_REGION15_R0_PMS_X_M (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S) +#define HP_APM_REGION15_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_X_S 0 +/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_W (BIT(1)) +#define HP_APM_REGION15_R0_PMS_W_M (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S) +#define HP_APM_REGION15_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_W_S 1 +/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_R (BIT(2)) +#define HP_APM_REGION15_R0_PMS_R_M (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S) +#define HP_APM_REGION15_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_R_S 2 +/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_X (BIT(4)) +#define HP_APM_REGION15_R1_PMS_X_M (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S) +#define HP_APM_REGION15_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_X_S 4 +/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_W (BIT(5)) +#define HP_APM_REGION15_R1_PMS_W_M (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S) +#define HP_APM_REGION15_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_W_S 5 +/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_R (BIT(6)) +#define HP_APM_REGION15_R1_PMS_R_M (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S) +#define HP_APM_REGION15_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_R_S 6 +/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_X (BIT(8)) +#define HP_APM_REGION15_R2_PMS_X_M (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S) +#define HP_APM_REGION15_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_X_S 8 +/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_W (BIT(9)) +#define HP_APM_REGION15_R2_PMS_W_M (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S) +#define HP_APM_REGION15_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_W_S 9 +/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_R (BIT(10)) +#define HP_APM_REGION15_R2_PMS_R_M (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S) +#define HP_APM_REGION15_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_R_S 10 + +/** HP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) +/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define HP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define HP_APM_M0_PMS_FUNC_EN_M (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S) +#define HP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M0_PMS_FUNC_EN_S 0 +/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define HP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define HP_APM_M1_PMS_FUNC_EN_M (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S) +#define HP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M1_PMS_FUNC_EN_S 1 +/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define HP_APM_M2_PMS_FUNC_EN (BIT(2)) +#define HP_APM_M2_PMS_FUNC_EN_M (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S) +#define HP_APM_M2_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M2_PMS_FUNC_EN_S 2 +/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define HP_APM_M3_PMS_FUNC_EN (BIT(3)) +#define HP_APM_M3_PMS_FUNC_EN_M (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S) +#define HP_APM_M3_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M3_PMS_FUNC_EN_S 3 + +/** HP_APM_M0_STATUS_REG register + * M0 status register + */ +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) +/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) +#define HP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_S 0 + +/** HP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) +/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M0_REGION_STATUS_CLR_M (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S) +#define HP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M0_REGION_STATUS_CLR_S 0 + +/** HP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) +/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) +#define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_S 0 +/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M0_EXCEPTION_MODE 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) +#define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_S 16 +/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M0_EXCEPTION_ID 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) +#define HP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_S 18 + +/** HP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) +/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) +#define HP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_S 0 + +/** HP_APM_M1_STATUS_REG register + * M1 status register + */ +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) +/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) +#define HP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_S 0 + +/** HP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) +/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M1_REGION_STATUS_CLR_M (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S) +#define HP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M1_REGION_STATUS_CLR_S 0 + +/** HP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) +/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) +#define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_S 0 +/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M1_EXCEPTION_MODE 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) +#define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_S 16 +/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M1_EXCEPTION_ID 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) +#define HP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_S 18 + +/** HP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) +/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) +#define HP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_S 0 + +/** HP_APM_M2_STATUS_REG register + * M2 status register + */ +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) +/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M2_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) +#define HP_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_S 0 + +/** HP_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) +/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M2_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M2_REGION_STATUS_CLR_M (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S) +#define HP_APM_M2_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M2_REGION_STATUS_CLR_S 0 + +/** HP_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) +/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) +#define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_S 0 +/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M2_EXCEPTION_MODE 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) +#define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_S 16 +/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M2_EXCEPTION_ID 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) +#define HP_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_S 18 + +/** HP_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) +/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) +#define HP_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_S 0 + +/** HP_APM_M3_STATUS_REG register + * M3 status register + */ +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) +/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M3_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) +#define HP_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_S 0 + +/** HP_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) +/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M3_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M3_REGION_STATUS_CLR_M (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S) +#define HP_APM_M3_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M3_REGION_STATUS_CLR_S 0 + +/** HP_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) +/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) +#define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_S 0 +/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M3_EXCEPTION_MODE 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) +#define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_S 16 +/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M3_EXCEPTION_ID 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) +#define HP_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_S 18 + +/** HP_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) +/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) +#define HP_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_S 0 + +/** HP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) +/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define HP_APM_M0_APM_INT_EN (BIT(0)) +#define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) +#define HP_APM_M0_APM_INT_EN_V 0x00000001U +#define HP_APM_M0_APM_INT_EN_S 0 +/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define HP_APM_M1_APM_INT_EN (BIT(1)) +#define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) +#define HP_APM_M1_APM_INT_EN_V 0x00000001U +#define HP_APM_M1_APM_INT_EN_S 1 +/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ +#define HP_APM_M2_APM_INT_EN (BIT(2)) +#define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) +#define HP_APM_M2_APM_INT_EN_V 0x00000001U +#define HP_APM_M2_APM_INT_EN_S 2 +/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ +#define HP_APM_M3_APM_INT_EN (BIT(3)) +#define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) +#define HP_APM_M3_APM_INT_EN_V 0x00000001U +#define HP_APM_M3_APM_INT_EN_S 3 + +/** HP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c) +/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define HP_APM_CLK_EN (BIT(0)) +#define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) +#define HP_APM_CLK_EN_V 0x00000001U +#define HP_APM_CLK_EN_S 0 + +/** HP_APM_DATE_REG register + * Version register + */ +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) +/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define HP_APM_DATE 0x0FFFFFFFU +#define HP_APM_DATE_M (HP_APM_DATE_V << HP_APM_DATE_S) +#define HP_APM_DATE_V 0x0FFFFFFFU +#define HP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hp_apm_struct.h b/components/soc/esp32h2/include/soc/hp_apm_struct.h new file mode 100644 index 0000000000..7d583f9539 --- /dev/null +++ b/components/soc/esp32h2/include/soc/hp_apm_struct.h @@ -0,0 +1,1670 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} hp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} hp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} hp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} hp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} hp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} hp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} hp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} hp_apm_region3_addr_end_reg_t; + +/** Type of region4_addr_start register + * Region address register + */ +typedef union { + struct { + /** region4_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ + uint32_t region4_addr_start:32; + }; + uint32_t val; +} hp_apm_region4_addr_start_reg_t; + +/** Type of region4_addr_end register + * Region address register + */ +typedef union { + struct { + /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ + uint32_t region4_addr_end:32; + }; + uint32_t val; +} hp_apm_region4_addr_end_reg_t; + +/** Type of region5_addr_start register + * Region address register + */ +typedef union { + struct { + /** region5_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ + uint32_t region5_addr_start:32; + }; + uint32_t val; +} hp_apm_region5_addr_start_reg_t; + +/** Type of region5_addr_end register + * Region address register + */ +typedef union { + struct { + /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ + uint32_t region5_addr_end:32; + }; + uint32_t val; +} hp_apm_region5_addr_end_reg_t; + +/** Type of region6_addr_start register + * Region address register + */ +typedef union { + struct { + /** region6_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ + uint32_t region6_addr_start:32; + }; + uint32_t val; +} hp_apm_region6_addr_start_reg_t; + +/** Type of region6_addr_end register + * Region address register + */ +typedef union { + struct { + /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ + uint32_t region6_addr_end:32; + }; + uint32_t val; +} hp_apm_region6_addr_end_reg_t; + +/** Type of region7_addr_start register + * Region address register + */ +typedef union { + struct { + /** region7_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ + uint32_t region7_addr_start:32; + }; + uint32_t val; +} hp_apm_region7_addr_start_reg_t; + +/** Type of region7_addr_end register + * Region address register + */ +typedef union { + struct { + /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ + uint32_t region7_addr_end:32; + }; + uint32_t val; +} hp_apm_region7_addr_end_reg_t; + +/** Type of region8_addr_start register + * Region address register + */ +typedef union { + struct { + /** region8_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ + uint32_t region8_addr_start:32; + }; + uint32_t val; +} hp_apm_region8_addr_start_reg_t; + +/** Type of region8_addr_end register + * Region address register + */ +typedef union { + struct { + /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ + uint32_t region8_addr_end:32; + }; + uint32_t val; +} hp_apm_region8_addr_end_reg_t; + +/** Type of region9_addr_start register + * Region address register + */ +typedef union { + struct { + /** region9_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ + uint32_t region9_addr_start:32; + }; + uint32_t val; +} hp_apm_region9_addr_start_reg_t; + +/** Type of region9_addr_end register + * Region address register + */ +typedef union { + struct { + /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ + uint32_t region9_addr_end:32; + }; + uint32_t val; +} hp_apm_region9_addr_end_reg_t; + +/** Type of region10_addr_start register + * Region address register + */ +typedef union { + struct { + /** region10_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ + uint32_t region10_addr_start:32; + }; + uint32_t val; +} hp_apm_region10_addr_start_reg_t; + +/** Type of region10_addr_end register + * Region address register + */ +typedef union { + struct { + /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ + uint32_t region10_addr_end:32; + }; + uint32_t val; +} hp_apm_region10_addr_end_reg_t; + +/** Type of region11_addr_start register + * Region address register + */ +typedef union { + struct { + /** region11_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ + uint32_t region11_addr_start:32; + }; + uint32_t val; +} hp_apm_region11_addr_start_reg_t; + +/** Type of region11_addr_end register + * Region address register + */ +typedef union { + struct { + /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ + uint32_t region11_addr_end:32; + }; + uint32_t val; +} hp_apm_region11_addr_end_reg_t; + +/** Type of region12_addr_start register + * Region address register + */ +typedef union { + struct { + /** region12_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ + uint32_t region12_addr_start:32; + }; + uint32_t val; +} hp_apm_region12_addr_start_reg_t; + +/** Type of region12_addr_end register + * Region address register + */ +typedef union { + struct { + /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ + uint32_t region12_addr_end:32; + }; + uint32_t val; +} hp_apm_region12_addr_end_reg_t; + +/** Type of region13_addr_start register + * Region address register + */ +typedef union { + struct { + /** region13_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ + uint32_t region13_addr_start:32; + }; + uint32_t val; +} hp_apm_region13_addr_start_reg_t; + +/** Type of region13_addr_end register + * Region address register + */ +typedef union { + struct { + /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ + uint32_t region13_addr_end:32; + }; + uint32_t val; +} hp_apm_region13_addr_end_reg_t; + +/** Type of region14_addr_start register + * Region address register + */ +typedef union { + struct { + /** region14_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ + uint32_t region14_addr_start:32; + }; + uint32_t val; +} hp_apm_region14_addr_start_reg_t; + +/** Type of region14_addr_end register + * Region address register + */ +typedef union { + struct { + /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ + uint32_t region14_addr_end:32; + }; + uint32_t val; +} hp_apm_region14_addr_end_reg_t; + +/** Type of region15_addr_start register + * Region address register + */ +typedef union { + struct { + /** region15_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ + uint32_t region15_addr_start:32; + }; + uint32_t val; +} hp_apm_region15_addr_start_reg_t; + +/** Type of region15_addr_end register + * Region address register + */ +typedef union { + struct { + /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ + uint32_t region15_addr_end:32; + }; + uint32_t val; +} hp_apm_region15_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region3_pms_attr_reg_t; + +/** Type of region4_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region4_r0_pms_x:1; + /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region4_r0_pms_w:1; + /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region4_r0_pms_r:1; + uint32_t reserved_3:1; + /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region4_r1_pms_x:1; + /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region4_r1_pms_w:1; + /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region4_r1_pms_r:1; + uint32_t reserved_7:1; + /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region4_r2_pms_x:1; + /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region4_r2_pms_w:1; + /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region4_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region4_pms_attr_reg_t; + +/** Type of region5_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region5_r0_pms_x:1; + /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region5_r0_pms_w:1; + /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region5_r0_pms_r:1; + uint32_t reserved_3:1; + /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region5_r1_pms_x:1; + /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region5_r1_pms_w:1; + /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region5_r1_pms_r:1; + uint32_t reserved_7:1; + /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region5_r2_pms_x:1; + /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region5_r2_pms_w:1; + /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region5_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region5_pms_attr_reg_t; + +/** Type of region6_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region6_r0_pms_x:1; + /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region6_r0_pms_w:1; + /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region6_r0_pms_r:1; + uint32_t reserved_3:1; + /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region6_r1_pms_x:1; + /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region6_r1_pms_w:1; + /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region6_r1_pms_r:1; + uint32_t reserved_7:1; + /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region6_r2_pms_x:1; + /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region6_r2_pms_w:1; + /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region6_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region6_pms_attr_reg_t; + +/** Type of region7_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region7_r0_pms_x:1; + /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region7_r0_pms_w:1; + /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region7_r0_pms_r:1; + uint32_t reserved_3:1; + /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region7_r1_pms_x:1; + /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region7_r1_pms_w:1; + /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region7_r1_pms_r:1; + uint32_t reserved_7:1; + /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region7_r2_pms_x:1; + /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region7_r2_pms_w:1; + /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region7_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region7_pms_attr_reg_t; + +/** Type of region8_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region8_r0_pms_x:1; + /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region8_r0_pms_w:1; + /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region8_r0_pms_r:1; + uint32_t reserved_3:1; + /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region8_r1_pms_x:1; + /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region8_r1_pms_w:1; + /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region8_r1_pms_r:1; + uint32_t reserved_7:1; + /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region8_r2_pms_x:1; + /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region8_r2_pms_w:1; + /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region8_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region8_pms_attr_reg_t; + +/** Type of region9_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region9_r0_pms_x:1; + /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region9_r0_pms_w:1; + /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region9_r0_pms_r:1; + uint32_t reserved_3:1; + /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region9_r1_pms_x:1; + /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region9_r1_pms_w:1; + /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region9_r1_pms_r:1; + uint32_t reserved_7:1; + /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region9_r2_pms_x:1; + /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region9_r2_pms_w:1; + /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region9_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region9_pms_attr_reg_t; + +/** Type of region10_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region10_r0_pms_x:1; + /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region10_r0_pms_w:1; + /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region10_r0_pms_r:1; + uint32_t reserved_3:1; + /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region10_r1_pms_x:1; + /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region10_r1_pms_w:1; + /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region10_r1_pms_r:1; + uint32_t reserved_7:1; + /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region10_r2_pms_x:1; + /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region10_r2_pms_w:1; + /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region10_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region10_pms_attr_reg_t; + +/** Type of region11_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region11_r0_pms_x:1; + /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region11_r0_pms_w:1; + /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region11_r0_pms_r:1; + uint32_t reserved_3:1; + /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region11_r1_pms_x:1; + /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region11_r1_pms_w:1; + /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region11_r1_pms_r:1; + uint32_t reserved_7:1; + /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region11_r2_pms_x:1; + /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region11_r2_pms_w:1; + /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region11_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region11_pms_attr_reg_t; + +/** Type of region12_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region12_r0_pms_x:1; + /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region12_r0_pms_w:1; + /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region12_r0_pms_r:1; + uint32_t reserved_3:1; + /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region12_r1_pms_x:1; + /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region12_r1_pms_w:1; + /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region12_r1_pms_r:1; + uint32_t reserved_7:1; + /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region12_r2_pms_x:1; + /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region12_r2_pms_w:1; + /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region12_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region12_pms_attr_reg_t; + +/** Type of region13_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region13_r0_pms_x:1; + /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region13_r0_pms_w:1; + /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region13_r0_pms_r:1; + uint32_t reserved_3:1; + /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region13_r1_pms_x:1; + /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region13_r1_pms_w:1; + /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region13_r1_pms_r:1; + uint32_t reserved_7:1; + /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region13_r2_pms_x:1; + /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region13_r2_pms_w:1; + /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region13_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region13_pms_attr_reg_t; + +/** Type of region14_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region14_r0_pms_x:1; + /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region14_r0_pms_w:1; + /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region14_r0_pms_r:1; + uint32_t reserved_3:1; + /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region14_r1_pms_x:1; + /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region14_r1_pms_w:1; + /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region14_r1_pms_r:1; + uint32_t reserved_7:1; + /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region14_r2_pms_x:1; + /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region14_r2_pms_w:1; + /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region14_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region14_pms_attr_reg_t; + +/** Type of region15_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region15_r0_pms_x:1; + /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region15_r0_pms_w:1; + /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region15_r0_pms_r:1; + uint32_t reserved_3:1; + /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region15_r1_pms_x:1; + /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region15_r1_pms_w:1; + /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region15_r1_pms_r:1; + uint32_t reserved_7:1; + /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region15_r2_pms_x:1; + /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region15_r2_pms_w:1; + /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region15_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region15_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + /** m2_pms_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_pms_func_en:1; + /** m3_pms_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_pms_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} hp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} hp_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m2_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} hp_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m3_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} hp_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_apm_date_reg_t; + + +typedef struct { + volatile hp_apm_region_filter_en_reg_t region_filter_en; + volatile hp_apm_region0_addr_start_reg_t region0_addr_start; + volatile hp_apm_region0_addr_end_reg_t region0_addr_end; + volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile hp_apm_region1_addr_start_reg_t region1_addr_start; + volatile hp_apm_region1_addr_end_reg_t region1_addr_end; + volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile hp_apm_region2_addr_start_reg_t region2_addr_start; + volatile hp_apm_region2_addr_end_reg_t region2_addr_end; + volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile hp_apm_region3_addr_start_reg_t region3_addr_start; + volatile hp_apm_region3_addr_end_reg_t region3_addr_end; + volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr; + volatile hp_apm_region4_addr_start_reg_t region4_addr_start; + volatile hp_apm_region4_addr_end_reg_t region4_addr_end; + volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr; + volatile hp_apm_region5_addr_start_reg_t region5_addr_start; + volatile hp_apm_region5_addr_end_reg_t region5_addr_end; + volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr; + volatile hp_apm_region6_addr_start_reg_t region6_addr_start; + volatile hp_apm_region6_addr_end_reg_t region6_addr_end; + volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr; + volatile hp_apm_region7_addr_start_reg_t region7_addr_start; + volatile hp_apm_region7_addr_end_reg_t region7_addr_end; + volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr; + volatile hp_apm_region8_addr_start_reg_t region8_addr_start; + volatile hp_apm_region8_addr_end_reg_t region8_addr_end; + volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr; + volatile hp_apm_region9_addr_start_reg_t region9_addr_start; + volatile hp_apm_region9_addr_end_reg_t region9_addr_end; + volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr; + volatile hp_apm_region10_addr_start_reg_t region10_addr_start; + volatile hp_apm_region10_addr_end_reg_t region10_addr_end; + volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr; + volatile hp_apm_region11_addr_start_reg_t region11_addr_start; + volatile hp_apm_region11_addr_end_reg_t region11_addr_end; + volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr; + volatile hp_apm_region12_addr_start_reg_t region12_addr_start; + volatile hp_apm_region12_addr_end_reg_t region12_addr_end; + volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr; + volatile hp_apm_region13_addr_start_reg_t region13_addr_start; + volatile hp_apm_region13_addr_end_reg_t region13_addr_end; + volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr; + volatile hp_apm_region14_addr_start_reg_t region14_addr_start; + volatile hp_apm_region14_addr_end_reg_t region14_addr_end; + volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr; + volatile hp_apm_region15_addr_start_reg_t region15_addr_start; + volatile hp_apm_region15_addr_end_reg_t region15_addr_end; + volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr; + volatile hp_apm_func_ctrl_reg_t func_ctrl; + volatile hp_apm_m0_status_reg_t m0_status; + volatile hp_apm_m0_status_clr_reg_t m0_status_clr; + volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile hp_apm_m1_status_reg_t m1_status; + volatile hp_apm_m1_status_clr_reg_t m1_status_clr; + volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile hp_apm_m2_status_reg_t m2_status; + volatile hp_apm_m2_status_clr_reg_t m2_status_clr; + volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile hp_apm_m3_status_reg_t m3_status; + volatile hp_apm_m3_status_clr_reg_t m3_status_clr; + volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1; + volatile hp_apm_int_en_reg_t int_en; + volatile hp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_110[443]; + volatile hp_apm_date_reg_t date; +} hp_apm_dev_t; + +extern hp_apm_dev_t HP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hp_system_reg.h b/components/soc/esp32h2/include/soc/hp_system_reg.h new file mode 100644 index 0000000000..1660509115 --- /dev/null +++ b/components/soc/esp32h2/include/soc/hp_system_reg.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0) +/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : HRO; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/** HP_SYSTEM_SRAM_USAGE_CONF_REG register + * HP memory usage configuration register + */ +#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4) +/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [14:10]; default: 0; + * 0: cpu use hp-memory. 1: mac-dump accessing hp-memory. + */ +#define HP_SYSTEM_SRAM_USAGE 0x0000001FU +#define HP_SYSTEM_SRAM_USAGE_M (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S) +#define HP_SYSTEM_SRAM_USAGE_V 0x0000001FU +#define HP_SYSTEM_SRAM_USAGE_S 10 +/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [24:20]; default: 0; + * reserved. + */ +#define HP_SYSTEM_MAC_DUMP_ALLOC 0x0000001FU +#define HP_SYSTEM_MAC_DUMP_ALLOC_M (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S) +#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x0000001FU +#define HP_SYSTEM_MAC_DUMP_ALLOC_S 20 +/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [31]; default: 0; + * reserved + */ +#define HP_SYSTEM_CACHE_USAGE (BIT(31)) +#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S) +#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U +#define HP_SYSTEM_CACHE_USAGE_S 31 + +/** HP_SYSTEM_SEC_DPA_CONF_REG register + * HP anti-DPA security configuration register + */ +#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8) +/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + */ +#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U +#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) +#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U +#define HP_SYSTEM_SEC_DPA_LEVEL_S 0 +/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL. + */ +#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2)) +#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S) +#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U +#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register + * CPU_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register + * CPU_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register + * CPU_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register + * HP_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18) +/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register + * HP_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c) +/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register + * HP_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20) +/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_ROM_TABLE_LOCK_REG register + * Rom-Table lock register + */ +#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x24) +/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; + * XXXX + */ +#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0)) +#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S) +#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U +#define HP_SYSTEM_ROM_TABLE_LOCK_S 0 + +/** HP_SYSTEM_ROM_TABLE_REG register + * Rom-Table register + */ +#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x28) +/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ +#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU +#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S) +#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU +#define HP_SYSTEM_ROM_TABLE_S 0 + +/** HP_SYSTEM_MEM_TEST_CONF_REG register + * MEM_TEST configuration register + */ +#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x2c) +/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0; + * This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V + * operating Voltage. + */ +#define HP_SYSTEM_HP_MEM_WPULSE 0x00000007U +#define HP_SYSTEM_HP_MEM_WPULSE_M (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S) +#define HP_SYSTEM_HP_MEM_WPULSE_V 0x00000007U +#define HP_SYSTEM_HP_MEM_WPULSE_S 0 +/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 5; + * This field controls hp system memory WA parameter. 0b100 for 1.1V operating + * Voltage, 0b101 for 1.0V, 0b110 for 0.9V. + */ +#define HP_SYSTEM_HP_MEM_WA 0x00000007U +#define HP_SYSTEM_HP_MEM_WA_M (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S) +#define HP_SYSTEM_HP_MEM_WA_V 0x00000007U +#define HP_SYSTEM_HP_MEM_WA_S 3 +/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0; + * This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating + * Voltage, 0b01 for 0.9V. + */ +#define HP_SYSTEM_HP_MEM_RA 0x00000003U +#define HP_SYSTEM_HP_MEM_RA_M (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S) +#define HP_SYSTEM_HP_MEM_RA_V 0x00000003U +#define HP_SYSTEM_HP_MEM_RA_S 6 +/** HP_SYSTEM_HP_MEM_RM : R/W; bitpos: [11:8]; default: 2; + * This field controls hp system memory RM parameter. 0b0011 for 1.1V operating + * Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V. + */ +#define HP_SYSTEM_HP_MEM_RM 0x0000000FU +#define HP_SYSTEM_HP_MEM_RM_M (HP_SYSTEM_HP_MEM_RM_V << HP_SYSTEM_HP_MEM_RM_S) +#define HP_SYSTEM_HP_MEM_RM_V 0x0000000FU +#define HP_SYSTEM_HP_MEM_RM_S 8 +/** HP_SYSTEM_ROM_RM : R/W; bitpos: [15:12]; default: 2; + * This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for + * 1.0V, 0b0010(default) or 0b0001(slow) for 0.9V. + */ +#define HP_SYSTEM_ROM_RM 0x0000000FU +#define HP_SYSTEM_ROM_RM_M (HP_SYSTEM_ROM_RM_V << HP_SYSTEM_ROM_RM_S) +#define HP_SYSTEM_ROM_RM_V 0x0000000FU +#define HP_SYSTEM_ROM_RM_S 12 + +/** HP_SYSTEM_RND_ECO_REG register + * redcy eco register. + */ +#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0) +/** HP_SYSTEM_REDCY_ENA : R/W; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_ENA (BIT(0)) +#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S) +#define HP_SYSTEM_REDCY_ENA_V 0x00000001U +#define HP_SYSTEM_REDCY_ENA_S 0 +/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_RESULT (BIT(1)) +#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S) +#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U +#define HP_SYSTEM_REDCY_RESULT_S 1 + +/** HP_SYSTEM_RND_ECO_LOW_REG register + * redcy eco low register. + */ +#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4) +/** HP_SYSTEM_REDCY_LOW : R/W; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S) +#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_LOW_S 0 + +/** HP_SYSTEM_RND_ECO_HIGH_REG register + * redcy eco high register. + */ +#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8) +/** HP_SYSTEM_REDCY_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S) +#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_HIGH_S 0 + +/** HP_SYSTEM_CLOCK_GATE_REG register + * HP-SYSTEM clock gating configure register + */ +#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8) +/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define HP_SYSTEM_CLK_EN (BIT(0)) +#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S) +#define HP_SYSTEM_CLK_EN_V 0x00000001U +#define HP_SYSTEM_CLK_EN_S 0 + +/** HP_SYSTEM_DATE_REG register + * Date register. + */ +#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) +/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35689073; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ +#define HP_SYSTEM_DATE 0x0FFFFFFFU +#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S) +#define HP_SYSTEM_DATE_V 0x0FFFFFFFU +#define HP_SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hp_system_struct.h b/components/soc/esp32h2/include/soc/hp_system_struct.h new file mode 100644 index 0000000000..575349312b --- /dev/null +++ b/components/soc/esp32h2/include/soc/hp_system_struct.h @@ -0,0 +1,360 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of external_device_encrypt_decrypt_control register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +typedef union { + struct { + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : HRO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ + uint32_t enable_download_manual_encrypt:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_sys_external_device_encrypt_decrypt_control_reg_t; + +/** Type of sram_usage_conf register + * HP memory usage configuration register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** sram_usage : R/W; bitpos: [14:10]; default: 0; + * 0: cpu use hp-memory. 1: mac-dump accessing hp-memory. + */ + uint32_t sram_usage:5; + uint32_t reserved_15:5; + /** mac_dump_alloc : R/W; bitpos: [24:20]; default: 0; + * reserved. + */ + uint32_t mac_dump_alloc:5; + uint32_t reserved_25:6; + /** cache_usage : HRO; bitpos: [31]; default: 0; + * reserved + */ + uint32_t cache_usage:1; + }; + uint32_t val; +} hp_sys_sram_usage_conf_reg_t; + +/** Type of sec_dpa_conf register + * HP anti-DPA security configuration register + */ +typedef union { + struct { + /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + */ + uint32_t sec_dpa_level:2; + /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_cfg_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} hp_sys_sec_dpa_conf_reg_t; + +/** Type of rom_table_lock register + * Rom-Table lock register + */ +typedef union { + struct { + /** rom_table_lock : R/W; bitpos: [0]; default: 0; + * XXXX + */ + uint32_t rom_table_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_sys_rom_table_lock_reg_t; + +/** Type of rom_table register + * Rom-Table register + */ +typedef union { + struct { + /** rom_table : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ + uint32_t rom_table:32; + }; + uint32_t val; +} hp_sys_rom_table_reg_t; + +/** Type of mem_test_conf register + * MEM_TEST configuration register + */ +typedef union { + struct { + /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0; + * This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V + * operating Voltage. + */ + uint32_t hp_mem_wpulse:3; + /** hp_mem_wa : R/W; bitpos: [5:3]; default: 5; + * This field controls hp system memory WA parameter. 0b100 for 1.1V operating + * Voltage, 0b101 for 1.0V, 0b110 for 0.9V. + */ + uint32_t hp_mem_wa:3; + /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0; + * This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating + * Voltage, 0b01 for 0.9V. + */ + uint32_t hp_mem_ra:2; + /** hp_mem_rm : R/W; bitpos: [11:8]; default: 2; + * This field controls hp system memory RM parameter. 0b0011 for 1.1V operating + * Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V. + */ + uint32_t hp_mem_rm:4; + /** rom_rm : R/W; bitpos: [15:12]; default: 2; + * This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for + * 1.0V, 0b0010(default) or 0b0001(slow) for 0.9V. + */ + uint32_t rom_rm:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_sys_mem_test_conf_reg_t; + +/** Type of clock_gate register + * HP-SYSTEM clock gating configure register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_sys_clock_gate_reg_t; + + +/** Group: Timeout Register */ +/** Type of cpu_peri_timeout_conf register + * CPU_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t cpu_peri_timeout_thres:16; + /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t cpu_peri_timeout_int_clear:1; + /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ + uint32_t cpu_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_conf_reg_t; + +/** Type of cpu_peri_timeout_addr register + * CPU_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t cpu_peri_timeout_addr:32; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_addr_reg_t; + +/** Type of cpu_peri_timeout_uid register + * CPU_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t cpu_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_uid_reg_t; + +/** Type of hp_peri_timeout_conf register + * HP_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t hp_peri_timeout_thres:16; + /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t hp_peri_timeout_int_clear:1; + /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ + uint32_t hp_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_conf_reg_t; + +/** Type of hp_peri_timeout_addr register + * HP_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t hp_peri_timeout_addr:32; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_addr_reg_t; + +/** Type of hp_peri_timeout_uid register + * HP_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t hp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_uid_reg_t; + + +/** Group: Redcy ECO Registers */ +/** Type of rnd_eco register + * redcy eco register. + */ +typedef union { + struct { + /** redcy_ena : R/W; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_ena:1; + /** redcy_result : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_sys_rnd_eco_reg_t; + +/** Type of rnd_eco_low register + * redcy eco low register. + */ +typedef union { + struct { + /** redcy_low : R/W; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_low:32; + }; + uint32_t val; +} hp_sys_rnd_eco_low_reg_t; + +/** Type of rnd_eco_high register + * redcy eco high register. + */ +typedef union { + struct { + /** redcy_high : R/W; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ + uint32_t redcy_high:32; + }; + uint32_t val; +} hp_sys_rnd_eco_high_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35689073; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_sys_date_reg_t; + + +typedef struct { + volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; + volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf; + volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf; + volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; + volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; + volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; + volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; + volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; + volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; + volatile hp_sys_rom_table_lock_reg_t rom_table_lock; + volatile hp_sys_rom_table_reg_t rom_table; + volatile hp_sys_mem_test_conf_reg_t mem_test_conf; + uint32_t reserved_030[236]; + volatile hp_sys_rnd_eco_reg_t rnd_eco; + volatile hp_sys_rnd_eco_low_reg_t rnd_eco_low; + volatile hp_sys_rnd_eco_high_reg_t rnd_eco_high; + uint32_t reserved_3ec[3]; + volatile hp_sys_clock_gate_reg_t clock_gate; + volatile hp_sys_date_reg_t date; +} hp_sys_dev_t; + +extern hp_sys_dev_t HP_SYSTEM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/hwcrypto_reg.h b/components/soc/esp32h2/include/soc/hwcrypto_reg.h new file mode 100644 index 0000000000..62b0f2fb01 --- /dev/null +++ b/components/soc/esp32h2/include/soc/hwcrypto_reg.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/aes_reg.h" +#include "soc/ds_reg.h" +#include "soc/hmac_reg.h" +#include "soc/rsa_reg.h" +#include "soc/sha_reg.h" diff --git a/components/soc/esp32h2/include/soc/i2c_reg.h b/components/soc/esp32h2/include/soc/i2c_reg.h new file mode 100644 index 0000000000..b965d0a464 --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2c_reg.h @@ -0,0 +1,1450 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define I2C_SCL_LOW_PERIOD_S 0 + +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) +/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * 1: direct output, 0: open drain output. + */ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) +#define I2C_SDA_FORCE_OUT_V 0x00000001U +#define I2C_SDA_FORCE_OUT_S 0 +/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * 1: direct output, 0: open drain output. + */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) +#define I2C_SCL_FORCE_OUT_V 0x00000001U +#define I2C_SCL_FORCE_OUT_S 1 +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; + * Set this bit to configure the module as an I2C Master. Clear this bit to configure + * the + * module as an I2C Slave. + */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) +#define I2C_MS_MODE_V 0x00000001U +#define I2C_MS_MODE_S 4 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit, + * 0: send data from the most significant bit. + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit, + * 0: receive data from the most significant bit. + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * synchronization bit + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 +/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; + * This is the enable bit for slave to send data automatically + */ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; + * This is the enable bit to check if the r/w bit of 10bit addressing consists with + * I2C protocol + */ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; + * This is the enable bit to support the 7bit general call function. + */ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) +#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/** I2C_SR_REG register + * Describe I2C work status. + */ +#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U +#define I2C_RESP_REC_S 0 +/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * When in slave mode, 1: master reads from slave, 0: master writes to slave. + */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) +#define I2C_SLAVE_RW_V 0x00000001U +#define I2C_SLAVE_RW_S 1 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; + * When configured as an I2C Slave, and the address sent by the master is + * equal to the address of the slave, then this bit will be of high level. + */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) +#define I2C_SLAVE_ADDRESSED_V 0x00000001U +#define I2C_SLAVE_ADDRESSED_S 5 +/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ +#define I2C_RXFIFO_CNT 0x0000003FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000003FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; + * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the + * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty + * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + */ +#define I2C_STRETCH_CAUSE 0x00000003U +#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) +#define I2C_STRETCH_CAUSE_V 0x00000003U +#define I2C_STRETCH_CAUSE_S 14 +/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; + * This field stores the amount of received data in RAM. + */ +#define I2C_TXFIFO_CNT 0x0000003FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000003FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: + * Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 + +/** I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU +#define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 + +/** I2C_SLAVE_ADDR_REG register + * Local slave address setting + */ +#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) +/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * When configured as an I2C Slave, this field is used to configure the slave address. + */ +#define I2C_SLAVE_ADDR 0x00007FFFU +#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) +#define I2C_SLAVE_ADDR_V 0x00007FFFU +#define I2C_SLAVE_ADDR_S 0 +/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * This field is used to enable the slave 10-bit addressing mode in master mode. + */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) +#define I2C_ADDR_10BIT_EN_V 0x00000001U +#define I2C_ADDR_10BIT_EN_S 31 + +/** I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ +#define I2C_RXFIFO_RADDR 0x0000001FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000001FU +#define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ +#define I2C_RXFIFO_WADDR 0x0000001FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000001FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ +#define I2C_TXFIFO_RADDR 0x0000001FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000001FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ +#define I2C_TXFIFO_WADDR 0x0000001FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000001FU +#define I2C_TXFIFO_WADDR_S 15 +/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; + * The received data in I2C slave mode. + */ +#define I2C_SLAVE_RW_POINT 0x000000FFU +#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) +#define I2C_SLAVE_RW_POINT_V 0x000000FFU +#define I2C_SLAVE_RW_POINT_S 22 + +/** I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define I2C_RXFIFO_WM_THRHD 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; + * When this bit is set to 1, the byte received after the I2C address byte represents + * the offset address in the I2C Slave RAM. + */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) +#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 + +/** I2C_DATA_REG register + * Rx FIFO read data. + */ +#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) +/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU +#define I2C_FIFO_RDATA_S 0 + +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 +/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) +#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 + +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 +/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) +#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 + +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 +/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) +#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 + +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 +/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) +#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ST_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 + +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU +#define I2C_SDA_HOLD_TIME_S 0 + +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_S 0 + +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains high in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_S 0 + +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU +#define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 + +/** I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) +/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_NUM 0x000000FFU +#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) +#define I2C_SCLK_DIV_NUM_V 0x000000FFU +#define I2C_SCLK_DIV_NUM_S 0 +/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_A 0x0000003FU +#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) +#define I2C_SCLK_DIV_A_V 0x0000003FU +#define I2C_SCLK_DIV_A_S 8 +/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_B 0x0000003FU +#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) +#define I2C_SCLK_DIV_B_V 0x0000003FU +#define I2C_SCLK_DIV_B_S 14 +/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) +#define I2C_SCLK_SEL_V 0x00000001U +#define I2C_SCLK_SEL_S 20 +/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) +#define I2C_SCLK_ACTIVE_V 0x00000001U +#define I2C_SCLK_ACTIVE_S 21 + +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU +#define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 + +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU +#define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 + +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU +#define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 + +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU +#define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 + +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU +#define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 + +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU +#define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 + +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU +#define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 + +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU +#define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 + +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 + +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U +#define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 + +/** I2C_SCL_STRETCH_CONF_REG register + * Set SCL stretch of I2C slave + */ +#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) +/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; + * Configure the period of I2C slave stretching SCL line. + */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) +#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_S 0 +/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; + * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL + * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch + * event happens. The stretch cause can be seen in reg_stretch_cause. + */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the I2C slave SCL stretch function. + */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; + * The enable bit for slave to control ACK level function. + */ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + */ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050; + * This is the the version register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU +#define I2C_DATE_S 0 + +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) +/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 + +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) +/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/i2c_struct.h b/components/soc/esp32h2/include/soc/i2c_struct.h new file mode 100644 index 0000000000..9617c458cf --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2c_struct.h @@ -0,0 +1,1197 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains high in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 0; + * 1: direct output, 0: open drain output. + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 0; + * 1: direct output, 0: open drain output. + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ + uint32_t rx_full_ack_level:1; + /** ms_mode : R/W; bitpos: [4]; default: 0; + * Set this bit to configure the module as an I2C Master. Clear this bit to configure + * the + * module as an I2C Slave. + */ + uint32_t ms_mode:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit, + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit, + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * synchronization bit + */ + uint32_t conf_upgate:1; + /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; + * This is the enable bit for slave to send data automatically + */ + uint32_t slv_tx_auto_start_en:1; + /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; + * This is the enable bit to check if the r/w bit of 10bit addressing consists with + * I2C protocol + */ + uint32_t addr_10bit_rw_check_en:1; + /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; + * This is the enable bit to support the 7bit general call function. + */ + uint32_t addr_broadcasting_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of slave_addr register + * Local slave address setting + */ +typedef union { + struct { + /** slave_addr : R/W; bitpos: [14:0]; default: 0; + * When configured as an I2C Slave, this field is used to configure the slave address. + */ + uint32_t slave_addr:15; + uint32_t reserved_15:16; + /** addr_10bit_en : R/W; bitpos: [31]; default: 0; + * This field is used to enable the slave 10-bit addressing mode in master mode. + */ + uint32_t addr_10bit_en:1; + }; + uint32_t val; +} i2c_slave_addr_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:5; + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:5; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; + * When this bit is set to 1, the byte received after the I2C address byte represents + * the offset address in the I2C Slave RAM. + */ + uint32_t fifo_addr_cfg_en:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ +typedef union { + struct { + /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; + * Configure the period of I2C slave stretching SCL line. + */ + uint32_t stretch_protect_num:10; + /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; + * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL + * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch + * event happens. The stretch cause can be seen in reg_stretch_cause. + */ + uint32_t slave_scl_stretch_en:1; + /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the I2C slave SCL stretch function. + */ + uint32_t slave_scl_stretch_clr:1; + /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; + * The enable bit for slave to control ACK level function. + */ + uint32_t slave_byte_ack_ctl_en:1; + /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + */ + uint32_t slave_byte_ack_lvl:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} i2c_scl_stretch_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ + uint32_t resp_rec:1; + /** slave_rw : RO; bitpos: [1]; default: 0; + * When in slave mode, 1: master reads from slave, 0: master writes to slave. + */ + uint32_t slave_rw:1; + uint32_t reserved_2:1; + /** arb_lost : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ + uint32_t bus_busy:1; + /** slave_addressed : RO; bitpos: [5]; default: 0; + * When configured as an I2C Slave, and the address sent by the master is + * equal to the address of the slave, then this bit will be of high level. + */ + uint32_t slave_addressed:1; + uint32_t reserved_6:2; + /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ + uint32_t rxfifo_cnt:6; + /** stretch_cause : RO; bitpos: [15:14]; default: 3; + * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the + * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty + * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + */ + uint32_t stretch_cause:2; + uint32_t reserved_16:2; + /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; + * This field stores the amount of received data in RAM. + */ + uint32_t txfifo_cnt:6; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: + * Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ + uint32_t rxfifo_raddr:5; + /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ + uint32_t rxfifo_waddr:5; + /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ + uint32_t txfifo_raddr:5; + /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ + uint32_t txfifo_waddr:5; + uint32_t reserved_20:2; + /** slave_rw_point : RO; bitpos: [29:22]; default: 0; + * The received data in I2C slave mode. + */ + uint32_t slave_rw_point:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_raw:1; + /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_raw:1; + /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_raw:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_clr:1; + /** general_call_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_clr:1; + /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_clr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_ena:1; + /** general_call_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_ena:1; + /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_ena:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_st:1; + /** general_call_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_st:1; + /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_st:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd0 register + * I2C command register 0 + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command0:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command0_done:1; + }; + uint32_t val; +} i2c_comd0_reg_t; + +/** Type of comd1 register + * I2C command register 1 + */ +typedef union { + struct { + /** command1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command1:14; + uint32_t reserved_14:17; + /** command1_done : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command1_done:1; + }; + uint32_t val; +} i2c_comd1_reg_t; + +/** Type of comd2 register + * I2C command register 2 + */ +typedef union { + struct { + /** command2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command2:14; + uint32_t reserved_14:17; + /** command2_done : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ + uint32_t command2_done:1; + }; + uint32_t val; +} i2c_comd2_reg_t; + +/** Type of comd3 register + * I2C command register 3 + */ +typedef union { + struct { + /** command3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command3:14; + uint32_t reserved_14:17; + /** command3_done : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command3_done:1; + }; + uint32_t val; +} i2c_comd3_reg_t; + +/** Type of comd4 register + * I2C command register 4 + */ +typedef union { + struct { + /** command4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command4:14; + uint32_t reserved_14:17; + /** command4_done : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command4_done:1; + }; + uint32_t val; +} i2c_comd4_reg_t; + +/** Type of comd5 register + * I2C command register 5 + */ +typedef union { + struct { + /** command5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command5:14; + uint32_t reserved_14:17; + /** command5_done : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command5_done:1; + }; + uint32_t val; +} i2c_comd5_reg_t; + +/** Type of comd6 register + * I2C command register 6 + */ +typedef union { + struct { + /** command6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command6:14; + uint32_t reserved_14:17; + /** command6_done : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command6_done:1; + }; + uint32_t val; +} i2c_comd6_reg_t; + +/** Type of comd7 register + * I2C command register 7 + */ +typedef union { + struct { + /** command7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command7:14; + uint32_t reserved_14:17; + /** command7_done : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command7_done:1; + }; + uint32_t val; +} i2c_comd7_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656050; + * This is the the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + volatile i2c_slave_addr_reg_t slave_addr; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + volatile i2c_clk_conf_reg_t clk_conf; + volatile i2c_comd0_reg_t comd0; + volatile i2c_comd1_reg_t comd1; + volatile i2c_comd2_reg_t comd2; + volatile i2c_comd3_reg_t comd3; + volatile i2c_comd4_reg_t comd4; + volatile i2c_comd5_reg_t comd5; + volatile i2c_comd6_reg_t comd6; + volatile i2c_comd7_reg_t comd7; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; + uint32_t reserved_088[28]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} i2c_dev_t; + +extern i2c_dev_t I2C0; +extern i2c_dev_t I2C1; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/i2s_reg.h b/components/soc/esp32h2/include/soc/i2s_reg.h new file mode 100644 index 0000000000..b79bdd298c --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2s_reg.h @@ -0,0 +1,1296 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2S_INT_RAW_REG register + * I2S interrupt raw register, valid in level. + */ +#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) +/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S) +#define I2S_RX_DONE_INT_RAW_V 0x00000001U +#define I2S_RX_DONE_INT_RAW_S 0 +/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S) +#define I2S_TX_DONE_INT_RAW_V 0x00000001U +#define I2S_TX_DONE_INT_RAW_S 1 +/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001U +#define I2S_RX_HUNG_INT_RAW_S 2 +/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001U +#define I2S_TX_HUNG_INT_RAW_S 3 + +/** I2S_INT_ST_REG register + * I2S interrupt status register. + */ +#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) +/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S) +#define I2S_RX_DONE_INT_ST_V 0x00000001U +#define I2S_RX_DONE_INT_ST_S 0 +/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S) +#define I2S_TX_DONE_INT_ST_V 0x00000001U +#define I2S_TX_DONE_INT_ST_S 1 +/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001U +#define I2S_RX_HUNG_INT_ST_S 2 +/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001U +#define I2S_TX_HUNG_INT_ST_S 3 + +/** I2S_INT_ENA_REG register + * I2S interrupt enable register. + */ +#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) +/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S) +#define I2S_RX_DONE_INT_ENA_V 0x00000001U +#define I2S_RX_DONE_INT_ENA_S 0 +/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S) +#define I2S_TX_DONE_INT_ENA_V 0x00000001U +#define I2S_TX_DONE_INT_ENA_S 1 +/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001U +#define I2S_RX_HUNG_INT_ENA_S 2 +/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001U +#define I2S_TX_HUNG_INT_ENA_S 3 + +/** I2S_INT_CLR_REG register + * I2S interrupt clear register. + */ +#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) +/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S) +#define I2S_RX_DONE_INT_CLR_V 0x00000001U +#define I2S_RX_DONE_INT_CLR_S 0 +/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S) +#define I2S_TX_DONE_INT_CLR_V 0x00000001U +#define I2S_TX_DONE_INT_CLR_S 1 +/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001U +#define I2S_RX_HUNG_INT_CLR_S 2 +/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001U +#define I2S_TX_HUNG_INT_CLR_S 3 + +/** I2S_RX_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20) +/** I2S_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001U +#define I2S_RX_RESET_S 0 +/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001U +#define I2S_RX_FIFO_RESET_S 1 +/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001U +#define I2S_RX_START_S 2 +/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001U +#define I2S_RX_SLAVE_MOD_S 3 +/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ +#define I2S_RX_STOP_MODE 0x00000003U +#define I2S_RX_STOP_MODE_M (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S) +#define I2S_RX_STOP_MODE_V 0x00000003U +#define I2S_RX_STOP_MODE_S 4 +/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ +#define I2S_RX_MONO (BIT(6)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001U +#define I2S_RX_MONO_S 6 +/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001U +#define I2S_RX_BIG_ENDIAN_S 7 +/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S) +#define I2S_RX_UPDATE_V 0x00000001U +#define I2S_RX_UPDATE_S 8 +/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S) +#define I2S_RX_MONO_FST_VLD_V 0x00000001U +#define I2S_RX_MONO_FST_VLD_S 9 +/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_RX_PCM_CONF 0x00000003U +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000003U +#define I2S_RX_PCM_CONF_S 10 +/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001U +#define I2S_RX_PCM_BYPASS_S 12 +/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ +#define I2S_RX_MSB_SHIFT (BIT(13)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001U +#define I2S_RX_MSB_SHIFT_S 13 +/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S) +#define I2S_RX_LEFT_ALIGN_V 0x00000001U +#define I2S_RX_LEFT_ALIGN_S 15 +/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S) +#define I2S_RX_24_FILL_EN_V 0x00000001U +#define I2S_RX_24_FILL_EN_S 16 +/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S) +#define I2S_RX_WS_IDLE_POL_V 0x00000001U +#define I2S_RX_WS_IDLE_POL_S 17 +/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S) +#define I2S_RX_BIT_ORDER_V 0x00000001U +#define I2S_RX_BIT_ORDER_S 18 +/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S) +#define I2S_RX_TDM_EN_V 0x00000001U +#define I2S_RX_TDM_EN_S 19 +/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S) +#define I2S_RX_PDM_EN_V 0x00000001U +#define I2S_RX_PDM_EN_S 20 +/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ +#define I2S_RX_BCK_DIV_NUM 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_S 21 + +/** I2S_TX_CONF_REG register + * I2S TX configure register + */ +#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24) +/** I2S_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001U +#define I2S_TX_RESET_S 0 +/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001U +#define I2S_TX_FIFO_RESET_S 1 +/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001U +#define I2S_TX_START_S 2 +/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001U +#define I2S_TX_SLAVE_MOD_S 3 +/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ +#define I2S_TX_STOP_EN (BIT(4)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001U +#define I2S_TX_STOP_EN_S 4 +/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ +#define I2S_TX_CHAN_EQUAL (BIT(5)) +#define I2S_TX_CHAN_EQUAL_M (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S) +#define I2S_TX_CHAN_EQUAL_V 0x00000001U +#define I2S_TX_CHAN_EQUAL_S 5 +/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ +#define I2S_TX_MONO (BIT(6)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001U +#define I2S_TX_MONO_S 6 +/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001U +#define I2S_TX_BIG_ENDIAN_S 7 +/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S) +#define I2S_TX_UPDATE_V 0x00000001U +#define I2S_TX_UPDATE_S 8 +/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S) +#define I2S_TX_MONO_FST_VLD_V 0x00000001U +#define I2S_TX_MONO_FST_VLD_S 9 +/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_TX_PCM_CONF 0x00000003U +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000003U +#define I2S_TX_PCM_CONF_S 10 +/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001U +#define I2S_TX_PCM_BYPASS_S 12 +/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ +#define I2S_TX_MSB_SHIFT (BIT(13)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001U +#define I2S_TX_MSB_SHIFT_S 13 +/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ +#define I2S_TX_BCK_NO_DLY (BIT(14)) +#define I2S_TX_BCK_NO_DLY_M (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S) +#define I2S_TX_BCK_NO_DLY_V 0x00000001U +#define I2S_TX_BCK_NO_DLY_S 14 +/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S) +#define I2S_TX_LEFT_ALIGN_V 0x00000001U +#define I2S_TX_LEFT_ALIGN_S 15 +/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S) +#define I2S_TX_24_FILL_EN_V 0x00000001U +#define I2S_TX_24_FILL_EN_S 16 +/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S) +#define I2S_TX_WS_IDLE_POL_V 0x00000001U +#define I2S_TX_WS_IDLE_POL_S 17 +/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S) +#define I2S_TX_BIT_ORDER_V 0x00000001U +#define I2S_TX_BIT_ORDER_S 18 +/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S) +#define I2S_TX_TDM_EN_V 0x00000001U +#define I2S_TX_TDM_EN_S 19 +/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S) +#define I2S_TX_PDM_EN_V 0x00000001U +#define I2S_TX_PDM_EN_S 20 +/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ +#define I2S_TX_BCK_DIV_NUM 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_S 21 +/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ +#define I2S_TX_CHAN_MOD 0x00000007U +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007U +#define I2S_TX_CHAN_MOD_S 27 +/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ +#define I2S_SIG_LOOPBACK (BIT(30)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001U +#define I2S_SIG_LOOPBACK_S 30 + +/** I2S_RX_CONF1_REG register + * I2S RX configure register 1 + */ +#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28) +/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_RX_TDM_WS_WIDTH 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_M (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S) +#define I2S_RX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_S 0 +/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_RX_BITS_MOD 0x0000001FU +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000001FU +#define I2S_RX_BITS_MOD_S 14 +/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ +#define I2S_RX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_M (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_S 19 +/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ +#define I2S_RX_TDM_CHAN_BITS 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_M (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S) +#define I2S_RX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_CONF1_REG register + * I2S TX configure register 1 + */ +#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c) +/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_TX_TDM_WS_WIDTH 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_M (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S) +#define I2S_TX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_S 0 +/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_TX_BITS_MOD 0x0000001FU +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000001FU +#define I2S_TX_BITS_MOD_S 14 +/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ +#define I2S_TX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_M (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_S 19 +/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ +#define I2S_TX_TDM_CHAN_BITS 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_M (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S) +#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_S 27 + +/** I2S_RX_CLKM_CONF_REG register + * I2S RX clock configure register + */ +#define I2S_RX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x30) +/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2; + * Integral I2S clock divider value + */ +#define I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define I2S_RX_CLKM_DIV_NUM_M (I2S_RX_CLKM_DIV_NUM_V << I2S_RX_CLKM_DIV_NUM_S) +#define I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define I2S_RX_CLKM_DIV_NUM_S 0 +/** I2S_RX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0; + * I2S Rx module clock enable signal. + */ +#define I2S_RX_CLK_ACTIVE (BIT(26)) +#define I2S_RX_CLK_ACTIVE_M (I2S_RX_CLK_ACTIVE_V << I2S_RX_CLK_ACTIVE_S) +#define I2S_RX_CLK_ACTIVE_V 0x00000001U +#define I2S_RX_CLK_ACTIVE_S 26 +/** I2S_RX_CLK_SEL : R/W; bitpos: [28:27]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define I2S_RX_CLK_SEL 0x00000003U +#define I2S_RX_CLK_SEL_M (I2S_RX_CLK_SEL_V << I2S_RX_CLK_SEL_S) +#define I2S_RX_CLK_SEL_V 0x00000003U +#define I2S_RX_CLK_SEL_S 27 +/** I2S_MCLK_SEL : R/W; bitpos: [29]; default: 0; + * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as + * I2S_MCLK_OUT. + */ +#define I2S_MCLK_SEL (BIT(29)) +#define I2S_MCLK_SEL_M (I2S_MCLK_SEL_V << I2S_MCLK_SEL_S) +#define I2S_MCLK_SEL_V 0x00000001U +#define I2S_MCLK_SEL_S 29 + +/** I2S_TX_CLKM_CONF_REG register + * I2S TX clock configure register + */ +#define I2S_TX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x34) +/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define I2S_TX_CLKM_DIV_NUM_M (I2S_TX_CLKM_DIV_NUM_V << I2S_TX_CLKM_DIV_NUM_S) +#define I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define I2S_TX_CLKM_DIV_NUM_S 0 +/** I2S_TX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0; + * I2S Tx module clock enable signal. + */ +#define I2S_TX_CLK_ACTIVE (BIT(26)) +#define I2S_TX_CLK_ACTIVE_M (I2S_TX_CLK_ACTIVE_V << I2S_TX_CLK_ACTIVE_S) +#define I2S_TX_CLK_ACTIVE_V 0x00000001U +#define I2S_TX_CLK_ACTIVE_S 26 +/** I2S_TX_CLK_SEL : R/W; bitpos: [28:27]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define I2S_TX_CLK_SEL 0x00000003U +#define I2S_TX_CLK_SEL_M (I2S_TX_CLK_SEL_V << I2S_TX_CLK_SEL_S) +#define I2S_TX_CLK_SEL_V 0x00000003U +#define I2S_TX_CLK_SEL_S 27 +/** I2S_CLK_EN : R/W; bitpos: [29]; default: 0; + * Set this bit to enable clk gate + */ +#define I2S_CLK_EN (BIT(29)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001U +#define I2S_CLK_EN_S 29 + +/** I2S_RX_CLKM_DIV_CONF_REG register + * I2S RX module clock divider configure register + */ +#define I2S_RX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x38) +/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define I2S_RX_CLKM_DIV_Z 0x000001FFU +#define I2S_RX_CLKM_DIV_Z_M (I2S_RX_CLKM_DIV_Z_V << I2S_RX_CLKM_DIV_Z_S) +#define I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define I2S_RX_CLKM_DIV_Z_S 0 +/** I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define I2S_RX_CLKM_DIV_Y 0x000001FFU +#define I2S_RX_CLKM_DIV_Y_M (I2S_RX_CLKM_DIV_Y_V << I2S_RX_CLKM_DIV_Y_S) +#define I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define I2S_RX_CLKM_DIV_Y_S 9 +/** I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define I2S_RX_CLKM_DIV_X 0x000001FFU +#define I2S_RX_CLKM_DIV_X_M (I2S_RX_CLKM_DIV_X_V << I2S_RX_CLKM_DIV_X_S) +#define I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define I2S_RX_CLKM_DIV_X_S 18 +/** I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_M (I2S_RX_CLKM_DIV_YN1_V << I2S_RX_CLKM_DIV_YN1_S) +#define I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define I2S_RX_CLKM_DIV_YN1_S 27 + +/** I2S_TX_CLKM_DIV_CONF_REG register + * I2S TX module clock divider configure register + */ +#define I2S_TX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x3c) +/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define I2S_TX_CLKM_DIV_Z 0x000001FFU +#define I2S_TX_CLKM_DIV_Z_M (I2S_TX_CLKM_DIV_Z_V << I2S_TX_CLKM_DIV_Z_S) +#define I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define I2S_TX_CLKM_DIV_Z_S 0 +/** I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define I2S_TX_CLKM_DIV_Y 0x000001FFU +#define I2S_TX_CLKM_DIV_Y_M (I2S_TX_CLKM_DIV_Y_V << I2S_TX_CLKM_DIV_Y_S) +#define I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define I2S_TX_CLKM_DIV_Y_S 9 +/** I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define I2S_TX_CLKM_DIV_X 0x000001FFU +#define I2S_TX_CLKM_DIV_X_M (I2S_TX_CLKM_DIV_X_V << I2S_TX_CLKM_DIV_X_S) +#define I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define I2S_TX_CLKM_DIV_X_S 18 +/** I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_M (I2S_TX_CLKM_DIV_YN1_V << I2S_TX_CLKM_DIV_YN1_S) +#define I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define I2S_TX_CLKM_DIV_YN1_S 27 + +/** I2S_TX_PCM2PDM_CONF_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40) +/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0; + * I2S TX PDM bypass hp filter or not. The option has been removed. + */ +#define I2S_TX_PDM_HP_BYPASS (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_M (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S) +#define I2S_TX_PDM_HP_BYPASS_V 0x00000001U +#define I2S_TX_PDM_HP_BYPASS_S 0 +/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_M (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S) +#define I2S_TX_PDM_SINC_OSR2_V 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_S 1 +/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ +#define I2S_TX_PDM_PRESCALE 0x000000FFU +#define I2S_TX_PDM_PRESCALE_M (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S) +#define I2S_TX_PDM_PRESCALE_V 0x000000FFU +#define I2S_TX_PDM_PRESCALE_S 5 +/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_M (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_M (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_M (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S) +#define I2S_PCM2PDM_CONV_EN_V 0x00000001U +#define I2S_PCM2PDM_CONV_EN_S 25 + +/** I2S_TX_PCM2PDM_CONF1_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44) +/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ +#define I2S_TX_PDM_FP 0x000003FFU +#define I2S_TX_PDM_FP_M (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S) +#define I2S_TX_PDM_FP_V 0x000003FFU +#define I2S_TX_PDM_FP_S 0 +/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ +#define I2S_TX_PDM_FS 0x000003FFU +#define I2S_TX_PDM_FS_M (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S) +#define I2S_TX_PDM_FS_V 0x000003FFU +#define I2S_TX_PDM_FS_S 10 +/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_M (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S) +#define I2S_TX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_M (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S) +#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_S 23 + +/** I2S_RX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50) +/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S) +#define I2S_RX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN8_EN_S 8 +/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S) +#define I2S_RX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN9_EN_S 9 +/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S) +#define I2S_RX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN10_EN_S 10 +/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S) +#define I2S_RX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN11_EN_S 11 +/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S) +#define I2S_RX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN12_EN_S 12 +/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S) +#define I2S_RX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN13_EN_S 13 +/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S) +#define I2S_RX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN14_EN_S 14 +/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S) +#define I2S_RX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN15_EN_S 15 +/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_M (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 + +/** I2S_TX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54) +/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S) +#define I2S_TX_TDM_CHAN0_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN0_EN_S 0 +/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S) +#define I2S_TX_TDM_CHAN1_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN1_EN_S 1 +/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S) +#define I2S_TX_TDM_CHAN2_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN2_EN_S 2 +/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S) +#define I2S_TX_TDM_CHAN3_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN3_EN_S 3 +/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S) +#define I2S_TX_TDM_CHAN4_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN4_EN_S 4 +/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S) +#define I2S_TX_TDM_CHAN5_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN5_EN_S 5 +/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S) +#define I2S_TX_TDM_CHAN6_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN6_EN_S 6 +/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S) +#define I2S_TX_TDM_CHAN7_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN7_EN_S 7 +/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S) +#define I2S_TX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN8_EN_S 8 +/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S) +#define I2S_TX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN9_EN_S 9 +/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S) +#define I2S_TX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN10_EN_S 10 +/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S) +#define I2S_TX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN11_EN_S 11 +/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S) +#define I2S_TX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN12_EN_S 12 +/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S) +#define I2S_TX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN13_EN_S 13 +/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S) +#define I2S_TX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN14_EN_S 14 +/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S) +#define I2S_TX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN15_EN_S 15 +/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_M (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x00000001U +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 + +/** I2S_RX_TIMING_REG register + * I2S RX timing control register + */ +#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58) +/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD_IN_DM 0x00000003U +#define I2S_RX_SD_IN_DM_M (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S) +#define I2S_RX_SD_IN_DM_V 0x00000003U +#define I2S_RX_SD_IN_DM_S 0 +/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_OUT_DM 0x00000003U +#define I2S_RX_WS_OUT_DM_M (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S) +#define I2S_RX_WS_OUT_DM_V 0x00000003U +#define I2S_RX_WS_OUT_DM_S 16 +/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_OUT_DM 0x00000003U +#define I2S_RX_BCK_OUT_DM_M (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S) +#define I2S_RX_BCK_OUT_DM_V 0x00000003U +#define I2S_RX_BCK_OUT_DM_S 20 +/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_IN_DM 0x00000003U +#define I2S_RX_WS_IN_DM_M (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S) +#define I2S_RX_WS_IN_DM_V 0x00000003U +#define I2S_RX_WS_IN_DM_S 24 +/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_IN_DM 0x00000003U +#define I2S_RX_BCK_IN_DM_M (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S) +#define I2S_RX_BCK_IN_DM_V 0x00000003U +#define I2S_RX_BCK_IN_DM_S 28 + +/** I2S_TX_TIMING_REG register + * I2S TX timing control register + */ +#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c) +/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD_OUT_DM 0x00000003U +#define I2S_TX_SD_OUT_DM_M (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S) +#define I2S_TX_SD_OUT_DM_V 0x00000003U +#define I2S_TX_SD_OUT_DM_S 0 +/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD1_OUT_DM 0x00000003U +#define I2S_TX_SD1_OUT_DM_M (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S) +#define I2S_TX_SD1_OUT_DM_V 0x00000003U +#define I2S_TX_SD1_OUT_DM_S 4 +/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_OUT_DM 0x00000003U +#define I2S_TX_WS_OUT_DM_M (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S) +#define I2S_TX_WS_OUT_DM_V 0x00000003U +#define I2S_TX_WS_OUT_DM_S 16 +/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_OUT_DM 0x00000003U +#define I2S_TX_BCK_OUT_DM_M (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S) +#define I2S_TX_BCK_OUT_DM_V 0x00000003U +#define I2S_TX_BCK_OUT_DM_S 20 +/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_IN_DM 0x00000003U +#define I2S_TX_WS_IN_DM_M (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S) +#define I2S_TX_WS_IN_DM_V 0x00000003U +#define I2S_TX_WS_IN_DM_S 24 +/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_IN_DM 0x00000003U +#define I2S_TX_BCK_IN_DM_M (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S) +#define I2S_TX_BCK_IN_DM_V 0x00000003U +#define I2S_TX_BCK_IN_DM_S 28 + +/** I2S_LC_HUNG_CONF_REG register + * I2S HUNG configure register. + */ +#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60) +/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_S 0 +/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/** I2S_RXEOF_NUM_REG register + * I2S RX data number control register. + */ +#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64) +/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ +#define I2S_RX_EOF_NUM 0x00000FFFU +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0x00000FFFU +#define I2S_RX_EOF_NUM_S 0 + +/** I2S_CONF_SIGLE_DATA_REG register + * I2S signal data register + */ +#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68) +/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ +#define I2S_SINGLE_DATA 0xFFFFFFFFU +#define I2S_SINGLE_DATA_M (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S) +#define I2S_SINGLE_DATA_V 0xFFFFFFFFU +#define I2S_SINGLE_DATA_S 0 + +/** I2S_STATE_REG register + * I2S TX status register + */ +#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c) +/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001U +#define I2S_TX_IDLE_S 0 + +/** I2S_ETM_CONF_REG register + * I2S ETM configure register + */ +#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70) +/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_TX_SEND_WORD_NUM 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_M (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S) +#define I2S_ETM_TX_SEND_WORD_NUM_V 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_S 0 +/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_RX_RECEIVE_WORD_NUM 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_M (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S) +#define I2S_ETM_RX_RECEIVE_WORD_NUM_V 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_S 10 + +/** I2S_DATE_REG register + * Version control register + */ +#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80) +/** I2S_DATE : R/W; bitpos: [27:0]; default: 35684944; + * I2S version control register + */ +#define I2S_DATE 0x0FFFFFFFU +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0x0FFFFFFFU +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/include/soc/i2s_struct.h new file mode 100644 index 0000000000..6d257e9f5c --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2s_struct.h @@ -0,0 +1,1022 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt registers */ +/** Type of int_raw register + * I2S interrupt raw register, valid in level. + */ +typedef union { + struct { + /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_raw:1; + /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_raw:1; + /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_raw_reg_t; + +/** Type of int_st register + * I2S interrupt status register. + */ +typedef union { + struct { + /** rx_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_st_reg_t; + +/** Type of int_ena register + * I2S interrupt enable register. + */ +typedef union { + struct { + /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_ena_reg_t; + +/** Type of int_clr register + * I2S interrupt clear register. + */ +typedef union { + struct { + /** rx_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of rx_conf register + * I2S RX configure register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ + uint32_t rx_reset:1; + /** rx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ + uint32_t rx_fifo_reset:1; + /** rx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ + uint32_t rx_start:1; + /** rx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ + uint32_t rx_slave_mod:1; + /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ + uint32_t rx_stop_mode:2; + /** rx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ + uint32_t rx_mono:1; + /** rx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ + uint32_t rx_big_endian:1; + /** rx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t rx_update:1; + /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ + uint32_t rx_mono_fst_vld:1; + /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t rx_pcm_conf:2; + /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + uint32_t rx_pcm_bypass:1; + /** rx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ + uint32_t rx_msb_shift:1; + uint32_t reserved_14:1; + /** rx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ + uint32_t rx_left_align:1; + /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ + uint32_t rx_24_fill_en:1; + /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ + uint32_t rx_ws_idle_pol:1; + /** rx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ + uint32_t rx_bit_order:1; + /** rx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ + uint32_t rx_tdm_en:1; + /** rx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ + uint32_t rx_pdm_en:1; + /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + uint32_t rx_bck_div_num:6; + uint32_t reserved_27:5; + }; + uint32_t val; +} i2s_rx_conf_reg_t; + +/** Type of rx_conf1 register + * I2S RX configure register 1 + */ +typedef union { + struct { + /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t rx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t rx_bits_mod:5; + /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ + uint32_t rx_half_sample_bits:8; + /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ + uint32_t rx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_rx_conf1_reg_t; + +/** Type of rx_clkm_conf register + * I2S RX clock configure register + */ +typedef union { + struct { + /** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2; + * Integral I2S clock divider value + */ + uint32_t rx_clkm_div_num:8; + uint32_t reserved_8:18; + /** rx_clk_active : R/W; bitpos: [26]; default: 0; + * I2S Rx module clock enable signal. + */ + uint32_t rx_clk_active:1; + /** rx_clk_sel : R/W; bitpos: [28:27]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ + uint32_t rx_clk_sel:2; + /** mclk_sel : R/W; bitpos: [29]; default: 0; + * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as + * I2S_MCLK_OUT. + */ + uint32_t mclk_sel:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_clkm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0; + * I2S TX PDM bypass hp filter or not. The option has been removed. + */ + uint32_t tx_pdm_hp_bypass:1; + /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ + uint32_t tx_pdm_sinc_osr2:4; + /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ + uint32_t tx_pdm_prescale:8; + /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_hp_in_shift:2; + /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_lp_in_shift:2; + /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sinc_in_shift:2; + /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sigmadelta_in_shift:2; + /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ + uint32_t tx_pdm_sigmadelta_dither2:1; + /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ + uint32_t tx_pdm_sigmadelta_dither:1; + /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ + uint32_t tx_pdm_dac_2out_en:1; + /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ + uint32_t tx_pdm_dac_mode_en:1; + /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ + uint32_t pcm2pdm_conv_en:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf1 register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ + uint32_t tx_pdm_fp:10; + /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ + uint32_t tx_pdm_fs:10; + /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t tx_iir_hp_mult12_5:3; + /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t tx_iir_hp_mult12_0:3; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf1_reg_t; + +/** Type of rx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan0_en:1; + /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan1_en:1; + /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan2_en:1; + /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan3_en:1; + /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan4_en:1; + /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan5_en:1; + /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan6_en:1; + /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan7_en:1; + /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan8_en:1; + /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan9_en:1; + /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan10_en:1; + /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan11_en:1; + /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan12_en:1; + /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan13_en:1; + /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan14_en:1; + /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan15_en:1; + /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t rx_tdm_tot_chan_num:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_rx_tdm_ctrl_reg_t; + +/** Type of rxeof_num register + * I2S RX data number control register. + */ +typedef union { + struct { + /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ + uint32_t rx_eof_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_rxeof_num_reg_t; + + +/** Group: TX Control and configuration registers */ +/** Type of tx_conf register + * I2S TX configure register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + uint32_t tx_reset:1; + /** tx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ + uint32_t tx_fifo_reset:1; + /** tx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ + uint32_t tx_start:1; + /** tx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ + uint32_t tx_slave_mod:1; + /** tx_stop_en : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ + uint32_t tx_stop_en:1; + /** tx_chan_equal : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ + uint32_t tx_chan_equal:1; + /** tx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + uint32_t tx_mono:1; + /** tx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ + uint32_t tx_big_endian:1; + /** tx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t tx_update:1; + /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ + uint32_t tx_mono_fst_vld:1; + /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t tx_pcm_conf:2; + /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + uint32_t tx_pcm_bypass:1; + /** tx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ + uint32_t tx_msb_shift:1; + /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ + uint32_t tx_bck_no_dly:1; + /** tx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ + uint32_t tx_left_align:1; + /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ + uint32_t tx_24_fill_en:1; + /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ + uint32_t tx_ws_idle_pol:1; + /** tx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ + uint32_t tx_bit_order:1; + /** tx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ + uint32_t tx_tdm_en:1; + /** tx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ + uint32_t tx_pdm_en:1; + /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + uint32_t tx_bck_div_num:6; + /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + uint32_t tx_chan_mod:3; + /** sig_loopback : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ + uint32_t sig_loopback:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2s_tx_conf_reg_t; + +/** Type of tx_conf1 register + * I2S TX configure register 1 + */ +typedef union { + struct { + /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t tx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t tx_bits_mod:5; + /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ + uint32_t tx_half_sample_bits:8; + /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ + uint32_t tx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_tx_conf1_reg_t; + +/** Type of tx_clkm_conf register + * I2S TX clock configure register + */ +typedef union { + struct { + /** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t tx_clkm_div_num:8; + uint32_t reserved_8:18; + /** tx_clk_active : R/W; bitpos: [26]; default: 0; + * I2S Tx module clock enable signal. + */ + uint32_t tx_clk_active:1; + /** tx_clk_sel : R/W; bitpos: [28:27]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ + uint32_t tx_clk_sel:2; + /** clk_en : R/W; bitpos: [29]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_clkm_conf_reg_t; + +/** Type of tx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan0_en:1; + /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan1_en:1; + /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan2_en:1; + /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan3_en:1; + /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan4_en:1; + /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan5_en:1; + /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan6_en:1; + /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan7_en:1; + /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan8_en:1; + /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan9_en:1; + /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan10_en:1; + /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan11_en:1; + /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan12_en:1; + /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan13_en:1; + /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan14_en:1; + /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan15_en:1; + /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t tx_tdm_tot_chan_num:4; + /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ + uint32_t tx_tdm_skip_msk_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} i2s_tx_tdm_ctrl_reg_t; + + +/** Group: RX clock and timing registers */ +/** Type of rx_clkm_div_conf register + * I2S RX module clock divider configure register + */ +typedef union { + struct { + /** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t rx_clkm_div_z:9; + /** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t rx_clkm_div_y:9; + /** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t rx_clkm_div_x:9; + /** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_rx_clkm_div_conf_reg_t; + +/** Type of rx_timing register + * I2S RX timing control register + */ +typedef union { + struct { + /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd_in_dm:2; + uint32_t reserved_2:14; + /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_out_dm:2; + uint32_t reserved_18:2; + /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_out_dm:2; + uint32_t reserved_22:2; + /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_in_dm:2; + uint32_t reserved_26:2; + /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_timing_reg_t; + + +/** Group: TX clock and timing registers */ +/** Type of tx_clkm_div_conf register + * I2S TX module clock divider configure register + */ +typedef union { + struct { + /** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t tx_clkm_div_z:9; + /** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t tx_clkm_div_y:9; + /** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t tx_clkm_div_x:9; + /** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_tx_clkm_div_conf_reg_t; + +/** Type of tx_timing register + * I2S TX timing control register + */ +typedef union { + struct { + /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd_out_dm:2; + uint32_t reserved_2:2; + /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd1_out_dm:2; + uint32_t reserved_6:10; + /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_out_dm:2; + uint32_t reserved_18:2; + /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_out_dm:2; + uint32_t reserved_22:2; + /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_in_dm:2; + uint32_t reserved_26:2; + /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_timing_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of lc_hung_conf register + * I2S HUNG configure register. + */ +typedef union { + struct { + /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ + uint32_t lc_fifo_timeout:8; + /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + uint32_t lc_fifo_timeout_shift:3; + /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + uint32_t lc_fifo_timeout_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_lc_hung_conf_reg_t; + +/** Type of conf_sigle_data register + * I2S signal data register + */ +typedef union { + struct { + /** single_data : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ + uint32_t single_data:32; + }; + uint32_t val; +} i2s_conf_sigle_data_reg_t; + + +/** Group: TX status registers */ +/** Type of state register + * I2S TX status register + */ +typedef union { + struct { + /** tx_idle : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ + uint32_t tx_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_state_reg_t; + + +/** Group: ETM registers */ +/** Type of etm_conf register + * I2S ETM configure register + */ +typedef union { + struct { + /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_tx_send_word_num:10; + /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_rx_receive_word_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_etm_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684944; + * I2S version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile i2s_int_raw_reg_t int_raw; + volatile i2s_int_st_reg_t int_st; + volatile i2s_int_ena_reg_t int_ena; + volatile i2s_int_clr_reg_t int_clr; + uint32_t reserved_01c; + volatile i2s_rx_conf_reg_t rx_conf; + volatile i2s_tx_conf_reg_t tx_conf; + volatile i2s_rx_conf1_reg_t rx_conf1; + volatile i2s_tx_conf1_reg_t tx_conf1; + volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf; + volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf; + volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf; + volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf; + volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; + volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; + uint32_t reserved_048[2]; + volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; + volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; + volatile i2s_rx_timing_reg_t rx_timing; + volatile i2s_tx_timing_reg_t tx_timing; + volatile i2s_lc_hung_conf_reg_t lc_hung_conf; + volatile i2s_rxeof_num_reg_t rxeof_num; + volatile i2s_conf_sigle_data_reg_t conf_sigle_data; + volatile i2s_state_reg_t state; + volatile i2s_etm_conf_reg_t etm_conf; + uint32_t reserved_074[3]; + volatile i2s_date_reg_t date; +} i2s_dev_t; + +extern i2s_dev_t I2S0; + +#ifndef __cplusplus +_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h b/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h new file mode 100644 index 0000000000..26f76cfb8e --- /dev/null +++ b/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h @@ -0,0 +1,856 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +// #include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTMTX_CORE0_PMU_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0) +/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_PMU_INTR mapping register + */ +#define INTMTX_CORE0_PMU_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PMU_INTR_MAP_M (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S) +#define INTMTX_CORE0_PMU_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PMU_INTR_MAP_S 0 + +/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4) +/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_EFUSE_INTR mapping register + */ +#define INTMTX_CORE0_EFUSE_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_EFUSE_INTR_MAP_M (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S) +#define INTMTX_CORE0_EFUSE_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_EFUSE_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8) +/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_RTC_TIMER_INTR mapping register + */ +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S) +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc) +/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_BLE_TIMER_INTR mapping register + */ +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S) +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10) +/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_WDT_INTR mapping register + */ +#define INTMTX_CORE0_LP_WDT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_WDT_INTR_MAP_M (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S) +#define INTMTX_CORE0_LP_WDT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_WDT_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14) +/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_PERI_TIMEOUT_INTR mapping register + */ +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18) +/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_APM_M0_INTR mapping register + */ +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S) +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_1 mapping register + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_2 mapping register + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_3 mapping register + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c) +/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_ASSIST_DEBUG_INTR mapping register + */ +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S) +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +/** INTMTX_CORE0_TRACE_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30) +/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_TRACE_INTR mapping register + */ +#define INTMTX_CORE0_TRACE_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TRACE_INTR_MAP_M (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S) +#define INTMTX_CORE0_TRACE_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TRACE_INTR_MAP_S 0 + +/** INTMTX_CORE0_CACHE_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34) +/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CACHE_INTR mapping register + */ +#define INTMTX_CORE0_CACHE_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CACHE_INTR_MAP_M (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S) +#define INTMTX_CORE0_CACHE_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CACHE_INTR_MAP_S 0 + +/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38) +/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_PERI_TIMEOUT_INTR mapping register + */ +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c) +/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_BT_MAC_INTR mapping register + */ +#define INTMTX_CORE0_BT_MAC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BT_MAC_INTR_MAP_M (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S) +#define INTMTX_CORE0_BT_MAC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BT_MAC_INTR_MAP_S 0 + +/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40) +/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_BT_BB_INTR mapping register + */ +#define INTMTX_CORE0_BT_BB_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BT_BB_INTR_MAP_M (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S) +#define INTMTX_CORE0_BT_BB_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BT_BB_INTR_MAP_S 0 + +/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44) +/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_BT_BB_NMI mapping register + */ +#define INTMTX_CORE0_BT_BB_NMI_MAP 0x0000001FU +#define INTMTX_CORE0_BT_BB_NMI_MAP_M (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S) +#define INTMTX_CORE0_BT_BB_NMI_MAP_V 0x0000001FU +#define INTMTX_CORE0_BT_BB_NMI_MAP_S 0 + +/** INTMTX_CORE0_COEX_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48) +/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_COEX_INTR mapping register + */ +#define INTMTX_CORE0_COEX_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_COEX_INTR_MAP_M (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S) +#define INTMTX_CORE0_COEX_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_COEX_INTR_MAP_S 0 + +/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c) +/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_BLE_TIMER_INTR mapping register + */ +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S) +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S 0 + +/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50) +/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_BLE_SEC_INTR mapping register + */ +#define INTMTX_CORE0_BLE_SEC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S) +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S 0 + +/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54) +/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_ZB_MAC_INTR mapping register + */ +#define INTMTX_CORE0_ZB_MAC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S) +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S 0 + +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * register description + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_GPIO_INTERRUPT_PRO mapping register + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * register description + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c) +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_GPIO_INTERRUPT_PRO_NMI mapping register + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +/** INTMTX_CORE0_PAU_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60) +/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_PAU_INTR mapping register + */ +#define INTMTX_CORE0_PAU_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PAU_INTR_MAP_M (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S) +#define INTMTX_CORE0_PAU_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PAU_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64) +/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_PERI_TIMEOUT_INTR mapping register + */ +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68) +/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M0_INTR mapping register + */ +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c) +/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M1_INTR mapping register + */ +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70) +/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M2_INTR mapping register + */ +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74) +/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M3_INTR mapping register + */ +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S 0 + +/** INTMTX_CORE0_MSPI_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78) +/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_MSPI_INTR mapping register + */ +#define INTMTX_CORE0_MSPI_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_MSPI_INTR_MAP_M (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S) +#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_MSPI_INTR_MAP_S 0 + +/** INTMTX_CORE0_I2S1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c) +/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_I2S1_INTR mapping register + */ +#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S) +#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_I2S1_INTR_MAP_S 0 + +/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80) +/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_UHCI0_INTR mapping register + */ +#define INTMTX_CORE0_UHCI0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_UHCI0_INTR_MAP_M (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S) +#define INTMTX_CORE0_UHCI0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_UHCI0_INTR_MAP_S 0 + +/** INTMTX_CORE0_UART0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84) +/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_UART0_INTR mapping register + */ +#define INTMTX_CORE0_UART0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_UART0_INTR_MAP_M (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S) +#define INTMTX_CORE0_UART0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_UART0_INTR_MAP_S 0 + +/** INTMTX_CORE0_UART1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88) +/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_UART1_INTR mapping register + */ +#define INTMTX_CORE0_UART1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_UART1_INTR_MAP_M (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S) +#define INTMTX_CORE0_UART1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_UART1_INTR_MAP_S 0 + +/** INTMTX_CORE0_LEDC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c) +/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_LEDC_INTR mapping register + */ +#define INTMTX_CORE0_LEDC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LEDC_INTR_MAP_M (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S) +#define INTMTX_CORE0_LEDC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LEDC_INTR_MAP_S 0 + +/** INTMTX_CORE0_CAN0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90) +/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_CAN0_INTR mapping register + */ +#define INTMTX_CORE0_CAN0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CAN0_INTR_MAP_M (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S) +#define INTMTX_CORE0_CAN0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CAN0_INTR_MAP_S 0 + +/** INTMTX_CORE0_USB_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) +/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_USB_INTR mapping register + */ +#define INTMTX_CORE0_USB_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_USB_INTR_MAP_M (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S) +#define INTMTX_CORE0_USB_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_USB_INTR_MAP_S 0 + +/** INTMTX_CORE0_RMT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98) +/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_RMT_INTR mapping register + */ +#define INTMTX_CORE0_RMT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_RMT_INTR_MAP_M (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S) +#define INTMTX_CORE0_RMT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_RMT_INTR_MAP_S 0 + +/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c) +/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_I2C_EXT0_INTR mapping register + */ +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S 0 + +/** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0) +/** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_I2C_EXT1_INTR mapping register + */ +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_M (INTMTX_CORE0_I2C_EXT1_INTR_MAP_V << INTMTX_CORE0_I2C_EXT1_INTR_MAP_S) +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4) +/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG0_T0_INTR mapping register + */ +#define INTMTX_CORE0_TG0_T0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG0_T0_INTR_MAP_M (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S) +#define INTMTX_CORE0_TG0_T0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG0_T0_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8) +/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG0_WDT_INTR mapping register + */ +#define INTMTX_CORE0_TG0_WDT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S) +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac) +/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG1_T0_INTR mapping register + */ +#define INTMTX_CORE0_TG1_T0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG1_T0_INTR_MAP_M (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S) +#define INTMTX_CORE0_TG1_T0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG1_T0_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0) +/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG1_WDT_INTR mapping register + */ +#define INTMTX_CORE0_TG1_WDT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S) +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S 0 + +/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4) +/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_SYSTIMER_TARGET0_INTR mapping register + */ +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 + +/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8) +/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_SYSTIMER_TARGET1_INTR mapping register + */ +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 + +/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc) +/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_SYSTIMER_TARGET2_INTR mapping register + */ +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 + +/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0) +/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_APB_ADC_INTR mapping register + */ +#define INTMTX_CORE0_APB_ADC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_APB_ADC_INTR_MAP_M (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S) +#define INTMTX_CORE0_APB_ADC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_APB_ADC_INTR_MAP_S 0 + +/** INTMTX_CORE0_PWM_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4) +/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_PWM_INTR mapping register + */ +#define INTMTX_CORE0_PWM_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PWM_INTR_MAP_M (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S) +#define INTMTX_CORE0_PWM_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PWM_INTR_MAP_S 0 + +/** INTMTX_CORE0_PCNT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8) +/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_PCNT_INTR mapping register + */ +#define INTMTX_CORE0_PCNT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PCNT_INTR_MAP_M (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S) +#define INTMTX_CORE0_PCNT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PCNT_INTR_MAP_S 0 + +/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc) +/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_PARL_IO_TX_INTR mapping register + */ +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_M (INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S) +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S 0 + +/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0) +/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_PARL_IO_RX_INTR mapping register + */ +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_M (INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S) +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4) +/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_IN_CH0_INTR mapping register + */ +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S) +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8) +/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_IN_CH1_INTR mapping register + */ +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S) +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc) +/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_IN_CH2_INTR mapping register + */ +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S) +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0) +/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_OUT_CH0_INTR mapping register + */ +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S) +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4) +/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_OUT_CH1_INTR mapping register + */ +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S) +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8) +/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_OUT_CH2_INTR mapping register + */ +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S) +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 + +/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec) +/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_GPSPI2_INTR mapping register + */ +#define INTMTX_CORE0_GPSPI2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_GPSPI2_INTR_MAP_M (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S) +#define INTMTX_CORE0_GPSPI2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_GPSPI2_INTR_MAP_S 0 + +/** INTMTX_CORE0_AES_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0) +/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_AES_INTR mapping register + */ +#define INTMTX_CORE0_AES_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_AES_INTR_MAP_M (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S) +#define INTMTX_CORE0_AES_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_AES_INTR_MAP_S 0 + +/** INTMTX_CORE0_SHA_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4) +/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_SHA_INTR mapping register + */ +#define INTMTX_CORE0_SHA_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SHA_INTR_MAP_M (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S) +#define INTMTX_CORE0_SHA_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SHA_INTR_MAP_S 0 + +/** INTMTX_CORE0_RSA_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8) +/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_RSA_INTR mapping register + */ +#define INTMTX_CORE0_RSA_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_RSA_INTR_MAP_M (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S) +#define INTMTX_CORE0_RSA_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_RSA_INTR_MAP_S 0 + +/** INTMTX_CORE0_ECC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc) +/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_ECC_INTR mapping register + */ +#define INTMTX_CORE0_ECC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ECC_INTR_MAP_M (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S) +#define INTMTX_CORE0_ECC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ECC_INTR_MAP_S 0 + +/** INTMTX_CORE0_ECDSA_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100) +/** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * CORE0_ECDSA_INTR mapping register + */ +#define INTMTX_CORE0_ECDSA_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ECDSA_INTR_MAP_M (INTMTX_CORE0_ECDSA_INTR_MAP_V << INTMTX_CORE0_ECDSA_INTR_MAP_S) +#define INTMTX_CORE0_ECDSA_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ECDSA_INTR_MAP_S 0 + +/** INTMTX_CORE0_INT_STATUS_REG_0_REG register + * register description + */ +#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104) +/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Status register for interrupt sources 0~31 mapping register + */ +#define INTMTX_CORE0_INT_STATUS_0 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_0_M (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S) +#define INTMTX_CORE0_INT_STATUS_0_V 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_0_S 0 + +/** INTMTX_CORE0_INT_STATUS_REG_1_REG register + * register description + */ +#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108) +/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Status register for interrupt sources 32~63 mapping register + */ +#define INTMTX_CORE0_INT_STATUS_1 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_1_M (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S) +#define INTMTX_CORE0_INT_STATUS_1_V 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_1_S 0 + +/** INTMTX_CORE0_INT_STATUS_REG_2_REG register + * register description + */ +#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c) +/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * Status register for interrupt sources 64~95 mapping register + */ +#define INTMTX_CORE0_INT_STATUS_2 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_2_M (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S) +#define INTMTX_CORE0_INT_STATUS_2_V 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_2_S 0 + +/** INTMTX_CORE0_CLOCK_GATE_REG register + * register description + */ +#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110) +/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Clock register + */ +#define INTMTX_CORE0_REG_CLK_EN (BIT(0)) +#define INTMTX_CORE0_REG_CLK_EN_M (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S) +#define INTMTX_CORE0_REG_CLK_EN_V 0x00000001U +#define INTMTX_CORE0_REG_CLK_EN_S 0 + +/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register + * register description + */ +#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc) +/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784; + * Version control register + */ +#define INTMTX_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTMTX_CORE0_INTERRUPT_REG_DATE_M (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S) +#define INTMTX_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU +#define INTMTX_CORE0_INTERRUPT_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h b/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h new file mode 100644 index 0000000000..254f1317b7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h @@ -0,0 +1,1074 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of pmu_intr_map register + * register description + */ +typedef union { + struct { + /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_PMU_INTR mapping register + */ + uint32_t pmu_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_pmu_intr_map_reg_t; + +/** Type of efuse_intr_map register + * register description + */ +typedef union { + struct { + /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_EFUSE_INTR mapping register + */ + uint32_t efuse_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_efuse_intr_map_reg_t; + +/** Type of lp_rtc_timer_intr_map register + * register description + */ +typedef union { + struct { + /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_RTC_TIMER_INTR mapping register + */ + uint32_t lp_rtc_timer_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_lp_rtc_timer_intr_map_reg_t; + +/** Type of lp_ble_timer_intr_map register + * register description + */ +typedef union { + struct { + /** lp_ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_BLE_TIMER_INTR mapping register + */ + uint32_t lp_ble_timer_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_lp_ble_timer_intr_map_reg_t; + +/** Type of lp_wdt_intr_map register + * register description + */ +typedef union { + struct { + /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_WDT_INTR mapping register + */ + uint32_t lp_wdt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_lp_wdt_intr_map_reg_t; + +/** Type of lp_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_PERI_TIMEOUT_INTR mapping register + */ + uint32_t lp_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_lp_peri_timeout_intr_map_reg_t; + +/** Type of lp_apm_m0_intr_map register + * register description + */ +typedef union { + struct { + /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_LP_APM_M0_INTR mapping register + */ + uint32_t lp_apm_m0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_lp_apm_m0_intr_map_reg_t; + +/** Type of cpu_intr_from_cpu_0_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_0 mapping register + */ + uint32_t cpu_intr_from_cpu_0_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_cpu_intr_from_cpu_0_map_reg_t; + +/** Type of cpu_intr_from_cpu_1_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_1 mapping register + */ + uint32_t cpu_intr_from_cpu_1_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_cpu_intr_from_cpu_1_map_reg_t; + +/** Type of cpu_intr_from_cpu_2_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_2 mapping register + */ + uint32_t cpu_intr_from_cpu_2_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_cpu_intr_from_cpu_2_map_reg_t; + +/** Type of cpu_intr_from_cpu_3_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_INTR_FROM_CPU_3 mapping register + */ + uint32_t cpu_intr_from_cpu_3_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_cpu_intr_from_cpu_3_map_reg_t; + +/** Type of assist_debug_intr_map register + * register description + */ +typedef union { + struct { + /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_ASSIST_DEBUG_INTR mapping register + */ + uint32_t assist_debug_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_assist_debug_intr_map_reg_t; + +/** Type of trace_intr_map register + * register description + */ +typedef union { + struct { + /** trace_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_TRACE_INTR mapping register + */ + uint32_t trace_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_trace_intr_map_reg_t; + +/** Type of cache_intr_map register + * register description + */ +typedef union { + struct { + /** cache_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CACHE_INTR mapping register + */ + uint32_t cache_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_cache_intr_map_reg_t; + +/** Type of cpu_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CPU_PERI_TIMEOUT_INTR mapping register + */ + uint32_t cpu_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_cpu_peri_timeout_intr_map_reg_t; + +/** Type of bt_mac_intr_map register + * register description + */ +typedef union { + struct { + /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_BT_MAC_INTR mapping register + */ + uint32_t bt_mac_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_bt_mac_intr_map_reg_t; + +/** Type of bt_bb_intr_map register + * register description + */ +typedef union { + struct { + /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_BT_BB_INTR mapping register + */ + uint32_t bt_bb_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_bt_bb_intr_map_reg_t; + +/** Type of bt_bb_nmi_map register + * register description + */ +typedef union { + struct { + /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_BT_BB_NMI mapping register + */ + uint32_t bt_bb_nmi_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_bt_bb_nmi_map_reg_t; + +/** Type of coex_intr_map register + * register description + */ +typedef union { + struct { + /** coex_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_COEX_INTR mapping register + */ + uint32_t coex_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_coex_intr_map_reg_t; + +/** Type of ble_timer_intr_map register + * register description + */ +typedef union { + struct { + /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_BLE_TIMER_INTR mapping register + */ + uint32_t ble_timer_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_ble_timer_intr_map_reg_t; + +/** Type of ble_sec_intr_map register + * register description + */ +typedef union { + struct { + /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_BLE_SEC_INTR mapping register + */ + uint32_t ble_sec_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_ble_sec_intr_map_reg_t; + +/** Type of zb_mac_intr_map register + * register description + */ +typedef union { + struct { + /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_ZB_MAC_INTR mapping register + */ + uint32_t zb_mac_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_zb_mac_intr_map_reg_t; + +/** Type of gpio_interrupt_pro_map register + * register description + */ +typedef union { + struct { + /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_GPIO_INTERRUPT_PRO mapping register + */ + uint32_t gpio_interrupt_pro_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_gpio_interrupt_pro_map_reg_t; + +/** Type of gpio_interrupt_pro_nmi_map register + * register description + */ +typedef union { + struct { + /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_GPIO_INTERRUPT_PRO_NMI mapping register + */ + uint32_t gpio_interrupt_pro_nmi_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_gpio_interrupt_pro_nmi_map_reg_t; + +/** Type of pau_intr_map register + * register description + */ +typedef union { + struct { + /** pau_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_PAU_INTR mapping register + */ + uint32_t pau_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_pau_intr_map_reg_t; + +/** Type of hp_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_PERI_TIMEOUT_INTR mapping register + */ + uint32_t hp_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_hp_peri_timeout_intr_map_reg_t; + +/** Type of hp_apm_m0_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M0_INTR mapping register + */ + uint32_t hp_apm_m0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_hp_apm_m0_intr_map_reg_t; + +/** Type of hp_apm_m1_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M1_INTR mapping register + */ + uint32_t hp_apm_m1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_hp_apm_m1_intr_map_reg_t; + +/** Type of hp_apm_m2_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M2_INTR mapping register + */ + uint32_t hp_apm_m2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_hp_apm_m2_intr_map_reg_t; + +/** Type of hp_apm_m3_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_HP_APM_M3_INTR mapping register + */ + uint32_t hp_apm_m3_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_hp_apm_m3_intr_map_reg_t; + +/** Type of mspi_intr_map register + * register description + */ +typedef union { + struct { + /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_MSPI_INTR mapping register + */ + uint32_t mspi_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_mspi_intr_map_reg_t; + +/** Type of i2s1_intr_map register + * register description + */ +typedef union { + struct { + /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_I2S1_INTR mapping register + */ + uint32_t i2s1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_i2s1_intr_map_reg_t; + +/** Type of uhci0_intr_map register + * register description + */ +typedef union { + struct { + /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_UHCI0_INTR mapping register + */ + uint32_t uhci0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_uhci0_intr_map_reg_t; + +/** Type of uart0_intr_map register + * register description + */ +typedef union { + struct { + /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_UART0_INTR mapping register + */ + uint32_t uart0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_uart0_intr_map_reg_t; + +/** Type of uart1_intr_map register + * register description + */ +typedef union { + struct { + /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_UART1_INTR mapping register + */ + uint32_t uart1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_uart1_intr_map_reg_t; + +/** Type of ledc_intr_map register + * register description + */ +typedef union { + struct { + /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_LEDC_INTR mapping register + */ + uint32_t ledc_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_ledc_intr_map_reg_t; + +/** Type of can0_intr_map register + * register description + */ +typedef union { + struct { + /** can0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_CAN0_INTR mapping register + */ + uint32_t can0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_can0_intr_map_reg_t; + +/** Type of usb_intr_map register + * register description + */ +typedef union { + struct { + /** usb_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_USB_INTR mapping register + */ + uint32_t usb_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_usb_intr_map_reg_t; + +/** Type of rmt_intr_map register + * register description + */ +typedef union { + struct { + /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_RMT_INTR mapping register + */ + uint32_t rmt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_rmt_intr_map_reg_t; + +/** Type of i2c_ext0_intr_map register + * register description + */ +typedef union { + struct { + /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_I2C_EXT0_INTR mapping register + */ + uint32_t i2c_ext0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_i2c_ext0_intr_map_reg_t; + +/** Type of i2c_ext1_intr_map register + * register description + */ +typedef union { + struct { + /** i2c_ext1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_I2C_EXT1_INTR mapping register + */ + uint32_t i2c_ext1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_i2c_ext1_intr_map_reg_t; + +/** Type of tg0_t0_intr_map register + * register description + */ +typedef union { + struct { + /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG0_T0_INTR mapping register + */ + uint32_t tg0_t0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_tg0_t0_intr_map_reg_t; + +/** Type of tg0_wdt_intr_map register + * register description + */ +typedef union { + struct { + /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG0_WDT_INTR mapping register + */ + uint32_t tg0_wdt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_tg0_wdt_intr_map_reg_t; + +/** Type of tg1_t0_intr_map register + * register description + */ +typedef union { + struct { + /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG1_T0_INTR mapping register + */ + uint32_t tg1_t0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_tg1_t0_intr_map_reg_t; + +/** Type of tg1_wdt_intr_map register + * register description + */ +typedef union { + struct { + /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_TG1_WDT_INTR mapping register + */ + uint32_t tg1_wdt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_tg1_wdt_intr_map_reg_t; + +/** Type of systimer_target0_intr_map register + * register description + */ +typedef union { + struct { + /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_SYSTIMER_TARGET0_INTR mapping register + */ + uint32_t systimer_target0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_systimer_target0_intr_map_reg_t; + +/** Type of systimer_target1_intr_map register + * register description + */ +typedef union { + struct { + /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_SYSTIMER_TARGET1_INTR mapping register + */ + uint32_t systimer_target1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_systimer_target1_intr_map_reg_t; + +/** Type of systimer_target2_intr_map register + * register description + */ +typedef union { + struct { + /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_SYSTIMER_TARGET2_INTR mapping register + */ + uint32_t systimer_target2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_systimer_target2_intr_map_reg_t; + +/** Type of apb_adc_intr_map register + * register description + */ +typedef union { + struct { + /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_APB_ADC_INTR mapping register + */ + uint32_t apb_adc_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_apb_adc_intr_map_reg_t; + +/** Type of pwm_intr_map register + * register description + */ +typedef union { + struct { + /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_PWM_INTR mapping register + */ + uint32_t pwm_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_pwm_intr_map_reg_t; + +/** Type of pcnt_intr_map register + * register description + */ +typedef union { + struct { + /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_PCNT_INTR mapping register + */ + uint32_t pcnt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_pcnt_intr_map_reg_t; + +/** Type of parl_io_tx_intr_map register + * register description + */ +typedef union { + struct { + /** parl_io_tx_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_PARL_IO_TX_INTR mapping register + */ + uint32_t parl_io_tx_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_parl_io_tx_intr_map_reg_t; + +/** Type of parl_io_rx_intr_map register + * register description + */ +typedef union { + struct { + /** parl_io_rx_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_PARL_IO_RX_INTR mapping register + */ + uint32_t parl_io_rx_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_parl_io_rx_intr_map_reg_t; + +/** Type of dma_in_ch0_intr_map register + * register description + */ +typedef union { + struct { + /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_IN_CH0_INTR mapping register + */ + uint32_t dma_in_ch0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_dma_in_ch0_intr_map_reg_t; + +/** Type of dma_in_ch1_intr_map register + * register description + */ +typedef union { + struct { + /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_IN_CH1_INTR mapping register + */ + uint32_t dma_in_ch1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_dma_in_ch1_intr_map_reg_t; + +/** Type of dma_in_ch2_intr_map register + * register description + */ +typedef union { + struct { + /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_IN_CH2_INTR mapping register + */ + uint32_t dma_in_ch2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_dma_in_ch2_intr_map_reg_t; + +/** Type of dma_out_ch0_intr_map register + * register description + */ +typedef union { + struct { + /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_OUT_CH0_INTR mapping register + */ + uint32_t dma_out_ch0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_dma_out_ch0_intr_map_reg_t; + +/** Type of dma_out_ch1_intr_map register + * register description + */ +typedef union { + struct { + /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_OUT_CH1_INTR mapping register + */ + uint32_t dma_out_ch1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_dma_out_ch1_intr_map_reg_t; + +/** Type of dma_out_ch2_intr_map register + * register description + */ +typedef union { + struct { + /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_DMA_OUT_CH2_INTR mapping register + */ + uint32_t dma_out_ch2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_dma_out_ch2_intr_map_reg_t; + +/** Type of gpspi2_intr_map register + * register description + */ +typedef union { + struct { + /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_GPSPI2_INTR mapping register + */ + uint32_t gpspi2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_gpspi2_intr_map_reg_t; + +/** Type of aes_intr_map register + * register description + */ +typedef union { + struct { + /** aes_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_AES_INTR mapping register + */ + uint32_t aes_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_aes_intr_map_reg_t; + +/** Type of sha_intr_map register + * register description + */ +typedef union { + struct { + /** sha_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_SHA_INTR mapping register + */ + uint32_t sha_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_sha_intr_map_reg_t; + +/** Type of rsa_intr_map register + * register description + */ +typedef union { + struct { + /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_RSA_INTR mapping register + */ + uint32_t rsa_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_rsa_intr_map_reg_t; + +/** Type of ecc_intr_map register + * register description + */ +typedef union { + struct { + /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_ECC_INTR mapping register + */ + uint32_t ecc_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_ecc_intr_map_reg_t; + +/** Type of ecdsa_intr_map register + * register description + */ +typedef union { + struct { + /** ecdsa_intr_map : R/W; bitpos: [4:0]; default: 0; + * CORE0_ECDSA_INTR mapping register + */ + uint32_t ecdsa_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} intmtx_core0_ecdsa_intr_map_reg_t; + +/** Type of int_status_reg_0 register + * register description + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Status register for interrupt sources 0~31 mapping register + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} intmtx_core0_int_status_reg_0_reg_t; + +/** Type of int_status_reg_1 register + * register description + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Status register for interrupt sources 32~63 mapping register + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} intmtx_core0_int_status_reg_1_reg_t; + +/** Type of int_status_reg_2 register + * register description + */ +typedef union { + struct { + /** int_status_2 : RO; bitpos: [31:0]; default: 0; + * Status register for interrupt sources 64~95 mapping register + */ + uint32_t int_status_2:32; + }; + uint32_t val; +} intmtx_core0_int_status_reg_2_reg_t; + +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * Clock register + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intmtx_core0_clock_gate_reg_t; + +/** Type of interrupt_reg_date register + * register description + */ +typedef union { + struct { + /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35688784; + * Version control register + */ + uint32_t interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} intmtx_core0_interrupt_reg_date_reg_t; + + +typedef struct { + volatile intmtx_core0_pmu_intr_map_reg_t pmu_intr_map; + volatile intmtx_core0_efuse_intr_map_reg_t efuse_intr_map; + volatile intmtx_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; + volatile intmtx_core0_lp_ble_timer_intr_map_reg_t lp_ble_timer_intr_map; + volatile intmtx_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map; + volatile intmtx_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; + volatile intmtx_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; + volatile intmtx_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; + volatile intmtx_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; + volatile intmtx_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; + volatile intmtx_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; + volatile intmtx_core0_assist_debug_intr_map_reg_t assist_debug_intr_map; + volatile intmtx_core0_trace_intr_map_reg_t trace_intr_map; + volatile intmtx_core0_cache_intr_map_reg_t cache_intr_map; + volatile intmtx_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; + volatile intmtx_core0_bt_mac_intr_map_reg_t bt_mac_intr_map; + volatile intmtx_core0_bt_bb_intr_map_reg_t bt_bb_intr_map; + volatile intmtx_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map; + volatile intmtx_core0_coex_intr_map_reg_t coex_intr_map; + volatile intmtx_core0_ble_timer_intr_map_reg_t ble_timer_intr_map; + volatile intmtx_core0_ble_sec_intr_map_reg_t ble_sec_intr_map; + volatile intmtx_core0_zb_mac_intr_map_reg_t zb_mac_intr_map; + volatile intmtx_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; + volatile intmtx_core0_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map; + volatile intmtx_core0_pau_intr_map_reg_t pau_intr_map; + volatile intmtx_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; + volatile intmtx_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; + volatile intmtx_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; + volatile intmtx_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; + volatile intmtx_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; + volatile intmtx_core0_mspi_intr_map_reg_t mspi_intr_map; + volatile intmtx_core0_i2s1_intr_map_reg_t i2s1_intr_map; + volatile intmtx_core0_uhci0_intr_map_reg_t uhci0_intr_map; + volatile intmtx_core0_uart0_intr_map_reg_t uart0_intr_map; + volatile intmtx_core0_uart1_intr_map_reg_t uart1_intr_map; + volatile intmtx_core0_ledc_intr_map_reg_t ledc_intr_map; + volatile intmtx_core0_can0_intr_map_reg_t can0_intr_map; + volatile intmtx_core0_usb_intr_map_reg_t usb_intr_map; + volatile intmtx_core0_rmt_intr_map_reg_t rmt_intr_map; + volatile intmtx_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; + volatile intmtx_core0_i2c_ext1_intr_map_reg_t i2c_ext1_intr_map; + volatile intmtx_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map; + volatile intmtx_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; + volatile intmtx_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map; + volatile intmtx_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; + volatile intmtx_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map; + volatile intmtx_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map; + volatile intmtx_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map; + volatile intmtx_core0_apb_adc_intr_map_reg_t apb_adc_intr_map; + volatile intmtx_core0_pwm_intr_map_reg_t pwm_intr_map; + volatile intmtx_core0_pcnt_intr_map_reg_t pcnt_intr_map; + volatile intmtx_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map; + volatile intmtx_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map; + volatile intmtx_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; + volatile intmtx_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; + volatile intmtx_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; + volatile intmtx_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; + volatile intmtx_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; + volatile intmtx_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map; + volatile intmtx_core0_gpspi2_intr_map_reg_t gpspi2_intr_map; + volatile intmtx_core0_aes_intr_map_reg_t aes_intr_map; + volatile intmtx_core0_sha_intr_map_reg_t sha_intr_map; + volatile intmtx_core0_rsa_intr_map_reg_t rsa_intr_map; + volatile intmtx_core0_ecc_intr_map_reg_t ecc_intr_map; + volatile intmtx_core0_ecdsa_intr_map_reg_t ecdsa_intr_map; + volatile intmtx_core0_int_status_reg_0_reg_t int_status_reg_0; + volatile intmtx_core0_int_status_reg_1_reg_t int_status_reg_1; + volatile intmtx_core0_int_status_reg_2_reg_t int_status_reg_2; + volatile intmtx_core0_clock_gate_reg_t clock_gate; + uint32_t reserved_114[442]; + volatile intmtx_core0_interrupt_reg_date_reg_t interrupt_reg_date; +} intmtx_core0_dev_t; + +extern interrupt_matrix_dev_t INTMTX; + +#ifndef __cplusplus +_Static_assert(sizeof(intmtx_core0_dev_t) == 0x800, "Invalid size of intmtx_core0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/interrupt_reg.h b/components/soc/esp32h2/include/soc/interrupt_reg.h new file mode 100644 index 0000000000..be4e6b0ebe --- /dev/null +++ b/components/soc/esp32h2/include/soc/interrupt_reg.h @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "interrupt_matrix_reg.h" +#include "plic_reg.h" +#include "soc/soc_caps.h" + +// ESP32H2 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y) +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG +#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE diff --git a/components/soc/esp32h2/include/soc/intpri_reg.h b/components/soc/esp32h2/include/soc/intpri_reg.h new file mode 100644 index 0000000000..f4d9c51fc7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/intpri_reg.h @@ -0,0 +1,574 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTPRI_CORE0_CPU_INT_ENABLE_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0) +/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_ENABLE_M (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S) +#define INTPRI_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_ENABLE_S 0 + +/** INTPRI_CORE0_CPU_INT_TYPE_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4) +/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_TYPE 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_TYPE_M (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S) +#define INTPRI_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_TYPE_S 0 + +/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8) +/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S) +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_0_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc) +/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_0_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_0_MAP_M (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S) +#define INTPRI_CORE0_CPU_PRI_0_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_0_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_1_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10) +/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_1_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_1_MAP_M (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S) +#define INTPRI_CORE0_CPU_PRI_1_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_1_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_2_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14) +/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_2_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_2_MAP_M (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S) +#define INTPRI_CORE0_CPU_PRI_2_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_2_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_3_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18) +/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_3_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_3_MAP_M (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S) +#define INTPRI_CORE0_CPU_PRI_3_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_3_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_4_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c) +/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_4_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_4_MAP_M (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S) +#define INTPRI_CORE0_CPU_PRI_4_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_4_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_5_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20) +/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_5_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_5_MAP_M (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S) +#define INTPRI_CORE0_CPU_PRI_5_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_5_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_6_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24) +/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_6_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_6_MAP_M (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S) +#define INTPRI_CORE0_CPU_PRI_6_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_6_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_7_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28) +/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_7_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_7_MAP_M (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S) +#define INTPRI_CORE0_CPU_PRI_7_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_7_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_8_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c) +/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_8_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_8_MAP_M (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S) +#define INTPRI_CORE0_CPU_PRI_8_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_8_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_9_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30) +/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_9_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_9_MAP_M (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S) +#define INTPRI_CORE0_CPU_PRI_9_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_9_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_10_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34) +/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_10_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_10_MAP_M (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S) +#define INTPRI_CORE0_CPU_PRI_10_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_10_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_11_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38) +/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_11_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_11_MAP_M (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S) +#define INTPRI_CORE0_CPU_PRI_11_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_11_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_12_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c) +/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_12_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_12_MAP_M (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S) +#define INTPRI_CORE0_CPU_PRI_12_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_12_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_13_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40) +/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_13_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_13_MAP_M (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S) +#define INTPRI_CORE0_CPU_PRI_13_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_13_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_14_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44) +/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_14_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_14_MAP_M (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S) +#define INTPRI_CORE0_CPU_PRI_14_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_14_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_15_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48) +/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_15_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_15_MAP_M (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S) +#define INTPRI_CORE0_CPU_PRI_15_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_15_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_16_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c) +/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_16_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_16_MAP_M (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S) +#define INTPRI_CORE0_CPU_PRI_16_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_16_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_17_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50) +/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_17_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_17_MAP_M (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S) +#define INTPRI_CORE0_CPU_PRI_17_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_17_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_18_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54) +/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_18_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_18_MAP_M (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S) +#define INTPRI_CORE0_CPU_PRI_18_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_18_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_19_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58) +/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_19_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_19_MAP_M (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S) +#define INTPRI_CORE0_CPU_PRI_19_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_19_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_20_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c) +/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_20_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_20_MAP_M (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S) +#define INTPRI_CORE0_CPU_PRI_20_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_20_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_21_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60) +/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_21_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_21_MAP_M (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S) +#define INTPRI_CORE0_CPU_PRI_21_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_21_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_22_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64) +/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_22_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_22_MAP_M (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S) +#define INTPRI_CORE0_CPU_PRI_22_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_22_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_23_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68) +/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_23_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_23_MAP_M (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S) +#define INTPRI_CORE0_CPU_PRI_23_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_23_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_24_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c) +/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_24_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_24_MAP_M (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S) +#define INTPRI_CORE0_CPU_PRI_24_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_24_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_25_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70) +/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_25_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_25_MAP_M (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S) +#define INTPRI_CORE0_CPU_PRI_25_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_25_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_26_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74) +/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_26_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_26_MAP_M (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S) +#define INTPRI_CORE0_CPU_PRI_26_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_26_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_27_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78) +/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_27_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_27_MAP_M (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S) +#define INTPRI_CORE0_CPU_PRI_27_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_27_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_28_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c) +/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_28_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_28_MAP_M (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S) +#define INTPRI_CORE0_CPU_PRI_28_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_28_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_29_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80) +/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_29_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_29_MAP_M (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S) +#define INTPRI_CORE0_CPU_PRI_29_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_29_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_30_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84) +/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_30_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_30_MAP_M (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S) +#define INTPRI_CORE0_CPU_PRI_30_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_30_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_31_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88) +/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_31_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_31_MAP_M (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S) +#define INTPRI_CORE0_CPU_PRI_31_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_31_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_THRESH_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c) +/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_THRESH 0x000000FFU +#define INTPRI_CORE0_CPU_INT_THRESH_M (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S) +#define INTPRI_CORE0_CPU_INT_THRESH_V 0x000000FFU +#define INTPRI_CORE0_CPU_INT_THRESH_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_0_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90) +/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S) +#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_0_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_1_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94) +/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S) +#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_1_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_2_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98) +/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S) +#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_2_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_3_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c) +/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S) +#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_3_S 0 + +/** INTPRI_DATE_REG register + * register description + */ +#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0) +/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824; + * Need add description + */ +#define INTPRI_DATE 0x0FFFFFFFU +#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S) +#define INTPRI_DATE_V 0x0FFFFFFFU +#define INTPRI_DATE_S 0 + +/** INTPRI_CLOCK_GATE_REG register + * register description + */ +#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4) +/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTPRI_CLK_EN (BIT(0)) +#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S) +#define INTPRI_CLK_EN_V 0x00000001U +#define INTPRI_CLK_EN_S 0 + +/** INTPRI_CORE0_CPU_INT_CLEAR_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8) +/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_CLEAR_M (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S) +#define INTPRI_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_CLEAR_S 0 + +/** INTPRI_RND_ECO_REG register + * redcy eco register. + */ +#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac) +/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_ENA (BIT(0)) +#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S) +#define INTPRI_REDCY_ENA_V 0x00000001U +#define INTPRI_REDCY_ENA_S 0 +/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_RESULT (BIT(1)) +#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S) +#define INTPRI_REDCY_RESULT_V 0x00000001U +#define INTPRI_REDCY_RESULT_S 1 + +/** INTPRI_RND_ECO_LOW_REG register + * redcy eco low register. + */ +#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0) +/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_LOW 0xFFFFFFFFU +#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S) +#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU +#define INTPRI_REDCY_LOW_S 0 + +/** INTPRI_RND_ECO_HIGH_REG register + * redcy eco high register. + */ +#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc) +/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_HIGH 0xFFFFFFFFU +#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S) +#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU +#define INTPRI_REDCY_HIGH_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/intpri_struct.h b/components/soc/esp32h2/include/soc/intpri_struct.h new file mode 100644 index 0000000000..e42d7892eb --- /dev/null +++ b/components/soc/esp32h2/include/soc/intpri_struct.h @@ -0,0 +1,256 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of core0_cpu_int_enable register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_enable:32; + }; + uint32_t val; +} intpri_core0_cpu_int_enable_reg_t; + +/** Type of core0_cpu_int_type register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_type:32; + }; + uint32_t val; +} intpri_core0_cpu_int_type_reg_t; + +/** Type of core0_cpu_int_eip_status register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_eip_status:32; + }; + uint32_t val; +} intpri_core0_cpu_int_eip_status_reg_t; + +/** Type of core0_cpu_int_pri_0 register + * register description + */ +typedef union { + struct { + /** core0_cpu_pri_0_map : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_pri_0_map:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} intpri_core0_cpu_int_pri_n_reg_t; + +/** Type of core0_cpu_int_thresh register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_thresh:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} intpri_core0_cpu_int_thresh_reg_t; + +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_clock_gate_reg_t; + +/** Type of core0_cpu_int_clear register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_clear:32; + }; + uint32_t val; +} intpri_core0_cpu_int_clear_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of cpu_intr_from_cpu_0 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_0_reg_t; + +/** Type of cpu_intr_from_cpu_1 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_1_reg_t; + +/** Type of cpu_intr_from_cpu_2 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_2:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_2_reg_t; + +/** Type of cpu_intr_from_cpu_3 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_3:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_3_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * register description + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655824; + * Need add description + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} intpri_date_reg_t; + + +/** Group: Redcy ECO Registers */ +/** Type of rnd_eco register + * redcy eco register. + */ +typedef union { + struct { + /** redcy_ena : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_ena:1; + /** redcy_result : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} intpri_rnd_eco_reg_t; + +/** Type of rnd_eco_low register + * redcy eco low register. + */ +typedef union { + struct { + /** redcy_low : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_low:32; + }; + uint32_t val; +} intpri_rnd_eco_low_reg_t; + +/** Type of rnd_eco_high register + * redcy eco high register. + */ +typedef union { + struct { + /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ + uint32_t redcy_high:32; + }; + uint32_t val; +} intpri_rnd_eco_high_reg_t; + + +typedef struct { + volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable; + volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type; + volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status; + volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32]; + volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh; + volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; + volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; + volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; + volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; + volatile intpri_date_reg_t date; + volatile intpri_clock_gate_reg_t clock_gate; + volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear; + volatile intpri_rnd_eco_reg_t rnd_eco; + volatile intpri_rnd_eco_low_reg_t rnd_eco_low; + uint32_t reserved_0b4[210]; + volatile intpri_rnd_eco_high_reg_t rnd_eco_high; +} intpri_dev_t; + +extern intpri_dev_t INTPRI; + +#ifndef __cplusplus +_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/include/soc/io_mux_reg.h new file mode 100644 index 0000000000..3898d8c680 --- /dev/null +++ b/components/soc/esp32h2/include/soc/io_mux_reg.h @@ -0,0 +1,313 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include "soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define SPI_HD_GPIO_NUM 18 +#define SPI_WP_GPIO_NUM 17 +#define SPI_CS0_GPIO_NUM 15 +#define SPI_CLK_GPIO_NUM 19 +#define SPI_D_GPIO_NUM 20 +#define SPI_Q_GPIO_NUM 16 + +#define MAX_RTC_GPIO_NUM 7 +#define MAX_PAD_GPIO_NUM 27 +#define MAX_GPIO_NUM 31 +#define HIGH_IO_HOLD_BIT_SHIFT 32 +#define GPIO_NUM_IN_FORCE_0 0x3c +#define GPIO_NUM_IN_FORCE_1 0x38 +#define GPIO_NUM_IN_INVALID 0x3a + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 IO_MUX_CLK_OUT3 +#define CLK_OUT3_V IO_MUX_CLK_OUT3_V +#define CLK_OUT3_S IO_MUX_CLK_OUT3_S +#define CLK_OUT3_M IO_MUX_CLK_OUT3_M +#define CLK_OUT2 IO_MUX_CLK_OUT2 +#define CLK_OUT2_V IO_MUX_CLK_OUT2_V +#define CLK_OUT2_S IO_MUX_CLK_OUT2_S +#define CLK_OUT2_M IO_MUX_CLK_OUT2_M +#define CLK_OUT1 IO_MUX_CLK_OUT1 +#define CLK_OUT1_V IO_MUX_CLK_OUT1_V +#define CLK_OUT1_S IO_MUX_CLK_OUT1_S +#define CLK_OUT1_M IO_MUX_CLK_OUT1_M +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4) +#define FUNC_GPIO0_FSPIQ 2 +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x8) +#define FUNC_GPIO1_FSPICS0 2 +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xC) +#define FUNC_MTMS_FSPIWP 2 +#define FUNC_MTMS_GPIO2 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x10) +#define FUNC_MTDO_FSPIHD 2 +#define FUNC_MTDO_GPIO3 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO4 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18) +#define FUNC_MTDI_FSPID 2 +#define FUNC_MTDI_GPIO5 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1C) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C) +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x38) +#define FUNC_XTAL_32K_P_GPIO13 1 +#define FUNC_XTAL_32K_P_GPIO13_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x3C) +#define FUNC_XTAL_32K_N_GPIO14 1 +#define FUNC_XTAL_32K_N_GPIO14_0 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x40) +#define FUNC_SPICS0_GPIO15 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x44) +#define FUNC_SPIQ_GPIO16 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x48) +#define FUNC_SPIWP_GPIO17 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x4C) +#define FUNC_SPIHD_GPIO18 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x50) +#define FUNC_SPICLK_GPIO19 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x54) +#define FUNC_SPID_GPIO20 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x58) +#define FUNC_VDD_SPI_GPIO21 1 +#define FUNC_VDD_SPI_GPIO21_0 0 + +#define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE + 0x5C) +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x60) +#define FUNC_U0RXD_FSPICS1 2 +#define FUNC_U0RXD_GPIO23 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x64) +#define FUNC_U0TXD_FSPICS2 2 +#define FUNC_U0TXD_GPIO24 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE + 0x68) +#define FUNC_GPIO25_FSPICS3 2 +#define FUNC_GPIO25_GPIO25 1 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE + 0x6C) +#define FUNC_GPIO26_FSPICS4 2 +#define FUNC_GPIO26_GPIO26 1 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE + 0x70) +#define FUNC_GPIO27_FSPICS5 2 +#define FUNC_GPIO27_GPIO27 1 +#define FUNC_GPIO27_GPIO27_0 0 + +#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0) +/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[14:10] ;default: 5'h7 ; */ +/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C +LK_OUT_out3 can be found in peripheral output signals..*/ +#define IO_MUX_CLK_OUT3 0x0000001F +#define IO_MUX_CLK_OUT3_M ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S)) +#define IO_MUX_CLK_OUT3_V 0x1F +#define IO_MUX_CLK_OUT3_S 10 +/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[9:5] ;default: 5'hf ; */ +/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C +LK_OUT_out2 can be found in peripheral output signals..*/ +#define IO_MUX_CLK_OUT2 0x0000001F +#define IO_MUX_CLK_OUT2_M ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S)) +#define IO_MUX_CLK_OUT2_V 0x1F +#define IO_MUX_CLK_OUT2_S 5 +/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[4:0] ;default: 5'hf ; */ +/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C +LK_OUT_out1 can be found in peripheral output signals..*/ +#define IO_MUX_CLK_OUT1 0x0000001F +#define IO_MUX_CLK_OUT1_M ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S)) +#define IO_MUX_CLK_OUT1_V 0x1F +#define IO_MUX_CLK_OUT1_S 0 +#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xBC) +/* IO_MUX_MODEM_DIAG_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio + matrix. 0:enable other signals into gpio matrix.*/ +#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFF +#define IO_MUX_MODEM_DIAG_EN_M ((IO_MUX_MODEM_DIAG_EN_V)<<(IO_MUX_MODEM_DIAG_EN_S)) +#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFF +#define IO_MUX_MODEM_DIAG_EN_S 0 +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xFC) +/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207270 ; */ +/*description: Version control register.*/ +#define IO_MUX_REG_DATE 0x0FFFFFFF +#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S)) +#define IO_MUX_REG_DATE_V 0xFFFFFFF +#define IO_MUX_REG_DATE_S 0 diff --git a/components/soc/esp32h2/include/soc/ledc_reg.h b/components/soc/esp32h2/include/soc/ledc_reg.h new file mode 100644 index 0000000000..a7c4311ad1 --- /dev/null +++ b/components/soc/esp32h2/include/soc/ledc_reg.h @@ -0,0 +1,2775 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 0. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 0. + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 0 is inactive (when + * LEDC_SIG_OUT_EN_CH0 is 0). + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, + * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel + * 0, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0 overflows for + * (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 0. + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 0. + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 1. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 1. + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 1 is inactive (when + * LEDC_SIG_OUT_EN_CH1 is 0). + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, + * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel + * 1, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1 overflows for + * (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 1. + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 1. + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 2. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 2. + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 2 is inactive (when + * LEDC_SIG_OUT_EN_CH2 is 0). + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, + * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel + * 2, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2 overflows for + * (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 2. + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 2. + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 3. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 3. + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 3 is inactive (when + * LEDC_SIG_OUT_EN_CH3 is 0). + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, + * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel + * 3, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3 overflows for + * (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 3. + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 3. + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 4. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 4. + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 4 is inactive (when + * LEDC_SIG_OUT_EN_CH4 is 0). + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, + * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel + * 4, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4 overflows for + * (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 4. + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 4. + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 5. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 5. + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 5 is inactive (when + * LEDC_SIG_OUT_EN_CH5 is 0). + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, + * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel + * 5, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5 overflows for + * (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 5. + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 5. + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 0. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 0. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 0. + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 0. The counter will show 0 after reset. + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 0. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER0 (BIT(25)) +#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) +#define LEDC_TICK_SEL_TIMER0_V 0x00000001U +#define LEDC_TICK_SEL_TIMER0_S 25 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 1. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 1. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 1. + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 1. The counter will show 0 after reset. + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 1. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER1 (BIT(25)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001U +#define LEDC_TICK_SEL_TIMER1_S 25 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 2. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 2. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 2. + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 2. The counter will show 0 after reset. + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 2. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER2 (BIT(25)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001U +#define LEDC_TICK_SEL_TIMER2_S 25 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 3. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 3. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 3. + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 3. The counter will show 0 after reset. + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 3. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER3 (BIT(25)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001U +#define LEDC_TICK_SEL_TIMER3_S 25 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Raw interrupt status + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Triggered when the timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Triggered when the timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Triggered when the timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Triggered when the timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/** LEDC_INT_ST_REG register + * Masked interrupt status + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when + * LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when + * LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when + * LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when + * LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT + * interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT + * interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT + * interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT + * interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT + * interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT + * interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when + * LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when + * LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when + * LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when + * LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when + * LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when + * LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/** LEDC_INT_ENA_REG register + * Interrupt enable bits + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/** LEDC_INT_CLR_REG register + * Interrupt clear bits + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/** LEDC_CH0_GAMMA_WR_REG register + * Ledc ch0 gamma ram write register. + */ +#define LEDC_CH0_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch0 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 0. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH0_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_DUTY_INC_M (LEDC_CH0_GAMMA_DUTY_INC_V << LEDC_CH0_GAMMA_DUTY_INC_S) +#define LEDC_CH0_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH0_GAMMA_DUTY_INC_S 0 +/** LEDC_CH0_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch0 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH0_GAMMA_DUTY_CYCLE on channel 0. + */ +#define LEDC_CH0_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_CYCLE_M (LEDC_CH0_GAMMA_DUTY_CYCLE_V << LEDC_CH0_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH0_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH0_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch0 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 0. + */ +#define LEDC_CH0_GAMMA_SCALE 0x000003FFU +#define LEDC_CH0_GAMMA_SCALE_M (LEDC_CH0_GAMMA_SCALE_V << LEDC_CH0_GAMMA_SCALE_S) +#define LEDC_CH0_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH0_GAMMA_SCALE_S 11 +/** LEDC_CH0_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch0 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH0_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_NUM_M (LEDC_CH0_GAMMA_DUTY_NUM_V << LEDC_CH0_GAMMA_DUTY_NUM_S) +#define LEDC_CH0_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH0_GAMMA_WR_ADDR_REG register + * Ledc ch0 gamma ram write address register. + */ +#define LEDC_CH0_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH0_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch0 gamma ram write address. + */ +#define LEDC_CH0_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH0_GAMMA_WR_ADDR_M (LEDC_CH0_GAMMA_WR_ADDR_V << LEDC_CH0_GAMMA_WR_ADDR_S) +#define LEDC_CH0_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH0_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH0_GAMMA_RD_ADDR_REG register + * Ledc ch0 gamma ram read address register. + */ +#define LEDC_CH0_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH0_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch0 gamma ram read address. + */ +#define LEDC_CH0_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH0_GAMMA_RD_ADDR_M (LEDC_CH0_GAMMA_RD_ADDR_V << LEDC_CH0_GAMMA_RD_ADDR_S) +#define LEDC_CH0_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH0_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH0_GAMMA_RD_DATA_REG register + * Ledc ch0 gamma ram read data register. + */ +#define LEDC_CH0_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH0_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch0 gamma ram read data. + */ +#define LEDC_CH0_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH0_GAMMA_RD_DATA_M (LEDC_CH0_GAMMA_RD_DATA_V << LEDC_CH0_GAMMA_RD_DATA_S) +#define LEDC_CH0_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH0_GAMMA_RD_DATA_S 0 + +/** LEDC_CH1_GAMMA_WR_REG register + * Ledc ch1 gamma ram write register. + */ +#define LEDC_CH1_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH1_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch1 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 1. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH1_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_DUTY_INC_M (LEDC_CH1_GAMMA_DUTY_INC_V << LEDC_CH1_GAMMA_DUTY_INC_S) +#define LEDC_CH1_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH1_GAMMA_DUTY_INC_S 0 +/** LEDC_CH1_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch1 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH1_GAMMA_DUTY_CYCLE on channel 1. + */ +#define LEDC_CH1_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_CYCLE_M (LEDC_CH1_GAMMA_DUTY_CYCLE_V << LEDC_CH1_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH1_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH1_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch1 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 1. + */ +#define LEDC_CH1_GAMMA_SCALE 0x000003FFU +#define LEDC_CH1_GAMMA_SCALE_M (LEDC_CH1_GAMMA_SCALE_V << LEDC_CH1_GAMMA_SCALE_S) +#define LEDC_CH1_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH1_GAMMA_SCALE_S 11 +/** LEDC_CH1_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch1 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH1_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_NUM_M (LEDC_CH1_GAMMA_DUTY_NUM_V << LEDC_CH1_GAMMA_DUTY_NUM_S) +#define LEDC_CH1_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH1_GAMMA_WR_ADDR_REG register + * Ledc ch1 gamma ram write address register. + */ +#define LEDC_CH1_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH1_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch1 gamma ram write address. + */ +#define LEDC_CH1_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH1_GAMMA_WR_ADDR_M (LEDC_CH1_GAMMA_WR_ADDR_V << LEDC_CH1_GAMMA_WR_ADDR_S) +#define LEDC_CH1_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH1_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH1_GAMMA_RD_ADDR_REG register + * Ledc ch1 gamma ram read address register. + */ +#define LEDC_CH1_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x118) +/** LEDC_CH1_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch1 gamma ram read address. + */ +#define LEDC_CH1_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH1_GAMMA_RD_ADDR_M (LEDC_CH1_GAMMA_RD_ADDR_V << LEDC_CH1_GAMMA_RD_ADDR_S) +#define LEDC_CH1_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH1_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH1_GAMMA_RD_DATA_REG register + * Ledc ch1 gamma ram read data register. + */ +#define LEDC_CH1_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x11c) +/** LEDC_CH1_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch1 gamma ram read data. + */ +#define LEDC_CH1_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH1_GAMMA_RD_DATA_M (LEDC_CH1_GAMMA_RD_DATA_V << LEDC_CH1_GAMMA_RD_DATA_S) +#define LEDC_CH1_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH1_GAMMA_RD_DATA_S 0 + +/** LEDC_CH2_GAMMA_WR_REG register + * Ledc ch2 gamma ram write register. + */ +#define LEDC_CH2_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_CH2_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch2 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 2. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH2_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_DUTY_INC_M (LEDC_CH2_GAMMA_DUTY_INC_V << LEDC_CH2_GAMMA_DUTY_INC_S) +#define LEDC_CH2_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH2_GAMMA_DUTY_INC_S 0 +/** LEDC_CH2_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch2 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH2_GAMMA_DUTY_CYCLE on channel 2. + */ +#define LEDC_CH2_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_CYCLE_M (LEDC_CH2_GAMMA_DUTY_CYCLE_V << LEDC_CH2_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH2_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH2_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch2 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 2. + */ +#define LEDC_CH2_GAMMA_SCALE 0x000003FFU +#define LEDC_CH2_GAMMA_SCALE_M (LEDC_CH2_GAMMA_SCALE_V << LEDC_CH2_GAMMA_SCALE_S) +#define LEDC_CH2_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH2_GAMMA_SCALE_S 11 +/** LEDC_CH2_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch2 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH2_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_NUM_M (LEDC_CH2_GAMMA_DUTY_NUM_V << LEDC_CH2_GAMMA_DUTY_NUM_S) +#define LEDC_CH2_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH2_GAMMA_WR_ADDR_REG register + * Ledc ch2 gamma ram write address register. + */ +#define LEDC_CH2_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_CH2_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch2 gamma ram write address. + */ +#define LEDC_CH2_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH2_GAMMA_WR_ADDR_M (LEDC_CH2_GAMMA_WR_ADDR_V << LEDC_CH2_GAMMA_WR_ADDR_S) +#define LEDC_CH2_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH2_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH2_GAMMA_RD_ADDR_REG register + * Ledc ch2 gamma ram read address register. + */ +#define LEDC_CH2_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_CH2_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch2 gamma ram read address. + */ +#define LEDC_CH2_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH2_GAMMA_RD_ADDR_M (LEDC_CH2_GAMMA_RD_ADDR_V << LEDC_CH2_GAMMA_RD_ADDR_S) +#define LEDC_CH2_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH2_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH2_GAMMA_RD_DATA_REG register + * Ledc ch2 gamma ram read data register. + */ +#define LEDC_CH2_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x12c) +/** LEDC_CH2_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch2 gamma ram read data. + */ +#define LEDC_CH2_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH2_GAMMA_RD_DATA_M (LEDC_CH2_GAMMA_RD_DATA_V << LEDC_CH2_GAMMA_RD_DATA_S) +#define LEDC_CH2_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH2_GAMMA_RD_DATA_S 0 + +/** LEDC_CH3_GAMMA_WR_REG register + * Ledc ch3 gamma ram write register. + */ +#define LEDC_CH3_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x130) +/** LEDC_CH3_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch3 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 3. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH3_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_DUTY_INC_M (LEDC_CH3_GAMMA_DUTY_INC_V << LEDC_CH3_GAMMA_DUTY_INC_S) +#define LEDC_CH3_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH3_GAMMA_DUTY_INC_S 0 +/** LEDC_CH3_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch3 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH3_GAMMA_DUTY_CYCLE on channel 3. + */ +#define LEDC_CH3_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_CYCLE_M (LEDC_CH3_GAMMA_DUTY_CYCLE_V << LEDC_CH3_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH3_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH3_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch3 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 3. + */ +#define LEDC_CH3_GAMMA_SCALE 0x000003FFU +#define LEDC_CH3_GAMMA_SCALE_M (LEDC_CH3_GAMMA_SCALE_V << LEDC_CH3_GAMMA_SCALE_S) +#define LEDC_CH3_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH3_GAMMA_SCALE_S 11 +/** LEDC_CH3_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch3 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH3_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_NUM_M (LEDC_CH3_GAMMA_DUTY_NUM_V << LEDC_CH3_GAMMA_DUTY_NUM_S) +#define LEDC_CH3_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH3_GAMMA_WR_ADDR_REG register + * Ledc ch3 gamma ram write address register. + */ +#define LEDC_CH3_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x134) +/** LEDC_CH3_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch3 gamma ram write address. + */ +#define LEDC_CH3_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH3_GAMMA_WR_ADDR_M (LEDC_CH3_GAMMA_WR_ADDR_V << LEDC_CH3_GAMMA_WR_ADDR_S) +#define LEDC_CH3_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH3_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH3_GAMMA_RD_ADDR_REG register + * Ledc ch3 gamma ram read address register. + */ +#define LEDC_CH3_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x138) +/** LEDC_CH3_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch3 gamma ram read address. + */ +#define LEDC_CH3_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH3_GAMMA_RD_ADDR_M (LEDC_CH3_GAMMA_RD_ADDR_V << LEDC_CH3_GAMMA_RD_ADDR_S) +#define LEDC_CH3_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH3_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH3_GAMMA_RD_DATA_REG register + * Ledc ch3 gamma ram read data register. + */ +#define LEDC_CH3_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x13c) +/** LEDC_CH3_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch3 gamma ram read data. + */ +#define LEDC_CH3_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH3_GAMMA_RD_DATA_M (LEDC_CH3_GAMMA_RD_DATA_V << LEDC_CH3_GAMMA_RD_DATA_S) +#define LEDC_CH3_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH3_GAMMA_RD_DATA_S 0 + +/** LEDC_CH4_GAMMA_WR_REG register + * Ledc ch4 gamma ram write register. + */ +#define LEDC_CH4_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_CH4_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch4 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 4. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH4_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_DUTY_INC_M (LEDC_CH4_GAMMA_DUTY_INC_V << LEDC_CH4_GAMMA_DUTY_INC_S) +#define LEDC_CH4_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH4_GAMMA_DUTY_INC_S 0 +/** LEDC_CH4_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch4 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH4_GAMMA_DUTY_CYCLE on channel 4. + */ +#define LEDC_CH4_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_CYCLE_M (LEDC_CH4_GAMMA_DUTY_CYCLE_V << LEDC_CH4_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH4_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH4_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch4 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 4. + */ +#define LEDC_CH4_GAMMA_SCALE 0x000003FFU +#define LEDC_CH4_GAMMA_SCALE_M (LEDC_CH4_GAMMA_SCALE_V << LEDC_CH4_GAMMA_SCALE_S) +#define LEDC_CH4_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH4_GAMMA_SCALE_S 11 +/** LEDC_CH4_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch4 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH4_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_NUM_M (LEDC_CH4_GAMMA_DUTY_NUM_V << LEDC_CH4_GAMMA_DUTY_NUM_S) +#define LEDC_CH4_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH4_GAMMA_WR_ADDR_REG register + * Ledc ch4 gamma ram write address register. + */ +#define LEDC_CH4_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_CH4_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch4 gamma ram write address. + */ +#define LEDC_CH4_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH4_GAMMA_WR_ADDR_M (LEDC_CH4_GAMMA_WR_ADDR_V << LEDC_CH4_GAMMA_WR_ADDR_S) +#define LEDC_CH4_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH4_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH4_GAMMA_RD_ADDR_REG register + * Ledc ch4 gamma ram read address register. + */ +#define LEDC_CH4_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_CH4_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch4 gamma ram read address. + */ +#define LEDC_CH4_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH4_GAMMA_RD_ADDR_M (LEDC_CH4_GAMMA_RD_ADDR_V << LEDC_CH4_GAMMA_RD_ADDR_S) +#define LEDC_CH4_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH4_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH4_GAMMA_RD_DATA_REG register + * Ledc ch4 gamma ram read data register. + */ +#define LEDC_CH4_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_CH4_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch4 gamma ram read data. + */ +#define LEDC_CH4_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH4_GAMMA_RD_DATA_M (LEDC_CH4_GAMMA_RD_DATA_V << LEDC_CH4_GAMMA_RD_DATA_S) +#define LEDC_CH4_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH4_GAMMA_RD_DATA_S 0 + +/** LEDC_CH5_GAMMA_WR_REG register + * Ledc ch5 gamma ram write register. + */ +#define LEDC_CH5_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_CH5_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch5 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 5. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH5_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_DUTY_INC_M (LEDC_CH5_GAMMA_DUTY_INC_V << LEDC_CH5_GAMMA_DUTY_INC_S) +#define LEDC_CH5_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH5_GAMMA_DUTY_INC_S 0 +/** LEDC_CH5_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch5 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH5_GAMMA_DUTY_CYCLE on channel 5. + */ +#define LEDC_CH5_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_CYCLE_M (LEDC_CH5_GAMMA_DUTY_CYCLE_V << LEDC_CH5_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH5_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH5_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch5 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 5. + */ +#define LEDC_CH5_GAMMA_SCALE 0x000003FFU +#define LEDC_CH5_GAMMA_SCALE_M (LEDC_CH5_GAMMA_SCALE_V << LEDC_CH5_GAMMA_SCALE_S) +#define LEDC_CH5_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH5_GAMMA_SCALE_S 11 +/** LEDC_CH5_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch5 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH5_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_NUM_M (LEDC_CH5_GAMMA_DUTY_NUM_V << LEDC_CH5_GAMMA_DUTY_NUM_S) +#define LEDC_CH5_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH5_GAMMA_WR_ADDR_REG register + * Ledc ch5 gamma ram write address register. + */ +#define LEDC_CH5_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_CH5_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch5 gamma ram write address. + */ +#define LEDC_CH5_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH5_GAMMA_WR_ADDR_M (LEDC_CH5_GAMMA_WR_ADDR_V << LEDC_CH5_GAMMA_WR_ADDR_S) +#define LEDC_CH5_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH5_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH5_GAMMA_RD_ADDR_REG register + * Ledc ch5 gamma ram read address register. + */ +#define LEDC_CH5_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_CH5_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch5 gamma ram read address. + */ +#define LEDC_CH5_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH5_GAMMA_RD_ADDR_M (LEDC_CH5_GAMMA_RD_ADDR_V << LEDC_CH5_GAMMA_RD_ADDR_S) +#define LEDC_CH5_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH5_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH5_GAMMA_RD_DATA_REG register + * Ledc ch5 gamma ram read data register. + */ +#define LEDC_CH5_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_CH5_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch5 gamma ram read data. + */ +#define LEDC_CH5_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH5_GAMMA_RD_DATA_M (LEDC_CH5_GAMMA_RD_DATA_V << LEDC_CH5_GAMMA_RD_DATA_S) +#define LEDC_CH5_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH5_GAMMA_RD_DATA_S 0 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x180) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch0 gamma entry num. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch0 gamma pause, write 1 to pause. + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch0 gamma resume, write 1 to resume. + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x184) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch1 gamma entry num. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch1 gamma pause, write 1 to pause. + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch1 gamma resume, write 1 to resume. + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x188) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch2 gamma entry num. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch2 gamma pause, write 1 to pause. + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch2 gamma resume, write 1 to resume. + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x18c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch3 gamma entry num. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch3 gamma pause, write 1 to pause. + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch3 gamma resume, write 1 to resume. + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x190) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch4 gamma entry num. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch4 gamma pause, write 1 to pause. + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch4 gamma resume, write 1 to resume. + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x194) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch5 gamma entry num. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch5 gamma pause, write 1 to pause. + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch5 gamma resume, write 1 to resume. + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x1a0) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Ledc ch0 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Ledc ch1 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Ledc ch2 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Ledc ch3 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Ledc ch4 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Ledc ch5 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Ledc timer0 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Ledc timer1 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Ledc timer2 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Ledc timer3 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Ledc timer0 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Ledc timer1 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Ledc timer2 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Ledc timer3 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Ledc ch0 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Ledc ch1 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Ledc ch2 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Ledc ch3 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Ledc ch4 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Ledc ch5 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x1a4) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Ledc timer0 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Ledc timer1 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Ledc timer2 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Ledc timer3 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Ledc timer0 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Ledc timer1 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Ledc timer2 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Ledc timer3 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Ledc ch0 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Ledc ch1 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Ledc ch2 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Ledc ch3 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Ledc ch4 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Ledc ch5 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Ledc timer0 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Ledc timer1 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Ledc timer2 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Ledc timer3 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Ledc timer0 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Ledc timer1 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Ledc timer2 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Ledc timer3 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x1a8) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Ledc ch0 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Ledc ch1 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Ledc ch2 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Ledc ch3 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Ledc ch4 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Ledc ch5 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Ledc ch0 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Ledc ch1 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Ledc ch2 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Ledc ch3 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Ledc ch4 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Ledc ch5 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Ledc ch0 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Ledc ch1 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Ledc ch2 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Ledc ch3 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Ledc ch4 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Ledc ch5 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x1b0) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer0 compare value. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x1b4) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer1 compare value. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x1b8) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer2 compare value. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x1bc) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer3 compare value. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 count value capture register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1c0) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 count value capture register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1c4) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 count value capture register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1c8) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 count value capture register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1cc) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * Global ledc configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x1f0) +/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * This bit is used to select clock source for the 4 timers . + * + * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + */ +#define LEDC_APB_CLK_SEL 0x00000003U +#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) +#define LEDC_APB_CLK_SEL_V 0x00000003U +#define LEDC_APB_CLK_SEL_S 0 +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x1fc) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 34672976; + * This is the version control register. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/ledc_struct.h b/components/soc/esp32h2/include/soc/ledc_struct.h new file mode 100644 index 0000000000..872315558e --- /dev/null +++ b/components/soc/esp32h2/include/soc/ledc_struct.h @@ -0,0 +1,1119 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel n. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ + uint32_t timer_sel:2; + /** sig_out_en : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel n. + */ + uint32_t sig_out_en:1; + /** idle_lv : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel n is inactive (when + * LEDC_SIG_OUT_EN_CHn is 0). + */ + uint32_t idle_lv:1; + /** para_up : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, + * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel + * n, and will be automatically cleared by hardware. + */ + uint32_t para_up:1; + /** ovf_num : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for + * (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num:10; + /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel n. + */ + uint32_t ovf_cnt_en:1; + /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel n. + */ + uint32_t ovf_cnt_reset:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CHn_CONF1_REG will start to take effect when this + * bit is set to 1. + */ + uint32_t duty_start:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Ledc ch0 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Ledc ch1 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Ledc ch2 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Ledc ch3 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Ledc ch4 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Ledc ch5 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch5_en:1; + uint32_t reserved_6:2; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + uint32_t reserved_14:2; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Ledc timer0 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Ledc timer1 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Ledc timer2 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Ledc timer3 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Ledc timer0 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Ledc timer1 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Ledc timer2 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Ledc timer3 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Ledc ch0 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Ledc ch1 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Ledc ch2 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Ledc ch3 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Ledc ch4 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Ledc ch5 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch5_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Ledc timer0 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Ledc timer1 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Ledc timer2 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Ledc timer3 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Ledc timer0 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Ledc timer1 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Ledc timer2 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Ledc timer3 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Ledc ch0 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Ledc ch1 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Ledc ch2 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Ledc ch3 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Ledc ch4 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Ledc ch5 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch5_en:1; + uint32_t reserved_14:2; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + uint32_t reserved_22:2; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Ledc timer0 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Ledc timer1 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Ledc timer2 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Ledc timer3 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Ledc timer0 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Ledc timer1 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Ledc timer2 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Ledc timer3 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Ledc ch0 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Ledc ch1 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Ledc ch2 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Ledc ch3 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Ledc ch4 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Ledc ch5 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch5_en:1; + uint32_t reserved_6:2; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Ledc ch0 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Ledc ch1 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Ledc ch2 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Ledc ch3 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Ledc ch4 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Ledc ch5 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch5_en:1; + uint32_t reserved_14:2; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Ledc ch0 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Ledc ch1 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Ledc ch2 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Ledc ch3 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Ledc ch4 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Ledc ch5 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch5_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** cmp : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timern compare value. + */ + uint32_t cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern count value capture register. + */ +typedef union { + struct { + /** cnt_cap : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timern count value. + */ + uint32_t cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + +/** Type of conf register + * Global ledc configuration register + */ +typedef union { + struct { + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * This bit is used to select clock source for the 4 timers . + * + * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + */ + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch5:1; + uint32_t reserved_8:23; + /** clk_en : R/W; bitpos: [31]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Hpoint Register */ +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ + uint32_t hpoint:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + + +/** Group: Duty Cycle Register */ +/** Type of chn_duty register + * Initial duty cycle for channel n + */ +typedef union { + struct { + /** duty : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ + uint32_t duty:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_duty_r register + * Current duty cycle for channel n + */ +typedef union { + struct { + /** duty_r : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel n. + */ + uint32_t duty_r:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + + +/** Group: Timer Register */ +/** Type of timern_conf register + * Timer n configuration + */ +typedef union { + struct { + /** duty_res : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer n. + */ + uint32_t duty_res:5; + /** clk_div : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer n. + * + * The least significant eight bits represent the fractional part. + */ + uint32_t clk_div:18; + /** pause : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer n. + */ + uint32_t pause:1; + /** rst : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer n. The counter will show 0 after reset. + */ + uint32_t rst:1; + /** tick_sel : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer n. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + uint32_t tick_sel:1; + /** para_up : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. + */ + uint32_t para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timerx_conf_reg_t; + +/** Type of timern_value register + * Timer n current counter value + */ +typedef union { + struct { + /** timer_cnt : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer n. + */ + uint32_t timer_cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timerx_value_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Triggered when the timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Triggered when the timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Triggered when the timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Triggered when the timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when + * LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when + * LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when + * LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when + * LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT + * interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT + * interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT + * interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT + * interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT + * interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT + * interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when + * LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when + * LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when + * LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when + * LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when + * LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when + * LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: Gamma RAM Register */ +/** Type of chn_gamma_wr register + * Ledc chn gamma ram write register. + */ +typedef union { + struct { + /** gamma_duty_inc : R/W; bitpos: [0]; default: 0; + * Ledc chn gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel n. + * + * 1: Increase 0: Decrease. + */ + uint32_t gamma_duty_inc:1; + /** gamma_duty_cycle : R/W; bitpos: [10:1]; default: 0; + * Ledc chn gamma duty cycle of current ram write address.The duty will change every + * LEDC_CHn_GAMMA_DUTY_CYCLE on channel n. + */ + uint32_t gamma_duty_cycle:10; + /** gamma_scale : R/W; bitpos: [20:11]; default: 0; + * Ledc chn gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel n. + */ + uint32_t gamma_scale:10; + /** gamma_duty_num : R/W; bitpos: [30:21]; default: 0; + * Ledc chn gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ + uint32_t gamma_duty_num:10; + uint32_t reserved_31:1; + }; + uint32_t val; +} ledc_chn_gamma_wr_reg_t; + +/** Type of chn_gamma_wr_addr register + * Ledc chn gamma ram write address register. + */ +typedef union { + struct { + /** gamma_wr_addr : R/W; bitpos: [3:0]; default: 0; + * Ledc chn gamma ram write address. + */ + uint32_t gamma_wr_addr:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ledc_chn_gamma_wr_addr_reg_t; + +/** Type of chn_gamma_rd_addr register + * Ledc chn gamma ram read address register. + */ +typedef union { + struct { + /** gamma_rd_addr : R/W; bitpos: [3:0]; default: 0; + * Ledc chn gamma ram read address. + */ + uint32_t gamma_rd_addr:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ledc_chn_gamma_rd_addr_reg_t; + +/** Type of chn_gamma_rd_data register + * Ledc chn gamma ram read data register. + */ +typedef union { + struct { + /** gamma_rd_data : RO; bitpos: [30:0]; default: 0; + * Ledc chn gamma ram read data. + */ + uint32_t gamma_rd_data:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} ledc_chn_gamma_rd_data_reg_t; + + +/** Group: Gamma Config Register */ +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Ledc chn gamma entry num. + */ + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; + * Ledc chn gamma pause, write 1 to pause. + */ + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; + * Ledc chn gamma resume, write 1 to resume. + */ + uint32_t gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 34672976; + * This is the version control register. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + +typedef struct { + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_rd; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[6]; +} ledc_ch_group_reg_t; + +typedef struct { + volatile ledc_timerx_conf_reg_t conf; + volatile ledc_timerx_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_timerx_reg_t timer[4]; +} ledc_timer_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_wr_reg_t wr; + volatile ledc_chn_gamma_wr_addr_reg_t wr_addr; + volatile ledc_chn_gamma_rd_addr_reg_t rd_addr; + volatile ledc_chn_gamma_rd_data_reg_t rd_data; +} ledc_chn_gamma_reg_t; + +typedef struct { + volatile ledc_chn_gamma_reg_t channel[6]; +} ledc_ch_gamma_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_conf_reg_t gamma_conf[6]; +} ledc_ch_gamma_conf_group_reg_t; + +typedef struct { + volatile ledc_timern_cmp_reg_t cmp[4]; +} ledc_timer_cmp_group_reg_t; + +typedef struct { + volatile ledc_timern_cnt_cap_reg_t cnt_cap[4]; +} ledc_timer_cnt_cap_group_reg_t; + +typedef struct ledc_dev_t { + volatile ledc_ch_group_reg_t channel_group[1]; + uint32_t reserved_078[10]; + volatile ledc_timer_group_reg_t timer_group[1]; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_ch_gamma_group_reg_t channel_gamma_group[1]; + uint32_t reserved_160[8]; + volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1]; + uint32_t reserved_198[2]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_1ac; + volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1]; + volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1]; + uint32_t reserved_1d0[8]; + volatile ledc_conf_reg_t conf; + uint32_t reserved_1f4[2]; + volatile ledc_date_reg_t date; +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x200, "Invalid size of ledc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h b/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h new file mode 100644 index 0000000000..d44ae667ae --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h @@ -0,0 +1,469 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x0) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x4) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_VDD_SOURCE_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDD_SOURCE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8) +/** LP_ANALOG_PERI_LP_ANA_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_DETMODE_SEL 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_DETMODE_SEL_M (LP_ANALOG_PERI_LP_ANA_DETMODE_SEL_V << LP_ANALOG_PERI_LP_ANA_DETMODE_SEL_S) +#define LP_ANALOG_PERI_LP_ANA_DETMODE_SEL_V 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_DETMODE_SEL_S 0 +/** LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD_M (LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD_V << LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD_S) +#define LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD_V 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_VGOOD_EVENT_RECORD_S 8 +/** LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR_M (LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR_V << LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR_V 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_VBAT_EVENT_RECORD_CLR_S 16 +/** LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA_V 0x000000FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_SOURCE_ENA_S 24 + +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_BOD_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_BOD_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xc) +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER (BIT(10)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGER_S 10 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR (BIT(11)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CNT_CLR_S 11 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S 12 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10) +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER (BIT(10)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CHARGER_S 10 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR (BIT(11)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_CNT_CLR_S 11 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S 12 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14) +/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_PG_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_PG_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18) +/** LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_POWER_GLITCH_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c) +/** LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_M (LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_V << LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0 + +#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) + +/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x20) +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW (BIT(27)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S 27 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW (BIT(28)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S 28 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW (BIT(29)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S 29 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW (BIT(30)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S 30 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANALOG_PERI_LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x24) +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST (BIT(27)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S 27 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST (BIT(28)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S 28 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST (BIT(29)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S 29 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST (BIT(30)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S 30 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANALOG_PERI_LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x28) +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA (BIT(27)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S 27 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA (BIT(28)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S 28 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA (BIT(29)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S 29 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA (BIT(30)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S 30 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x2c) +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR (BIT(27)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S 27 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR (BIT(28)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S 28 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR (BIT(29)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S 29 +/** LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR (BIT(30)) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S 30 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x30) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x34) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x38) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3c) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANALOG_PERI_LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc) +/** LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35684944; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_M (LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_V << LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_S) +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_S 0 +/** LP_ANALOG_PERI_LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_CLK_EN (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_CLK_EN_M (LP_ANALOG_PERI_LP_ANA_CLK_EN_V << LP_ANALOG_PERI_LP_ANA_CLK_EN_S) +#define LP_ANALOG_PERI_LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_struct.h b/components/soc/esp32h2/include/soc/lp_analog_peri_struct.h new file mode 100644 index 0000000000..b150e51d60 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_analog_peri_struct.h @@ -0,0 +1,419 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of vdd_source_cntl register + * need_des + */ +typedef union { + struct { + /** detmode_sel : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t detmode_sel:8; + /** vgood_event_record : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t vgood_event_record:8; + /** vbat_event_record_clr : WT; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t vbat_event_record_clr:8; + /** bod_source_ena : R/W; bitpos: [31:24]; default: 4; + * need_des + */ + uint32_t bod_source_ena:8; + }; + uint32_t val; +} lp_ana_vdd_source_cntl_reg_t; + +/** Type of vddbat_bod_cntl register + * need_des + */ +typedef union { + struct { + /** vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_flag:1; + uint32_t reserved_1:9; + /** vddbat_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t vddbat_charger:1; + /** vddbat_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t vddbat_cnt_clr:1; + /** vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_target:10; + /** vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t vddbat_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_bod_cntl_reg_t; + +/** Type of vddbat_charge_cntl register + * need_des + */ +typedef union { + struct { + /** vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_flag:1; + uint32_t reserved_1:9; + /** vddbat_charge_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t vddbat_charge_charger:1; + /** vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t vddbat_charge_cnt_clr:1; + /** vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_target:10; + /** vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t vddbat_charge_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_charge_cntl_reg_t; + +/** Type of ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of pg_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** power_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t power_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_pg_glitch_cntl_reg_t; + +/** Type of fib_enable register + * need_des + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_raw:1; + /** vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_raw:1; + /** vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_raw:1; + /** vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_raw:1; + /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_st:1; + /** vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_st:1; + /** vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_st:1; + /** vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_st:1; + /** bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_ena:1; + /** vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_ena:1; + /** vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_ena:1; + /** vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_ena:1; + /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_clr:1; + /** vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_clr:1; + /** vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_clr:1; + /** vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_clr:1; + /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_ana_date : R/W; bitpos: [30:0]; default: 35684944; + * need_des + */ + uint32_t lp_ana_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_ana_vdd_source_cntl_reg_t vdd_source_cntl; + volatile lp_ana_vddbat_bod_cntl_reg_t vddbat_bod_cntl; + volatile lp_ana_vddbat_charge_cntl_reg_t vddbat_charge_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl; + volatile lp_ana_pg_glitch_cntl_reg_t pg_glitch_cntl; + volatile lp_ana_fib_enable_reg_t fib_enable; + volatile lp_ana_int_raw_reg_t int_raw; + volatile lp_ana_int_st_reg_t int_st; + volatile lp_ana_int_ena_reg_t int_ena; + volatile lp_ana_int_clr_reg_t int_clr; + volatile lp_ana_lp_int_raw_reg_t lp_int_raw; + volatile lp_ana_lp_int_st_reg_t lp_int_st; + volatile lp_ana_lp_int_ena_reg_t lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_040[239]; + volatile lp_ana_date_reg_t date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_aon_reg.h b/components/soc/esp32h2/include/soc/lp_aon_reg.h new file mode 100644 index 0000000000..13a82b3f88 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_aon_reg.h @@ -0,0 +1,471 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_ANA_FIB_SWD_ENABLE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_SWD_ENABLE (BIT(0)) +#define LP_AON_ANA_FIB_SWD_ENABLE_M (LP_AON_ANA_FIB_SWD_ENABLE_V << LP_AON_ANA_FIB_SWD_ENABLE_S) +#define LP_AON_ANA_FIB_SWD_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_SWD_ENABLE_S 0 +/** LP_AON_ANA_FIB_CK_GLITCH_ENABLE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE (BIT(1)) +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_M (LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V << LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S) +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S 1 +/** LP_AON_ANA_FIB_BOD_ENABLE : RO; bitpos: [2]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_BOD_ENABLE (BIT(2)) +#define LP_AON_ANA_FIB_BOD_ENABLE_M (LP_AON_ANA_FIB_BOD_ENABLE_V << LP_AON_ANA_FIB_BOD_ENABLE_S) +#define LP_AON_ANA_FIB_BOD_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_BOD_ENABLE_S 2 +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_PULL_LDO 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_M (LP_AON_IO_MUX_PULL_LDO_V << LP_AON_IO_MUX_PULL_LDO_S) +#define LP_AON_IO_MUX_PULL_LDO_V 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_S 28 +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_LPBUS_REG register + * need_des + */ +#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) +/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; + * This field controls fast memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V + * operating Voltage. + */ +#define LP_AON_FAST_MEM_WPULSE 0x00000007U +#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) +#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U +#define LP_AON_FAST_MEM_WPULSE_S 16 +/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 5; + * This field controls fast memory WA parameter. 0b100 for 1.1V operating Voltage, + * 0b101 for 1.0V, 0b110 for 0.9V. + */ +#define LP_AON_FAST_MEM_WA 0x00000007U +#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) +#define LP_AON_FAST_MEM_WA_V 0x00000007U +#define LP_AON_FAST_MEM_WA_S 19 +/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; + * This field controls fast memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, + * 0b01 for 0.9V. + */ +#define LP_AON_FAST_MEM_RA 0x00000003U +#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) +#define LP_AON_FAST_MEM_RA_V 0x00000003U +#define LP_AON_FAST_MEM_RA_S 22 +/** LP_AON_FAST_MEM_RM : R/W; bitpos: [27:24]; default: 2; + * This field controls fast memory RM parameter. 0b0011 for 1.1V operating Voltage, + * 0b0010 for 1.0V, 0b0000 for 0.9V. + */ +#define LP_AON_FAST_MEM_RM 0x0000000FU +#define LP_AON_FAST_MEM_RM_M (LP_AON_FAST_MEM_RM_V << LP_AON_FAST_MEM_RM_S) +#define LP_AON_FAST_MEM_RM_V 0x0000000FU +#define LP_AON_FAST_MEM_RM_S 24 +/** LP_AON_FAST_MEM_MUX_FSM_IDLE : HRO; bitpos: [28]; default: 0; + * reserved + */ +#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 +/** LP_AON_FAST_MEM_MUX_SEL_STATUS : HRO; bitpos: [29]; default: 0; + * reserved + */ +#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 +/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : HRO; bitpos: [30]; default: 0; + * reserved + */ +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 +/** LP_AON_FAST_MEM_MUX_SEL : HRO; bitpos: [31]; default: 0; + * reserved + */ +#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) +#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) +#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_S 31 + +/** LP_AON_SDIO_ACTIVE_REG register + * need_des + */ +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des + */ +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_JTAG_SEL_REG register + * need_des + */ +#define LP_AON_JTAG_SEL_REG (DR_REG_LP_AON_BASE + 0x58) +/** LP_AON_JTAG_SEL_SOFT : R/W; bitpos: [31]; default: 1; + * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or + * usb_jtag is disabled by efuse, this field determines which one jtag between + * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + */ +#define LP_AON_JTAG_SEL_SOFT (BIT(31)) +#define LP_AON_JTAG_SEL_SOFT_M (LP_AON_JTAG_SEL_SOFT_V << LP_AON_JTAG_SEL_SOFT_S) +#define LP_AON_JTAG_SEL_SOFT_V 0x00000001U +#define LP_AON_JTAG_SEL_SOFT_S 31 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35717264; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_aon_struct.h b/components/soc/esp32h2/include/soc/lp_aon_struct.h new file mode 100644 index 0000000000..f68ed231cf --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_aon_struct.h @@ -0,0 +1,346 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of store register + * need_des + */ +typedef union { + struct { + /** store : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t store:32; + }; + uint32_t val; +} lp_aon_store_reg_t; + +/** Type of gpio_mux register + * need_des + */ +typedef union { + struct { + /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of sys_cfg register + * need_des + */ +typedef union { + struct { + /** ana_fib_swd_enable : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t ana_fib_swd_enable:1; + /** ana_fib_ck_glitch_enable : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t ana_fib_ck_glitch_enable:1; + /** ana_fib_bod_enable : RO; bitpos: [2]; default: 1; + * need_des + */ + uint32_t ana_fib_bod_enable:1; + uint32_t reserved_3:27; + /** force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t force_download_boot:1; + /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_reset:1; + /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t cpu_core0_ocd_halt_on_reset:1; + /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t cpu_core0_stat_vector_sel:1; + /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t io_mux_pull_ldo:3; + /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status:8; + uint32_t reserved_8:6; + /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status_clr:1; + /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t ext_wakeup_sel:8; + /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t ext_wakeup_lv:8; + /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of lpbus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0; + * This field controls fast memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V + * operating Voltage. + */ + uint32_t fast_mem_wpulse:3; + /** fast_mem_wa : R/W; bitpos: [21:19]; default: 5; + * This field controls fast memory WA parameter. 0b100 for 1.1V operating Voltage, + * 0b101 for 1.0V, 0b110 for 0.9V. + */ + uint32_t fast_mem_wa:3; + /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0; + * This field controls fast memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, + * 0b01 for 0.9V. + */ + uint32_t fast_mem_ra:2; + /** fast_mem_rm : R/W; bitpos: [27:24]; default: 2; + * This field controls fast memory RM parameter. 0b0011 for 1.1V operating Voltage, + * 0b0010 for 1.0V, 0b0000 for 0.9V. + */ + uint32_t fast_mem_rm:4; + /** fast_mem_mux_fsm_idle : HRO; bitpos: [28]; default: 0; + * reserved + */ + uint32_t fast_mem_mux_fsm_idle:1; + /** fast_mem_mux_sel_status : HRO; bitpos: [29]; default: 0; + * reserved + */ + uint32_t fast_mem_mux_sel_status:1; + /** fast_mem_mux_sel_update : HRO; bitpos: [30]; default: 0; + * reserved + */ + uint32_t fast_mem_mux_sel_update:1; + /** fast_mem_mux_sel : HRO; bitpos: [31]; default: 0; + * reserved + */ + uint32_t fast_mem_mux_sel:1; + }; + uint32_t val; +} lp_aon_lpbus_reg_t; + +/** Type of sdio_active register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des + */ + uint32_t sdio_act_dnum:10; + }; + uint32_t val; +} lp_aon_sdio_active_reg_t; + +/** Type of lpcore register + * need_des + */ +typedef union { + struct { + /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag_clr:1; + /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of jtag_sel register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** jtag_sel_soft : R/W; bitpos: [31]; default: 1; + * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or + * usb_jtag is disabled by efuse, this field determines which one jtag between + * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + */ + uint32_t jtag_sel_soft:1; + }; + uint32_t val; +} lp_aon_jtag_sel_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 35717264; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +typedef struct { + volatile lp_aon_store_reg_t store[10]; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + volatile lp_aon_lpbus_reg_t lpbus; + volatile lp_aon_sdio_active_reg_t sdio_active; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + volatile lp_aon_jtag_sel_reg_t jtag_sel; + uint32_t reserved_05c[232]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_apm0_reg.h b/components/soc/esp32h2/include/soc/lp_apm0_reg.h new file mode 100644 index 0000000000..05612739a5 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_apm0_reg.h @@ -0,0 +1,506 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM0_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) +#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_S 0 + +/** LP_APM0_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) +/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) +#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_S 0 + +/** LP_APM0_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) +/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) +#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_S 0 + +/** LP_APM0_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) +/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) +#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_X_S 0 +/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) +#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_W_S 1 +/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) +#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_R_S 2 +/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) +#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_X_S 4 +/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) +#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_W_S 5 +/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) +#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_R_S 6 +/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) +#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_X_S 8 +/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) +#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_W_S 9 +/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) +#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_R_S 10 + +/** LP_APM0_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) +/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) +#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_S 0 + +/** LP_APM0_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) +/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) +#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_S 0 + +/** LP_APM0_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) +/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) +#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_X_S 0 +/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) +#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_W_S 1 +/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) +#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_R_S 2 +/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) +#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_X_S 4 +/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) +#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_W_S 5 +/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) +#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_R_S 6 +/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) +#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_X_S 8 +/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) +#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_W_S 9 +/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) +#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_R_S 10 + +/** LP_APM0_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) +/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) +#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_S 0 + +/** LP_APM0_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) +/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) +#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_S 0 + +/** LP_APM0_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) +/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) +#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_X_S 0 +/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) +#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_W_S 1 +/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) +#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_R_S 2 +/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) +#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_X_S 4 +/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) +#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_W_S 5 +/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) +#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_R_S 6 +/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) +#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_X_S 8 +/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) +#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_W_S 9 +/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) +#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_R_S 10 + +/** LP_APM0_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) +/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) +#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_S 0 + +/** LP_APM0_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) +/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) +#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_S 0 + +/** LP_APM0_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) +/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) +#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_X_S 0 +/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) +#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_W_S 1 +/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) +#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_R_S 2 +/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) +#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_X_S 4 +/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) +#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_W_S 5 +/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) +#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_R_S 6 +/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) +#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_X_S 8 +/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) +#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_W_S 9 +/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) +#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_R_S 10 + +/** LP_APM0_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) +/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) +#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM0_M0_PMS_FUNC_EN_S 0 + +/** LP_APM0_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) +/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) +#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM0_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) +/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) +#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM0_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM0_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) +#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_S 0 +/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) +#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_S 16 +/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) +#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_S 18 + +/** LP_APM0_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) +/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) +#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM0_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) +/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM0_M0_APM_INT_EN (BIT(0)) +#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) +#define LP_APM0_M0_APM_INT_EN_V 0x00000001U +#define LP_APM0_M0_APM_INT_EN_S 0 + +/** LP_APM0_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) +/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM0_CLK_EN (BIT(0)) +#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) +#define LP_APM0_CLK_EN_V 0x00000001U +#define LP_APM0_CLK_EN_S 0 + +/** LP_APM0_DATE_REG register + * Version register + */ +#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) +/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define LP_APM0_DATE 0x0FFFFFFFU +#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) +#define LP_APM0_DATE_V 0x0FFFFFFFU +#define LP_APM0_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_apm0_struct.h b/components/soc/esp32h2/include/soc/lp_apm0_struct.h new file mode 100644 index 0000000000..7a2cf7247f --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_apm0_struct.h @@ -0,0 +1,499 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm0_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm0_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm0_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm0_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm0_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm0_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm0_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm0_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm0_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm0_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm0_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm0_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm0_date_reg_t; + + +typedef struct { + volatile lp_apm0_region_filter_en_reg_t region_filter_en; + volatile lp_apm0_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm0_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm0_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm0_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm0_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm0_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm0_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm0_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm0_func_ctrl_reg_t func_ctrl; + volatile lp_apm0_m0_status_reg_t m0_status; + volatile lp_apm0_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm0_int_en_reg_t int_en; + volatile lp_apm0_clock_gate_reg_t clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm0_date_reg_t date; +} lp_apm0_dev_t; + +extern lp_apm0_dev_t LP_APM0; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_apm_reg.h b/components/soc/esp32h2/include/soc/lp_apm_reg.h new file mode 100644 index 0000000000..54bcc784d3 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_apm_reg.h @@ -0,0 +1,322 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [1:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x00000003U +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x00000003U +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [1:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x00000003U +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x00000003U +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35680864; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_apm_struct.h b/components/soc/esp32h2/include/soc/lp_apm_struct.h new file mode 100644 index 0000000000..ef463eff87 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_apm_struct.h @@ -0,0 +1,346 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [1:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [1:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:2; + uint32_t reserved_2:14; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35680864; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct { + volatile lp_apm_region_filter_en_reg_t region_filter_en; + volatile lp_apm_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr; + uint32_t reserved_01c[42]; + volatile lp_apm_func_ctrl_reg_t func_ctrl; + volatile lp_apm_m0_status_reg_t m0_status; + volatile lp_apm_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; + uint32_t reserved_0d8[4]; + volatile lp_apm_int_en_reg_t int_en; + volatile lp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_clkrst_reg.h b/components/soc/esp32h2/include/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..31d57ba97a --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_clkrst_reg.h @@ -0,0 +1,424 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * need_des + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * need_des + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * need_des + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 600; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 650; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_LP_BLETIMER_DIV_NUM : R/W; bitpos: [23:12]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_DIV_NUM 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_M (LP_CLKRST_LP_BLETIMER_DIV_NUM_V << LP_CLKRST_LP_BLETIMER_DIV_NUM_S) +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_V 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_S 12 +/** LP_CLKRST_LP_BLETIMER_32K_SEL : R/W; bitpos: [25:24]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_32K_SEL 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_M (LP_CLKRST_LP_BLETIMER_32K_SEL_V << LP_CLKRST_LP_BLETIMER_32K_SEL_S) +#define LP_CLKRST_LP_BLETIMER_32K_SEL_V 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_S 24 +/** LP_CLKRST_LP_SEL_OSC_SLOW : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_SLOW (BIT(26)) +#define LP_CLKRST_LP_SEL_OSC_SLOW_M (LP_CLKRST_LP_SEL_OSC_SLOW_V << LP_CLKRST_LP_SEL_OSC_SLOW_S) +#define LP_CLKRST_LP_SEL_OSC_SLOW_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_SLOW_S 26 +/** LP_CLKRST_LP_SEL_OSC_FAST : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_FAST (BIT(27)) +#define LP_CLKRST_LP_SEL_OSC_FAST_M (LP_CLKRST_LP_SEL_OSC_FAST_V << LP_CLKRST_LP_SEL_OSC_FAST_S) +#define LP_CLKRST_LP_SEL_OSC_FAST_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_FAST_S 27 +/** LP_CLKRST_LP_SEL_XTAL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL (BIT(28)) +#define LP_CLKRST_LP_SEL_XTAL_M (LP_CLKRST_LP_SEL_XTAL_V << LP_CLKRST_LP_SEL_XTAL_S) +#define LP_CLKRST_LP_SEL_XTAL_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL_S 28 +/** LP_CLKRST_LP_SEL_XTAL32K : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL32K (BIT(29)) +#define LP_CLKRST_LP_SEL_XTAL32K_M (LP_CLKRST_LP_SEL_XTAL32K_V << LP_CLKRST_LP_SEL_XTAL32K_S) +#define LP_CLKRST_LP_SEL_XTAL32K_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL32K_S 29 +/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) +#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) +#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 +/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) +#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) +#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_UART_CLK_SEL_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35680896; + * need_des + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_clkrst_struct.h b/components/soc/esp32h2/include/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..1fd563fd2b --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_clkrst_struct.h @@ -0,0 +1,365 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * need_des + */ + uint32_t fast_clk_sel:2; + /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; + * need_des + */ + uint32_t lp_peri_div_num:8; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t aon_slow_oen:1; + /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t aon_fast_oen:1; + /** sosc_oen : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t sosc_oen:1; + /** fosc_oen : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t fosc_oen:1; + /** osc32k_oen : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t osc32k_oen:1; + /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t xtal32k_oen:1; + /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t core_efuse_oen:1; + /** slow_oen : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t slow_oen:1; + /** fast_oen : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t fast_oen:1; + /** rng_oen : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t rng_oen:1; + /** lpbus_oen : R/W; bitpos: [10]; default: 1; + * need_des + */ + uint32_t lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t aon_efuse_core_reset_en:1; + /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_timer_reset_en:1; + /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_reset_en:1; + /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of reset_cause register + * need_des + */ +typedef union { + struct { + /** reset_cause : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t reset_cause:5; + /** core0_reset_flag : RO; bitpos: [5]; default: 1; + * need_des + */ + uint32_t core0_reset_flag:1; + uint32_t reserved_6:23; + /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t core0_reset_cause_clr:1; + /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_set:1; + /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of cpu_reset register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_length:3; + /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_en:1; + /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * need_des + */ + uint32_t cpu_stall_wait:5; + /** cpu_stall_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 600; + * need_des + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 650; + * need_des + */ + uint32_t rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0; + * need_des + */ + uint32_t lp_bletimer_div_num:12; + /** lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0; + * need_des + */ + uint32_t lp_bletimer_32k_sel:2; + /** lp_sel_osc_slow : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_sel_osc_slow:1; + /** lp_sel_osc_fast : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sel_osc_fast:1; + /** lp_sel_xtal : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sel_xtal:1; + /** lp_sel_xtal32k : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_sel_xtal32k:1; + /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_i2c_clk_sel:1; + /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_uart_clk_sel:1; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** clkrst_date : R/W; bitpos: [30:0]; default: 35680896; + * need_des + */ + uint32_t clkrst_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_lpperi_reg_t lpperi; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_timer_reg.h b/components/soc/esp32h2/include/soc/lp_timer_reg.h new file mode 100644 index 0000000000..2fedde439f --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_timer_reg.h @@ -0,0 +1,235 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_timer_struct.h b/components/soc/esp32h2/include/soc/lp_timer_struct.h new file mode 100644 index 0000000000..1c24dafa1a --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_timer_struct.h @@ -0,0 +1,255 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of tar0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of tar0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** main_timer_update : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t main_timer_update:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of main_buf0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of main_buf0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of main_buf1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of main_buf1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t tar0_low; + volatile lp_timer_tar0_high_reg_t tar0_high; + uint32_t reserved_008[2]; + volatile lp_timer_update_reg_t update; + volatile lp_timer_main_buf0_low_reg_t main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t main_buf1_high; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + uint32_t reserved_038[241]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_wdt_reg.h b/components/soc/esp32h2/include/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..6ae1949037 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_wdt_reg.h @@ -0,0 +1,366 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32H2-TODO: IDF-5730 better to move to wdt_types.h +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ +#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 +/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */ +#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1 + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ +#define RTC_WDT_RESET_LENGTH_100_NS 0 +#define RTC_WDT_RESET_LENGTH_200_NS 1 +#define RTC_WDT_RESET_LENGTH_300_NS 2 +#define RTC_WDT_RESET_LENGTH_400_NS 3 +#define RTC_WDT_RESET_LENGTH_500_NS 4 +#define RTC_WDT_RESET_LENGTH_800_NS 5 +#define RTC_WDT_RESET_LENGTH_1600_NS 6 +#define RTC_WDT_RESET_LENGTH_3200_NS 7 + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_CONFIG5_REG register + * need_des + */ +#define LP_WDT_CONFIG5_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_CHIP_RESET_TARGET : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_WDT_CHIP_RESET_TARGET 0x000000FFU +#define LP_WDT_CHIP_RESET_TARGET_M (LP_WDT_CHIP_RESET_TARGET_V << LP_WDT_CHIP_RESET_TARGET_S) +#define LP_WDT_CHIP_RESET_TARGET_V 0x000000FFU +#define LP_WDT_CHIP_RESET_TARGET_S 0 +/** LP_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_WDT_CHIP_RESET_EN (BIT(8)) +#define LP_WDT_CHIP_RESET_EN_M (LP_WDT_CHIP_RESET_EN_V << LP_WDT_CHIP_RESET_EN_S) +#define LP_WDT_CHIP_RESET_EN_V 0x00000001U +#define LP_WDT_CHIP_RESET_EN_S 8 +/** LP_WDT_CHIP_RESET_KEY : R/W; bitpos: [16:9]; default: 0; + * need_des + */ +#define LP_WDT_CHIP_RESET_KEY 0x000000FFU +#define LP_WDT_CHIP_RESET_KEY_M (LP_WDT_CHIP_RESET_KEY_V << LP_WDT_CHIP_RESET_KEY_S) +#define LP_WDT_CHIP_RESET_KEY_V 0x000000FFU +#define LP_WDT_CHIP_RESET_KEY_S 9 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x34) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lp_wdt_struct.h b/components/soc/esp32h2/include/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..125ab730d2 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lp_wdt_struct.h @@ -0,0 +1,333 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of config0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of config1 register + * need_des + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of config2 register + * need_des + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of config3 register + * need_des + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of config4 register + * need_des + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of config5 register + * need_des + */ +typedef union { + struct { + /** chip_reset_target : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t chip_reset_target:8; + /** chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t chip_reset_en:1; + /** chip_reset_key : R/W; bitpos: [16:9]; default: 0; + * need_des + */ + uint32_t chip_reset_key:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_wdt_config5_reg_t; + +/** Type of feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of swd_config register + * need_des + */ +typedef union { + struct { + /** swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t swd_reset_flag:1; + uint32_t reserved_1:17; + /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t swd_auto_feed_en:1; + /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t swd_rst_flag_clr:1; + /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t swd_signal_width:10; + /** swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t swd_disable:1; + /** swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of swd_wprotect register + * need_des + */ +typedef union { + struct { + /** swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_raw:1; + /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ + uint32_t lp_wdt_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct { + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_config5_reg_t config5; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; + uint32_t reserved_038[241]; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lpperi_reg.h b/components/soc/esp32h2/include/soc/lpperi_reg.h new file mode 100644 index 0000000000..86fff049b9 --- /dev/null +++ b/components/soc/esp32h2/include/soc/lpperi_reg.h @@ -0,0 +1,336 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24)) +#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S) +#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U +#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DEBUG_SEL0_REG register + * need des + */ +#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL0 0x0000007FU +#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S) +#define LPPERI_DEBUG_SEL0_V 0x0000007FU +#define LPPERI_DEBUG_SEL0_S 0 +/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL1 0x0000007FU +#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S) +#define LPPERI_DEBUG_SEL1_V 0x0000007FU +#define LPPERI_DEBUG_SEL1_S 7 +/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL2 0x0000007FU +#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S) +#define LPPERI_DEBUG_SEL2_V 0x0000007FU +#define LPPERI_DEBUG_SEL2_S 14 +/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL3 0x0000007FU +#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S) +#define LPPERI_DEBUG_SEL3_V 0x0000007FU +#define LPPERI_DEBUG_SEL3_S 21 + +/** LPPERI_DEBUG_SEL1_REG register + * need des + */ +#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL4 0x0000007FU +#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S) +#define LPPERI_DEBUG_SEL4_V 0x0000007FU +#define LPPERI_DEBUG_SEL4_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 35676464; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lpperi_struct.h b/components/soc/esp32h2/include/soc/lpperi_struct.h new file mode 100644 index 0000000000..3a07daa0ed --- /dev/null +++ b/components/soc/esp32h2/include/soc/lpperi_struct.h @@ -0,0 +1,307 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_debug_sel1_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 35676464; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_debug_sel0_reg_t debug_sel0; + volatile lpperi_debug_sel1_reg_t debug_sel1; + uint32_t reserved_02c[244]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/mcpwm_reg.h b/components/soc/esp32h2/include/soc/mcpwm_reg.h new file mode 100644 index 0000000000..f851de75ce --- /dev/null +++ b/components/soc/esp32h2/include/soc/mcpwm_reg.h @@ -0,0 +1,4137 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU +#define MCPWM_CLK_PRESCALE_S 0 + +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 + * starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U +#define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 + +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER0_SYNCI_EN_S 0 +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction when timer0 mode is up-down mode: + * 0-increase,1-decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer0 counter value + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer0 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_DIRECTION_S 16 + +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: + * if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 + * starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U +#define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 + +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER1_SYNCI_EN_S 0 +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer1_sync_sw bit + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer1's direction when timer1 mode is up-down mode: + * 0-increase,1-decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer1 counter value + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer1 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_DIRECTION_S 16 + +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: + * if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 + * starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U +#define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 + +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER2_SYNCI_EN_S 0 +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer2's direction when timer2 mode is up-down mode: + * 0-increase,1-decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer2 counter value + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer2 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_DIRECTION_S 16 + +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection for three PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 + +/** MCPWM_OPERATOR_TIMERSEL_REG register + * Select specific timer for PWM operators. + */ +#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 + +/** MCPWM_GEN0_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c) +/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) +#define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR0_A_UPMETHOD_S 0 +/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 0 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) +#define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR0_B_UPMETHOD_S 4 +/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) +#define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR0_A_SHDW_FULL_S 8 +/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) +#define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR0_B_SHDW_FULL_S 9 + +/** MCPWM_GEN0_TSTMP_A_REG register + * Shadow register for register A. + */ +#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40) +/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp A's shadow register + */ +#define MCPWM_CMPR0_A 0x0000FFFFU +#define MCPWM_CMPR0_A_M (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S) +#define MCPWM_CMPR0_A_V 0x0000FFFFU +#define MCPWM_CMPR0_A_S 0 + +/** MCPWM_GEN0_TSTMP_B_REG register + * Shadow register for register B. + */ +#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44) +/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp B's shadow register + */ +#define MCPWM_CMPR0_B 0x0000FFFFU +#define MCPWM_CMPR0_B_M (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S) +#define MCPWM_CMPR0_B_V 0x0000FFFFU +#define MCPWM_CMPR0_B_S 0 + +/** MCPWM_GEN0_CFG0_REG register + * Fault event T0 and T1 handling + */ +#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 0 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 0 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 + +/** MCPWM_GEN0_FORCE_REG register + * Permissives to force PWM0A and PWM0B outputs by software + */ +#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator0. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN0_A_REG register + * Actions triggered by events on PWM0A + */ +#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0A triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U +#define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0A triggered by event TEP when timer increasing + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0A triggered by event TEA when timer increasing + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0A triggered by event TEB when timer increasing + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0A triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0A triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0A triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0A triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0A triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0A triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0A triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 + +/** MCPWM_GEN0_B_REG register + * Actions triggered by events on PWM0B + */ +#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0B triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U +#define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0B triggered by event TEP when timer increasing + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0B triggered by event TEA when timer increasing + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0B triggered by event TEB when timer increasing + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0B triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0B triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0B triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0B triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0B triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0B triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0B triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 + +/** MCPWM_DT0_CFG_REG register + * dead time type selection and configuration + */ +#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58) +/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB0_FED_UPMETHOD_M (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S) +#define MCPWM_DB0_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB0_FED_UPMETHOD_S 0 +/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB0_RED_UPMETHOD_M (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S) +#define MCPWM_DB0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB0_RED_UPMETHOD_S 4 +/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB0_DEB_MODE (BIT(8)) +#define MCPWM_DB0_DEB_MODE_M (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S) +#define MCPWM_DB0_DEB_MODE_V 0x00000001U +#define MCPWM_DB0_DEB_MODE_S 8 +/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DB0_A_OUTSWAP (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_M (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S) +#define MCPWM_DB0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB0_A_OUTSWAP_S 9 +/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DB0_B_OUTSWAP (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_M (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S) +#define MCPWM_DB0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB0_B_OUTSWAP_S 10 +/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DB0_RED_INSEL (BIT(11)) +#define MCPWM_DB0_RED_INSEL_M (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S) +#define MCPWM_DB0_RED_INSEL_V 0x00000001U +#define MCPWM_DB0_RED_INSEL_S 11 +/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DB0_FED_INSEL (BIT(12)) +#define MCPWM_DB0_FED_INSEL_M (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S) +#define MCPWM_DB0_FED_INSEL_V 0x00000001U +#define MCPWM_DB0_FED_INSEL_S 12 +/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_M (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S) +#define MCPWM_DB0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB0_RED_OUTINVERT_S 13 +/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_M (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S) +#define MCPWM_DB0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB0_FED_OUTINVERT_S 14 +/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_M (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S) +#define MCPWM_DB0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB0_A_OUTBYPASS_S 15 +/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_M (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S) +#define MCPWM_DB0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB0_B_OUTBYPASS_S 16 +/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DB0_CLK_SEL (BIT(17)) +#define MCPWM_DB0_CLK_SEL_M (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S) +#define MCPWM_DB0_CLK_SEL_V 0x00000001U +#define MCPWM_DB0_CLK_SEL_S 17 + +/** MCPWM_DT0_FED_CFG_REG register + * Shadow register for falling edge delay (FED). + */ +#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c) +/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DB0_FED 0x0000FFFFU +#define MCPWM_DB0_FED_M (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S) +#define MCPWM_DB0_FED_V 0x0000FFFFU +#define MCPWM_DB0_FED_S 0 + +/** MCPWM_DT0_RED_CFG_REG register + * Shadow register for rising edge delay (RED). + */ +#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60) +/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DB0_RED 0x0000FFFFU +#define MCPWM_DB0_RED_M (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S) +#define MCPWM_DB0_RED_V 0x0000FFFFU +#define MCPWM_DB0_RED_S 0 + +/** MCPWM_CARRIER0_CFG_REG register + * Carrier enable and configuratoin + */ +#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64) +/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + */ +#define MCPWM_CHOPPER0_EN (BIT(0)) +#define MCPWM_CHOPPER0_EN_M (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S) +#define MCPWM_CHOPPER0_EN_V 0x00000001U +#define MCPWM_CHOPPER0_EN_S 0 +/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER0_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER0_PRESCALE_M (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S) +#define MCPWM_CHOPPER0_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER0_PRESCALE_S 1 +/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER0_DUTY 0x00000007U +#define MCPWM_CHOPPER0_DUTY_M (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S) +#define MCPWM_CHOPPER0_DUTY_V 0x00000007U +#define MCPWM_CHOPPER0_DUTY_S 5 +/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CHOPPER0_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER0_OSHTWTH_M (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S) +#define MCPWM_CHOPPER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER0_OSHTWTH_S 8 +/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_M (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S) +#define MCPWM_CHOPPER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER0_OUT_INVERT_S 12 +/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_M (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S) +#define MCPWM_CHOPPER0_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER0_IN_INVERT_S 13 + +/** MCPWM_FH0_CFG0_REG register + * Actions on PWM0A and PWM0B trip events + */ +#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68) +/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_SW_CBC (BIT(0)) +#define MCPWM_TZ0_SW_CBC_M (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S) +#define MCPWM_TZ0_SW_CBC_V 0x00000001U +#define MCPWM_TZ0_SW_CBC_S 0 +/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F2_CBC (BIT(1)) +#define MCPWM_TZ0_F2_CBC_M (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S) +#define MCPWM_TZ0_F2_CBC_V 0x00000001U +#define MCPWM_TZ0_F2_CBC_S 1 +/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F1_CBC (BIT(2)) +#define MCPWM_TZ0_F1_CBC_M (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S) +#define MCPWM_TZ0_F1_CBC_V 0x00000001U +#define MCPWM_TZ0_F1_CBC_S 2 +/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F0_CBC (BIT(3)) +#define MCPWM_TZ0_F0_CBC_M (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S) +#define MCPWM_TZ0_F0_CBC_V 0x00000001U +#define MCPWM_TZ0_F0_CBC_S 3 +/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_SW_OST (BIT(4)) +#define MCPWM_TZ0_SW_OST_M (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S) +#define MCPWM_TZ0_SW_OST_V 0x00000001U +#define MCPWM_TZ0_SW_OST_S 4 +/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F2_OST (BIT(5)) +#define MCPWM_TZ0_F2_OST_M (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S) +#define MCPWM_TZ0_F2_OST_V 0x00000001U +#define MCPWM_TZ0_F2_OST_S 5 +/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F1_OST (BIT(6)) +#define MCPWM_TZ0_F1_OST_M (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S) +#define MCPWM_TZ0_F1_OST_V 0x00000001U +#define MCPWM_TZ0_F1_OST_S 6 +/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F0_OST (BIT(7)) +#define MCPWM_TZ0_F0_OST_M (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S) +#define MCPWM_TZ0_F0_OST_V 0x00000001U +#define MCPWM_TZ0_F0_OST_S 7 +/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_CBC_D 0x00000003U +#define MCPWM_TZ0_A_CBC_D_M (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S) +#define MCPWM_TZ0_A_CBC_D_V 0x00000003U +#define MCPWM_TZ0_A_CBC_D_S 8 +/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_CBC_U 0x00000003U +#define MCPWM_TZ0_A_CBC_U_M (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S) +#define MCPWM_TZ0_A_CBC_U_V 0x00000003U +#define MCPWM_TZ0_A_CBC_U_S 10 +/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_OST_D 0x00000003U +#define MCPWM_TZ0_A_OST_D_M (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S) +#define MCPWM_TZ0_A_OST_D_V 0x00000003U +#define MCPWM_TZ0_A_OST_D_S 12 +/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_OST_U 0x00000003U +#define MCPWM_TZ0_A_OST_U_M (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S) +#define MCPWM_TZ0_A_OST_U_V 0x00000003U +#define MCPWM_TZ0_A_OST_U_S 14 +/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_CBC_D 0x00000003U +#define MCPWM_TZ0_B_CBC_D_M (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S) +#define MCPWM_TZ0_B_CBC_D_V 0x00000003U +#define MCPWM_TZ0_B_CBC_D_S 16 +/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_CBC_U 0x00000003U +#define MCPWM_TZ0_B_CBC_U_M (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S) +#define MCPWM_TZ0_B_CBC_U_V 0x00000003U +#define MCPWM_TZ0_B_CBC_U_S 18 +/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_OST_D 0x00000003U +#define MCPWM_TZ0_B_OST_D_M (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S) +#define MCPWM_TZ0_B_OST_D_V 0x00000003U +#define MCPWM_TZ0_B_OST_D_S 20 +/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_OST_U 0x00000003U +#define MCPWM_TZ0_B_OST_U_M (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S) +#define MCPWM_TZ0_B_OST_U_V 0x00000003U +#define MCPWM_TZ0_B_OST_U_S 22 + +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c) +/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_TZ0_CLR_OST (BIT(0)) +#define MCPWM_TZ0_CLR_OST_M (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S) +#define MCPWM_TZ0_CLR_OST_V 0x00000001U +#define MCPWM_TZ0_CLR_OST_S 0 +/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_TZ0_CBCPULSE 0x00000003U +#define MCPWM_TZ0_CBCPULSE_M (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S) +#define MCPWM_TZ0_CBCPULSE_V 0x00000003U +#define MCPWM_TZ0_CBCPULSE_S 1 +/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_TZ0_FORCE_CBC (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_M (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S) +#define MCPWM_TZ0_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ0_FORCE_CBC_S 3 +/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_TZ0_FORCE_OST (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_M (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S) +#define MCPWM_TZ0_FORCE_OST_V 0x00000001U +#define MCPWM_TZ0_FORCE_OST_S 4 + +/** MCPWM_FH0_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70) +/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_TZ0_CBC_ON (BIT(0)) +#define MCPWM_TZ0_CBC_ON_M (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S) +#define MCPWM_TZ0_CBC_ON_V 0x00000001U +#define MCPWM_TZ0_CBC_ON_S 0 +/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_TZ0_OST_ON (BIT(1)) +#define MCPWM_TZ0_OST_ON_M (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S) +#define MCPWM_TZ0_OST_ON_V 0x00000001U +#define MCPWM_TZ0_OST_ON_S 1 + +/** MCPWM_GEN1_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74) +/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR1_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR1_A_UPMETHOD_M (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S) +#define MCPWM_CMPR1_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR1_A_UPMETHOD_S 0 +/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 1 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR1_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR1_B_UPMETHOD_M (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S) +#define MCPWM_CMPR1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR1_B_UPMETHOD_S 4 +/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_M (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S) +#define MCPWM_CMPR1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR1_A_SHDW_FULL_S 8 +/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_M (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S) +#define MCPWM_CMPR1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR1_B_SHDW_FULL_S 9 + +/** MCPWM_GEN1_TSTMP_A_REG register + * Shadow register for register A. + */ +#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78) +/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp A's shadow register + */ +#define MCPWM_CMPR1_A 0x0000FFFFU +#define MCPWM_CMPR1_A_M (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S) +#define MCPWM_CMPR1_A_V 0x0000FFFFU +#define MCPWM_CMPR1_A_S 0 + +/** MCPWM_GEN1_TSTMP_B_REG register + * Shadow register for register B. + */ +#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c) +/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp B's shadow register + */ +#define MCPWM_CMPR1_B 0x0000FFFFU +#define MCPWM_CMPR1_B_M (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S) +#define MCPWM_CMPR1_B_V 0x0000FFFFU +#define MCPWM_CMPR1_B_S 0 + +/** MCPWM_GEN1_CFG0_REG register + * Fault event T0 and T1 handling + */ +#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:sync;when bit3 is set to 1:disable the update. + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 1 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 1 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 + +/** MCPWM_GEN1_FORCE_REG register + * Permissives to force PWM1A and PWM1B outputs by software + */ +#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 1. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN1_A_REG register + * Actions triggered by events on PWM1A + */ +#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1A triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U +#define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1A triggered by event TEP when timer increasing + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1A triggered by event TEA when timer increasing + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1A triggered by event TEB when timer increasing + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1A triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1A triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1A triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1A triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1A triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1A triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1A triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 + +/** MCPWM_GEN1_B_REG register + * Actions triggered by events on PWM1B + */ +#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1B triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U +#define MCPWM_GEN1_B_UTEZ_S 0 +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1B triggered by event TEP when timer increasing + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1B triggered by event TEA when timer increasing + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1B triggered by event TEB when timer increasing + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1B triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1B triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1B triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1B triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1B triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1B triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1B triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 + +/** MCPWM_DT1_CFG_REG register + * dead time type selection and configuration + */ +#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90) +/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB1_FED_UPMETHOD_M (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S) +#define MCPWM_DB1_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB1_FED_UPMETHOD_S 0 +/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB1_RED_UPMETHOD_M (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S) +#define MCPWM_DB1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB1_RED_UPMETHOD_S 4 +/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB1_DEB_MODE (BIT(8)) +#define MCPWM_DB1_DEB_MODE_M (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S) +#define MCPWM_DB1_DEB_MODE_V 0x00000001U +#define MCPWM_DB1_DEB_MODE_S 8 +/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DB1_A_OUTSWAP (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_M (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S) +#define MCPWM_DB1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB1_A_OUTSWAP_S 9 +/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DB1_B_OUTSWAP (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_M (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S) +#define MCPWM_DB1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB1_B_OUTSWAP_S 10 +/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DB1_RED_INSEL (BIT(11)) +#define MCPWM_DB1_RED_INSEL_M (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S) +#define MCPWM_DB1_RED_INSEL_V 0x00000001U +#define MCPWM_DB1_RED_INSEL_S 11 +/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DB1_FED_INSEL (BIT(12)) +#define MCPWM_DB1_FED_INSEL_M (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S) +#define MCPWM_DB1_FED_INSEL_V 0x00000001U +#define MCPWM_DB1_FED_INSEL_S 12 +/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_M (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S) +#define MCPWM_DB1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB1_RED_OUTINVERT_S 13 +/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_M (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S) +#define MCPWM_DB1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB1_FED_OUTINVERT_S 14 +/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_M (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S) +#define MCPWM_DB1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB1_A_OUTBYPASS_S 15 +/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_M (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S) +#define MCPWM_DB1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB1_B_OUTBYPASS_S 16 +/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DB1_CLK_SEL (BIT(17)) +#define MCPWM_DB1_CLK_SEL_M (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S) +#define MCPWM_DB1_CLK_SEL_V 0x00000001U +#define MCPWM_DB1_CLK_SEL_S 17 + +/** MCPWM_DT1_FED_CFG_REG register + * Shadow register for falling edge delay (FED). + */ +#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94) +/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DB1_FED 0x0000FFFFU +#define MCPWM_DB1_FED_M (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S) +#define MCPWM_DB1_FED_V 0x0000FFFFU +#define MCPWM_DB1_FED_S 0 + +/** MCPWM_DT1_RED_CFG_REG register + * Shadow register for rising edge delay (RED). + */ +#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98) +/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DB1_RED 0x0000FFFFU +#define MCPWM_DB1_RED_M (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S) +#define MCPWM_DB1_RED_V 0x0000FFFFU +#define MCPWM_DB1_RED_S 0 + +/** MCPWM_CARRIER1_CFG_REG register + * Carrier enable and configuratoin + */ +#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c) +/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + */ +#define MCPWM_CHOPPER1_EN (BIT(0)) +#define MCPWM_CHOPPER1_EN_M (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S) +#define MCPWM_CHOPPER1_EN_V 0x00000001U +#define MCPWM_CHOPPER1_EN_S 0 +/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER1_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER1_PRESCALE_M (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S) +#define MCPWM_CHOPPER1_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER1_PRESCALE_S 1 +/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER1_DUTY 0x00000007U +#define MCPWM_CHOPPER1_DUTY_M (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S) +#define MCPWM_CHOPPER1_DUTY_V 0x00000007U +#define MCPWM_CHOPPER1_DUTY_S 5 +/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CHOPPER1_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER1_OSHTWTH_M (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S) +#define MCPWM_CHOPPER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER1_OSHTWTH_S 8 +/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_M (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S) +#define MCPWM_CHOPPER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER1_OUT_INVERT_S 12 +/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_M (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S) +#define MCPWM_CHOPPER1_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER1_IN_INVERT_S 13 + +/** MCPWM_FH1_CFG0_REG register + * Actions on PWM1A and PWM1B trip events + */ +#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0) +/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_SW_CBC (BIT(0)) +#define MCPWM_TZ1_SW_CBC_M (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S) +#define MCPWM_TZ1_SW_CBC_V 0x00000001U +#define MCPWM_TZ1_SW_CBC_S 0 +/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F2_CBC (BIT(1)) +#define MCPWM_TZ1_F2_CBC_M (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S) +#define MCPWM_TZ1_F2_CBC_V 0x00000001U +#define MCPWM_TZ1_F2_CBC_S 1 +/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F1_CBC (BIT(2)) +#define MCPWM_TZ1_F1_CBC_M (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S) +#define MCPWM_TZ1_F1_CBC_V 0x00000001U +#define MCPWM_TZ1_F1_CBC_S 2 +/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F0_CBC (BIT(3)) +#define MCPWM_TZ1_F0_CBC_M (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S) +#define MCPWM_TZ1_F0_CBC_V 0x00000001U +#define MCPWM_TZ1_F0_CBC_S 3 +/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_SW_OST (BIT(4)) +#define MCPWM_TZ1_SW_OST_M (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S) +#define MCPWM_TZ1_SW_OST_V 0x00000001U +#define MCPWM_TZ1_SW_OST_S 4 +/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F2_OST (BIT(5)) +#define MCPWM_TZ1_F2_OST_M (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S) +#define MCPWM_TZ1_F2_OST_V 0x00000001U +#define MCPWM_TZ1_F2_OST_S 5 +/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F1_OST (BIT(6)) +#define MCPWM_TZ1_F1_OST_M (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S) +#define MCPWM_TZ1_F1_OST_V 0x00000001U +#define MCPWM_TZ1_F1_OST_S 6 +/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F0_OST (BIT(7)) +#define MCPWM_TZ1_F0_OST_M (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S) +#define MCPWM_TZ1_F0_OST_V 0x00000001U +#define MCPWM_TZ1_F0_OST_S 7 +/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_CBC_D 0x00000003U +#define MCPWM_TZ1_A_CBC_D_M (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S) +#define MCPWM_TZ1_A_CBC_D_V 0x00000003U +#define MCPWM_TZ1_A_CBC_D_S 8 +/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_CBC_U 0x00000003U +#define MCPWM_TZ1_A_CBC_U_M (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S) +#define MCPWM_TZ1_A_CBC_U_V 0x00000003U +#define MCPWM_TZ1_A_CBC_U_S 10 +/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: + * do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_OST_D 0x00000003U +#define MCPWM_TZ1_A_OST_D_M (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S) +#define MCPWM_TZ1_A_OST_D_V 0x00000003U +#define MCPWM_TZ1_A_OST_D_S 12 +/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_OST_U 0x00000003U +#define MCPWM_TZ1_A_OST_U_M (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S) +#define MCPWM_TZ1_A_OST_U_V 0x00000003U +#define MCPWM_TZ1_A_OST_U_S 14 +/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_CBC_D 0x00000003U +#define MCPWM_TZ1_B_CBC_D_M (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S) +#define MCPWM_TZ1_B_CBC_D_V 0x00000003U +#define MCPWM_TZ1_B_CBC_D_S 16 +/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_CBC_U 0x00000003U +#define MCPWM_TZ1_B_CBC_U_M (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S) +#define MCPWM_TZ1_B_CBC_U_V 0x00000003U +#define MCPWM_TZ1_B_CBC_U_S 18 +/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_OST_D 0x00000003U +#define MCPWM_TZ1_B_OST_D_M (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S) +#define MCPWM_TZ1_B_OST_D_V 0x00000003U +#define MCPWM_TZ1_B_OST_D_S 20 +/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_OST_U 0x00000003U +#define MCPWM_TZ1_B_OST_U_M (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S) +#define MCPWM_TZ1_B_OST_U_V 0x00000003U +#define MCPWM_TZ1_B_OST_U_S 22 + +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4) +/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_TZ1_CLR_OST (BIT(0)) +#define MCPWM_TZ1_CLR_OST_M (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S) +#define MCPWM_TZ1_CLR_OST_V 0x00000001U +#define MCPWM_TZ1_CLR_OST_S 0 +/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_TZ1_CBCPULSE 0x00000003U +#define MCPWM_TZ1_CBCPULSE_M (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S) +#define MCPWM_TZ1_CBCPULSE_V 0x00000003U +#define MCPWM_TZ1_CBCPULSE_S 1 +/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_TZ1_FORCE_CBC (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_M (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S) +#define MCPWM_TZ1_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ1_FORCE_CBC_S 3 +/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_TZ1_FORCE_OST (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_M (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S) +#define MCPWM_TZ1_FORCE_OST_V 0x00000001U +#define MCPWM_TZ1_FORCE_OST_S 4 + +/** MCPWM_FH1_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8) +/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_TZ1_CBC_ON (BIT(0)) +#define MCPWM_TZ1_CBC_ON_M (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S) +#define MCPWM_TZ1_CBC_ON_V 0x00000001U +#define MCPWM_TZ1_CBC_ON_S 0 +/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_TZ1_OST_ON (BIT(1)) +#define MCPWM_TZ1_OST_ON_M (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S) +#define MCPWM_TZ1_OST_ON_V 0x00000001U +#define MCPWM_TZ1_OST_ON_S 1 + +/** MCPWM_GEN2_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac) +/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR2_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR2_A_UPMETHOD_M (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S) +#define MCPWM_CMPR2_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR2_A_UPMETHOD_S 0 +/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 2 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR2_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR2_B_UPMETHOD_M (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S) +#define MCPWM_CMPR2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR2_B_UPMETHOD_S 4 +/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_M (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S) +#define MCPWM_CMPR2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR2_A_SHDW_FULL_S 8 +/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_M (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S) +#define MCPWM_CMPR2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR2_B_SHDW_FULL_S 9 + +/** MCPWM_GEN2_TSTMP_A_REG register + * Shadow register for register A. + */ +#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0) +/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp A's shadow register + */ +#define MCPWM_CMPR2_A 0x0000FFFFU +#define MCPWM_CMPR2_A_M (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S) +#define MCPWM_CMPR2_A_V 0x0000FFFFU +#define MCPWM_CMPR2_A_S 0 + +/** MCPWM_GEN2_TSTMP_B_REG register + * Shadow register for register B. + */ +#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4) +/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp B's shadow register + */ +#define MCPWM_CMPR2_B 0x0000FFFFU +#define MCPWM_CMPR2_B_M (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S) +#define MCPWM_CMPR2_B_V 0x0000FFFFU +#define MCPWM_CMPR2_B_S 0 + +/** MCPWM_GEN2_CFG0_REG register + * Fault event T0 and T1 handling + */ +#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2's active register of configuration. 0: + * immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is + * set to 1:disable the update. + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 2 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 2 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 + +/** MCPWM_GEN2_FORCE_REG register + * Permissives to force PWM2A and PWM2B outputs by software + */ +#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 2. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN2_A_REG register + * Actions triggered by events on PWM2A + */ +#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2A triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U +#define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2A triggered by event TEP when timer increasing + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2A triggered by event TEA when timer increasing + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2A triggered by event TEB when timer increasing + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2A triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2A triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2A triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2A triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2A triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2A triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2A triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 + +/** MCPWM_GEN2_B_REG register + * Actions triggered by events on PWM2B + */ +#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2B triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U +#define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2B triggered by event TEP when timer increasing + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2B triggered by event TEA when timer increasing + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2B triggered by event TEB when timer increasing + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2B triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2B triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2B triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2B triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2B triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2B triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2B triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 + +/** MCPWM_DT2_CFG_REG register + * dead time type selection and configuration + */ +#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8) +/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB2_FED_UPMETHOD_M (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S) +#define MCPWM_DB2_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB2_FED_UPMETHOD_S 0 +/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB2_RED_UPMETHOD_M (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S) +#define MCPWM_DB2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB2_RED_UPMETHOD_S 4 +/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB2_DEB_MODE (BIT(8)) +#define MCPWM_DB2_DEB_MODE_M (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S) +#define MCPWM_DB2_DEB_MODE_V 0x00000001U +#define MCPWM_DB2_DEB_MODE_S 8 +/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DB2_A_OUTSWAP (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_M (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S) +#define MCPWM_DB2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB2_A_OUTSWAP_S 9 +/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DB2_B_OUTSWAP (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_M (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S) +#define MCPWM_DB2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB2_B_OUTSWAP_S 10 +/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DB2_RED_INSEL (BIT(11)) +#define MCPWM_DB2_RED_INSEL_M (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S) +#define MCPWM_DB2_RED_INSEL_V 0x00000001U +#define MCPWM_DB2_RED_INSEL_S 11 +/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DB2_FED_INSEL (BIT(12)) +#define MCPWM_DB2_FED_INSEL_M (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S) +#define MCPWM_DB2_FED_INSEL_V 0x00000001U +#define MCPWM_DB2_FED_INSEL_S 12 +/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_M (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S) +#define MCPWM_DB2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB2_RED_OUTINVERT_S 13 +/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_M (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S) +#define MCPWM_DB2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB2_FED_OUTINVERT_S 14 +/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_M (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S) +#define MCPWM_DB2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB2_A_OUTBYPASS_S 15 +/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_M (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S) +#define MCPWM_DB2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB2_B_OUTBYPASS_S 16 +/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DB2_CLK_SEL (BIT(17)) +#define MCPWM_DB2_CLK_SEL_M (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S) +#define MCPWM_DB2_CLK_SEL_V 0x00000001U +#define MCPWM_DB2_CLK_SEL_S 17 + +/** MCPWM_DT2_FED_CFG_REG register + * Shadow register for falling edge delay (FED). + */ +#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc) +/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DB2_FED 0x0000FFFFU +#define MCPWM_DB2_FED_M (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S) +#define MCPWM_DB2_FED_V 0x0000FFFFU +#define MCPWM_DB2_FED_S 0 + +/** MCPWM_DT2_RED_CFG_REG register + * Shadow register for rising edge delay (RED). + */ +#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0) +/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DB2_RED 0x0000FFFFU +#define MCPWM_DB2_RED_M (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S) +#define MCPWM_DB2_RED_V 0x0000FFFFU +#define MCPWM_DB2_RED_S 0 + +/** MCPWM_CARRIER2_CFG_REG register + * Carrier enable and configuratoin + */ +#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4) +/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + */ +#define MCPWM_CHOPPER2_EN (BIT(0)) +#define MCPWM_CHOPPER2_EN_M (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S) +#define MCPWM_CHOPPER2_EN_V 0x00000001U +#define MCPWM_CHOPPER2_EN_S 0 +/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER2_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER2_PRESCALE_M (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S) +#define MCPWM_CHOPPER2_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER2_PRESCALE_S 1 +/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER2_DUTY 0x00000007U +#define MCPWM_CHOPPER2_DUTY_M (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S) +#define MCPWM_CHOPPER2_DUTY_V 0x00000007U +#define MCPWM_CHOPPER2_DUTY_S 5 +/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CHOPPER2_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER2_OSHTWTH_M (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S) +#define MCPWM_CHOPPER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER2_OSHTWTH_S 8 +/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_M (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S) +#define MCPWM_CHOPPER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER2_OUT_INVERT_S 12 +/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_M (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S) +#define MCPWM_CHOPPER2_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER2_IN_INVERT_S 13 + +/** MCPWM_FH2_CFG0_REG register + * Actions on PWM2A and PWM2B trip events + */ +#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8) +/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_SW_CBC (BIT(0)) +#define MCPWM_TZ2_SW_CBC_M (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S) +#define MCPWM_TZ2_SW_CBC_V 0x00000001U +#define MCPWM_TZ2_SW_CBC_S 0 +/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F2_CBC (BIT(1)) +#define MCPWM_TZ2_F2_CBC_M (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S) +#define MCPWM_TZ2_F2_CBC_V 0x00000001U +#define MCPWM_TZ2_F2_CBC_S 1 +/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F1_CBC (BIT(2)) +#define MCPWM_TZ2_F1_CBC_M (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S) +#define MCPWM_TZ2_F1_CBC_V 0x00000001U +#define MCPWM_TZ2_F1_CBC_S 2 +/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F0_CBC (BIT(3)) +#define MCPWM_TZ2_F0_CBC_M (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S) +#define MCPWM_TZ2_F0_CBC_V 0x00000001U +#define MCPWM_TZ2_F0_CBC_S 3 +/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_SW_OST (BIT(4)) +#define MCPWM_TZ2_SW_OST_M (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S) +#define MCPWM_TZ2_SW_OST_V 0x00000001U +#define MCPWM_TZ2_SW_OST_S 4 +/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F2_OST (BIT(5)) +#define MCPWM_TZ2_F2_OST_M (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S) +#define MCPWM_TZ2_F2_OST_V 0x00000001U +#define MCPWM_TZ2_F2_OST_S 5 +/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F1_OST (BIT(6)) +#define MCPWM_TZ2_F1_OST_M (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S) +#define MCPWM_TZ2_F1_OST_V 0x00000001U +#define MCPWM_TZ2_F1_OST_S 6 +/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F0_OST (BIT(7)) +#define MCPWM_TZ2_F0_OST_M (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S) +#define MCPWM_TZ2_F0_OST_V 0x00000001U +#define MCPWM_TZ2_F0_OST_S 7 +/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_CBC_D 0x00000003U +#define MCPWM_TZ2_A_CBC_D_M (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S) +#define MCPWM_TZ2_A_CBC_D_V 0x00000003U +#define MCPWM_TZ2_A_CBC_D_S 8 +/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_CBC_U 0x00000003U +#define MCPWM_TZ2_A_CBC_U_M (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S) +#define MCPWM_TZ2_A_CBC_U_V 0x00000003U +#define MCPWM_TZ2_A_CBC_U_S 10 +/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_OST_D 0x00000003U +#define MCPWM_TZ2_A_OST_D_M (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S) +#define MCPWM_TZ2_A_OST_D_V 0x00000003U +#define MCPWM_TZ2_A_OST_D_S 12 +/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_OST_U 0x00000003U +#define MCPWM_TZ2_A_OST_U_M (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S) +#define MCPWM_TZ2_A_OST_U_V 0x00000003U +#define MCPWM_TZ2_A_OST_U_S 14 +/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_CBC_D 0x00000003U +#define MCPWM_TZ2_B_CBC_D_M (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S) +#define MCPWM_TZ2_B_CBC_D_V 0x00000003U +#define MCPWM_TZ2_B_CBC_D_S 16 +/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_CBC_U 0x00000003U +#define MCPWM_TZ2_B_CBC_U_M (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S) +#define MCPWM_TZ2_B_CBC_U_V 0x00000003U +#define MCPWM_TZ2_B_CBC_U_S 18 +/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_OST_D 0x00000003U +#define MCPWM_TZ2_B_OST_D_M (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S) +#define MCPWM_TZ2_B_OST_D_V 0x00000003U +#define MCPWM_TZ2_B_OST_D_S 20 +/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_OST_U 0x00000003U +#define MCPWM_TZ2_B_OST_U_M (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S) +#define MCPWM_TZ2_B_OST_U_V 0x00000003U +#define MCPWM_TZ2_B_OST_U_S 22 + +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc) +/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_TZ2_CLR_OST (BIT(0)) +#define MCPWM_TZ2_CLR_OST_M (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S) +#define MCPWM_TZ2_CLR_OST_V 0x00000001U +#define MCPWM_TZ2_CLR_OST_S 0 +/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_TZ2_CBCPULSE 0x00000003U +#define MCPWM_TZ2_CBCPULSE_M (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S) +#define MCPWM_TZ2_CBCPULSE_V 0x00000003U +#define MCPWM_TZ2_CBCPULSE_S 1 +/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_TZ2_FORCE_CBC (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_M (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S) +#define MCPWM_TZ2_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ2_FORCE_CBC_S 3 +/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_TZ2_FORCE_OST (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_M (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S) +#define MCPWM_TZ2_FORCE_OST_V 0x00000001U +#define MCPWM_TZ2_FORCE_OST_S 4 + +/** MCPWM_FH2_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0) +/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_TZ2_CBC_ON (BIT(0)) +#define MCPWM_TZ2_CBC_ON_M (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S) +#define MCPWM_TZ2_CBC_ON_V 0x00000001U +#define MCPWM_TZ2_CBC_ON_S 0 +/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_TZ2_OST_ON (BIT(1)) +#define MCPWM_TZ2_OST_ON_M (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S) +#define MCPWM_TZ2_OST_ON_V 0x00000001U +#define MCPWM_TZ2_OST_ON_S 1 + +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status + */ +#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * When set, event_f0 generation is enabled + */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U +#define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * When set, event_f1 generation is enabled + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * When set, event_f2 generation is enabled + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, event_f0 is on going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, event_f1 is on going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, event_f2 is on going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 + +/** MCPWM_CAP_TIMER_CFG_REG register + * Configure capture timer + */ +#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U +#define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 + +/** MCPWM_CAP_TIMER_PHASE_REG register + * Phase for capture timer sync + */ +#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec) +/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ +#define MCPWM_CAP_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration and enable + */ +#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U +#define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP0 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 + +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration and enable + */ +#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U +#define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP1 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 + +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration and enable + */ +#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U +#define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP2 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 + +/** MCPWM_CAP_CH0_REG register + * ch0 capture value status register + */ +#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_S 0 + +/** MCPWM_CAP_CH1_REG register + * ch1 capture value status register + */ +#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_S 0 + +/** MCPWM_CAP_CH2_REG register + * ch2 capture value status register + */ +#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_S 0 + +/** MCPWM_CAP_STATUS_REG register + * Edge of last capture trigger + */ +#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U +#define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 + +/** MCPWM_UPDATE_CFG_REG register + * Enable update. + */ +#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U +#define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 + +/** MCPWM_INT_ENA_REG register + * Interrupt enable bits + */ +#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) +#define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ENA_S 24 +/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) +#define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ENA_S 25 +/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) +#define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 + +/** MCPWM_INT_RAW_REG register + * Raw interrupt status + */ +#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) +#define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_OST_INT_RAW_S 24 +/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) +#define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_OST_INT_RAW_S 25 +/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) +#define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 + +/** MCPWM_INT_ST_REG register + * Masked interrupt status + */ +#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) +#define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ST_S 21 +/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) +#define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ST_S 22 +/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) +#define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ST_S 23 +/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) +#define MCPWM_TZ0_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ST_S 24 +/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) +#define MCPWM_TZ1_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ST_S 25 +/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) +#define MCPWM_TZ2_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 + +/** MCPWM_INT_CLR_REG register + * Interrupt clear bits + */ +#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) +#define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_OST_INT_CLR_S 24 +/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) +#define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_OST_INT_CLR_S 25 +/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) +#define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 + +/** MCPWM_EVT_EN_REG register + * MCPWM event enable register + */ +#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120) +/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; + * set this bit high to enable timer0 stop event generate + */ +#define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) +#define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) +#define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_STOP_EN_S 0 +/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; + * set this bit high to enable timer1 stop event generate + */ +#define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) +#define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) +#define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_STOP_EN_S 1 +/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; + * set this bit high to enable timer2 stop event generate + */ +#define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) +#define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) +#define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_STOP_EN_S 2 +/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; + * set this bit high to enable timer0 equal zero event generate + */ +#define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) +#define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) +#define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEZ_EN_S 3 +/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; + * set this bit high to enable timer1 equal zero event generate + */ +#define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) +#define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) +#define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEZ_EN_S 4 +/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; + * set this bit high to enable timer2 equal zero event generate + */ +#define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) +#define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) +#define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEZ_EN_S 5 +/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; + * set this bit high to enable timer0 equal period event generate + */ +#define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) +#define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) +#define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEP_EN_S 6 +/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer1 equal period event generate + */ +#define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) +#define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) +#define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEP_EN_S 7 +/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer2 equal period event generate + */ +#define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) +#define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) +#define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEP_EN_S 8 +/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; + * set this bit high to enable PWM generator0 timer equal a event generate + */ +#define MCPWM_EVT_OP0_TEA_EN (BIT(9)) +#define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) +#define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEA_EN_S 9 +/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; + * set this bit high to enable PWM generator1 timer equal a event generate + */ +#define MCPWM_EVT_OP1_TEA_EN (BIT(10)) +#define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) +#define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEA_EN_S 10 +/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; + * set this bit high to enable PWM generator2 timer equal a event generate + */ +#define MCPWM_EVT_OP2_TEA_EN (BIT(11)) +#define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) +#define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEA_EN_S 11 +/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; + * set this bit high to enable PWM generator0 timer equal b event generate + */ +#define MCPWM_EVT_OP0_TEB_EN (BIT(12)) +#define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) +#define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEB_EN_S 12 +/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; + * set this bit high to enable PWM generator1 timer equal b event generate + */ +#define MCPWM_EVT_OP1_TEB_EN (BIT(13)) +#define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) +#define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEB_EN_S 13 +/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; + * set this bit high to enable PWM generator2 timer equal b event generate + */ +#define MCPWM_EVT_OP2_TEB_EN (BIT(14)) +#define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) +#define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEB_EN_S 14 +/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; + * set this bit high to enable fault0 event generate + */ +#define MCPWM_EVT_F0_EN (BIT(15)) +#define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) +#define MCPWM_EVT_F0_EN_V 0x00000001U +#define MCPWM_EVT_F0_EN_S 15 +/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; + * set this bit high to enable fault1 event generate + */ +#define MCPWM_EVT_F1_EN (BIT(16)) +#define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) +#define MCPWM_EVT_F1_EN_V 0x00000001U +#define MCPWM_EVT_F1_EN_S 16 +/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; + * set this bit high to enable fault2 event generate + */ +#define MCPWM_EVT_F2_EN (BIT(17)) +#define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) +#define MCPWM_EVT_F2_EN_V 0x00000001U +#define MCPWM_EVT_F2_EN_S 17 +/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; + * set this bit high to enable fault0 clear event generate + */ +#define MCPWM_EVT_F0_CLR_EN (BIT(18)) +#define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) +#define MCPWM_EVT_F0_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F0_CLR_EN_S 18 +/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; + * set this bit high to enable fault1 clear event generate + */ +#define MCPWM_EVT_F1_CLR_EN (BIT(19)) +#define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) +#define MCPWM_EVT_F1_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F1_CLR_EN_S 19 +/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; + * set this bit high to enable fault2 clear event generate + */ +#define MCPWM_EVT_F2_CLR_EN (BIT(20)) +#define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) +#define MCPWM_EVT_F2_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F2_CLR_EN_S 20 +/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; + * set this bit high to enable cycle by cycle trip0 event generate + */ +#define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) +#define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) +#define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_CBC_EN_S 21 +/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; + * set this bit high to enable cycle by cycle trip1 event generate + */ +#define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) +#define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) +#define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_CBC_EN_S 22 +/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; + * set this bit high to enable cycle by cycle trip2 event generate + */ +#define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) +#define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) +#define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_CBC_EN_S 23 +/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; + * set this bit high to enable one shot trip0 event generate + */ +#define MCPWM_EVT_TZ0_OST_EN (BIT(24)) +#define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) +#define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_OST_EN_S 24 +/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; + * set this bit high to enable one shot trip1 event generate + */ +#define MCPWM_EVT_TZ1_OST_EN (BIT(25)) +#define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) +#define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_OST_EN_S 25 +/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; + * set this bit high to enable one shot trip2 event generate + */ +#define MCPWM_EVT_TZ2_OST_EN (BIT(26)) +#define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) +#define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_OST_EN_S 26 +/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; + * set this bit high to enable capture0 event generate + */ +#define MCPWM_EVT_CAP0_EN (BIT(27)) +#define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) +#define MCPWM_EVT_CAP0_EN_V 0x00000001U +#define MCPWM_EVT_CAP0_EN_S 27 +/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; + * set this bit high to enable capture1 event generate + */ +#define MCPWM_EVT_CAP1_EN (BIT(28)) +#define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) +#define MCPWM_EVT_CAP1_EN_V 0x00000001U +#define MCPWM_EVT_CAP1_EN_S 28 +/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; + * set this bit high to enable capture2 event generate + */ +#define MCPWM_EVT_CAP2_EN (BIT(29)) +#define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) +#define MCPWM_EVT_CAP2_EN_V 0x00000001U +#define MCPWM_EVT_CAP2_EN_S 29 + +/** MCPWM_TASK_EN_REG register + * MCPWM task enable register + */ +#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124) +/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; + * set this bit high to enable PWM generator0 timer stamp A's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) +#define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) +#define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_A_UP_EN_S 0 +/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; + * set this bit high to enable PWM generator1 timer stamp A's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) +#define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) +#define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_A_UP_EN_S 1 +/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; + * set this bit high to enable PWM generator2 timer stamp A's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) +#define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) +#define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_A_UP_EN_S 2 +/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; + * set this bit high to enable PWM generator0 timer stamp B's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) +#define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) +#define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_B_UP_EN_S 3 +/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; + * set this bit high to enable PWM generator1 timer stamp B's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) +#define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) +#define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_B_UP_EN_S 4 +/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; + * set this bit high to enable PWM generator2 timer stamp B's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) +#define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) +#define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_B_UP_EN_S 5 +/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; + * set this bit high to enable all PWM generate stop task receive + */ +#define MCPWM_TASK_GEN_STOP_EN (BIT(6)) +#define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) +#define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U +#define MCPWM_TASK_GEN_STOP_EN_S 6 +/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer0 sync task receive + */ +#define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) +#define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) +#define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_SYNC_EN_S 7 +/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer1 sync task receive + */ +#define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) +#define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) +#define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_SYNC_EN_S 8 +/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; + * set this bit high to enable timer2 sync task receive + */ +#define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) +#define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) +#define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_SYNC_EN_S 9 +/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; + * set this bit high to enable timer0 period update task receive + */ +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 +/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; + * set this bit high to enable timer1 period update task receive + */ +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 +/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; + * set this bit high to enable timer2 period update task receive + */ +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 +/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; + * set this bit high to enable one shot trip0 task receive + */ +#define MCPWM_TASK_TZ0_OST_EN (BIT(13)) +#define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) +#define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ0_OST_EN_S 13 +/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; + * set this bit high to enable one shot trip1 task receive + */ +#define MCPWM_TASK_TZ1_OST_EN (BIT(14)) +#define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) +#define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ1_OST_EN_S 14 +/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; + * set this bit high to enable one shot trip2 task receive + */ +#define MCPWM_TASK_TZ2_OST_EN (BIT(15)) +#define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) +#define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ2_OST_EN_S 15 +/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; + * set this bit high to enable one shot trip0 clear task receive + */ +#define MCPWM_TASK_CLR0_OST_EN (BIT(16)) +#define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) +#define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR0_OST_EN_S 16 +/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; + * set this bit high to enable one shot trip1 clear task receive + */ +#define MCPWM_TASK_CLR1_OST_EN (BIT(17)) +#define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) +#define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR1_OST_EN_S 17 +/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; + * set this bit high to enable one shot trip2 clear task receive + */ +#define MCPWM_TASK_CLR2_OST_EN (BIT(18)) +#define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) +#define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR2_OST_EN_S 18 +/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; + * set this bit high to enable capture0 task receive + */ +#define MCPWM_TASK_CAP0_EN (BIT(19)) +#define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) +#define MCPWM_TASK_CAP0_EN_V 0x00000001U +#define MCPWM_TASK_CAP0_EN_S 19 +/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; + * set this bit high to enable capture1 task receive + */ +#define MCPWM_TASK_CAP1_EN (BIT(20)) +#define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) +#define MCPWM_TASK_CAP1_EN_V 0x00000001U +#define MCPWM_TASK_CAP1_EN_S 20 +/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; + * set this bit high to enable capture2 task receive + */ +#define MCPWM_TASK_CAP2_EN (BIT(21)) +#define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) +#define MCPWM_TASK_CAP2_EN_V 0x00000001U +#define MCPWM_TASK_CAP2_EN_S 21 + +/** MCPWM_CLK_REG register + * MCPWM APB configuration register + */ +#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x128) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U +#define MCPWM_CLK_EN_S 0 + +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x12c) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256; + * Version of this register file + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU +#define MCPWM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/mcpwm_struct.h b/components/soc/esp32h2/include/soc/mcpwm_struct.h new file mode 100644 index 0000000000..1a91a623f6 --- /dev/null +++ b/components/soc/esp32h2/include/soc/mcpwm_struct.h @@ -0,0 +1,1694 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Prescaler configuration */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ + uint32_t clk_prescale:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + + +/** Group: MCPWM Timer Configuration and status */ +/** Type of timer_cfg0 register + * PWM timer period and update method configuration register. + */ +typedef union { + struct { + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1) + */ + uint32_t timer_prescale:8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer + */ + uint32_t timer_period:16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ + uint32_t timer_period_upmethod:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} mcpwm_timer_cfg0_reg_t; + +/** Type of timer_cfg1 register + * PWM timer0 working mode and start/stop control configuration register. + */ +typedef union { + struct { + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer + * starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ + uint32_t timer_start:3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; + * PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ + uint32_t timer_mod:2; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_timer_cfg1_reg_t; + +/** Type of timer_sync register + * PWM timer sync function configuration register. + */ +typedef union { + struct { + /** timer_synci_en : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ + uint32_t timer_synci_en:1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ + uint32_t timer_sync_sw:1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; + * PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ + uint32_t timer_synco_sel:2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ + uint32_t timer_phase:16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction when timer mode is up-down mode: + * 0-increase,1-decrease + */ + uint32_t timer_phase_direction:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} mcpwm_timer_sync_reg_t; + +/** Type of timer_status register + * PWM timer status register. + */ +typedef union { + struct { + /** timer_value : RO; bitpos: [15:0]; default: 0; + * current PWM timer counter value + */ + uint32_t timer_value:16; + /** timer_direction : RO; bitpos: [16]; default: 0; + * current PWM timer counter direction, 0: increment 1: decrement + */ + uint32_t timer_direction:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} mcpwm_timer_status_reg_t; + + +/** Group: Common configuration for MCPWM timers */ +/** Type of timer_synci_cfg register + * Synchronization input selection for three PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer0_syncisel:3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer1_syncisel:3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer2_syncisel:3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ + uint32_t external_synci0_invert:1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ + uint32_t external_synci1_invert:1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ + uint32_t external_synci2_invert:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * Select specific timer for PWM operators. + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator0_timersel:2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator1_timersel:2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator2_timersel:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: MCPWM Operator Configuration and Status */ +/** Type of gen_stmp_cfg register + * Transfer status and update method for time stamp registers A and B + */ +typedef union { + struct { + /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t cmpr_a_upmethod:4; + /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t cmpr_b_upmethod:4; + /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ + uint32_t cmpr_a_shdw_full:1; + /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ + uint32_t cmpr_b_shdw_full:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_gen_stmp_cfg_reg_t; + +/** Type of gen_tstmp register + * Shadow register for register B. + */ +typedef union { + struct { + /** cmpr : R/W; bitpos: [15:0]; default: 0; + * PWM generator time stamp's shadow register + */ + uint32_t cmpr:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_gen_tstmp_reg_t; + +/** Type of gen_cfg0 register + * Fault event T0 and T1 handling + */ +typedef union { + struct { + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ + uint32_t gen_cfg_upmethod:4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t0_sel:3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t1_sel:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_gen_cfg0_reg_t; + +/** Type of gen_force register + * Permissives to force PWM0A and PWM0B outputs by software + */ +typedef union { + struct { + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ + uint32_t gen_cntuforce_upmethod:6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_a_cntuforce_mode:2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_b_cntuforce_mode:2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWMnA, a toggle will + * trigger a force event. + */ + uint32_t gen_a_nciforce:1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_a_nciforce_mode:2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWMnB, a toggle will + * trigger a force event. + */ + uint32_t gen_b_nciforce:1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_b_nciforce_mode:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_gen_force_reg_t; + +/** Type of gen register + * Actions triggered by events on PWM0B + */ +typedef union { + struct { + /** gen_utez : R/W; bitpos: [1:0]; default: 0; + * Action on PWMnA/B triggered by event TEZ when timer increasing + */ + uint32_t gen_utez:2; + /** gen_utep : R/W; bitpos: [3:2]; default: 0; + * Action on PWMnA/B triggered by event TEP when timer increasing + */ + uint32_t gen_utep:2; + /** gen_utea : R/W; bitpos: [5:4]; default: 0; + * Action on PWMnA/B triggered by event TEA when timer increasing + */ + uint32_t gen_utea:2; + /** gen_uteb : R/W; bitpos: [7:6]; default: 0; + * Action on PWMnA/B triggered by event TEB when timer increasing + */ + uint32_t gen_uteb:2; + /** gen_ut0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWMnA/B triggered by event_t0 when timer increasing + */ + uint32_t gen_ut0:2; + /** gen_ut1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWMnA/B triggered by event_t1 when timer increasing + */ + uint32_t gen_ut1:2; + /** gen_dtez : R/W; bitpos: [13:12]; default: 0; + * Action on PWMnA/B triggered by event TEZ when timer decreasing + */ + uint32_t gen_dtez:2; + /** gen_dtep : R/W; bitpos: [15:14]; default: 0; + * Action on PWMnA/B triggered by event TEP when timer decreasing + */ + uint32_t gen_dtep:2; + /** gen_dtea : R/W; bitpos: [17:16]; default: 0; + * Action on PWMnA/B triggered by event TEA when timer decreasing + */ + uint32_t gen_dtea:2; + /** gen_dteb : R/W; bitpos: [19:18]; default: 0; + * Action on PWMnA/B triggered by event TEB when timer decreasing + */ + uint32_t gen_dteb:2; + /** gen_dt0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWMnA/B triggered by event_t0 when timer decreasing + */ + uint32_t gen_dt0:2; + /** gen_dt1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_gen_reg_t; + +/** Type of dt_cfg register + * dead time type selection and configuration + */ +typedef union { + struct { + /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t db_fed_upmethod:4; + /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t db_red_upmethod:4; + /** db_deb_mode : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t db_deb_mode:1; + /** db_a_outswap : R/W; bitpos: [9]; default: 0; + * S6 in table + */ + uint32_t db_a_outswap:1; + /** db_b_outswap : R/W; bitpos: [10]; default: 0; + * S7 in table + */ + uint32_t db_b_outswap:1; + /** db_red_insel : R/W; bitpos: [11]; default: 0; + * S4 in table + */ + uint32_t db_red_insel:1; + /** db_fed_insel : R/W; bitpos: [12]; default: 0; + * S5 in table + */ + uint32_t db_fed_insel:1; + /** db_red_outinvert : R/W; bitpos: [13]; default: 0; + * S2 in table + */ + uint32_t db_red_outinvert:1; + /** db_fed_outinvert : R/W; bitpos: [14]; default: 0; + * S3 in table + */ + uint32_t db_fed_outinvert:1; + /** db_a_outbypass : R/W; bitpos: [15]; default: 1; + * S1 in table + */ + uint32_t db_a_outbypass:1; + /** db_b_outbypass : R/W; bitpos: [16]; default: 1; + * S0 in table + */ + uint32_t db_b_outbypass:1; + /** db_clk_sel : R/W; bitpos: [17]; default: 0; + * Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk + */ + uint32_t db_clk_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} mcpwm_dt_cfg_reg_t; + +/** Type of dt_fed_cfg register + * Shadow register for falling edge delay (FED). + */ +typedef union { + struct { + /** db_fed : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ + uint32_t db_fed:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dt_fed_cfg_reg_t; + +/** Type of dt_red_cfg register + * Shadow register for rising edge delay (RED). + */ +typedef union { + struct { + /** db_red : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ + uint32_t db_red:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dt_red_cfg_reg_t; + +/** Type of carrier_cfg register + * Carrier enable and configuratoin + */ +typedef union { + struct { + /** chopper_en : R/W; bitpos: [0]; default: 0; + * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + */ + uint32_t chopper_en:1; + /** chopper_prescale : R/W; bitpos: [4:1]; default: 0; + * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ + uint32_t chopper_prescale:4; + /** chopper_duty : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ + uint32_t chopper_duty:3; + /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ + uint32_t chopper_oshtwth:4; + /** chopper_out_invert : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ + uint32_t chopper_out_invert:1; + /** chopper_in_invert : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ + uint32_t chopper_in_invert:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} mcpwm_carrier_cfg_reg_t; + +/** Type of fh_cfg0 register + * Actions on PWM0A and PWM0B trip events + */ +typedef union { + struct { + /** tz_sw_cbc : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_sw_cbc:1; + /** tz_f2_cbc : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_f2_cbc:1; + /** tz_f1_cbc : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_f1_cbc:1; + /** tz_f0_cbc : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_f0_cbc:1; + /** tz_sw_ost : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_sw_ost:1; + /** tz_f2_ost : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_f2_ost:1; + /** tz_f1_ost : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_f1_ost:1; + /** tz_f0_ost : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_f0_ost:1; + /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_cbc_d:2; + /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_cbc_u:2; + /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_ost_d:2; + /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_ost_u:2; + /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_cbc_d:2; + /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_cbc_u:2; + /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_ost_d:2; + /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_ost_u:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_fh_cfg0_reg_t; + +/** Type of fh_cfg1 register + * Software triggers for fault handler actions + */ +typedef union { + struct { + /** tz_clr_ost : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ + uint32_t tz_clr_ost:1; + /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ + uint32_t tz_cbcpulse:2; + /** tz_force_cbc : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ + uint32_t tz_force_cbc:1; + /** tz_force_ost : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ + uint32_t tz_force_ost:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_fh_cfg1_reg_t; + +/** Type of fh_status register + * Status of fault events. + */ +typedef union { + struct { + /** tz_cbc_on : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ + uint32_t tz_cbc_on:1; + /** tz_ost_on : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ + uint32_t tz_ost_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mcpwm_fh_status_reg_t; + + +/** Group: Fault Detection Configuration and Status */ +/** Type of fault_detect register + * Fault detection configuration and status + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * When set, event_f0 generation is enabled + */ + uint32_t f0_en:1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * When set, event_f1 generation is enabled + */ + uint32_t f1_en:1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * When set, event_f2 generation is enabled + */ + uint32_t f2_en:1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ + uint32_t f0_pole:1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ + uint32_t f1_pole:1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ + uint32_t f2_pole:1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, event_f0 is on going + */ + uint32_t event_f0:1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, event_f1 is on going + */ + uint32_t event_f1:1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, event_f2 is on going + */ + uint32_t event_f2:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: Capture Configuration and Status */ +/** Type of cap_timer_cfg register + * Configure capture timer + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ + uint32_t cap_timer_en:1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ + uint32_t cap_synci_en:1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ + uint32_t cap_synci_sel:3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ + uint32_t cap_sync_sw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + +/** Type of cap_timer_phase register + * Phase for capture timer sync + */ +typedef union { + struct { + /** cap_phase : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ + uint32_t cap_phase:32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + +/** Type of cap_chn_cfg register + * Capture channel n configuration and enable + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel n after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + + * 1 + */ + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * when set, CAPn form GPIO matrix is inverted before prescale + */ + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel n + */ + uint32_t capn_sw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + +/** Type of cap_chn register + * chn capture value status register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel n + */ + uint32_t capn_value:32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + +/** Type of cap_status register + * Edge of last capture trigger + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ + uint32_t cap0_edge:1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ + uint32_t cap1_edge:1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ + uint32_t cap2_edge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: Enable update of active registers */ +/** Type of update_cfg register + * Enable update. + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ + uint32_t global_up_en:1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ + uint32_t global_force_up:1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ + uint32_t op0_up_en:1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ + uint32_t op0_force_up:1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ + uint32_t op1_up_en:1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ + uint32_t op1_force_up:1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ + uint32_t op2_up_en:1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ + uint32_t op2_force_up:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: Manage Interrupts */ +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena:1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena:1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena:1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena:1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena:1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena:1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena:1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena:1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena:1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_ena:1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_ena:1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_ena:1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_ena:1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_ena:1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_ena:1; + /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_ena:1; + /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_ena:1; + /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_ena:1; + /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_ena:1; + /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_ena:1; + /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_ena:1; + /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_ena:1; + /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_ena:1; + /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_ena:1; + /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_ena:1; + /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_ena:1; + /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_ena:1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_ena:1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_ena:1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_raw:1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_raw:1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_raw:1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_raw:1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_raw:1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_raw:1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_raw:1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_raw:1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_raw:1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_raw:1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_raw:1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_raw:1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_raw:1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_raw:1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_raw:1; + /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_raw:1; + /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_raw:1; + /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_raw:1; + /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_raw:1; + /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_raw:1; + /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_raw:1; + /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t tz0_cbc_int_raw:1; + /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t tz1_cbc_int_raw:1; + /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t tz2_cbc_int_raw:1; + /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_raw:1; + /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_raw:1; + /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_raw:1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_raw:1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_raw:1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_st:1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_st:1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_st:1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st:1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st:1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st:1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_st:1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_st:1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_st:1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_st:1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_st:1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_st:1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_st:1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_st:1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_st:1; + /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_st:1; + /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_st:1; + /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_st:1; + /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_st:1; + /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_st:1; + /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_st:1; + /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t tz0_cbc_int_st:1; + /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t tz1_cbc_int_st:1; + /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t tz2_cbc_int_st:1; + /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_st:1; + /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_st:1; + /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_st:1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_st:1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_st:1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr:1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr:1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr:1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr:1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr:1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr:1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr:1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr:1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr:1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_clr:1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_clr:1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_clr:1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_clr:1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_clr:1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_clr:1; + /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_clr:1; + /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_clr:1; + /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_clr:1; + /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_clr:1; + /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_clr:1; + /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_clr:1; + /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t tz0_cbc_int_clr:1; + /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t tz1_cbc_int_clr:1; + /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t tz2_cbc_int_clr:1; + /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_clr:1; + /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_clr:1; + /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_clr:1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_clr:1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_clr:1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: MCPWM event enable register */ +/** Type of evt_en register + * MCPWM event enable register + */ +typedef union { + struct { + /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; + * set this bit high to enable timer0 stop event generate + */ + uint32_t evt_timer0_stop_en:1; + /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; + * set this bit high to enable timer1 stop event generate + */ + uint32_t evt_timer1_stop_en:1; + /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; + * set this bit high to enable timer2 stop event generate + */ + uint32_t evt_timer2_stop_en:1; + /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; + * set this bit high to enable timer0 equal zero event generate + */ + uint32_t evt_timer0_tez_en:1; + /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; + * set this bit high to enable timer1 equal zero event generate + */ + uint32_t evt_timer1_tez_en:1; + /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; + * set this bit high to enable timer2 equal zero event generate + */ + uint32_t evt_timer2_tez_en:1; + /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; + * set this bit high to enable timer0 equal period event generate + */ + uint32_t evt_timer0_tep_en:1; + /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer1 equal period event generate + */ + uint32_t evt_timer1_tep_en:1; + /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer2 equal period event generate + */ + uint32_t evt_timer2_tep_en:1; + /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; + * set this bit high to enable PWM generator0 timer equal a event generate + */ + uint32_t evt_op0_tea_en:1; + /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; + * set this bit high to enable PWM generator1 timer equal a event generate + */ + uint32_t evt_op1_tea_en:1; + /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; + * set this bit high to enable PWM generator2 timer equal a event generate + */ + uint32_t evt_op2_tea_en:1; + /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; + * set this bit high to enable PWM generator0 timer equal b event generate + */ + uint32_t evt_op0_teb_en:1; + /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; + * set this bit high to enable PWM generator1 timer equal b event generate + */ + uint32_t evt_op1_teb_en:1; + /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; + * set this bit high to enable PWM generator2 timer equal b event generate + */ + uint32_t evt_op2_teb_en:1; + /** evt_f0_en : R/W; bitpos: [15]; default: 0; + * set this bit high to enable fault0 event generate + */ + uint32_t evt_f0_en:1; + /** evt_f1_en : R/W; bitpos: [16]; default: 0; + * set this bit high to enable fault1 event generate + */ + uint32_t evt_f1_en:1; + /** evt_f2_en : R/W; bitpos: [17]; default: 0; + * set this bit high to enable fault2 event generate + */ + uint32_t evt_f2_en:1; + /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; + * set this bit high to enable fault0 clear event generate + */ + uint32_t evt_f0_clr_en:1; + /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; + * set this bit high to enable fault1 clear event generate + */ + uint32_t evt_f1_clr_en:1; + /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; + * set this bit high to enable fault2 clear event generate + */ + uint32_t evt_f2_clr_en:1; + /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; + * set this bit high to enable cycle by cycle trip0 event generate + */ + uint32_t evt_tz0_cbc_en:1; + /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; + * set this bit high to enable cycle by cycle trip1 event generate + */ + uint32_t evt_tz1_cbc_en:1; + /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; + * set this bit high to enable cycle by cycle trip2 event generate + */ + uint32_t evt_tz2_cbc_en:1; + /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; + * set this bit high to enable one shot trip0 event generate + */ + uint32_t evt_tz0_ost_en:1; + /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; + * set this bit high to enable one shot trip1 event generate + */ + uint32_t evt_tz1_ost_en:1; + /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; + * set this bit high to enable one shot trip2 event generate + */ + uint32_t evt_tz2_ost_en:1; + /** evt_cap0_en : R/W; bitpos: [27]; default: 0; + * set this bit high to enable capture0 event generate + */ + uint32_t evt_cap0_en:1; + /** evt_cap1_en : R/W; bitpos: [28]; default: 0; + * set this bit high to enable capture1 event generate + */ + uint32_t evt_cap1_en:1; + /** evt_cap2_en : R/W; bitpos: [29]; default: 0; + * set this bit high to enable capture2 event generate + */ + uint32_t evt_cap2_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_evt_en_reg_t; + + +/** Group: MCPWM task enable register */ +/** Type of task_en register + * MCPWM task enable register + */ +typedef union { + struct { + /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; + * set this bit high to enable PWM generator0 timer stamp A's shadow register update + * task receive + */ + uint32_t task_cmpr0_a_up_en:1; + /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; + * set this bit high to enable PWM generator1 timer stamp A's shadow register update + * task receive + */ + uint32_t task_cmpr1_a_up_en:1; + /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; + * set this bit high to enable PWM generator2 timer stamp A's shadow register update + * task receive + */ + uint32_t task_cmpr2_a_up_en:1; + /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; + * set this bit high to enable PWM generator0 timer stamp B's shadow register update + * task receive + */ + uint32_t task_cmpr0_b_up_en:1; + /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; + * set this bit high to enable PWM generator1 timer stamp B's shadow register update + * task receive + */ + uint32_t task_cmpr1_b_up_en:1; + /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; + * set this bit high to enable PWM generator2 timer stamp B's shadow register update + * task receive + */ + uint32_t task_cmpr2_b_up_en:1; + /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; + * set this bit high to enable all PWM generate stop task receive + */ + uint32_t task_gen_stop_en:1; + /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer0 sync task receive + */ + uint32_t task_timer0_sync_en:1; + /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer1 sync task receive + */ + uint32_t task_timer1_sync_en:1; + /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; + * set this bit high to enable timer2 sync task receive + */ + uint32_t task_timer2_sync_en:1; + /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; + * set this bit high to enable timer0 period update task receive + */ + uint32_t task_timer0_period_up_en:1; + /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; + * set this bit high to enable timer1 period update task receive + */ + uint32_t task_timer1_period_up_en:1; + /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; + * set this bit high to enable timer2 period update task receive + */ + uint32_t task_timer2_period_up_en:1; + /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; + * set this bit high to enable one shot trip0 task receive + */ + uint32_t task_tz0_ost_en:1; + /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; + * set this bit high to enable one shot trip1 task receive + */ + uint32_t task_tz1_ost_en:1; + /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; + * set this bit high to enable one shot trip2 task receive + */ + uint32_t task_tz2_ost_en:1; + /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; + * set this bit high to enable one shot trip0 clear task receive + */ + uint32_t task_clr0_ost_en:1; + /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; + * set this bit high to enable one shot trip1 clear task receive + */ + uint32_t task_clr1_ost_en:1; + /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; + * set this bit high to enable one shot trip2 clear task receive + */ + uint32_t task_clr2_ost_en:1; + /** task_cap0_en : R/W; bitpos: [19]; default: 0; + * set this bit high to enable capture0 task receive + */ + uint32_t task_cap0_en:1; + /** task_cap1_en : R/W; bitpos: [20]; default: 0; + * set this bit high to enable capture1 task receive + */ + uint32_t task_cap1_en:1; + /** task_cap2_en : R/W; bitpos: [21]; default: 0; + * set this bit high to enable capture2 task receive + */ + uint32_t task_cap2_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} mcpwm_task_en_reg_t; + + +/** Group: MCPWM APB configuration register */ +/** Type of clk register + * MCPWM APB configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35656256; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mcpwm_version_reg_t; + +typedef struct { + mcpwm_timer_cfg0_reg_t timer_cfg0; + mcpwm_timer_cfg1_reg_t timer_cfg1; + mcpwm_timer_sync_reg_t timer_sync; + mcpwm_timer_status_reg_t timer_status; +} mcpwm_timer_regs_t; + +typedef struct { + mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; + mcpwm_gen_tstmp_reg_t timestamp[2]; + mcpwm_gen_cfg0_reg_t gen_cfg0; + mcpwm_gen_force_reg_t gen_force; + mcpwm_gen_reg_t generator[2]; + mcpwm_dt_cfg_reg_t dt_cfg; + mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; + mcpwm_dt_red_cfg_reg_t dt_red_cfg; + mcpwm_carrier_cfg_reg_t carrier_cfg; + mcpwm_fh_cfg0_reg_t fh_cfg0; + mcpwm_fh_cfg1_reg_t fh_cfg1; + mcpwm_fh_status_reg_t fh_status; +} mcpwm_operator_reg_t; + +typedef struct mcpwm_dev_t { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timer_regs_t timer[3]; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_operator_reg_t operators[3]; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_evt_en_reg_t evt_en; + volatile mcpwm_task_en_reg_t task_en; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM0; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/mem_monitor_reg.h b/components/soc/esp32h2/include/soc/mem_monitor_reg.h new file mode 100644 index 0000000000..bbddf93b89 --- /dev/null +++ b/components/soc/esp32h2/include/soc/mem_monitor_reg.h @@ -0,0 +1,184 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MEM_MONITOR_LOG_SETTING_REG register + * log config regsiter + */ +#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) +/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0; + * enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu + */ +#define MEM_MONITOR_LOG_ENA 0x00000007U +#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S) +#define MEM_MONITOR_LOG_ENA_V 0x00000007U +#define MEM_MONITOR_LOG_ENA_S 0 +/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0; + * This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: + * HALFWORD monitor, 4'b1000: BYTE monitor. + */ +#define MEM_MONITOR_LOG_MODE 0x0000000FU +#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) +#define MEM_MONITOR_LOG_MODE_V 0x0000000FU +#define MEM_MONITOR_LOG_MODE_S 3 +/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7)) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7 + +/** MEM_MONITOR_LOG_CHECK_DATA_REG register + * check data regsiter + */ +#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4) +/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ +#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S) +#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_S 0 + +/** MEM_MONITOR_LOG_DATA_MASK_REG register + * check data mask register + */ +#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8) +/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ +#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) +#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_S 0 + +/** MEM_MONITOR_LOG_MIN_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc) +/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ +#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S) +#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_S 0 + +/** MEM_MONITOR_LOG_MAX_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10) +/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ +#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S) +#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_S 0 + +/** MEM_MONITOR_LOG_MEM_START_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14) +/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S) +#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_S 0 + +/** MEM_MONITOR_LOG_MEM_END_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18) +/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S) +#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_S 0 + +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register + * current writing address. + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S) +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 + +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register + * writing address update + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20) +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 + +/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register + * full flag status register + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24) +/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 +/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 + +/** MEM_MONITOR_CLOCK_GATE_REG register + * clock gate force on register + */ +#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28) +/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ +#define MEM_MONITOR_CLK_EN (BIT(0)) +#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) +#define MEM_MONITOR_CLK_EN_V 0x00000001U +#define MEM_MONITOR_CLK_EN_S 0 + +/** MEM_MONITOR_DATE_REG register + * version register + */ +#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc) +/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096; + * version register + */ +#define MEM_MONITOR_DATE 0x0FFFFFFFU +#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S) +#define MEM_MONITOR_DATE_V 0x0FFFFFFFU +#define MEM_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/mem_monitor_struct.h b/components/soc/esp32h2/include/soc/mem_monitor_struct.h new file mode 100644 index 0000000000..8d4628467f --- /dev/null +++ b/components/soc/esp32h2/include/soc/mem_monitor_struct.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of log_setting register + * log config regsiter + */ +typedef union { + struct { + /** log_ena : R/W; bitpos: [2:0]; default: 0; + * enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu + */ + uint32_t log_ena:3; + /** log_mode : R/W; bitpos: [6:3]; default: 0; + * This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: + * HALFWORD monitor, 4'b1000: BYTE monitor. + */ + uint32_t log_mode:4; + /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ + uint32_t log_mem_loop_enable:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mem_monitor_log_setting_reg_t; + +/** Type of log_check_data register + * check data regsiter + */ +typedef union { + struct { + /** log_check_data : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ + uint32_t log_check_data:32; + }; + uint32_t val; +} mem_monitor_log_check_data_reg_t; + +/** Type of log_data_mask register + * check data mask register + */ +typedef union { + struct { + /** log_data_mask : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ + uint32_t log_data_mask:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} mem_monitor_log_data_mask_reg_t; + +/** Type of log_min register + * log boundary regsiter + */ +typedef union { + struct { + /** log_min : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ + uint32_t log_min:32; + }; + uint32_t val; +} mem_monitor_log_min_reg_t; + +/** Type of log_max register + * log boundary regsiter + */ +typedef union { + struct { + /** log_max : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ + uint32_t log_max:32; + }; + uint32_t val; +} mem_monitor_log_max_reg_t; + +/** Type of log_mem_start register + * log message store range register + */ +typedef union { + struct { + /** log_mem_start : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ + uint32_t log_mem_start:32; + }; + uint32_t val; +} mem_monitor_log_mem_start_reg_t; + +/** Type of log_mem_end register + * log message store range register + */ +typedef union { + struct { + /** log_mem_end : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ + uint32_t log_mem_end:32; + }; + uint32_t val; +} mem_monitor_log_mem_end_reg_t; + +/** Type of log_mem_current_addr register + * current writing address. + */ +typedef union { + struct { + /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ + uint32_t log_mem_current_addr:32; + }; + uint32_t val; +} mem_monitor_log_mem_current_addr_reg_t; + +/** Type of log_mem_addr_update register + * writing address update + */ +typedef union { + struct { + /** log_mem_addr_update : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ + uint32_t log_mem_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_log_mem_addr_update_reg_t; + +/** Type of log_mem_full_flag register + * full flag status register + */ +typedef union { + struct { + /** log_mem_full_flag : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ + uint32_t log_mem_full_flag:1; + /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ + uint32_t clr_log_mem_full_flag:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mem_monitor_log_mem_full_flag_reg_t; + + +/** Group: clk register */ +/** Type of clock_gate register + * clock gate force on register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_clock_gate_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35660096; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mem_monitor_date_reg_t; + + +typedef struct { + volatile mem_monitor_log_setting_reg_t log_setting; + volatile mem_monitor_log_check_data_reg_t log_check_data; + volatile mem_monitor_log_data_mask_reg_t log_data_mask; + volatile mem_monitor_log_min_reg_t log_min; + volatile mem_monitor_log_max_reg_t log_max; + volatile mem_monitor_log_mem_start_reg_t log_mem_start; + volatile mem_monitor_log_mem_end_reg_t log_mem_end; + volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr; + volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update; + volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag; + volatile mem_monitor_clock_gate_reg_t clock_gate; + uint32_t reserved_02c[244]; + volatile mem_monitor_date_reg_t date; +} mem_monitor_dev_t; + +extern mem_monitor_dev_t MEM_MONITOR; + +#ifndef __cplusplus +_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/memprot_defs.h b/components/soc/esp32h2/include/soc/memprot_defs.h new file mode 100644 index 0000000000..447ad17e3b --- /dev/null +++ b/components/soc/esp32h2/include/soc/memprot_defs.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc.h" +#include "esp32h2/rom/cache.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct { + uint32_t cat0 : 2; + uint32_t cat1 : 2; + uint32_t cat2 : 2; + uint32_t res0 : 8; + uint32_t splitaddr : 8; + uint32_t res1 : 10; + }; + uint32_t val; +} constrain_reg_fields_t; + +#ifndef I_D_SRAM_SEGMENT_SIZE +#define I_D_SRAM_SEGMENT_SIZE 0x20000 +#endif + +#define I_D_SPLIT_LINE_SHIFT 0x9 +#define I_D_FAULT_ADDR_SHIFT 0x2 + +#define DRAM_SRAM_START 0x3FC7C000 + +//IRAM0 + +//16kB (ICACHE) +#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 +#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF + +//128kB (LEVEL 1) +#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 +#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF + +//128kB (LEVEL 2) +#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 +#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF + +//128kB (LEVEL 3) +#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 +#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF + +//permission bits +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 + +//DRAM0 + +//16kB ICACHE not available from DRAM0 + +//128kB (LEVEL 1) +#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 +#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF + +//128kB (LEVEL 2) +#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 +#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF + +//128kB (LEVEL 3) +#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 +#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 + +//RTC FAST + +//permission bits +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 + +#define AREA_LOW 0 +#define AREA_HIGH 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/mmu.h b/components/soc/esp32h2/include/soc/mmu.h new file mode 100644 index 0000000000..4ce5d7326f --- /dev/null +++ b/components/soc/esp32h2/include/soc/mmu.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/ext_mem_defs.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 1 +#define SOC_MMU_PAGES_PER_REGION 256 +#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK (MMU_VALID - 1) +#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START +#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/parl_io_reg.h b/components/soc/esp32h2/include/soc/parl_io_reg.h new file mode 100644 index 0000000000..810530ded7 --- /dev/null +++ b/components/soc/esp32h2/include/soc/parl_io_reg.h @@ -0,0 +1,472 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PARL_IO_RX_MODE_CFG_REG register + * Parallel RX Sampling mode configuration register. + */ +#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0) +/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ +#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S) +#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_S 21 +/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable data sampling by software. + */ +#define PARL_IO_RX_SW_EN (BIT(25)) +#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S) +#define PARL_IO_RX_SW_EN_V 0x00000001U +#define PARL_IO_RX_SW_EN_S 25 +/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0; + * Set this bit to invert the external enable signal. + */ +#define PARL_IO_RX_EXT_EN_INV (BIT(26)) +#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S) +#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U +#define PARL_IO_RX_EXT_EN_INV_S 26 +/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 4'd0: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 4'd1: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 4'd4: positive pulse start(data bit included) && length end + * 4'd5: positive pulse start(data bit excluded) && length end + */ +#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S) +#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27 +/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 2'b00: external level enable mode + * 2'b01: external pulse enable mode + * 2'b10: internal software enable mode + */ +#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S) +#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_S 30 + +/** PARL_IO_RX_DATA_CFG_REG register + * Parallel RX data configuration register. + */ +#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4) +/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ +#define PARL_IO_RX_BITLEN 0x0007FFFFU +#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S) +#define PARL_IO_RX_BITLEN_V 0x0007FFFFU +#define PARL_IO_RX_BITLEN_S 9 +/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + */ +#define PARL_IO_RX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S) +#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_RX_DATA_ORDER_INV_S 28 +/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ +#define PARL_IO_RX_BUS_WID_SEL 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S) +#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_S 29 + +/** PARL_IO_RX_GENRL_CFG_REG register + * Parallel RX general configuration register. + */ +#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8) +/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0; + * Set this bit to enable the clock gating of output rx clock. + */ +#define PARL_IO_RX_GATING_EN (BIT(12)) +#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S) +#define PARL_IO_RX_GATING_EN_V 0x00000001U +#define PARL_IO_RX_GATING_EN_S 12 +/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ +#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S) +#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_S 13 +/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to enable timeout function to generate error eof. + */ +#define PARL_IO_RX_TIMEOUT_EN (BIT(29)) +#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S) +#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U +#define PARL_IO_RX_TIMEOUT_EN_S 29 +/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte + * length. 1'b1: eof generated by external enable signal. + */ +#define PARL_IO_RX_EOF_GEN_SEL (BIT(30)) +#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S) +#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_RX_EOF_GEN_SEL_S 30 + +/** PARL_IO_RX_START_CFG_REG register + * Parallel RX Start configuration register. + */ +#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc) +/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start rx data sampling. + */ +#define PARL_IO_RX_START (BIT(31)) +#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S) +#define PARL_IO_RX_START_V 0x00000001U +#define PARL_IO_RX_START_S 31 + +/** PARL_IO_TX_DATA_CFG_REG register + * Parallel TX data configuration register. + */ +#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10) +/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ +#define PARL_IO_TX_BITLEN 0x0007FFFFU +#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S) +#define PARL_IO_TX_BITLEN_V 0x0007FFFFU +#define PARL_IO_TX_BITLEN_S 9 +/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + */ +#define PARL_IO_TX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S) +#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_TX_DATA_ORDER_INV_S 28 +/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ +#define PARL_IO_TX_BUS_WID_SEL 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S) +#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_S 29 + +/** PARL_IO_TX_START_CFG_REG register + * Parallel TX Start configuration register. + */ +#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14) +/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start tx data transmit. + */ +#define PARL_IO_TX_START (BIT(31)) +#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S) +#define PARL_IO_TX_START_V 0x00000001U +#define PARL_IO_TX_START_S 31 + +/** PARL_IO_TX_GENRL_CFG_REG register + * Parallel TX general configuration register. + */ +#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18) +/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ +#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S) +#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_S 14 +/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0; + * Set this bit to enable the clock gating of output tx clock. + */ +#define PARL_IO_TX_GATING_EN (BIT(30)) +#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S) +#define PARL_IO_TX_GATING_EN_V 0x00000001U +#define PARL_IO_TX_GATING_EN_S 30 +/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable the output of tx data valid signal. + */ +#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31)) +#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S) +#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U +#define PARL_IO_TX_VALID_OUTPUT_EN_S 31 + +/** PARL_IO_FIFO_CFG_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c) +/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; + * Set this bit to reset async fifo in tx module. + */ +#define PARL_IO_TX_FIFO_SRST (BIT(30)) +#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S) +#define PARL_IO_TX_FIFO_SRST_V 0x00000001U +#define PARL_IO_TX_FIFO_SRST_S 30 +/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0; + * Set this bit to reset async fifo in rx module. + */ +#define PARL_IO_RX_FIFO_SRST (BIT(31)) +#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S) +#define PARL_IO_RX_FIFO_SRST_V 0x00000001U +#define PARL_IO_RX_FIFO_SRST_S 31 + +/** PARL_IO_REG_UPDATE_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20) +/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0; + * Set this bit to update rx register configuration. + */ +#define PARL_IO_RX_REG_UPDATE (BIT(31)) +#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S) +#define PARL_IO_RX_REG_UPDATE_V 0x00000001U +#define PARL_IO_RX_REG_UPDATE_S 31 + +/** PARL_IO_ST_REG register + * Parallel IO module status register0. + */ +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24) +/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ +#define PARL_IO_TX_READY (BIT(31)) +#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S) +#define PARL_IO_TX_READY_V 0x00000001U +#define PARL_IO_TX_READY_S 31 + +/** PARL_IO_INT_ENA_REG register + * Parallel IO interrupt enable singal configuration register. + */ +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) +/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1 +/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ENA (BIT(2)) +#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S) +#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ENA_S 2 + +/** PARL_IO_INT_RAW_REG register + * Parallel IO interrupt raw singal status register. + */ +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) +/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1 +/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_RAW (BIT(2)) +#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S) +#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U +#define PARL_IO_TX_EOF_INT_RAW_S 2 + +/** PARL_IO_INT_ST_REG register + * Parallel IO interrupt singal status register. + */ +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) +/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1 +/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ST (BIT(2)) +#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S) +#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ST_S 2 + +/** PARL_IO_INT_CLR_REG register + * Parallel IO interrupt clear singal configuration register. + */ +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) +/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1 +/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_CLR (BIT(2)) +#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S) +#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U +#define PARL_IO_TX_EOF_INT_CLR_S 2 + +/** PARL_IO_RX_ST0_REG register + * Parallel IO RX status register0 + */ +#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38) +/** PARL_IO_RX_CNT : RO; bitpos: [12:9]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ +#define PARL_IO_RX_CNT 0x0000000FU +#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S) +#define PARL_IO_RX_CNT_V 0x0000000FU +#define PARL_IO_RX_CNT_S 9 +/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ +#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S) +#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13 + +/** PARL_IO_RX_ST1_REG register + * Parallel IO RX status register1 + */ +#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c) +/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ +#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_TX_ST0_REG register + * Parallel IO TX status register0 + */ +#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40) +/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ +#define PARL_IO_TX_CNT 0x0000007FU +#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S) +#define PARL_IO_TX_CNT_V 0x0000007FU +#define PARL_IO_TX_CNT_S 6 +/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ +#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_RX_CLK_CFG_REG register + * Parallel IO RX clk configuration register + */ +#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44) +/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Rx core clock. + */ +#define PARL_IO_RX_CLK_I_INV (BIT(30)) +#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S) +#define PARL_IO_RX_CLK_I_INV_V 0x00000001U +#define PARL_IO_RX_CLK_I_INV_S 30 +/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Rx core clock. + */ +#define PARL_IO_RX_CLK_O_INV (BIT(31)) +#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S) +#define PARL_IO_RX_CLK_O_INV_V 0x00000001U +#define PARL_IO_RX_CLK_O_INV_S 31 + +/** PARL_IO_TX_CLK_CFG_REG register + * Parallel IO TX clk configuration register + */ +#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48) +/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Tx core clock. + */ +#define PARL_IO_TX_CLK_I_INV (BIT(30)) +#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S) +#define PARL_IO_TX_CLK_I_INV_V 0x00000001U +#define PARL_IO_TX_CLK_I_INV_S 30 +/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Tx core clock. + */ +#define PARL_IO_TX_CLK_O_INV (BIT(31)) +#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S) +#define PARL_IO_TX_CLK_O_INV_V 0x00000001U +#define PARL_IO_TX_CLK_O_INV_S 31 + +/** PARL_IO_CLK_REG register + * Parallel IO clk configuration register + */ +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) +/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ +#define PARL_IO_CLK_EN (BIT(31)) +#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S) +#define PARL_IO_CLK_EN_V 0x00000001U +#define PARL_IO_CLK_EN_S 31 + +/** PARL_IO_VERSION_REG register + * Version register. + */ +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) +/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35684928; + * Version of this register file + */ +#define PARL_IO_DATE 0x0FFFFFFFU +#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S) +#define PARL_IO_DATE_V 0x0FFFFFFFU +#define PARL_IO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/parl_io_struct.h b/components/soc/esp32h2/include/soc/parl_io_struct.h new file mode 100644 index 0000000000..b7dd931b8b --- /dev/null +++ b/components/soc/esp32h2/include/soc/parl_io_struct.h @@ -0,0 +1,504 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PARL_IO RX Mode Configuration */ +/** Type of rx_mode_cfg register + * Parallel RX Sampling mode configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ + uint32_t rx_ext_en_sel:4; + /** rx_sw_en : R/W; bitpos: [25]; default: 0; + * Set this bit to enable data sampling by software. + */ + uint32_t rx_sw_en:1; + /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0; + * Set this bit to invert the external enable signal. + */ + uint32_t rx_ext_en_inv:1; + /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 4'd0: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 4'd1: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 4'd4: positive pulse start(data bit included) && length end + * 4'd5: positive pulse start(data bit excluded) && length end + */ + uint32_t rx_pulse_submode_sel:3; + /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 2'b00: external level enable mode + * 2'b01: external pulse enable mode + * 2'b10: internal software enable mode + */ + uint32_t rx_smp_mode_sel:2; + }; + uint32_t val; +} parl_io_rx_mode_cfg_reg_t; + + +/** Group: PARL_IO RX Data Configuration */ +/** Type of rx_data_cfg register + * Parallel RX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** rx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ + uint32_t rx_bitlen:19; + /** rx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + */ + uint32_t rx_data_order_inv:1; + /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ + uint32_t rx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_rx_data_cfg_reg_t; + + +/** Group: PARL_IO RX General Configuration */ +/** Type of rx_genrl_cfg register + * Parallel RX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rx_gating_en : R/W; bitpos: [12]; default: 0; + * Set this bit to enable the clock gating of output rx clock. + */ + uint32_t rx_gating_en:1; + /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ + uint32_t rx_timeout_thres:16; + /** rx_timeout_en : R/W; bitpos: [29]; default: 1; + * Set this bit to enable timeout function to generate error eof. + */ + uint32_t rx_timeout_en:1; + /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte + * length. 1'b1: eof generated by external enable signal. + */ + uint32_t rx_eof_gen_sel:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} parl_io_rx_genrl_cfg_reg_t; + + +/** Group: PARL_IO RX Start Configuration */ +/** Type of rx_start_cfg register + * Parallel RX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start rx data sampling. + */ + uint32_t rx_start:1; + }; + uint32_t val; +} parl_io_rx_start_cfg_reg_t; + + +/** Group: PARL_IO TX Data Configuration */ +/** Type of tx_data_cfg register + * Parallel TX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ + uint32_t tx_bitlen:19; + /** tx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + */ + uint32_t tx_data_order_inv:1; + /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ + uint32_t tx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_tx_data_cfg_reg_t; + + +/** Group: PARL_IO TX Start Configuration */ +/** Type of tx_start_cfg register + * Parallel TX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start tx data transmit. + */ + uint32_t tx_start:1; + }; + uint32_t val; +} parl_io_tx_start_cfg_reg_t; + + +/** Group: PARL_IO TX General Configuration */ +/** Type of tx_genrl_cfg register + * Parallel TX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** tx_idle_value : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ + uint32_t tx_idle_value:16; + /** tx_gating_en : R/W; bitpos: [30]; default: 0; + * Set this bit to enable the clock gating of output tx clock. + */ + uint32_t tx_gating_en:1; + /** tx_valid_output_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable the output of tx data valid signal. + */ + uint32_t tx_valid_output_en:1; + }; + uint32_t val; +} parl_io_tx_genrl_cfg_reg_t; + + +/** Group: PARL_IO FIFO Configuration */ +/** Type of fifo_cfg register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_fifo_srst : R/W; bitpos: [30]; default: 0; + * Set this bit to reset async fifo in tx module. + */ + uint32_t tx_fifo_srst:1; + /** rx_fifo_srst : R/W; bitpos: [31]; default: 0; + * Set this bit to reset async fifo in rx module. + */ + uint32_t rx_fifo_srst:1; + }; + uint32_t val; +} parl_io_fifo_cfg_reg_t; + + +/** Group: PARL_IO Register Update Configuration */ +/** Type of reg_update register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_reg_update : WT; bitpos: [31]; default: 0; + * Set this bit to update rx register configuration. + */ + uint32_t rx_reg_update:1; + }; + uint32_t val; +} parl_io_reg_update_reg_t; + + +/** Group: PARL_IO Status */ +/** Type of st register + * Parallel IO module status register0. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_ready : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ + uint32_t tx_ready:1; + }; + uint32_t val; +} parl_io_st_reg_t; + + +/** Group: PARL_IO Interrupt Configuration and Status */ +/** Type of int_ena register + * Parallel IO interrupt enable singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_ena:1; + /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_ena:1; + /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable TX_EOF_INT. + */ + uint32_t tx_eof_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_ena_reg_t; + +/** Type of int_raw register + * Parallel IO interrupt raw singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_raw:1; + /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_raw:1; + /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_raw_reg_t; + +/** Type of int_st register + * Parallel IO interrupt singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_st:1; + /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_st:1; + /** tx_eof_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_st_reg_t; + +/** Type of int_clr register + * Parallel IO interrupt clear singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_clr:1; + /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_clr:1; + /** tx_eof_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear TX_EOF_INT. + */ + uint32_t tx_eof_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_clr_reg_t; + + +/** Group: PARL_IO Rx Status0 */ +/** Type of rx_st0 register + * Parallel IO RX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** rx_cnt : RO; bitpos: [12:9]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ + uint32_t rx_cnt:4; + /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ + uint32_t rx_fifo_wr_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st0_reg_t; + + +/** Group: PARL_IO Rx Status1 */ +/** Type of rx_st1 register + * Parallel IO RX status register1 + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ + uint32_t rx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st1_reg_t; + + +/** Group: PARL_IO Tx Status0 */ +/** Type of tx_st0 register + * Parallel IO TX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** tx_cnt : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ + uint32_t tx_cnt:7; + /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ + uint32_t tx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_tx_st0_reg_t; + + +/** Group: PARL_IO Rx Clock Configuration */ +/** Type of rx_clk_cfg register + * Parallel IO RX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Rx core clock. + */ + uint32_t rx_clk_i_inv:1; + /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Rx core clock. + */ + uint32_t rx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_rx_clk_cfg_reg_t; + + +/** Group: PARL_IO Tx Clock Configuration */ +/** Type of tx_clk_cfg register + * Parallel IO TX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Tx core clock. + */ + uint32_t tx_clk_i_inv:1; + /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Tx core clock. + */ + uint32_t tx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_tx_clk_cfg_reg_t; + + +/** Group: PARL_IO Clock Configuration */ +/** Type of clk register + * Parallel IO clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + }; + uint32_t val; +} parl_io_clk_reg_t; + + +/** Group: PARL_IO Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684928; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} parl_io_version_reg_t; + + +typedef struct { + volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; + volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; + volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; + volatile parl_io_rx_start_cfg_reg_t rx_start_cfg; + volatile parl_io_tx_data_cfg_reg_t tx_data_cfg; + volatile parl_io_tx_start_cfg_reg_t tx_start_cfg; + volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg; + volatile parl_io_fifo_cfg_reg_t fifo_cfg; + volatile parl_io_reg_update_reg_t reg_update; + volatile parl_io_st_reg_t st; + volatile parl_io_int_ena_reg_t int_ena; + volatile parl_io_int_raw_reg_t int_raw; + volatile parl_io_int_st_reg_t int_st; + volatile parl_io_int_clr_reg_t int_clr; + volatile parl_io_rx_st0_reg_t rx_st0; + volatile parl_io_rx_st1_reg_t rx_st1; + volatile parl_io_tx_st0_reg_t tx_st0; + volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg; + volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg; + uint32_t reserved_04c[53]; + volatile parl_io_clk_reg_t clk; + uint32_t reserved_124[182]; + volatile parl_io_version_reg_t version; +} parl_io_dev_t; + +extern parl_io_dev_t PARL_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pau_reg.h b/components/soc/esp32h2/include/soc/pau_reg.h new file mode 100644 index 0000000000..a2f7ad9a89 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pau_reg.h @@ -0,0 +1,356 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PAU_REGDMA_CONF_REG register + * Peri backup control register + */ +#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) +/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; + * backup error type + */ +#define PAU_FLOW_ERR 0x00000007U +#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) +#define PAU_FLOW_ERR_V 0x00000007U +#define PAU_FLOW_ERR_S 0 +/** PAU_START : WT; bitpos: [3]; default: 0; + * backup start signal + */ +#define PAU_START (BIT(3)) +#define PAU_START_M (PAU_START_V << PAU_START_S) +#define PAU_START_V 0x00000001U +#define PAU_START_S 3 +/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM (BIT(4)) +#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) +#define PAU_TO_MEM_V 0x00000001U +#define PAU_TO_MEM_S 4 +/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; + * Link select + */ +#define PAU_LINK_SEL 0x00000003U +#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) +#define PAU_LINK_SEL_V 0x00000003U +#define PAU_LINK_SEL_S 5 +/** PAU_START_MAC : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ +#define PAU_START_MAC (BIT(7)) +#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) +#define PAU_START_MAC_V 0x00000001U +#define PAU_START_MAC_S 7 +/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM_MAC (BIT(8)) +#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) +#define PAU_TO_MEM_MAC_V 0x00000001U +#define PAU_TO_MEM_MAC_S 8 +/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ +#define PAU_SEL_MAC (BIT(9)) +#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) +#define PAU_SEL_MAC_V 0x00000001U +#define PAU_SEL_MAC_S 9 + +/** PAU_REGDMA_CLK_CONF_REG register + * Clock control register + */ +#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) +/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define PAU_CLK_EN (BIT(0)) +#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) +#define PAU_CLK_EN_V 0x00000001U +#define PAU_CLK_EN_S 0 + +/** PAU_REGDMA_ETM_CTRL_REG register + * ETM start ctrl reg + */ +#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) +/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ +#define PAU_ETM_START_0 (BIT(0)) +#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) +#define PAU_ETM_START_0_V 0x00000001U +#define PAU_ETM_START_0_S 0 +/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ +#define PAU_ETM_START_1 (BIT(1)) +#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) +#define PAU_ETM_START_1_V 0x00000001U +#define PAU_ETM_START_1_S 1 +/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ +#define PAU_ETM_START_2 (BIT(2)) +#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) +#define PAU_ETM_START_2_V 0x00000001U +#define PAU_ETM_START_2_S 2 +/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ +#define PAU_ETM_START_3 (BIT(3)) +#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) +#define PAU_ETM_START_3_V 0x00000001U +#define PAU_ETM_START_3_S 3 + +/** PAU_REGDMA_LINK_0_ADDR_REG register + * link_0_addr + */ +#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) +/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ +#define PAU_LINK_ADDR_0 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) +#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_S 0 + +/** PAU_REGDMA_LINK_1_ADDR_REG register + * Link_1_addr + */ +#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) +/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ +#define PAU_LINK_ADDR_1 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) +#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_S 0 + +/** PAU_REGDMA_LINK_2_ADDR_REG register + * Link_2_addr + */ +#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) +/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ +#define PAU_LINK_ADDR_2 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) +#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_S 0 + +/** PAU_REGDMA_LINK_3_ADDR_REG register + * Link_3_addr + */ +#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) +/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ +#define PAU_LINK_ADDR_3 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) +#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_S 0 + +/** PAU_REGDMA_LINK_MAC_ADDR_REG register + * Link_mac_addr + */ +#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) +/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ +#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) +#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_S 0 + +/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register + * current link addr + */ +#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) +/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ +#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) +#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_S 0 + +/** PAU_REGDMA_BACKUP_ADDR_REG register + * Backup addr + */ +#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) +/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ +#define PAU_BACKUP_ADDR 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) +#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_S 0 + +/** PAU_REGDMA_MEM_ADDR_REG register + * mem addr + */ +#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) +/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ +#define PAU_MEM_ADDR 0xFFFFFFFFU +#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) +#define PAU_MEM_ADDR_V 0xFFFFFFFFU +#define PAU_MEM_ADDR_S 0 + +/** PAU_REGDMA_BKP_CONF_REG register + * backup config + */ +#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) +/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ +#define PAU_READ_INTERVAL 0x0000007FU +#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) +#define PAU_READ_INTERVAL_V 0x0000007FU +#define PAU_READ_INTERVAL_S 0 +/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ +#define PAU_LINK_TOUT_THRES 0x000003FFU +#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) +#define PAU_LINK_TOUT_THRES_V 0x000003FFU +#define PAU_LINK_TOUT_THRES_S 7 +/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ +#define PAU_BURST_LIMIT 0x0000001FU +#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) +#define PAU_BURST_LIMIT_V 0x0000001FU +#define PAU_BURST_LIMIT_S 17 +/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ +#define PAU_BACKUP_TOUT_THRES 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) +#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_S 22 + +/** PAU_RETENTION_LINK_BASE_REG register + * retention dma link base + */ +#define PAU_RETENTION_LINK_BASE_REG (DR_REG_PAU_BASE + 0x30) +/** PAU_LINK_BASE_ADDR : R/W; bitpos: [26:0]; default: 0; + * retention dma link base + */ +#define PAU_LINK_BASE_ADDR 0x07FFFFFFU +#define PAU_LINK_BASE_ADDR_M (PAU_LINK_BASE_ADDR_V << PAU_LINK_BASE_ADDR_S) +#define PAU_LINK_BASE_ADDR_V 0x07FFFFFFU +#define PAU_LINK_BASE_ADDR_S 0 + +/** PAU_RETENTION_CFG_REG register + * retention_cfg + */ +#define PAU_RETENTION_CFG_REG (DR_REG_PAU_BASE + 0x34) +/** PAU_RET_INV_CFG : R/W; bitpos: [31:0]; default: 4294967295; + * retention inv scan out + */ +#define PAU_RET_INV_CFG 0xFFFFFFFFU +#define PAU_RET_INV_CFG_M (PAU_RET_INV_CFG_V << PAU_RET_INV_CFG_S) +#define PAU_RET_INV_CFG_V 0xFFFFFFFFU +#define PAU_RET_INV_CFG_S 0 + +/** PAU_INT_ENA_REG register + * Read only register for error and done + */ +#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x38) +/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ENA (BIT(0)) +#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) +#define PAU_DONE_INT_ENA_V 0x00000001U +#define PAU_DONE_INT_ENA_S 0 +/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ENA (BIT(1)) +#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) +#define PAU_ERROR_INT_ENA_V 0x00000001U +#define PAU_ERROR_INT_ENA_S 1 + +/** PAU_INT_RAW_REG register + * Read only register for error and done + */ +#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x3c) +/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_RAW (BIT(0)) +#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) +#define PAU_DONE_INT_RAW_V 0x00000001U +#define PAU_DONE_INT_RAW_S 0 +/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_RAW (BIT(1)) +#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) +#define PAU_ERROR_INT_RAW_V 0x00000001U +#define PAU_ERROR_INT_RAW_S 1 + +/** PAU_INT_CLR_REG register + * Read only register for error and done + */ +#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x40) +/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_CLR (BIT(0)) +#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) +#define PAU_DONE_INT_CLR_V 0x00000001U +#define PAU_DONE_INT_CLR_S 0 +/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_CLR (BIT(1)) +#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) +#define PAU_ERROR_INT_CLR_V 0x00000001U +#define PAU_ERROR_INT_CLR_S 1 + +/** PAU_INT_ST_REG register + * Read only register for error and done + */ +#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x44) +/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ST (BIT(0)) +#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) +#define PAU_DONE_INT_ST_V 0x00000001U +#define PAU_DONE_INT_ST_S 0 +/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ST (BIT(1)) +#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) +#define PAU_ERROR_INT_ST_V 0x00000001U +#define PAU_ERROR_INT_ST_S 1 + +/** PAU_DATE_REG register + * Date register. + */ +#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) +/** PAU_DATE : R/W; bitpos: [27:0]; default: 35663984; + * REGDMA date information/ REGDMA version information. + */ +#define PAU_DATE 0x0FFFFFFFU +#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) +#define PAU_DATE_V 0x0FFFFFFFU +#define PAU_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pau_struct.h b/components/soc/esp32h2/include/soc/pau_struct.h new file mode 100644 index 0000000000..610b0e4e07 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pau_struct.h @@ -0,0 +1,368 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of regdma_conf register + * Peri backup control register + */ +typedef union { + struct { + /** flow_err : RO; bitpos: [2:0]; default: 0; + * backup error type + */ + uint32_t flow_err:3; + /** start : WT; bitpos: [3]; default: 0; + * backup start signal + */ + uint32_t start:1; + /** to_mem : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem:1; + /** link_sel : R/W; bitpos: [6:5]; default: 0; + * Link select + */ + uint32_t link_sel:2; + /** start_mac : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ + uint32_t start_mac:1; + /** to_mem_mac : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem_mac:1; + /** sel_mac : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ + uint32_t sel_mac:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pau_regdma_conf_reg_t; + +/** Type of regdma_clk_conf register + * Clock control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pau_regdma_clk_conf_reg_t; + +/** Type of regdma_etm_ctrl register + * ETM start ctrl reg + */ +typedef union { + struct { + /** etm_start_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ + uint32_t etm_start_0:1; + /** etm_start_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ + uint32_t etm_start_1:1; + /** etm_start_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ + uint32_t etm_start_2:1; + /** etm_start_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ + uint32_t etm_start_3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pau_regdma_etm_ctrl_reg_t; + +/** Type of regdma_link_0_addr register + * link_0_addr + */ +typedef union { + struct { + /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ + uint32_t link_addr_0:32; + }; + uint32_t val; +} pau_regdma_link_0_addr_reg_t; + +/** Type of regdma_link_1_addr register + * Link_1_addr + */ +typedef union { + struct { + /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ + uint32_t link_addr_1:32; + }; + uint32_t val; +} pau_regdma_link_1_addr_reg_t; + +/** Type of regdma_link_2_addr register + * Link_2_addr + */ +typedef union { + struct { + /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ + uint32_t link_addr_2:32; + }; + uint32_t val; +} pau_regdma_link_2_addr_reg_t; + +/** Type of regdma_link_3_addr register + * Link_3_addr + */ +typedef union { + struct { + /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ + uint32_t link_addr_3:32; + }; + uint32_t val; +} pau_regdma_link_3_addr_reg_t; + +/** Type of regdma_link_mac_addr register + * Link_mac_addr + */ +typedef union { + struct { + /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ + uint32_t link_addr_mac:32; + }; + uint32_t val; +} pau_regdma_link_mac_addr_reg_t; + +/** Type of regdma_current_link_addr register + * current link addr + */ +typedef union { + struct { + /** current_link_addr : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ + uint32_t current_link_addr:32; + }; + uint32_t val; +} pau_regdma_current_link_addr_reg_t; + +/** Type of regdma_backup_addr register + * Backup addr + */ +typedef union { + struct { + /** backup_addr : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ + uint32_t backup_addr:32; + }; + uint32_t val; +} pau_regdma_backup_addr_reg_t; + +/** Type of regdma_mem_addr register + * mem addr + */ +typedef union { + struct { + /** mem_addr : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ + uint32_t mem_addr:32; + }; + uint32_t val; +} pau_regdma_mem_addr_reg_t; + +/** Type of regdma_bkp_conf register + * backup config + */ +typedef union { + struct { + /** read_interval : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ + uint32_t read_interval:7; + /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ + uint32_t link_tout_thres:10; + /** burst_limit : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ + uint32_t burst_limit:5; + /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ + uint32_t backup_tout_thres:10; + }; + uint32_t val; +} pau_regdma_bkp_conf_reg_t; + +/** Type of retention_link_base register + * retention dma link base + */ +typedef union { + struct { + /** link_base_addr : R/W; bitpos: [26:0]; default: 0; + * retention dma link base + */ + uint32_t link_base_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} pau_retention_link_base_reg_t; + +/** Type of retention_cfg register + * retention_cfg + */ +typedef union { + struct { + /** ret_inv_cfg : R/W; bitpos: [31:0]; default: 4294967295; + * retention inv scan out + */ + uint32_t ret_inv_cfg:32; + }; + uint32_t val; +} pau_retention_cfg_reg_t; + +/** Type of int_ena register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_ena:1; + /** error_int_ena : R/W; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_ena_reg_t; + +/** Type of int_raw register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_raw:1; + /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_raw_reg_t; + +/** Type of int_clr register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_clr:1; + /** error_int_clr : WT; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_clr_reg_t; + +/** Type of int_st register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_st:1; + /** error_int_st : RO; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35663984; + * REGDMA date information/ REGDMA version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pau_date_reg_t; + + +typedef struct { + volatile pau_regdma_conf_reg_t regdma_conf; + volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; + volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; + volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr; + volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr; + volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr; + volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr; + volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr; + volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr; + volatile pau_regdma_backup_addr_reg_t regdma_backup_addr; + volatile pau_regdma_mem_addr_reg_t regdma_mem_addr; + volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf; + volatile pau_retention_link_base_reg_t retention_link_base; + volatile pau_retention_cfg_reg_t retention_cfg; + volatile pau_int_ena_reg_t int_ena; + volatile pau_int_raw_reg_t int_raw; + volatile pau_int_clr_reg_t int_clr; + volatile pau_int_st_reg_t int_st; + uint32_t reserved_048[237]; + volatile pau_date_reg_t date; +} pau_dev_t; + +extern pau_dev_t PAU; + +#ifndef __cplusplus +_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pcnt_reg.h b/components/soc/esp32h2/include/soc/pcnt_reg.h new file mode 100644 index 0000000000..0b65257ef6 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pcnt_reg.h @@ -0,0 +1,1242 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCNT_U0_CONF0_REG register + * Configuration register 0 for unit 0 + */ +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) +/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U0 0x000003FFU +#define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) +#define PCNT_FILTER_THRES_U0_V 0x000003FFU +#define PCNT_FILTER_THRES_U0_S 0 +/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 0's input filter. + */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) +#define PCNT_FILTER_EN_U0_V 0x00000001U +#define PCNT_FILTER_EN_U0_S 10 +/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 0's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) +#define PCNT_THR_ZERO_EN_U0_V 0x00000001U +#define PCNT_THR_ZERO_EN_U0_S 11 +/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) +#define PCNT_THR_H_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U0_S 12 +/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) +#define PCNT_THR_L_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U0_S 13 +/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 0's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) +#define PCNT_THR_THRES0_EN_U0_V 0x00000001U +#define PCNT_THR_THRES0_EN_U0_S 14 +/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 0's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) +#define PCNT_THR_THRES1_EN_U0_V 0x00000001U +#define PCNT_THR_THRES1_EN_U0_S 15 +/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) +#define PCNT_CH0_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_S 16 +/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U0 0x00000003U +#define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) +#define PCNT_CH0_POS_MODE_U0_V 0x00000003U +#define PCNT_CH0_POS_MODE_U0_S 18 +/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) +#define PCNT_CH1_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_S 24 +/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U0 0x00000003U +#define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) +#define PCNT_CH1_POS_MODE_U0_V 0x00000003U +#define PCNT_CH1_POS_MODE_U0_S 26 +/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_S 30 + +/** PCNT_U0_CONF1_REG register + * Configuration register 1 for unit 0 + */ +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) +/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 0. + */ +#define PCNT_CNT_THRES0_U0 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) +#define PCNT_CNT_THRES0_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_S 0 +/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 0. + */ +#define PCNT_CNT_THRES1_U0 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) +#define PCNT_CNT_THRES1_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_S 16 + +/** PCNT_U0_CONF2_REG register + * Configuration register 2 for unit 0 + */ +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) +/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 0. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) +#define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_S 0 +/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 0. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) +#define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_S 16 + +/** PCNT_U1_CONF0_REG register + * Configuration register 0 for unit 1 + */ +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc) +/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U1 0x000003FFU +#define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) +#define PCNT_FILTER_THRES_U1_V 0x000003FFU +#define PCNT_FILTER_THRES_U1_S 0 +/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 1's input filter. + */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) +#define PCNT_FILTER_EN_U1_V 0x00000001U +#define PCNT_FILTER_EN_U1_S 10 +/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 1's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) +#define PCNT_THR_ZERO_EN_U1_V 0x00000001U +#define PCNT_THR_ZERO_EN_U1_S 11 +/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) +#define PCNT_THR_H_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U1_S 12 +/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) +#define PCNT_THR_L_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U1_S 13 +/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 1's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) +#define PCNT_THR_THRES0_EN_U1_V 0x00000001U +#define PCNT_THR_THRES0_EN_U1_S 14 +/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 1's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) +#define PCNT_THR_THRES1_EN_U1_V 0x00000001U +#define PCNT_THR_THRES1_EN_U1_S 15 +/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) +#define PCNT_CH0_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_S 16 +/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U1 0x00000003U +#define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) +#define PCNT_CH0_POS_MODE_U1_V 0x00000003U +#define PCNT_CH0_POS_MODE_U1_S 18 +/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) +#define PCNT_CH1_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_S 24 +/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U1 0x00000003U +#define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) +#define PCNT_CH1_POS_MODE_U1_V 0x00000003U +#define PCNT_CH1_POS_MODE_U1_S 26 +/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_S 30 + +/** PCNT_U1_CONF1_REG register + * Configuration register 1 for unit 1 + */ +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) +/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 1. + */ +#define PCNT_CNT_THRES0_U1 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) +#define PCNT_CNT_THRES0_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_S 0 +/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 1. + */ +#define PCNT_CNT_THRES1_U1 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) +#define PCNT_CNT_THRES1_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_S 16 + +/** PCNT_U1_CONF2_REG register + * Configuration register 2 for unit 1 + */ +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) +/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 1. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) +#define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_S 0 +/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 1. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) +#define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_S 16 + +/** PCNT_U2_CONF0_REG register + * Configuration register 0 for unit 2 + */ +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) +/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U2 0x000003FFU +#define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) +#define PCNT_FILTER_THRES_U2_V 0x000003FFU +#define PCNT_FILTER_THRES_U2_S 0 +/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 2's input filter. + */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) +#define PCNT_FILTER_EN_U2_V 0x00000001U +#define PCNT_FILTER_EN_U2_S 10 +/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 2's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) +#define PCNT_THR_ZERO_EN_U2_V 0x00000001U +#define PCNT_THR_ZERO_EN_U2_S 11 +/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) +#define PCNT_THR_H_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U2_S 12 +/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) +#define PCNT_THR_L_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U2_S 13 +/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 2's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) +#define PCNT_THR_THRES0_EN_U2_V 0x00000001U +#define PCNT_THR_THRES0_EN_U2_S 14 +/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 2's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) +#define PCNT_THR_THRES1_EN_U2_V 0x00000001U +#define PCNT_THR_THRES1_EN_U2_S 15 +/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) +#define PCNT_CH0_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_S 16 +/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U2 0x00000003U +#define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) +#define PCNT_CH0_POS_MODE_U2_V 0x00000003U +#define PCNT_CH0_POS_MODE_U2_S 18 +/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) +#define PCNT_CH1_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_S 24 +/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U2 0x00000003U +#define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) +#define PCNT_CH1_POS_MODE_U2_V 0x00000003U +#define PCNT_CH1_POS_MODE_U2_S 26 +/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_S 30 + +/** PCNT_U2_CONF1_REG register + * Configuration register 1 for unit 2 + */ +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c) +/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 2. + */ +#define PCNT_CNT_THRES0_U2 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) +#define PCNT_CNT_THRES0_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_S 0 +/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 2. + */ +#define PCNT_CNT_THRES1_U2 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) +#define PCNT_CNT_THRES1_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_S 16 + +/** PCNT_U2_CONF2_REG register + * Configuration register 2 for unit 2 + */ +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) +/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 2. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) +#define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_S 0 +/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 2. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) +#define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_S 16 + +/** PCNT_U3_CONF0_REG register + * Configuration register 0 for unit 3 + */ +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) +/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U3 0x000003FFU +#define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) +#define PCNT_FILTER_THRES_U3_V 0x000003FFU +#define PCNT_FILTER_THRES_U3_S 0 +/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 3's input filter. + */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) +#define PCNT_FILTER_EN_U3_V 0x00000001U +#define PCNT_FILTER_EN_U3_S 10 +/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 3's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) +#define PCNT_THR_ZERO_EN_U3_V 0x00000001U +#define PCNT_THR_ZERO_EN_U3_S 11 +/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) +#define PCNT_THR_H_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U3_S 12 +/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) +#define PCNT_THR_L_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U3_S 13 +/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 3's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) +#define PCNT_THR_THRES0_EN_U3_V 0x00000001U +#define PCNT_THR_THRES0_EN_U3_S 14 +/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 3's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) +#define PCNT_THR_THRES1_EN_U3_V 0x00000001U +#define PCNT_THR_THRES1_EN_U3_S 15 +/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) +#define PCNT_CH0_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_S 16 +/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U3 0x00000003U +#define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) +#define PCNT_CH0_POS_MODE_U3_V 0x00000003U +#define PCNT_CH0_POS_MODE_U3_S 18 +/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) +#define PCNT_CH1_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_S 24 +/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U3 0x00000003U +#define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) +#define PCNT_CH1_POS_MODE_U3_V 0x00000003U +#define PCNT_CH1_POS_MODE_U3_S 26 +/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_S 30 + +/** PCNT_U3_CONF1_REG register + * Configuration register 1 for unit 3 + */ +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) +/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 3. + */ +#define PCNT_CNT_THRES0_U3 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) +#define PCNT_CNT_THRES0_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_S 0 +/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 3. + */ +#define PCNT_CNT_THRES1_U3 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) +#define PCNT_CNT_THRES1_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_S 16 + +/** PCNT_U3_CONF2_REG register + * Configuration register 2 for unit 3 + */ +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c) +/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 3. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) +#define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_S 0 +/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 3. When pluse_cnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) +#define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_S 16 + +/** PCNT_U0_CNT_REG register + * Counter value for unit 0 + */ +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) +/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 0. + */ +#define PCNT_PULSE_CNT_U0 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) +#define PCNT_PULSE_CNT_U0_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_S 0 + +/** PCNT_U1_CNT_REG register + * Counter value for unit 1 + */ +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) +/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 1. + */ +#define PCNT_PULSE_CNT_U1 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) +#define PCNT_PULSE_CNT_U1_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_S 0 + +/** PCNT_U2_CNT_REG register + * Counter value for unit 2 + */ +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) +/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 2. + */ +#define PCNT_PULSE_CNT_U2 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) +#define PCNT_PULSE_CNT_U2_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_S 0 + +/** PCNT_U3_CNT_REG register + * Counter value for unit 3 + */ +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c) +/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 3. + */ +#define PCNT_PULSE_CNT_U3 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) +#define PCNT_PULSE_CNT_U3_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_S 0 + +/** PCNT_INT_RAW_REG register + * Interrupt raw status register + */ +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) +/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 + +/** PCNT_INT_ST_REG register + * Interrupt status register + */ +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) +/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 + +/** PCNT_INT_ENA_REG register + * Interrupt enable register + */ +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) +/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 + +/** PCNT_INT_CLR_REG register + * Interrupt clear register + */ +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c) +/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 + +/** PCNT_U0_STATUS_REG register + * PNCT UNIT0 status register + */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) +/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U0 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 + +/** PCNT_U1_STATUS_REG register + * PNCT UNIT1 status register + */ +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) +/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U1 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 + +/** PCNT_U2_STATUS_REG register + * PNCT UNIT2 status register + */ +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) +/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U2 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 + +/** PCNT_U3_STATUS_REG register + * PNCT UNIT3 status register + */ +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c) +/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U3 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 + +/** PCNT_CTRL_REG register + * Control register for all counters + */ +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) +/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) +#define PCNT_PULSE_CNT_RST_U0_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U0_S 0 +/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) +#define PCNT_CNT_PAUSE_U0_V 0x00000001U +#define PCNT_CNT_PAUSE_U0_S 1 +/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) +#define PCNT_PULSE_CNT_RST_U1_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U1_S 2 +/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) +#define PCNT_CNT_PAUSE_U1_V 0x00000001U +#define PCNT_CNT_PAUSE_U1_S 3 +/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) +#define PCNT_PULSE_CNT_RST_U2_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U2_S 4 +/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) +#define PCNT_CNT_PAUSE_U2_V 0x00000001U +#define PCNT_CNT_PAUSE_U2_S 5 +/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) +#define PCNT_PULSE_CNT_RST_U3_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U3_S 6 +/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) +#define PCNT_CNT_PAUSE_U3_V 0x00000001U +#define PCNT_CNT_PAUSE_U3_S 7 +/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) +#define PCNT_CLK_EN_V 0x00000001U +#define PCNT_CLK_EN_S 16 + +/** PCNT_DATE_REG register + * PCNT version control register + */ +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) +/** PCNT_DATE : R/W; bitpos: [31:0]; default: 403121664; + * This is the PCNT version control register. + */ +#define PCNT_DATE 0xFFFFFFFFU +#define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) +#define PCNT_DATE_V 0xFFFFFFFFU +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pcnt_struct.h b/components/soc/esp32h2/include/soc/pcnt_struct.h new file mode 100644 index 0000000000..4c372320c5 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pcnt_struct.h @@ -0,0 +1,404 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ + uint32_t filter_thres:10; + /** filter_en : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en:1; + /** thr_zero_en : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en:1; + /** thr_h_lim_en : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. + */ + uint32_t thr_h_lim_en:1; + /** thr_l_lim_en : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. + */ + uint32_t thr_l_lim_en:1; + /** thr_thres0_en : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en:1; + /** thr_thres1_en : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en:1; + /** ch0_neg_mode : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_neg_mode:2; + /** ch0_pos_mode : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_pos_mode:2; + /** ch0_hctrl_mode : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode:2; + /** ch0_lctrl_mode : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode:2; + /** ch1_neg_mode : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_neg_mode:2; + /** ch1_pos_mode : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_pos_mode:2; + /** ch1_hctrl_mode : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode:2; + /** ch1_lctrl_mode : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit n. + */ + uint32_t cnt_thres0:16; + /** cnt_thres1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit n. + */ + uint32_t cnt_thres1:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit n. + */ + uint32_t cnt_h_lim:16; + /** cnt_l_lim : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit n. + */ + uint32_t cnt_l_lim:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + uint32_t reserved_8:8; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit n. + */ + uint32_t pulse_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ + uint32_t cnt_thr_zero_mode:2; + /** cnt_thr_thres1_lat : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres1_lat:1; + /** cnt_thr_thres0_lat : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres0_lat:1; + /** cnt_thr_l_lim_lat : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ + uint32_t cnt_thr_l_lim_lat:1; + /** cnt_thr_h_lim_lat : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ + uint32_t cnt_thr_h_lim_lat:1; + /** cnt_thr_zero_lat : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_Un when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ + uint32_t cnt_thr_zero_lat:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 403121664; + * This is the PCNT version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + +typedef struct pcnt_dev_t { + volatile struct { + pcnt_un_conf0_reg_t conf0; + pcnt_un_conf1_reg_t conf1; + pcnt_un_conf2_reg_t conf2; + } conf_unit[4]; + volatile pcnt_un_cnt_reg_t cnt_unit[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t status_unit[4]; + volatile pcnt_ctrl_reg_t ctrl; + uint32_t reserved_064[38]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pcr_reg.h b/components/soc/esp32h2/include/soc/pcr_reg.h new file mode 100644 index 0000000000..f44d7a31ea --- /dev/null +++ b/components/soc/esp32h2/include/soc/pcr_reg.h @@ -0,0 +1,2347 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_CLK_SEL : R/W; bitpos: [4:3]; default: 0; + * set this field to select clock-source. + */ +#define PCR_MSPI_CLK_SEL 0x00000003U +#define PCR_MSPI_CLK_SEL_M (PCR_MSPI_CLK_SEL_V << PCR_MSPI_CLK_SEL_S) +#define PCR_MSPI_CLK_SEL_V 0x00000003U +#define PCR_MSPI_CLK_SEL_S 3 +/** PCR_MSPI_READY : RO; bitpos: [5]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(5)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 5 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 + +/** PCR_I2C0_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C0_CLK_EN (BIT(0)) +#define PCR_I2C0_CLK_EN_M (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S) +#define PCR_I2C0_CLK_EN_V 0x00000001U +#define PCR_I2C0_CLK_EN_S 0 +/** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C0_RST_EN (BIT(1)) +#define PCR_I2C0_RST_EN_M (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S) +#define PCR_I2C0_RST_EN_V 0x00000001U +#define PCR_I2C0_RST_EN_S 1 +/** PCR_I2C0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c0 module + */ +#define PCR_I2C0_READY (BIT(2)) +#define PCR_I2C0_READY_M (PCR_I2C0_READY_V << PCR_I2C0_READY_S) +#define PCR_I2C0_READY_V 0x00000001U +#define PCR_I2C0_READY_S 2 + +/** PCR_I2C0_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_A 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_M (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S) +#define PCR_I2C0_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_S 0 +/** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_B 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_M (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S) +#define PCR_I2C0_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_S 6 +/** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_M (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S) +#define PCR_I2C0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_S 12 +/** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C0_SCLK_SEL (BIT(20)) +#define PCR_I2C0_SCLK_SEL_M (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S) +#define PCR_I2C0_SCLK_SEL_V 0x00000001U +#define PCR_I2C0_SCLK_SEL_S 20 +/** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C0_SCLK_EN (BIT(22)) +#define PCR_I2C0_SCLK_EN_M (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S) +#define PCR_I2C0_SCLK_EN_V 0x00000001U +#define PCR_I2C0_SCLK_EN_S 22 + +/** PCR_I2C1_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C1_CLK_EN (BIT(0)) +#define PCR_I2C1_CLK_EN_M (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S) +#define PCR_I2C1_CLK_EN_V 0x00000001U +#define PCR_I2C1_CLK_EN_S 0 +/** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C1_RST_EN (BIT(1)) +#define PCR_I2C1_RST_EN_M (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S) +#define PCR_I2C1_RST_EN_V 0x00000001U +#define PCR_I2C1_RST_EN_S 1 +/** PCR_I2C1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c1 module + */ +#define PCR_I2C1_READY (BIT(2)) +#define PCR_I2C1_READY_M (PCR_I2C1_READY_V << PCR_I2C1_READY_S) +#define PCR_I2C1_READY_V 0x00000001U +#define PCR_I2C1_READY_S 2 + +/** PCR_I2C1_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_A 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_M (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S) +#define PCR_I2C1_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_S 0 +/** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_B 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_M (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S) +#define PCR_I2C1_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_S 6 +/** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_M (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S) +#define PCR_I2C1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_S 12 +/** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C1_SCLK_SEL (BIT(20)) +#define PCR_I2C1_SCLK_SEL_M (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S) +#define PCR_I2C1_SCLK_SEL_V 0x00000001U +#define PCR_I2C1_SCLK_SEL_S 20 +/** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C1_SCLK_EN (BIT(22)) +#define PCR_I2C1_SCLK_EN_M (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S) +#define PCR_I2C1_SCLK_EN_V 0x00000001U +#define PCR_I2C1_SCLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 +/** PCR_RMT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rmt module + */ +#define PCR_RMT_READY (BIT(2)) +#define PCR_RMT_READY_M (PCR_RMT_READY_V << PCR_RMT_READY_S) +#define PCR_RMT_READY_V 0x00000001U +#define PCR_RMT_READY_S 2 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_RMT_SCLK_SEL (BIT(20)) +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000001U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(21)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 21 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(2)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 2 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 +/** PCR_PWM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ +#define PCR_PWM_READY (BIT(2)) +#define PCR_PWM_READY_M (PCR_PWM_READY_V << PCR_PWM_READY_S) +#define PCR_PWM_READY_V 0x00000001U +#define PCR_PWM_READY_S 2 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 +/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ +#define PCR_MEM_MONITOR_READY (BIT(2)) +#define PCR_MEM_MONITOR_READY_M (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S) +#define PCR_MEM_MONITOR_READY_V 0x00000001U +#define PCR_MEM_MONITOR_READY_S 2 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_MODEM_CLK_SEL (BIT(0)) +#define PCR_MODEM_CLK_SEL_M (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S) +#define PCR_MODEM_CLK_SEL_V 0x00000001U +#define PCR_MODEM_CLK_SEL_S 0 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * xxxx + */ +#define PCR_MODEM_CLK_EN (BIT(1)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 1 +/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(2)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 32; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_CPUPERIOD_SEL 0x00000003U +#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) +#define PCR_CPUPERIOD_SEL_V 0x00000003U +#define PCR_CPUPERIOD_SEL_S 0 +/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_PLL_FREQ_SEL (BIT(2)) +#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) +#define PCR_PLL_FREQ_SEL_V 0x00000001U +#define PCR_PLL_FREQ_SEL_S 2 +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: + * open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(4)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 4 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(5)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 5 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 8m clock + */ +#define PCR_CLK8_OEN (BIT(0)) +#define PCR_CLK8_OEN_M (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S) +#define PCR_CLK8_OEN_V 0x00000001U +#define PCR_CLK8_OEN_S 0 +/** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 16m clock + */ +#define PCR_CLK16_OEN (BIT(1)) +#define PCR_CLK16_OEN_M (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S) +#define PCR_CLK16_OEN_V 0x00000001U +#define PCR_CLK16_OEN_S 1 +/** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 32m clock + */ +#define PCR_CLK32_OEN (BIT(2)) +#define PCR_CLK32_OEN_M (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S) +#define PCR_CLK32_OEN_V 0x00000001U +#define PCR_CLK32_OEN_S 2 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(3)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 3 +/** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1; + * Reserved + */ +#define PCR_CLK_DFM_INF_OEN (BIT(4)) +#define PCR_CLK_DFM_INF_OEN_M (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S) +#define PCR_CLK_DFM_INF_OEN_V 0x00000001U +#define PCR_CLK_DFM_INF_OEN_S 4 +/** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1; + * Reserved + */ +#define PCR_CLK_SDM_MOD_OEN (BIT(5)) +#define PCR_CLK_SDM_MOD_OEN_M (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S) +#define PCR_CLK_SDM_MOD_OEN_V 0x00000001U +#define PCR_CLK_SDM_MOD_OEN_S 5 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(6)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 6 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 +/** PCR_32K_MODEM_SEL : R/W; bitpos: [3:2]; default: 0; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_MODEM_SEL 0x00000003U +#define PCR_32K_MODEM_SEL_M (PCR_32K_MODEM_SEL_V << PCR_32K_MODEM_SEL_S) +#define PCR_32K_MODEM_SEL_V 0x00000003U +#define PCR_32K_MODEM_SEL_S 2 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:13]; default: 3; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000003U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000003U +#define PCR_ROM_FORCE_PU_S 13 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [16:15]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000003U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000003U +#define PCR_ROM_FORCE_PD_S 15 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [18:17]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_S 17 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000001FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000001FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000001FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000001FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [29:25]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 25 + +/** PCR_SEC_CONF_REG register + * xxxx + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 + +/** PCR_ADC_INV_PHASE_CONF_REG register + * xxxx + */ +#define PCR_ADC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140) +/** PCR_CLK_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_CLK_ADC_INV_PHASE_ENA (BIT(0)) +#define PCR_CLK_ADC_INV_PHASE_ENA_M (PCR_CLK_ADC_INV_PHASE_ENA_V << PCR_CLK_ADC_INV_PHASE_ENA_S) +#define PCR_CLK_ADC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_ADC_INV_PHASE_ENA_S 0 + +/** PCR_SDM_INV_PHASE_CONF_REG register + * xxxx + */ +#define PCR_SDM_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x144) +/** PCR_CLK_SDM_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_CLK_SDM_INV_PHASE_ENA (BIT(0)) +#define PCR_CLK_SDM_INV_PHASE_ENA_M (PCR_CLK_SDM_INV_PHASE_ENA_V << PCR_CLK_SDM_INV_PHASE_ENA_S) +#define PCR_CLK_SDM_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_SDM_INV_PHASE_ENA_S 0 +/** PCR_CLK_SDM_INV_PHASE_SEL : R/W; bitpos: [3:1]; default: 0; + * xxxx + */ +#define PCR_CLK_SDM_INV_PHASE_SEL 0x00000007U +#define PCR_CLK_SDM_INV_PHASE_SEL_M (PCR_CLK_SDM_INV_PHASE_SEL_V << PCR_CLK_SDM_INV_PHASE_SEL_S) +#define PCR_CLK_SDM_INV_PHASE_SEL_V 0x00000007U +#define PCR_CLK_SDM_INV_PHASE_SEL_S 1 + +/** PCR_BUS_CLK_UPDATE_REG register + * xxxx + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * xxxx + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) +#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 +/** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_READER_EN (BIT(8)) +#define PCR_PWDET_SAR_READER_EN_M (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S) +#define PCR_PWDET_SAR_READER_EN_V 0x00000001U +#define PCR_PWDET_SAR_READER_EN_S 8 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 35717248; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pcr_struct.h b/components/soc/esp32h2/include/soc/pcr_struct.h new file mode 100644 index 0000000000..a81e45de56 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pcr_struct.h @@ -0,0 +1,2141 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of uart0_conf register + * UART0 configuration register + */ +typedef union { + struct { + /** uart0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ + uint32_t uart0_clk_en:1; + /** uart0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ + uint32_t uart0_rst_en:1; + /** uart0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ + uint32_t uart0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_conf_reg_t; + +/** Type of uart0_sclk_conf register + * UART0_SCLK configuration register + */ +typedef union { + struct { + /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_a:6; + /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_b:6; + /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_num:8; + /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t uart0_sclk_sel:2; + /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart0_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart0_sclk_conf_reg_t; + +/** Type of uart0_pd_ctrl register + * UART0 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ + uint32_t uart0_mem_force_pu:1; + /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ + uint32_t uart0_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_pd_ctrl_reg_t; + +/** Type of uart1_conf register + * UART1 configuration register + */ +typedef union { + struct { + /** uart1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ + uint32_t uart1_clk_en:1; + /** uart1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ + uint32_t uart1_rst_en:1; + /** uart1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ + uint32_t uart1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_conf_reg_t; + +/** Type of uart1_sclk_conf register + * UART1_SCLK configuration register + */ +typedef union { + struct { + /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_a:6; + /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_b:6; + /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_num:8; + /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t uart1_sclk_sel:2; + /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart1_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart1_sclk_conf_reg_t; + +/** Type of uart1_pd_ctrl register + * UART1 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ + uint32_t uart1_mem_force_pu:1; + /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ + uint32_t uart1_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_pd_ctrl_reg_t; + +/** Type of mspi_conf register + * MSPI configuration register + */ +typedef union { + struct { + /** mspi_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ + uint32_t mspi_clk_en:1; + /** mspi_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ + uint32_t mspi_rst_en:1; + /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ + uint32_t mspi_pll_clk_en:1; + /** mspi_clk_sel : R/W; bitpos: [4:3]; default: 0; + * set this field to select clock-source. + */ + uint32_t mspi_clk_sel:2; + /** mspi_ready : RO; bitpos: [5]; default: 1; + * Query this field after reset mspi module + */ + uint32_t mspi_ready:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pcr_mspi_conf_reg_t; + +/** Type of mspi_clk_conf register + * MSPI_CLK configuration register + */ +typedef union { + struct { + /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ + uint32_t mspi_fast_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_mspi_clk_conf_reg_t; + +/** Type of i2c0_conf register + * I2C configuration register + */ +typedef union { + struct { + /** i2c0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ + uint32_t i2c0_clk_en:1; + /** i2c0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ + uint32_t i2c0_rst_en:1; + /** i2c0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c0 module + */ + uint32_t i2c0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_i2c0_conf_reg_t; + +/** Type of i2c0_sclk_conf register + * I2C_SCLK configuration register + */ +typedef union { + struct { + /** i2c0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c0_sclk_div_a:6; + /** i2c0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c0_sclk_div_b:6; + /** i2c0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c0_sclk_div_num:8; + /** i2c0_sclk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t i2c0_sclk_sel:1; + uint32_t reserved_21:1; + /** i2c0_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ + uint32_t i2c0_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2c0_sclk_conf_reg_t; + +/** Type of i2c1_conf register + * I2C configuration register + */ +typedef union { + struct { + /** i2c1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ + uint32_t i2c1_clk_en:1; + /** i2c1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ + uint32_t i2c1_rst_en:1; + /** i2c1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c1 module + */ + uint32_t i2c1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_i2c1_conf_reg_t; + +/** Type of i2c1_sclk_conf register + * I2C_SCLK configuration register + */ +typedef union { + struct { + /** i2c1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c1_sclk_div_a:6; + /** i2c1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c1_sclk_div_b:6; + /** i2c1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c1_sclk_div_num:8; + /** i2c1_sclk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t i2c1_sclk_sel:1; + uint32_t reserved_21:1; + /** i2c1_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ + uint32_t i2c1_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2c1_sclk_conf_reg_t; + +/** Type of uhci_conf register + * UHCI configuration register + */ +typedef union { + struct { + /** uhci_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ + uint32_t uhci_clk_en:1; + /** uhci_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ + uint32_t uhci_rst_en:1; + /** uhci_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ + uint32_t uhci_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uhci_conf_reg_t; + +/** Type of rmt_conf register + * RMT configuration register + */ +typedef union { + struct { + /** rmt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ + uint32_t rmt_clk_en:1; + /** rmt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ + uint32_t rmt_rst_en:1; + /** rmt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset rmt module + */ + uint32_t rmt_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rmt_conf_reg_t; + +/** Type of rmt_sclk_conf register + * RMT_SCLK configuration register + */ +typedef union { + struct { + /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_a:6; + /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_b:6; + /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_num:8; + /** rmt_sclk_sel : R/W; bitpos: [20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ + uint32_t rmt_sclk_sel:1; + /** rmt_sclk_en : R/W; bitpos: [21]; default: 1; + * Set 1 to enable rmt function clock + */ + uint32_t rmt_sclk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} pcr_rmt_sclk_conf_reg_t; + +/** Type of ledc_conf register + * LEDC configuration register + */ +typedef union { + struct { + /** ledc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ + uint32_t ledc_clk_en:1; + /** ledc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ + uint32_t ledc_rst_en:1; + /** ledc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ + uint32_t ledc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ledc_conf_reg_t; + +/** Type of ledc_sclk_conf register + * LEDC_SCLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ + uint32_t ledc_sclk_sel:2; + /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ + uint32_t ledc_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_ledc_sclk_conf_reg_t; + +/** Type of timergroup0_conf register + * TIMERGROUP0 configuration register + */ +typedef union { + struct { + /** tg0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ + uint32_t tg0_clk_en:1; + /** tg0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ + uint32_t tg0_rst_en:1; + /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ + uint32_t tg0_wdt_ready:1; + /** tg0_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ + uint32_t tg0_timer0_ready:1; + /** tg0_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg0_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup0_conf_reg_t; + +/** Type of timergroup0_timer_clk_conf register + * TIMERGROUP0_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_timer_clk_sel:2; + /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ + uint32_t tg0_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_timer_clk_conf_reg_t; + +/** Type of timergroup0_wdt_clk_conf register + * TIMERGROUP0_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_wdt_clk_sel:2; + /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg0_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_wdt_clk_conf_reg_t; + +/** Type of timergroup1_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ + uint32_t tg1_clk_en:1; + /** tg1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ + uint32_t tg1_rst_en:1; + /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ + uint32_t tg1_wdt_ready:1; + /** tg1_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ + uint32_t tg1_timer0_ready:1; + /** tg1_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg1_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup1_conf_reg_t; + +/** Type of timergroup1_timer_clk_conf register + * TIMERGROUP1_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_timer_clk_sel:2; + /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ + uint32_t tg1_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_timer_clk_conf_reg_t; + +/** Type of timergroup1_wdt_clk_conf register + * TIMERGROUP1_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_wdt_clk_sel:2; + /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg1_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_wdt_clk_conf_reg_t; + +/** Type of systimer_conf register + * SYSTIMER configuration register + */ +typedef union { + struct { + /** systimer_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ + uint32_t systimer_clk_en:1; + /** systimer_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ + uint32_t systimer_rst_en:1; + /** systimer_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ + uint32_t systimer_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_systimer_conf_reg_t; + +/** Type of systimer_func_clk_conf register + * SYSTIMER_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t systimer_func_clk_sel:1; + uint32_t reserved_21:1; + /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ + uint32_t systimer_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_systimer_func_clk_conf_reg_t; + +/** Type of twai0_conf register + * TWAI0 configuration register + */ +typedef union { + struct { + /** twai0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ + uint32_t twai0_clk_en:1; + /** twai0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ + uint32_t twai0_rst_en:1; + /** twai0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ + uint32_t twai0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_twai0_conf_reg_t; + +/** Type of twai0_func_clk_conf register + * TWAI0_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai0_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ + uint32_t twai0_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai0_func_clk_conf_reg_t; + +/** Type of i2s_conf register + * I2S configuration register + */ +typedef union { + struct { + /** i2s_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ + uint32_t i2s_clk_en:1; + /** i2s_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ + uint32_t i2s_rst_en:1; + /** i2s_rx_ready : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ + uint32_t i2s_rx_ready:1; + /** i2s_tx_ready : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ + uint32_t i2s_tx_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_i2s_conf_reg_t; + +/** Type of i2s_tx_clkm_conf register + * I2S_TX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t i2s_tx_clkm_div_num:8; + /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ + uint32_t i2s_tx_clkm_sel:2; + /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ + uint32_t i2s_tx_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2s_tx_clkm_conf_reg_t; + +/** Type of i2s_tx_clkm_div_conf register + * I2S_TX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_tx_clkm_div_z:9; + /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_tx_clkm_div_y:9; + /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_tx_clkm_div_x:9; + /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_tx_clkm_div_conf_reg_t; + +/** Type of i2s_rx_clkm_conf register + * I2S_RX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ + uint32_t i2s_rx_clkm_div_num:8; + /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ + uint32_t i2s_rx_clkm_sel:2; + /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ + uint32_t i2s_rx_clkm_en:1; + /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ + uint32_t i2s_mclk_sel:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_i2s_rx_clkm_conf_reg_t; + +/** Type of i2s_rx_clkm_div_conf register + * I2S_RX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_rx_clkm_div_z:9; + /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_rx_clkm_div_y:9; + /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_rx_clkm_div_x:9; + /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_rx_clkm_div_conf_reg_t; + +/** Type of saradc_conf register + * SARADC configuration register + */ +typedef union { + struct { + /** saradc_clk_en : R/W; bitpos: [0]; default: 1; + * no use + */ + uint32_t saradc_clk_en:1; + /** saradc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ + uint32_t saradc_rst_en:1; + /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ + uint32_t saradc_reg_clk_en:1; + /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ + uint32_t saradc_reg_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_saradc_conf_reg_t; + +/** Type of saradc_clkm_conf register + * SARADC_CLKM configuration register + */ +typedef union { + struct { + /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t saradc_clkm_sel:2; + /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ + uint32_t saradc_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_saradc_clkm_conf_reg_t; + +/** Type of tsens_clk_conf register + * TSENS_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ + uint32_t tsens_clk_sel:1; + uint32_t reserved_21:1; + /** tsens_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ + uint32_t tsens_clk_en:1; + /** tsens_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ + uint32_t tsens_rst_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_tsens_clk_conf_reg_t; + +/** Type of usb_device_conf register + * USB_DEVICE configuration register + */ +typedef union { + struct { + /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ + uint32_t usb_device_clk_en:1; + /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ + uint32_t usb_device_rst_en:1; + /** usb_device_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ + uint32_t usb_device_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_usb_device_conf_reg_t; + +/** Type of intmtx_conf register + * INTMTX configuration register + */ +typedef union { + struct { + /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ + uint32_t intmtx_clk_en:1; + /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ + uint32_t intmtx_rst_en:1; + /** intmtx_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ + uint32_t intmtx_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_intmtx_conf_reg_t; + +/** Type of pcnt_conf register + * PCNT configuration register + */ +typedef union { + struct { + /** pcnt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ + uint32_t pcnt_clk_en:1; + /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ + uint32_t pcnt_rst_en:1; + /** pcnt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ + uint32_t pcnt_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_pcnt_conf_reg_t; + +/** Type of etm_conf register + * ETM configuration register + */ +typedef union { + struct { + /** etm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ + uint32_t etm_clk_en:1; + /** etm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ + uint32_t etm_rst_en:1; + /** etm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ + uint32_t etm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_etm_conf_reg_t; + +/** Type of pwm_conf register + * PWM configuration register + */ +typedef union { + struct { + /** pwm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ + uint32_t pwm_clk_en:1; + /** pwm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ + uint32_t pwm_rst_en:1; + /** pwm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ + uint32_t pwm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_pwm_conf_reg_t; + +/** Type of pwm_clk_conf register + * PWM_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** pwm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ + uint32_t pwm_div_num:8; + /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ + uint32_t pwm_clkm_sel:2; + /** pwm_clkm_en : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ + uint32_t pwm_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pwm_clk_conf_reg_t; + +/** Type of parl_io_conf register + * PARL_IO configuration register + */ +typedef union { + struct { + /** parl_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ + uint32_t parl_clk_en:1; + /** parl_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ + uint32_t parl_rst_en:1; + /** parl_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ + uint32_t parl_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_parl_io_conf_reg_t; + +/** Type of parl_clk_rx_conf register + * PARL_CLK_RX configuration register + */ +typedef union { + struct { + /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ + uint32_t parl_clk_rx_div_num:16; + /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_rx_sel:2; + /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ + uint32_t parl_clk_rx_en:1; + /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ + uint32_t parl_rx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_rx_conf_reg_t; + +/** Type of parl_clk_tx_conf register + * PARL_CLK_TX configuration register + */ +typedef union { + struct { + /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ + uint32_t parl_clk_tx_div_num:16; + /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_tx_sel:2; + /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ + uint32_t parl_clk_tx_en:1; + /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ + uint32_t parl_tx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_tx_conf_reg_t; + +/** Type of pvt_monitor_conf register + * PVT_MONITOR configuration register + */ +typedef union { + struct { + /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ + uint32_t pvt_monitor_clk_en:1; + /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ + uint32_t pvt_monitor_rst_en:1; + /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ + uint32_t pvt_monitor_site1_clk_en:1; + /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ + uint32_t pvt_monitor_site2_clk_en:1; + /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ + uint32_t pvt_monitor_site3_clk_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_pvt_monitor_conf_reg_t; + +/** Type of pvt_monitor_func_clk_conf register + * PVT_MONITOR function clock configuration register + */ +typedef union { + struct { + /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ + uint32_t pvt_monitor_func_clk_div_num:4; + uint32_t reserved_4:16; + /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ + uint32_t pvt_monitor_func_clk_sel:1; + uint32_t reserved_21:1; + /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ + uint32_t pvt_monitor_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pvt_monitor_func_clk_conf_reg_t; + +/** Type of gdma_conf register + * GDMA configuration register + */ +typedef union { + struct { + /** gdma_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ + uint32_t gdma_clk_en:1; + /** gdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ + uint32_t gdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_gdma_conf_reg_t; + +/** Type of spi2_conf register + * SPI2 configuration register + */ +typedef union { + struct { + /** spi2_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ + uint32_t spi2_clk_en:1; + /** spi2_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ + uint32_t spi2_rst_en:1; + /** spi2_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ + uint32_t spi2_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_spi2_conf_reg_t; + +/** Type of spi2_clkm_conf register + * SPI2_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t spi2_clkm_sel:2; + /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ + uint32_t spi2_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_spi2_clkm_conf_reg_t; + +/** Type of aes_conf register + * AES configuration register + */ +typedef union { + struct { + /** aes_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ + uint32_t aes_clk_en:1; + /** aes_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ + uint32_t aes_rst_en:1; + /** aes_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ + uint32_t aes_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_aes_conf_reg_t; + +/** Type of sha_conf register + * SHA configuration register + */ +typedef union { + struct { + /** sha_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ + uint32_t sha_clk_en:1; + /** sha_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ + uint32_t sha_rst_en:1; + /** sha_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ + uint32_t sha_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sha_conf_reg_t; + +/** Type of rsa_conf register + * RSA configuration register + */ +typedef union { + struct { + /** rsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ + uint32_t rsa_clk_en:1; + /** rsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ + uint32_t rsa_rst_en:1; + /** rsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ + uint32_t rsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_conf_reg_t; + +/** Type of rsa_pd_ctrl register + * RSA power control register + */ +typedef union { + struct { + /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ + uint32_t rsa_mem_pd:1; + /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ + uint32_t rsa_mem_force_pu:1; + /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ + uint32_t rsa_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_pd_ctrl_reg_t; + +/** Type of ecc_conf register + * ECC configuration register + */ +typedef union { + struct { + /** ecc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ + uint32_t ecc_clk_en:1; + /** ecc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ + uint32_t ecc_rst_en:1; + /** ecc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ + uint32_t ecc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_conf_reg_t; + +/** Type of ecc_pd_ctrl register + * ECC power control register + */ +typedef union { + struct { + /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ + uint32_t ecc_mem_pd:1; + /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ + uint32_t ecc_mem_force_pu:1; + /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ + uint32_t ecc_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_pd_ctrl_reg_t; + +/** Type of ds_conf register + * DS configuration register + */ +typedef union { + struct { + /** ds_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ + uint32_t ds_clk_en:1; + /** ds_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ + uint32_t ds_rst_en:1; + /** ds_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ + uint32_t ds_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ds_conf_reg_t; + +/** Type of hmac_conf register + * HMAC configuration register + */ +typedef union { + struct { + /** hmac_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ + uint32_t hmac_clk_en:1; + /** hmac_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ + uint32_t hmac_rst_en:1; + /** hmac_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ + uint32_t hmac_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_hmac_conf_reg_t; + +/** Type of ecdsa_conf register + * ECDSA configuration register + */ +typedef union { + struct { + /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ + uint32_t ecdsa_clk_en:1; + /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ + uint32_t ecdsa_rst_en:1; + /** ecdsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ + uint32_t ecdsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecdsa_conf_reg_t; + +/** Type of iomux_conf register + * IOMUX configuration register + */ +typedef union { + struct { + /** iomux_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ + uint32_t iomux_clk_en:1; + /** iomux_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ + uint32_t iomux_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_iomux_conf_reg_t; + +/** Type of iomux_clk_conf register + * IOMUX_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t iomux_func_clk_sel:2; + /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ + uint32_t iomux_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_iomux_clk_conf_reg_t; + +/** Type of mem_monitor_conf register + * MEM_MONITOR configuration register + */ +typedef union { + struct { + /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ + uint32_t mem_monitor_clk_en:1; + /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ + uint32_t mem_monitor_rst_en:1; + /** mem_monitor_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ + uint32_t mem_monitor_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_mem_monitor_conf_reg_t; + +/** Type of regdma_conf register + * REGDMA configuration register + */ +typedef union { + struct { + /** regdma_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ + uint32_t regdma_clk_en:1; + /** regdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ + uint32_t regdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_regdma_conf_reg_t; + +/** Type of trace_conf register + * TRACE configuration register + */ +typedef union { + struct { + /** trace_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ + uint32_t trace_clk_en:1; + /** trace_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ + uint32_t trace_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_trace_conf_reg_t; + +/** Type of assist_conf register + * ASSIST configuration register + */ +typedef union { + struct { + /** assist_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ + uint32_t assist_clk_en:1; + /** assist_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ + uint32_t assist_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_assist_conf_reg_t; + +/** Type of cache_conf register + * CACHE configuration register + */ +typedef union { + struct { + /** cache_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ + uint32_t cache_clk_en:1; + /** cache_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ + uint32_t cache_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_cache_conf_reg_t; + +/** Type of modem_conf register + * MODEM_APB configuration register + */ +typedef union { + struct { + /** modem_clk_sel : R/W; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t modem_clk_sel:1; + /** modem_clk_en : R/W; bitpos: [1]; default: 1; + * xxxx + */ + uint32_t modem_clk_en:1; + /** modem_rst_en : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ + uint32_t modem_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_modem_conf_reg_t; + +/** Type of timeout_conf register + * TIMEOUT configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ + uint32_t cpu_timeout_rst_en:1; + /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ + uint32_t hp_timeout_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_timeout_conf_reg_t; + +/** Type of sysclk_conf register + * SYSCLK configuration register + */ +typedef union { + struct { + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; + /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ + uint32_t soc_clk_sel:2; + uint32_t reserved_18:6; + /** clk_xtal_freq : RO; bitpos: [30:24]; default: 32; + * This field indicates the frequency(MHz) of XTAL. + */ + uint32_t clk_xtal_freq:7; + uint32_t reserved_31:1; + }; + uint32_t val; +} pcr_sysclk_conf_reg_t; + +/** Type of cpu_waiti_conf register + * CPU_WAITI configuration register + */ +typedef union { + struct { + /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ + uint32_t cpuperiod_sel:2; + /** pll_freq_sel : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ + uint32_t pll_freq_sel:1; + /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ + uint32_t cpu_wait_mode_force_on:1; + /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ + uint32_t cpu_waiti_delay_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_waiti_conf_reg_t; + +/** Type of cpu_freq_conf register + * CPU_FREQ configuration register + */ +typedef union { + struct { + /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ + uint32_t cpu_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_freq_conf_reg_t; + +/** Type of ahb_freq_conf register + * AHB_FREQ configuration register + */ +typedef union { + struct { + /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ + uint32_t ahb_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_ahb_freq_conf_reg_t; + +/** Type of apb_freq_conf register + * APB_FREQ configuration register + */ +typedef union { + struct { + /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ + uint32_t apb_decrease_div_num:8; + /** apb_div_num : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ + uint32_t apb_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_apb_freq_conf_reg_t; + +/** Type of pll_div_clk_en register + * SPLL DIV clock-gating configuration register + */ +typedef union { + struct { + /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; + * This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: + * open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_240m_clk_en:1; + /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; + * This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_160m_clk_en:1; + /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; + * This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_120m_clk_en:1; + /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; + * This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_80m_clk_en:1; + /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1; + * This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_48m_clk_en:1; + /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1; + * This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_40m_clk_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pcr_pll_div_clk_en_reg_t; + +/** Type of ctrl_clk_out_en register + * CLK_OUT_EN configuration register + */ +typedef union { + struct { + /** clk8_oen : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 8m clock + */ + uint32_t clk8_oen:1; + /** clk16_oen : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 16m clock + */ + uint32_t clk16_oen:1; + /** clk32_oen : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 32m clock + */ + uint32_t clk32_oen:1; + /** clk_adc_inf_oen : R/W; bitpos: [3]; default: 1; + * Reserved + */ + uint32_t clk_adc_inf_oen:1; + /** clk_dfm_inf_oen : R/W; bitpos: [4]; default: 1; + * Reserved + */ + uint32_t clk_dfm_inf_oen:1; + /** clk_sdm_mod_oen : R/W; bitpos: [5]; default: 1; + * Reserved + */ + uint32_t clk_sdm_mod_oen:1; + /** clk_xtal_oen : R/W; bitpos: [6]; default: 1; + * Set 1 to enable xtal clock + */ + uint32_t clk_xtal_oen:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcr_ctrl_clk_out_en_reg_t; + +/** Type of ctrl_tick_conf register + * TICK configuration register + */ +typedef union { + struct { + /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ + uint32_t xtal_tick_num:8; + /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ + uint32_t fosc_tick_num:8; + /** tick_enable : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ + uint32_t tick_enable:1; + /** rst_tick_cnt : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ + uint32_t rst_tick_cnt:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_ctrl_tick_conf_reg_t; + +/** Type of ctrl_32k_conf register + * 32KHz clock configuration register + */ +typedef union { + struct { + /** 32k_sel : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ + uint32_t 32k_sel:2; + /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 0; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ + uint32_t 32k_modem_sel:2; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_ctrl_32k_conf_reg_t; + +/** Type of sram_power_conf_0 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** rom_force_pu : R/W; bitpos: [14:13]; default: 3; + * Set this bit to force power up ROM + */ + uint32_t rom_force_pu:2; + /** rom_force_pd : R/W; bitpos: [16:15]; default: 0; + * Set this bit to force power down ROM. + */ + uint32_t rom_force_pd:2; + /** rom_clkgate_force_on : R/W; bitpos: [18:17]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ + uint32_t rom_clkgate_force_on:2; + uint32_t reserved_19:13; + }; + uint32_t val; +} pcr_sram_power_conf_0_reg_t; + +/** Type of sram_power_conf_1 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** sram_force_pu : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ + uint32_t sram_force_pu:5; + uint32_t reserved_5:5; + /** sram_force_pd : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ + uint32_t sram_force_pd:5; + uint32_t reserved_15:10; + /** sram_clkgate_force_on : R/W; bitpos: [29:25]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ + uint32_t sram_clkgate_force_on:5; + uint32_t reserved_30:2; + }; + uint32_t val; +} pcr_sram_power_conf_1_reg_t; + +/** Type of sec_conf register + * xxxx + */ +typedef union { + struct { + /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ + uint32_t sec_clk_sel:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sec_conf_reg_t; + +/** Type of adc_inv_phase_conf register + * xxxx + */ +typedef union { + struct { + /** clk_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t clk_adc_inv_phase_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_adc_inv_phase_conf_reg_t; + +/** Type of sdm_inv_phase_conf register + * xxxx + */ +typedef union { + struct { + /** clk_sdm_inv_phase_ena : R/W; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t clk_sdm_inv_phase_ena:1; + /** clk_sdm_inv_phase_sel : R/W; bitpos: [3:1]; default: 0; + * xxxx + */ + uint32_t clk_sdm_inv_phase_sel:3; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_sdm_inv_phase_conf_reg_t; + +/** Type of bus_clk_update register + * xxxx + */ +typedef union { + struct { + /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t bus_clock_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_bus_clk_update_reg_t; + +/** Type of sar_clk_div register + * xxxx + */ +typedef union { + struct { + /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ + uint32_t sar2_clk_div_num:8; + /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ + uint32_t sar1_clk_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_sar_clk_div_reg_t; + +/** Type of pwdet_sar_clk_conf register + * xxxx + */ +typedef union { + struct { + /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ + uint32_t pwdet_sar_clk_div_num:8; + /** pwdet_sar_reader_en : R/W; bitpos: [8]; default: 1; + * xxxx + */ + uint32_t pwdet_sar_reader_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pwdet_sar_clk_conf_reg_t; + +/** Type of reset_event_bypass register + * reset event bypass backdoor configuration register + */ +typedef union { + struct { + /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ + uint32_t reset_event_bypass_apm:1; + /** reset_event_bypass : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ + uint32_t reset_event_bypass:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_reset_event_bypass_reg_t; + +/** Type of clock_gate register + * PCR clock gating configure register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_clock_gate_reg_t; + + +/** Group: Frequency Statistics Register */ +/** Type of sysclk_freq_query_0 register + * SYSCLK frequency query 0 register + */ +typedef union { + struct { + /** fosc_freq : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ + uint32_t fosc_freq:8; + /** pll_freq : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ + uint32_t pll_freq:10; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_sysclk_freq_query_0_reg_t; + + +/** Group: FPGA Debug Register */ +/** Type of fpga_debug register + * fpga debug register + */ +typedef union { + struct { + /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ + uint32_t fpga_debug:32; + }; + uint32_t val; +} pcr_fpga_debug_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35717248; + * PCR version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_date_reg_t; + + +typedef struct { + volatile pcr_uart0_conf_reg_t uart0_conf; + volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; + volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; + volatile pcr_uart1_conf_reg_t uart1_conf; + volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; + volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; + volatile pcr_mspi_conf_reg_t mspi_conf; + volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; + volatile pcr_i2c0_conf_reg_t i2c0_conf; + volatile pcr_i2c0_sclk_conf_reg_t i2c0_sclk_conf; + volatile pcr_i2c1_conf_reg_t i2c1_conf; + volatile pcr_i2c1_sclk_conf_reg_t i2c1_sclk_conf; + volatile pcr_uhci_conf_reg_t uhci_conf; + volatile pcr_rmt_conf_reg_t rmt_conf; + volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; + volatile pcr_ledc_conf_reg_t ledc_conf; + volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; + volatile pcr_timergroup0_conf_reg_t timergroup0_conf; + volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; + volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; + volatile pcr_timergroup1_conf_reg_t timergroup1_conf; + volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; + volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; + volatile pcr_systimer_conf_reg_t systimer_conf; + volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; + volatile pcr_twai0_conf_reg_t twai0_conf; + volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; + volatile pcr_i2s_conf_reg_t i2s_conf; + volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; + volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; + volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; + volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; + volatile pcr_saradc_conf_reg_t saradc_conf; + volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; + volatile pcr_usb_device_conf_reg_t usb_device_conf; + volatile pcr_intmtx_conf_reg_t intmtx_conf; + volatile pcr_pcnt_conf_reg_t pcnt_conf; + volatile pcr_etm_conf_reg_t etm_conf; + volatile pcr_pwm_conf_reg_t pwm_conf; + volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf; + volatile pcr_parl_io_conf_reg_t parl_io_conf; + volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf; + volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf; + volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; + volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; + volatile pcr_gdma_conf_reg_t gdma_conf; + volatile pcr_spi2_conf_reg_t spi2_conf; + volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; + volatile pcr_aes_conf_reg_t aes_conf; + volatile pcr_sha_conf_reg_t sha_conf; + volatile pcr_rsa_conf_reg_t rsa_conf; + volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + volatile pcr_ecc_conf_reg_t ecc_conf; + volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; + volatile pcr_ds_conf_reg_t ds_conf; + volatile pcr_hmac_conf_reg_t hmac_conf; + volatile pcr_ecdsa_conf_reg_t ecdsa_conf; + volatile pcr_iomux_conf_reg_t iomux_conf; + volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; + volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf; + volatile pcr_regdma_conf_reg_t regdma_conf; + volatile pcr_trace_conf_reg_t trace_conf; + volatile pcr_assist_conf_reg_t assist_conf; + volatile pcr_cache_conf_reg_t cache_conf; + volatile pcr_modem_conf_reg_t modem_conf; + volatile pcr_timeout_conf_reg_t timeout_conf; + volatile pcr_sysclk_conf_reg_t sysclk_conf; + volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; + volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; + volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; + volatile pcr_apb_freq_conf_reg_t apb_freq_conf; + volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; + volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; + volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; + volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf; + volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; + volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; + volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; + volatile pcr_sec_conf_reg_t sec_conf; + volatile pcr_adc_inv_phase_conf_reg_t adc_inv_phase_conf; + volatile pcr_sdm_inv_phase_conf_reg_t sdm_inv_phase_conf; + volatile pcr_bus_clk_update_reg_t bus_clk_update; + volatile pcr_sar_clk_div_reg_t sar_clk_div; + volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + uint32_t reserved_154[935]; + volatile pcr_reset_event_bypass_reg_t reset_event_bypass; + volatile pcr_fpga_debug_reg_t fpga_debug; + volatile pcr_clock_gate_reg_t clock_gate; + volatile pcr_date_reg_t date; +} pcr_dev_t; + +extern pcr_dev_t PCR; + +#ifndef __cplusplus +_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h new file mode 100644 index 0000000000..464c16370d --- /dev/null +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -0,0 +1,116 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_SPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_WIFI_BT_COMMON_MODULE, + PERIPH_BT_BASEBAND_MODULE, + PERIPH_BT_LC_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_MODULE_MAX +} periph_module_t; + +typedef enum { + ETS_PMU_INTR_SOURCE = 0, + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_BLE_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_PWM_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ + ETS_GSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_ECDSA_INTR_SOURCE, /**< interrupt of ECDSA accelerator, level*/ + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/plic_reg.h b/components/soc/esp32h2/include/soc/plic_reg.h new file mode 100644 index 0000000000..b744601310 --- /dev/null +++ b/components/soc/esp32h2/include/soc/plic_reg.h @@ -0,0 +1,633 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define DR_REG_PLIC_MX_BASE ( 0x20001000 ) +#define DR_REG_PLIC_UX_BASE ( 0x20001400 ) +#define PLIC_MXINT_CONF_REG ( 0x200013FC ) +#define PLIC_UXINT_CONF_REG ( 0x200017FC ) + +#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) + +/*PLIC MX*/ +#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0) +/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S)) +#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_S 0 + +#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4) +/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S)) +#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_S 0 + +#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8) +/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S)) +#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_S 0 + +#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10) +/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT0_PRI 0x0000000F +#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S)) +#define PLIC_CPU_MXINT0_PRI_V 0xF +#define PLIC_CPU_MXINT0_PRI_S 0 + +#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14) +/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT1_PRI 0x0000000F +#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S)) +#define PLIC_CPU_MXINT1_PRI_V 0xF +#define PLIC_CPU_MXINT1_PRI_S 0 + +#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18) +/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT2_PRI 0x0000000F +#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S)) +#define PLIC_CPU_MXINT2_PRI_V 0xF +#define PLIC_CPU_MXINT2_PRI_S 0 + +#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C) +/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT3_PRI 0x0000000F +#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S)) +#define PLIC_CPU_MXINT3_PRI_V 0xF +#define PLIC_CPU_MXINT3_PRI_S 0 + +#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20) +/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT4_PRI 0x0000000F +#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S)) +#define PLIC_CPU_MXINT4_PRI_V 0xF +#define PLIC_CPU_MXINT4_PRI_S 0 + +#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24) +/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT5_PRI 0x0000000F +#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S)) +#define PLIC_CPU_MXINT5_PRI_V 0xF +#define PLIC_CPU_MXINT5_PRI_S 0 + +#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28) +/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT6_PRI 0x0000000F +#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S)) +#define PLIC_CPU_MXINT6_PRI_V 0xF +#define PLIC_CPU_MXINT6_PRI_S 0 + +#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C) +/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT7_PRI 0x0000000F +#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S)) +#define PLIC_CPU_MXINT7_PRI_V 0xF +#define PLIC_CPU_MXINT7_PRI_S 0 + +#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30) +/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT8_PRI 0x0000000F +#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S)) +#define PLIC_CPU_MXINT8_PRI_V 0xF +#define PLIC_CPU_MXINT8_PRI_S 0 + +#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34) +/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT9_PRI 0x0000000F +#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S)) +#define PLIC_CPU_MXINT9_PRI_V 0xF +#define PLIC_CPU_MXINT9_PRI_S 0 + +#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38) +/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT10_PRI 0x0000000F +#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S)) +#define PLIC_CPU_MXINT10_PRI_V 0xF +#define PLIC_CPU_MXINT10_PRI_S 0 + +#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C) +/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT11_PRI 0x0000000F +#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S)) +#define PLIC_CPU_MXINT11_PRI_V 0xF +#define PLIC_CPU_MXINT11_PRI_S 0 + +#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40) +/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT12_PRI 0x0000000F +#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S)) +#define PLIC_CPU_MXINT12_PRI_V 0xF +#define PLIC_CPU_MXINT12_PRI_S 0 + +#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44) +/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT13_PRI 0x0000000F +#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S)) +#define PLIC_CPU_MXINT13_PRI_V 0xF +#define PLIC_CPU_MXINT13_PRI_S 0 + +#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48) +/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT14_PRI 0x0000000F +#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S)) +#define PLIC_CPU_MXINT14_PRI_V 0xF +#define PLIC_CPU_MXINT14_PRI_S 0 + +#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C) +/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT15_PRI 0x0000000F +#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S)) +#define PLIC_CPU_MXINT15_PRI_V 0xF +#define PLIC_CPU_MXINT15_PRI_S 0 + +#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50) +/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT16_PRI 0x0000000F +#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S)) +#define PLIC_CPU_MXINT16_PRI_V 0xF +#define PLIC_CPU_MXINT16_PRI_S 0 + +#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54) +/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT17_PRI 0x0000000F +#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S)) +#define PLIC_CPU_MXINT17_PRI_V 0xF +#define PLIC_CPU_MXINT17_PRI_S 0 + +#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58) +/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT18_PRI 0x0000000F +#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S)) +#define PLIC_CPU_MXINT18_PRI_V 0xF +#define PLIC_CPU_MXINT18_PRI_S 0 + +#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C) +/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT19_PRI 0x0000000F +#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S)) +#define PLIC_CPU_MXINT19_PRI_V 0xF +#define PLIC_CPU_MXINT19_PRI_S 0 + +#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60) +/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT20_PRI 0x0000000F +#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S)) +#define PLIC_CPU_MXINT20_PRI_V 0xF +#define PLIC_CPU_MXINT20_PRI_S 0 + +#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64) +/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT21_PRI 0x0000000F +#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S)) +#define PLIC_CPU_MXINT21_PRI_V 0xF +#define PLIC_CPU_MXINT21_PRI_S 0 + +#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68) +/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT22_PRI 0x0000000F +#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S)) +#define PLIC_CPU_MXINT22_PRI_V 0xF +#define PLIC_CPU_MXINT22_PRI_S 0 + +#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C) +/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT23_PRI 0x0000000F +#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S)) +#define PLIC_CPU_MXINT23_PRI_V 0xF +#define PLIC_CPU_MXINT23_PRI_S 0 + +#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70) +/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT24_PRI 0x0000000F +#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S)) +#define PLIC_CPU_MXINT24_PRI_V 0xF +#define PLIC_CPU_MXINT24_PRI_S 0 + +#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74) +/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT25_PRI 0x0000000F +#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S)) +#define PLIC_CPU_MXINT25_PRI_V 0xF +#define PLIC_CPU_MXINT25_PRI_S 0 + +#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78) +/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT26_PRI 0x0000000F +#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S)) +#define PLIC_CPU_MXINT26_PRI_V 0xF +#define PLIC_CPU_MXINT26_PRI_S 0 + +#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C) +/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT27_PRI 0x0000000F +#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S)) +#define PLIC_CPU_MXINT27_PRI_V 0xF +#define PLIC_CPU_MXINT27_PRI_S 0 + +#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80) +/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT28_PRI 0x0000000F +#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S)) +#define PLIC_CPU_MXINT28_PRI_V 0xF +#define PLIC_CPU_MXINT28_PRI_S 0 + +#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84) +/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT29_PRI 0x0000000F +#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S)) +#define PLIC_CPU_MXINT29_PRI_V 0xF +#define PLIC_CPU_MXINT29_PRI_S 0 + +#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88) +/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT30_PRI 0x0000000F +#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S)) +#define PLIC_CPU_MXINT30_PRI_V 0xF +#define PLIC_CPU_MXINT30_PRI_S 0 + +#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C) +/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT31_PRI 0x0000000F +#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S)) +#define PLIC_CPU_MXINT31_PRI_V 0xF +#define PLIC_CPU_MXINT31_PRI_S 0 + +#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90) +/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_THRESH 0x000000FF +#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S)) +#define PLIC_CPU_MXINT_THRESH_V 0xFF +#define PLIC_CPU_MXINT_THRESH_S 0 + +#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94) +/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/ +#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S)) +#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_S 0 + +/*PLIC UX*/ +#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0) +/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S)) +#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_S 0 + +#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4) +/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S)) +#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_S 0 + +#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8) +/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S)) +#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_S 0 + +#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10) +/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT0_PRI 0x0000000F +#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S)) +#define PLIC_CPU_UXINT0_PRI_V 0xF +#define PLIC_CPU_UXINT0_PRI_S 0 + +#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14) +/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT1_PRI 0x0000000F +#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S)) +#define PLIC_CPU_UXINT1_PRI_V 0xF +#define PLIC_CPU_UXINT1_PRI_S 0 + +#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18) +/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT2_PRI 0x0000000F +#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S)) +#define PLIC_CPU_UXINT2_PRI_V 0xF +#define PLIC_CPU_UXINT2_PRI_S 0 + +#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C) +/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT3_PRI 0x0000000F +#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S)) +#define PLIC_CPU_UXINT3_PRI_V 0xF +#define PLIC_CPU_UXINT3_PRI_S 0 + +#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20) +/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT4_PRI 0x0000000F +#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S)) +#define PLIC_CPU_UXINT4_PRI_V 0xF +#define PLIC_CPU_UXINT4_PRI_S 0 + +#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24) +/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT5_PRI 0x0000000F +#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S)) +#define PLIC_CPU_UXINT5_PRI_V 0xF +#define PLIC_CPU_UXINT5_PRI_S 0 + +#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28) +/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT6_PRI 0x0000000F +#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S)) +#define PLIC_CPU_UXINT6_PRI_V 0xF +#define PLIC_CPU_UXINT6_PRI_S 0 + +#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C) +/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT7_PRI 0x0000000F +#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S)) +#define PLIC_CPU_UXINT7_PRI_V 0xF +#define PLIC_CPU_UXINT7_PRI_S 0 + +#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30) +/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT8_PRI 0x0000000F +#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S)) +#define PLIC_CPU_UXINT8_PRI_V 0xF +#define PLIC_CPU_UXINT8_PRI_S 0 + +#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34) +/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT9_PRI 0x0000000F +#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S)) +#define PLIC_CPU_UXINT9_PRI_V 0xF +#define PLIC_CPU_UXINT9_PRI_S 0 + +#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38) +/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT10_PRI 0x0000000F +#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S)) +#define PLIC_CPU_UXINT10_PRI_V 0xF +#define PLIC_CPU_UXINT10_PRI_S 0 + +#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C) +/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT11_PRI 0x0000000F +#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S)) +#define PLIC_CPU_UXINT11_PRI_V 0xF +#define PLIC_CPU_UXINT11_PRI_S 0 + +#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40) +/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT12_PRI 0x0000000F +#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S)) +#define PLIC_CPU_UXINT12_PRI_V 0xF +#define PLIC_CPU_UXINT12_PRI_S 0 + +#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44) +/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT13_PRI 0x0000000F +#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S)) +#define PLIC_CPU_UXINT13_PRI_V 0xF +#define PLIC_CPU_UXINT13_PRI_S 0 + +#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48) +/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT14_PRI 0x0000000F +#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S)) +#define PLIC_CPU_UXINT14_PRI_V 0xF +#define PLIC_CPU_UXINT14_PRI_S 0 + +#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C) +/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT15_PRI 0x0000000F +#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S)) +#define PLIC_CPU_UXINT15_PRI_V 0xF +#define PLIC_CPU_UXINT15_PRI_S 0 + +#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50) +/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT16_PRI 0x0000000F +#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S)) +#define PLIC_CPU_UXINT16_PRI_V 0xF +#define PLIC_CPU_UXINT16_PRI_S 0 + +#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54) +/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT17_PRI 0x0000000F +#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S)) +#define PLIC_CPU_UXINT17_PRI_V 0xF +#define PLIC_CPU_UXINT17_PRI_S 0 + +#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58) +/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT18_PRI 0x0000000F +#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S)) +#define PLIC_CPU_UXINT18_PRI_V 0xF +#define PLIC_CPU_UXINT18_PRI_S 0 + +#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C) +/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT19_PRI 0x0000000F +#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S)) +#define PLIC_CPU_UXINT19_PRI_V 0xF +#define PLIC_CPU_UXINT19_PRI_S 0 + +#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60) +/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT20_PRI 0x0000000F +#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S)) +#define PLIC_CPU_UXINT20_PRI_V 0xF +#define PLIC_CPU_UXINT20_PRI_S 0 + +#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64) +/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT21_PRI 0x0000000F +#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S)) +#define PLIC_CPU_UXINT21_PRI_V 0xF +#define PLIC_CPU_UXINT21_PRI_S 0 + +#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68) +/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT22_PRI 0x0000000F +#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S)) +#define PLIC_CPU_UXINT22_PRI_V 0xF +#define PLIC_CPU_UXINT22_PRI_S 0 + +#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C) +/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT23_PRI 0x0000000F +#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S)) +#define PLIC_CPU_UXINT23_PRI_V 0xF +#define PLIC_CPU_UXINT23_PRI_S 0 + +#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70) +/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT24_PRI 0x0000000F +#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S)) +#define PLIC_CPU_UXINT24_PRI_V 0xF +#define PLIC_CPU_UXINT24_PRI_S 0 + +#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74) +/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT25_PRI 0x0000000F +#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S)) +#define PLIC_CPU_UXINT25_PRI_V 0xF +#define PLIC_CPU_UXINT25_PRI_S 0 + +#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78) +/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT26_PRI 0x0000000F +#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S)) +#define PLIC_CPU_UXINT26_PRI_V 0xF +#define PLIC_CPU_UXINT26_PRI_S 0 + +#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C) +/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT27_PRI 0x0000000F +#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S)) +#define PLIC_CPU_UXINT27_PRI_V 0xF +#define PLIC_CPU_UXINT27_PRI_S 0 + +#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80) +/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT28_PRI 0x0000000F +#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S)) +#define PLIC_CPU_UXINT28_PRI_V 0xF +#define PLIC_CPU_UXINT28_PRI_S 0 + +#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84) +/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT29_PRI 0x0000000F +#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S)) +#define PLIC_CPU_UXINT29_PRI_V 0xF +#define PLIC_CPU_UXINT29_PRI_S 0 + +#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88) +/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT30_PRI 0x0000000F +#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S)) +#define PLIC_CPU_UXINT30_PRI_V 0xF +#define PLIC_CPU_UXINT30_PRI_S 0 + +#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C) +/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT31_PRI 0x0000000F +#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S)) +#define PLIC_CPU_UXINT31_PRI_V 0xF +#define PLIC_CPU_UXINT31_PRI_S 0 + +#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90) +/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_THRESH 0x000000FF +#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S)) +#define PLIC_CPU_UXINT_THRESH_V 0xFF +#define PLIC_CPU_UXINT_THRESH_S 0 + +#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94) +/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S)) +#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pmu_icg_mapping.h b/components/soc/esp32h2/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..02064042ac --- /dev/null +++ b/components/soc/esp32h2/include/soc/pmu_icg_mapping.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define PMU_ICG_APB_ENA_CAN0 18 +#define PMU_ICG_APB_ENA_CAN1 19 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_I2C 13 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_FUNC_ENA_CAN0 31 +#define PMU_ICG_FUNC_ENA_CAN1 30 +#define PMU_ICG_FUNC_ENA_I2C 29 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_RETENTION 9 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#endif /* _SOC_ICG_MAP_H_ */ diff --git a/components/soc/esp32h2/include/soc/pmu_reg.h b/components/soc/esp32h2/include/soc/pmu_reg.h new file mode 100644 index 0000000000..b2c8f9bb56 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pmu_reg.h @@ -0,0 +1,3449 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 27 +/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) +#define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) +#define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 30 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_TRX (BIT(24)) +#define PMU_HP_ACTIVE_XPD_TRX_M (PMU_HP_ACTIVE_XPD_TRX_V << PMU_HP_ACTIVE_XPD_TRX_S) +#define PMU_HP_ACTIVE_XPD_TRX_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_TRX_S 24 +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 0 +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 17; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 16; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_TRX (BIT(24)) +#define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S) +#define PMU_HP_MODEM_XPD_TRX_V 0x00000001U +#define PMU_HP_MODEM_XPD_TRX_S 24 +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 26 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 27 +/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) +#define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) +#define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BB_I2C_S 28 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 30 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_TRX (BIT(24)) +#define PMU_HP_SLEEP_XPD_TRX_M (PMU_HP_SLEEP_XPD_TRX_V << PMU_HP_SLEEP_XPD_TRX_S) +#define PMU_HP_SLEEP_XPD_TRX_V 0x00000001U +#define PMU_HP_SLEEP_XPD_TRX_S 24 +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S 0 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) +/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_M (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S) +#define PMU_HP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_HP_SLEEP_XPD_LPPLL_M (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S) +#define PMU_HP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_LPPLL_S 27 +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) +/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_M (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S) +#define PMU_LP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_LP_SLEEP_XPD_LPPLL_M (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S) +#define PMU_LP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_LPPLL_S 27 +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 2 +/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) +#define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) +#define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BB_I2C_S 3 +/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 +/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) +#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) +#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_S 5 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(6)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 27 +/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) +#define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) +#define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BB_I2C_S 28 +/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 +/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) +#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_S 9 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_S 16 +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 +/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 6 +/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_PD_MASK 0x0000001FU +#define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) +#define PMU_PD_TOP_PD_MASK_V 0x0000001FU +#define PMU_PD_TOP_PD_MASK_S 27 + +/** PMU_POWER_PD_HPAON_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_RESET (BIT(0)) +#define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) +#define PMU_FORCE_HP_AON_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_RESET_S 0 +/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_ISO (BIT(1)) +#define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) +#define PMU_FORCE_HP_AON_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_ISO_S 1 +/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_PU (BIT(2)) +#define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) +#define PMU_FORCE_HP_AON_PU_V 0x00000001U +#define PMU_FORCE_HP_AON_PU_S 2 +/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) +#define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_RESET_S 3 +/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) +#define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_ISO_S 4 +/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_PD (BIT(5)) +#define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) +#define PMU_FORCE_HP_AON_PD_V 0x00000001U +#define PMU_FORCE_HP_AON_PD_S 5 +/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_MASK 0x0000001FU +#define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) +#define PMU_PD_HP_AON_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_MASK_S 6 +/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_PD_MASK 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) +#define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_S 27 + +/** PMU_POWER_PD_HPCPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 6 +/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_PD_MASK 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) +#define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_S 27 + +/** PMU_POWER_PD_HPPERI_RESERVE_REG register + * need_des + */ +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_PERI_RESERVE 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) +#define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_S 0 + +/** PMU_POWER_PD_HPWIFI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_RESET (BIT(0)) +#define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) +#define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_RESET_S 0 +/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_ISO (BIT(1)) +#define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) +#define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_ISO_S 1 +/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PU (BIT(2)) +#define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) +#define PMU_FORCE_HP_WIFI_PU_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PU_S 2 +/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) +#define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_RESET_S 3 +/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) +#define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_ISO_S 4 +/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PD (BIT(5)) +#define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) +#define PMU_FORCE_HP_WIFI_PD_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PD_S 5 +/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) +#define PMU_PD_HP_WIFI_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_S 6 +/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) +#define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_S 27 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_MEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_S 0 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_S 4 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_S 24 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_S 28 + +/** PMU_POWER_PD_MEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) +#define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_S 0 +/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) +#define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_S 5 +/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) +#define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_S 10 +/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) +#define PMU_PD_HP_MEM2_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_S 17 +/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) +#define PMU_PD_HP_MEM1_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_S 22 +/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) +#define PMU_PD_HP_MEM0_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_VDD_SPI_CNTL_REG register + * need_des + */ +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; + * need_des + */ +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; + * need_des + */ +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) +#define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_S 0 +/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) +#define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_RFTX_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_RFTX_I2C (BIT(28)) +#define PMU_XPD_RFTX_I2C_M (PMU_XPD_RFTX_I2C_V << PMU_XPD_RFTX_I2C_S) +#define PMU_XPD_RFTX_I2C_V 0x00000001U +#define PMU_XPD_RFTX_I2C_S 28 +/** PMU_XPD_RFRX_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_I2C (BIT(29)) +#define PMU_XPD_RFRX_I2C_M (PMU_XPD_RFRX_I2C_V << PMU_XPD_RFRX_I2C_S) +#define PMU_XPD_RFRX_I2C_V 0x00000001U +#define PMU_XPD_RFRX_I2C_S 29 +/** PMU_XPD_RFPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_RFPLL (BIT(30)) +#define PMU_XPD_RFPLL_M (PMU_XPD_RFPLL_V << PMU_XPD_RFPLL_S) +#define PMU_XPD_RFPLL_V 0x00000001U +#define PMU_XPD_RFPLL_S 30 +/** PMU_XPD_FORCE_RFPLL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_XPD_FORCE_RFPLL (BIT(31)) +#define PMU_XPD_FORCE_RFPLL_M (PMU_XPD_FORCE_RFPLL_V << PMU_XPD_FORCE_RFPLL_S) +#define PMU_XPD_FORCE_RFPLL_V 0x00000001U +#define PMU_XPD_FORCE_RFPLL_S 31 + +/** PMU_VDDBAT_CFG_REG register + * need_des + */ +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; + * need_des + */ +#define PMU_VDDBAT_MODE 0x00000003U +#define PMU_VDDBAT_MODE_M (PMU_VDDBAT_MODE_V << PMU_VDDBAT_MODE_S) +#define PMU_VDDBAT_MODE_V 0x00000003U +#define PMU_VDDBAT_MODE_S 0 +/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDDBAT_SW_UPDATE (BIT(31)) +#define PMU_VDDBAT_SW_UPDATE_M (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S) +#define PMU_VDDBAT_SW_UPDATE_V 0x00000001U +#define PMU_VDDBAT_SW_UPDATE_S 31 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) +#define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) +#define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; + * need_des + */ +#define PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) +#define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) +#define PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_BACKUP_ST_STATE_S 13 +/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) +#define PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_LP_PWR_ST_STATE_S 18 +/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) +#define PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) +#define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) +#define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_BBPLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 1 +/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) +#define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_SYS_CLK_SLP_SEL_STATE_S 15 +/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) +#define PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_S 16 +/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) +#define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_SYS_CLK_NO_DIV_STATE_S 18 +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) +#define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_ICG_SYS_CLK_EN_STATE_S 19 +/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) +#define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_ICG_MODEM_SWITCH_STATE_S 20 +/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_S 21 +/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_ICG_SLP_SEL_STATE (BIT(23)) +#define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) +#define PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_ICG_SLP_SEL_STATE_S 23 +/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) +#define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_XTAL_STATE_S 24 +/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) +#define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_PLL_STATE_S 25 +/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) +#define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_ANA_I2C_ISO_EN_STATE_S 26 +/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) +#define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_ANA_I2C_RETENTION_STATE_S 27 +/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) +#define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) +#define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BB_I2C_STATE_S 28 +/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 +/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) +#define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) +#define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_STATE_S 30 +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) +#define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) +#define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_VDD_SPI_STATUS_REG register + * need_des + */ +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35688960; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/pmu_struct.h b/components/soc/esp32h2/include/soc/pmu_struct.h new file mode 100644 index 0000000000..3dcd18d263 --- /dev/null +++ b/components/soc/esp32h2/include/soc/pmu_struct.h @@ -0,0 +1,2869 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_spi_pd_en:1; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_trx:1; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + uint32_t reserved_26:4; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:2; + /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_retention_mode:1; + /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_retention_en:1; + /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2active_retention_en:1; + uint32_t reserved_13:1; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + uint32_t reserved_18:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:3; + /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:3; + uint32_t reserved_26:3; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_active_hp_power_det_bypass:1; + uint32_t reserved_1:3; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 17; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 16; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_modem_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_vdd_spi_pd_en:1; + /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_mem_dslp:1; + /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_mem_pd_en:4; + /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_cpu_pd_en:1; + /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_aon_pd_en:1; + /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_modem_dig_power_reg_t; + +/** Type of hp_modem_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_func_reg_t; + +/** Type of hp_modem_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_apb_reg_t; + +/** Type of hp_modem_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_modem_icg_modem_reg_t; + +/** Type of hp_modem_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_modem_uart_wakeup_en:1; + /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_lp_pad_hold_all:1; + /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_pad_hold_all:1; + /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pad_slp_sel:1; + /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pause_wdt:1; + /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_hp_sys_cntl_reg_t; + +/** Type of hp_modem_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_iso_en:1; + /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_retention:1; + /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bb_i2c:1; + /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll_i2c:1; + /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_modem_hp_ck_power_reg_t; + +/** Type of hp_modem_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_modem_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_modem_xpd_trx:1; + /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bias:1; + uint32_t reserved_26:4; + /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cur:1; + /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_modem_bias_reg_t; + +/** Type of hp_modem_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_modem_clk_code:2; + uint32_t reserved_6:4; + /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_modem_retention_mode:1; + /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_retention_en:1; + uint32_t reserved_12:2; + /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_clk_sel:2; + uint32_t reserved_16:4; + /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_mode:3; + uint32_t reserved_23:6; + /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_backup_reg_t; + +/** Type of hp_modem_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_backup_clk_reg_t; + +/** Type of hp_modem_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_no_div:1; + /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_sys_clock_en:1; + /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_sys_clk_slp_sel:1; + /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_slp_sel:1; + /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_modem_sysclk_reg_t; + +/** Type of hp_modem_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_modem_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_power_det_bypass:1; + uint32_t reserved_1:15; + /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; + /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; + /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_xpd:1; + /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; + /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; + /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_modem_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator0_reg_t; + +/** Type of hp_modem_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator1_reg_t; + +/** Type of hp_modem_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_modem_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_modem_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_spi_pd_en:1; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_trx:1; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + uint32_t reserved_26:4; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_retention_mode:1; + uint32_t reserved_11:1; + /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_retention_en:1; + /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_retention_en:1; + uint32_t reserved_14:2; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + uint32_t reserved_20:3; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:3; + /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:3; + uint32_t reserved_29:1; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_power_det_bypass:1; + uint32_t reserved_1:15; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 17; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dcdc_reserve register + * need_des + */ +typedef union { + struct { + /** hp_sleep_lp_dcdc_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_dcdc_reserve:32; + }; + uint32_t val; +} pmu_hp_sleep_lp_dcdc_reserve_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_bod_source_sel:1; + /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_vddbat_mode:2; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_lppll:1; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_bias_reserve register + * need_des + */ +typedef union { + struct { + /** lp_sleep_lp_bias_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_bias_reserve:32; + }; + uint32_t val; +} pmu_lp_sleep_lp_bias_reserve_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 17; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_bod_source_sel:1; + /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_vddbat_mode:2; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_lppll:1; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + uint32_t reserved_26:4; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + uint32_t reserved_7:18; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 255; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 255; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpperi_reserve register + * need_des + */ +typedef union { + struct { + /** hp_peri_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_peri_reserve:32; + }; + uint32_t val; +} pmu_power_pd_hpperi_reserve_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_vdd_spi_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; + * need_des + */ + uint32_t vdd_spi_pwr_wait:11; + /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; + * need_des + */ + uint32_t vdd_spi_pwr_sw:2; + /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vdd_spi_pwr_sel_sw:1; + }; + uint32_t val; +} pmu_power_vdd_spi_cntl_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_rftx_i2c:1; + /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_i2c:1; + /** xpd_rfpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_rfpll:1; + /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_force_rfpll:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of vddbat_cfg register + * need_des + */ +typedef union { + struct { + /** vddbat_mode : RO; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t vddbat_mode:2; + uint32_t reserved_2:29; + /** vddbat_sw_update : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vddbat_sw_update:1; + }; + uint32_t val; +} pmu_vddbat_cfg_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 1; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 35688960; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +/** Type of vdd_spi_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t stable_vdd_spi_pwr_drv:1; + }; + uint32_t val; +} pmu_vdd_spi_status_reg_t; + + +typedef struct { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; + volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; + volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; + volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; + volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; + volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; + volatile pmu_hp_modem_bias_reg_t hp_modem_bias; + volatile pmu_hp_modem_backup_reg_t hp_modem_backup; + volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; + volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; + volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; + volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; + volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + volatile pmu_hp_sleep_lp_dcdc_reserve_reg_t hp_sleep_lp_dcdc_reserve; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + volatile pmu_lp_sleep_lp_bias_reserve_reg_t lp_sleep_lp_bias_reserve; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_vddbat_cfg_reg_t vddbat_cfg; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_vdd_spi_status_reg_t vdd_spi_status; + uint32_t reserved_1a8[149]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h new file mode 100644 index 0000000000..356c0e01b1 --- /dev/null +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_SPI0_BASE 0x60002000 +#define DR_REG_SPI1_BASE 0x60003000 +#define DR_REG_I2C_EXT0_BASE 0x60004000 +#define DR_REG_I2C_EXT1_BASE 0x60005000 +#define DR_REG_UHCI0_BASE 0x60006000 +#define DR_REG_RMT_BASE 0x60007000 +#define DR_REG_LEDC_BASE 0x60008000 +#define DR_REG_TIMERGROUP0_BASE 0x60009000 +#define DR_REG_TIMERGROUP1_BASE 0x6000A000 +#define DR_REG_SYSTIMER_BASE 0x6000B000 +#define DR_REG_TWAI_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000D000 +#define DR_REG_APB_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_PCNT_BASE 0x60012000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_MCPWM_BASE 0x60014000 +#define DR_REG_PARl_IO_BASE 0x60015000 +#define DR_REG_PVT_MONITOR_BASE 0x60019000 +#define DR_REG_GDMA_BASE 0x60080000 +#define DR_REG_SPI2_BASE 0x60081000 +#define DR_REG_AES_BASE 0x60088000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_RSA_BASE 0x6008A000 +#define DR_REG_ECC_MULT_BASE 0x6008B000 +#define DR_REG_DS_BASE 0x6008C000 +#define DR_REG_HMAC_BASE 0x6008D000 +#define DR_REG_ECDSA_BASE 0x6008E000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_MEM_ACS_MONITOR_BASE 0x60092000 +#define DR_REG_REGDMA_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_BASE 0x60098000 +#define DR_REG_HP_APM_BASE 0x60099000 +#define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_MISC_BASE 0x6009F000 + +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_EFUSE_BASE 0x600B0800 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LP_IO_BASE 0x600B2000 +#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_OTP_DEBUG_BASE 0x600B3C00 + +#define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 +#define DR_REG_INTPRI_BASE 0x600C5000 +#define DR_REG_EXTMEM_BASE 0x600C8000 diff --git a/components/soc/esp32h2/include/soc/regi2c_bbpll.h b/components/soc/esp32h2/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..3adc301b9a --- /dev/null +++ b/components/soc/esp32h2/include/soc/regi2c_bbpll.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 diff --git a/components/soc/esp32h2/include/soc/regi2c_bias.h b/components/soc/esp32h2/include/soc/regi2c_bias.h new file mode 100644 index 0000000000..512cb54989 --- /dev/null +++ b/components/soc/esp32h2/include/soc/regi2c_bias.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * bootloader_hardware_init function in bootloader_esp32c3.c. + */ + +#define I2C_BIAS 0X6A +#define I2C_BIAS_HOSTID 0 + +#define I2C_BIAS_DREG_1P1_PVT 1 +#define I2C_BIAS_DREG_1P1_PVT_MSB 3 +#define I2C_BIAS_DREG_1P1_PVT_LSB 0 diff --git a/components/soc/esp32h2/include/soc/regi2c_brownout.h b/components/soc/esp32h2/include/soc/regi2c_brownout.h new file mode 100644 index 0000000000..635ad74782 --- /dev/null +++ b/components/soc/esp32h2/include/soc/regi2c_brownout.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_brownout.h + * @brief Register definitions for brownout detector + * + * This file lists register fields of the brownout detector, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h. + */ + +#define I2C_BOD 0x61 +#define I2C_BOD_HOSTID 0 + +#define I2C_BOD_THRESHOLD 0x5 +#define I2C_BOD_THRESHOLD_MSB 2 +#define I2C_BOD_THRESHOLD_LSB 0 diff --git a/components/soc/esp32h2/include/soc/regi2c_defs.h b/components/soc/esp32h2/include/soc/regi2c_defs.h new file mode 100644 index 0000000000..9ff42a0da6 --- /dev/null +++ b/components/soc/esp32h2/include/soc/regi2c_defs.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +#define I2C_MST_ANA_CONF0_REG 0x6000E040 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) + +#define ANA_CONFIG_REG 0x6000E044 +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + + +#define ANA_CONFIG2_REG 0x6000E048 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) + +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround, and is fixed on later chips + */ +#define REGI2C_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32h2/include/soc/regi2c_lp_bias.h b/components/soc/esp32h2/include/soc/regi2c_lp_bias.h new file mode 100644 index 0000000000..4c69ac7d26 --- /dev/null +++ b/components/soc/esp32h2/include/soc/regi2c_lp_bias.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_lp_bias.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of low power dbais, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_init function in rtc_init.c. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 0 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 + +#define I2C_ULP_IR_FORCE_XPD_CK 0 +#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 +#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 + +#define I2C_ULP_IR_FORCE_XPD_IPH 0 +#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4 +#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4 + +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6 + +#define I2C_ULP_O_DONE_FLAG 3 +#define I2C_ULP_O_DONE_FLAG_MSB 0 +#define I2C_ULP_O_DONE_FLAG_LSB 0 + +#define I2C_ULP_BG_O_DONE_FLAG 3 +#define I2C_ULP_BG_O_DONE_FLAG_MSB 3 +#define I2C_ULP_BG_O_DONE_FLAG_LSB 3 + +#define I2C_ULP_OCODE 4 +#define I2C_ULP_OCODE_MSB 7 +#define I2C_ULP_OCODE_LSB 0 + +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 6 +#define I2C_ULP_IR_FORCE_CODE_LSB 6 + +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 diff --git a/components/soc/esp32h2/include/soc/regi2c_saradc.h b/components/soc/esp32h2/include/soc/regi2c_saradc.h new file mode 100644 index 0000000000..c7137f3bb0 --- /dev/null +++ b/components/soc/esp32h2/include/soc/regi2c_saradc.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_saradc.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * function in adc_ll.h. + */ + +#define I2C_SAR_ADC 0X69 +#define I2C_SAR_ADC_HOSTID 0 + +#define ADC_SAR1_ENCAL_GND_ADDR 0x7 +#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 +#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 + +#define ADC_SAR2_ENCAL_GND_ADDR 0x7 +#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 +#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 + +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR1_DREF_ADDR 0x2 +#define ADC_SAR1_DREF_ADDR_MSB 0x6 +#define ADC_SAR1_DREF_ADDR_LSB 0x4 + +#define ADC_SAR2_DREF_ADDR 0x5 +#define ADC_SAR2_DREF_ADDR_MSB 0x6 +#define ADC_SAR2_DREF_ADDR_LSB 0x4 + +#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 + +#define ADC_SARADC_DTEST_RTC_ADDR 0x7 +#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1 +#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0 + +#define ADC_SARADC_ENT_TSENS_ADDR 0x7 +#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2 +#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2 + +#define ADC_SARADC_ENT_RTC_ADDR 0x7 +#define ADC_SARADC_ENT_RTC_ADDR_MSB 3 +#define ADC_SARADC_ENT_RTC_ADDR_LSB 3 + +#define ADC_SARADC1_ENCAL_REF_ADDR 0x7 +#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4 +#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4 + +#define ADC_SARADC2_ENCAL_REF_ADDR 0x7 +#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6 +#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6 + +#define I2C_SARADC_TSENS_DAC 0x6 +#define I2C_SARADC_TSENS_DAC_MSB 3 +#define I2C_SARADC_TSENS_DAC_LSB 0 diff --git a/components/soc/esp32h2/include/soc/reset_reasons.h b/components/soc/esp32h2/include/soc/reset_reasons.h new file mode 100644 index 0000000000..dddfc94eef --- /dev/null +++ b/components/soc/esp32h2/include/soc/reset_reasons.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +// ESP32H2-TODO: IDF-5719 Need update +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core + RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rmt_reg.h b/components/soc/esp32h2/include/soc/rmt_reg.h new file mode 100644 index 0000000000..0bc75f17fc --- /dev/null +++ b/components/soc/esp32h2/include/soc/rmt_reg.h @@ -0,0 +1,1519 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFFU +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFFU +#define RMT_CH0DATA_S 0 + +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFFU +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFFU +#define RMT_CH1DATA_S 0 + +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFFU +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFFU +#define RMT_CH2DATA_S 0 + +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFFU +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFFU +#define RMT_CH3DATA_S 0 + +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) +#define RMT_TX_START_CH0_V 0x00000001U +#define RMT_TX_START_CH0_S 0 +/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) +#define RMT_MEM_RD_RST_CH0_V 0x00000001U +#define RMT_MEM_RD_RST_CH0_S 1 +/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) +#define RMT_APB_MEM_RST_CH0_V 0x00000001U +#define RMT_APB_MEM_RST_CH0_S 2 +/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) +#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH0_S 3 +/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) +#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH0_S 5 +/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) +#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH0_S 6 +/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) +#define RMT_TX_STOP_CH0_V 0x00000001U +#define RMT_TX_STOP_CH0_S 7 +/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_CH0 0x000000FFU +#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) +#define RMT_DIV_CNT_CH0_V 0x000000FFU +#define RMT_DIV_CNT_CH0_S 8 +/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_CH0 0x00000007U +#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) +#define RMT_MEM_SIZE_CH0_V 0x00000007U +#define RMT_MEM_SIZE_CH0_S 16 +/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) +#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) +#define RMT_CARRIER_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EN_CH0_S 21 +/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) +#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/** RMT_AFIFO_RST_CH0 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH0 (BIT(23)) +#define RMT_AFIFO_RST_CH0_M (RMT_AFIFO_RST_CH0_V << RMT_AFIFO_RST_CH0_S) +#define RMT_AFIFO_RST_CH0_V 0x00000001U +#define RMT_AFIFO_RST_CH0_S 23 +/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S) +#define RMT_CONF_UPDATE_CH0_V 0x00000001U +#define RMT_CONF_UPDATE_CH0_S 24 + +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 1 +/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 2 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 3 +/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 5 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 6 +/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 7 +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_CH1 0x00000007U +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x00000007U +#define RMT_MEM_SIZE_CH1_S 16 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 21 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/** RMT_AFIFO_RST_CH1 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH1 (BIT(23)) +#define RMT_AFIFO_RST_CH1_M (RMT_AFIFO_RST_CH1_V << RMT_AFIFO_RST_CH1_S) +#define RMT_AFIFO_RST_CH1_V 0x00000001U +#define RMT_AFIFO_RST_CH1_S 23 +/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S) +#define RMT_CONF_UPDATE_CH1_V 0x00000001U +#define RMT_CONF_UPDATE_CH1_S 24 + +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 0 +/** RMT_IDLE_THRES_CH2 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH2 0x00007FFFU +#define RMT_IDLE_THRES_CH2_M (RMT_IDLE_THRES_CH2_V << RMT_IDLE_THRES_CH2_S) +#define RMT_IDLE_THRES_CH2_V 0x00007FFFU +#define RMT_IDLE_THRES_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_CH2 0x00000007U +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x00000007U +#define RMT_MEM_SIZE_CH2_S 23 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 28 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 29 + +/** RMT_CH2CONF1_REG register + * Channel 2 configure register 1 + */ +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_RX_EN_CH2 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL2. + */ +#define RMT_RX_EN_CH2 (BIT(0)) +#define RMT_RX_EN_CH2_M (RMT_RX_EN_CH2_V << RMT_RX_EN_CH2_S) +#define RMT_RX_EN_CH2_V 0x00000001U +#define RMT_RX_EN_CH2_S 0 +/** RMT_MEM_WR_RST_CH2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL2 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH2 (BIT(1)) +#define RMT_MEM_WR_RST_CH2_M (RMT_MEM_WR_RST_CH2_V << RMT_MEM_WR_RST_CH2_S) +#define RMT_MEM_WR_RST_CH2_V 0x00000001U +#define RMT_MEM_WR_RST_CH2_S 1 +/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 2 +/** RMT_MEM_OWNER_CH2 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL2's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH2 (BIT(3)) +#define RMT_MEM_OWNER_CH2_M (RMT_MEM_OWNER_CH2_V << RMT_MEM_OWNER_CH2_S) +#define RMT_MEM_OWNER_CH2_V 0x00000001U +#define RMT_MEM_OWNER_CH2_S 3 +/** RMT_RX_FILTER_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL2. + */ +#define RMT_RX_FILTER_EN_CH2 (BIT(4)) +#define RMT_RX_FILTER_EN_CH2_M (RMT_RX_FILTER_EN_CH2_V << RMT_RX_FILTER_EN_CH2_S) +#define RMT_RX_FILTER_EN_CH2_V 0x00000001U +#define RMT_RX_FILTER_EN_CH2_S 4 +/** RMT_RX_FILTER_THRES_CH2 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH2 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_M (RMT_RX_FILTER_THRES_CH2_V << RMT_RX_FILTER_THRES_CH2_S) +#define RMT_RX_FILTER_THRES_CH2_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_S 5 +/** RMT_MEM_RX_WRAP_EN_CH2 : R/W; bitpos: [13]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH2_M (RMT_MEM_RX_WRAP_EN_CH2_V << RMT_MEM_RX_WRAP_EN_CH2_S) +#define RMT_MEM_RX_WRAP_EN_CH2_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH2_S 13 +/** RMT_AFIFO_RST_CH2 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH2 (BIT(14)) +#define RMT_AFIFO_RST_CH2_M (RMT_AFIFO_RST_CH2_V << RMT_AFIFO_RST_CH2_S) +#define RMT_AFIFO_RST_CH2_V 0x00000001U +#define RMT_AFIFO_RST_CH2_S 14 +/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_CH2 (BIT(15)) +#define RMT_CONF_UPDATE_CH2_M (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S) +#define RMT_CONF_UPDATE_CH2_V 0x00000001U +#define RMT_CONF_UPDATE_CH2_S 15 + +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 0 +/** RMT_IDLE_THRES_CH3 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH3 0x00007FFFU +#define RMT_IDLE_THRES_CH3_M (RMT_IDLE_THRES_CH3_V << RMT_IDLE_THRES_CH3_S) +#define RMT_IDLE_THRES_CH3_V 0x00007FFFU +#define RMT_IDLE_THRES_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_CH3 0x00000007U +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x00000007U +#define RMT_MEM_SIZE_CH3_S 23 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 28 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 29 + +/** RMT_CH3CONF1_REG register + * Channel 3 configure register 1 + */ +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_RX_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL3. + */ +#define RMT_RX_EN_CH3 (BIT(0)) +#define RMT_RX_EN_CH3_M (RMT_RX_EN_CH3_V << RMT_RX_EN_CH3_S) +#define RMT_RX_EN_CH3_V 0x00000001U +#define RMT_RX_EN_CH3_S 0 +/** RMT_MEM_WR_RST_CH3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL3 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH3 (BIT(1)) +#define RMT_MEM_WR_RST_CH3_M (RMT_MEM_WR_RST_CH3_V << RMT_MEM_WR_RST_CH3_S) +#define RMT_MEM_WR_RST_CH3_V 0x00000001U +#define RMT_MEM_WR_RST_CH3_S 1 +/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 2 +/** RMT_MEM_OWNER_CH3 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL3's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH3 (BIT(3)) +#define RMT_MEM_OWNER_CH3_M (RMT_MEM_OWNER_CH3_V << RMT_MEM_OWNER_CH3_S) +#define RMT_MEM_OWNER_CH3_V 0x00000001U +#define RMT_MEM_OWNER_CH3_S 3 +/** RMT_RX_FILTER_EN_CH3 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL3. + */ +#define RMT_RX_FILTER_EN_CH3 (BIT(4)) +#define RMT_RX_FILTER_EN_CH3_M (RMT_RX_FILTER_EN_CH3_V << RMT_RX_FILTER_EN_CH3_S) +#define RMT_RX_FILTER_EN_CH3_V 0x00000001U +#define RMT_RX_FILTER_EN_CH3_S 4 +/** RMT_RX_FILTER_THRES_CH3 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH3 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_M (RMT_RX_FILTER_THRES_CH3_V << RMT_RX_FILTER_THRES_CH3_S) +#define RMT_RX_FILTER_THRES_CH3_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_S 5 +/** RMT_MEM_RX_WRAP_EN_CH3 : R/W; bitpos: [13]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH3_M (RMT_MEM_RX_WRAP_EN_CH3_V << RMT_MEM_RX_WRAP_EN_CH3_S) +#define RMT_MEM_RX_WRAP_EN_CH3_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH3_S 13 +/** RMT_AFIFO_RST_CH3 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH3 (BIT(14)) +#define RMT_AFIFO_RST_CH3_M (RMT_AFIFO_RST_CH3_V << RMT_AFIFO_RST_CH3_S) +#define RMT_AFIFO_RST_CH3_V 0x00000001U +#define RMT_AFIFO_RST_CH3_S 14 +/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_CH3 (BIT(15)) +#define RMT_CONF_UPDATE_CH3_M (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S) +#define RMT_CONF_UPDATE_CH3_V 0x00000001U +#define RMT_CONF_UPDATE_CH3_S 15 + +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH0 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) +#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_STATE_CH0 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_CH0 0x00000007U +#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) +#define RMT_STATE_CH0_V 0x00000007U +#define RMT_STATE_CH0_S 9 +/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH0 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) +#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_S 12 +/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH0 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) +#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH0_S 21 +/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH0 (BIT(22)) +#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) +#define RMT_MEM_EMPTY_CH0_V 0x00000001U +#define RMT_MEM_EMPTY_CH0_S 22 +/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH0_S 23 +/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH0 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) +#define RMT_APB_MEM_RADDR_CH0_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_S 24 + +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH1 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_STATE_CH1 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 9 +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH1 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_S 12 +/** RMT_APB_MEM_RD_ERR_CH1 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH1_M (RMT_APB_MEM_RD_ERR_CH1_V << RMT_APB_MEM_RD_ERR_CH1_S) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH1_S 21 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH1 (BIT(22)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 22 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 23 +/** RMT_APB_MEM_RADDR_CH1 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH1 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_M (RMT_APB_MEM_RADDR_CH1_V << RMT_APB_MEM_RADDR_CH1_S) +#define RMT_APB_MEM_RADDR_CH1_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_S 24 + +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_MEM_WADDR_EX_CH2 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL2 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH2 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_M (RMT_MEM_WADDR_EX_CH2_V << RMT_MEM_WADDR_EX_CH2_S) +#define RMT_MEM_WADDR_EX_CH2_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_S 0 +/** RMT_APB_MEM_RADDR_CH2 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH2 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_M (RMT_APB_MEM_RADDR_CH2_V << RMT_APB_MEM_RADDR_CH2_S) +#define RMT_APB_MEM_RADDR_CH2_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_S 12 +/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 22 +/** RMT_MEM_OWNER_ERR_CH2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH2 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH2_M (RMT_MEM_OWNER_ERR_CH2_V << RMT_MEM_OWNER_ERR_CH2_S) +#define RMT_MEM_OWNER_ERR_CH2_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH2_S 25 +/** RMT_MEM_FULL_CH2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH2 (BIT(26)) +#define RMT_MEM_FULL_CH2_M (RMT_MEM_FULL_CH2_V << RMT_MEM_FULL_CH2_S) +#define RMT_MEM_FULL_CH2_V 0x00000001U +#define RMT_MEM_FULL_CH2_S 26 +/** RMT_APB_MEM_RD_ERR_CH2 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_M (RMT_APB_MEM_RD_ERR_CH2_V << RMT_APB_MEM_RD_ERR_CH2_S) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH2_S 27 + +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_MEM_WADDR_EX_CH3 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL3 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH3 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_M (RMT_MEM_WADDR_EX_CH3_V << RMT_MEM_WADDR_EX_CH3_S) +#define RMT_MEM_WADDR_EX_CH3_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_S 0 +/** RMT_APB_MEM_RADDR_CH3 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH3 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_M (RMT_APB_MEM_RADDR_CH3_V << RMT_APB_MEM_RADDR_CH3_S) +#define RMT_APB_MEM_RADDR_CH3_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_S 12 +/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 22 +/** RMT_MEM_OWNER_ERR_CH3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH3 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH3_M (RMT_MEM_OWNER_ERR_CH3_V << RMT_MEM_OWNER_ERR_CH3_S) +#define RMT_MEM_OWNER_ERR_CH3_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH3_S 25 +/** RMT_MEM_FULL_CH3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH3 (BIT(26)) +#define RMT_MEM_FULL_CH3_M (RMT_MEM_FULL_CH3_V << RMT_MEM_FULL_CH3_S) +#define RMT_MEM_FULL_CH3_V 0x00000001U +#define RMT_MEM_FULL_CH3_S 26 +/** RMT_APB_MEM_RD_ERR_CH3 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_M (RMT_APB_MEM_RD_ERR_CH3_V << RMT_APB_MEM_RD_ERR_CH3_S) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH3_S 27 + +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_RX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ +#define RMT_CH2_RX_END_INT_RAW (BIT(2)) +#define RMT_CH2_RX_END_INT_RAW_M (RMT_CH2_RX_END_INT_RAW_V << RMT_CH2_RX_END_INT_RAW_S) +#define RMT_CH2_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_END_INT_RAW_S 2 +/** RMT_CH3_RX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ +#define RMT_CH3_RX_END_INT_RAW (BIT(3)) +#define RMT_CH3_RX_END_INT_RAW_M (RMT_CH3_RX_END_INT_RAW_V << RMT_CH3_RX_END_INT_RAW_S) +#define RMT_CH3_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001U +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001U +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001U +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001U +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (RMT_CH2_RX_THR_EVENT_INT_RAW_V << RMT_CH2_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (RMT_CH3_RX_THR_EVENT_INT_RAW_V << RMT_CH3_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 + +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001U +#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001U +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_RX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ST (BIT(2)) +#define RMT_CH2_RX_END_INT_ST_M (RMT_CH2_RX_END_INT_ST_V << RMT_CH2_RX_END_INT_ST_S) +#define RMT_CH2_RX_END_INT_ST_V 0x00000001U +#define RMT_CH2_RX_END_INT_ST_S 2 +/** RMT_CH3_RX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ST (BIT(3)) +#define RMT_CH3_RX_END_INT_ST_M (RMT_CH3_RX_END_INT_ST_V << RMT_CH3_RX_END_INT_ST_S) +#define RMT_CH3_RX_END_INT_ST_V 0x00000001U +#define RMT_CH3_RX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001U +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001U +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001U +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001U +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ST_M (RMT_CH2_RX_THR_EVENT_INT_ST_V << RMT_CH2_RX_THR_EVENT_INT_ST_S) +#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ST_M (RMT_CH3_RX_THR_EVENT_INT_ST_V << RMT_CH3_RX_THR_EVENT_INT_ST_S) +#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ST_S 13 + +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_RX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ENA (BIT(2)) +#define RMT_CH2_RX_END_INT_ENA_M (RMT_CH2_RX_END_INT_ENA_V << RMT_CH2_RX_END_INT_ENA_S) +#define RMT_CH2_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_END_INT_ENA_S 2 +/** RMT_CH3_RX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ENA (BIT(3)) +#define RMT_CH3_RX_END_INT_ENA_M (RMT_CH3_RX_END_INT_ENA_V << RMT_CH3_RX_END_INT_ENA_S) +#define RMT_CH3_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001U +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001U +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001U +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001U +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (RMT_CH2_RX_THR_EVENT_INT_ENA_V << RMT_CH2_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (RMT_CH3_RX_THR_EVENT_INT_ENA_V << RMT_CH3_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 + +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_RX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ +#define RMT_CH2_RX_END_INT_CLR (BIT(2)) +#define RMT_CH2_RX_END_INT_CLR_M (RMT_CH2_RX_END_INT_CLR_V << RMT_CH2_RX_END_INT_CLR_S) +#define RMT_CH2_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_END_INT_CLR_S 2 +/** RMT_CH3_RX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ +#define RMT_CH3_RX_END_INT_CLR (BIT(3)) +#define RMT_CH3_RX_END_INT_CLR_M (RMT_CH3_RX_END_INT_CLR_V << RMT_CH3_RX_END_INT_CLR_S) +#define RMT_CH3_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001U +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001U +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001U +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001U +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (RMT_CH2_RX_THR_EVENT_INT_CLR_V << RMT_CH2_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (RMT_CH3_RX_THR_EVENT_INT_CLR_V << RMT_CH3_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 + +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_S 16 + +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 + +/** RMT_CH2_RX_CARRIER_RM_REG register + * Channel 2 carrier remove register + */ +#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_CARRIER_LOW_THRES_CH2 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_M (RMT_CARRIER_LOW_THRES_CH2_V << RMT_CARRIER_LOW_THRES_CH2_S) +#define RMT_CARRIER_LOW_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_S 0 +/** RMT_CARRIER_HIGH_THRES_CH2 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_M (RMT_CARRIER_HIGH_THRES_CH2_V << RMT_CARRIER_HIGH_THRES_CH2_S) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 + +/** RMT_CH3_RX_CARRIER_RM_REG register + * Channel 3 carrier remove register + */ +#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_CARRIER_LOW_THRES_CH3 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_M (RMT_CARRIER_LOW_THRES_CH3_V << RMT_CARRIER_LOW_THRES_CH3_S) +#define RMT_CARRIER_LOW_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_S 0 +/** RMT_CARRIER_HIGH_THRES_CH3 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_M (RMT_CARRIER_HIGH_THRES_CH3_V << RMT_CARRIER_HIGH_THRES_CH3_S) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 + +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FFU +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FFU +#define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL0. + */ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S) +#define RMT_LOOP_STOP_EN_CH0_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH0_S 21 + +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL1. + */ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S) +#define RMT_LOOP_STOP_EN_CH1_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH1_S 21 + +/** RMT_CH2_RX_LIM_REG register + * Channel 2 Rx event configuration register + */ +#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can receive. + */ +#define RMT_RMT_RX_LIM_CH2 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_M (RMT_RMT_RX_LIM_CH2_V << RMT_RMT_RX_LIM_CH2_S) +#define RMT_RMT_RX_LIM_CH2_V 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_S 0 + +/** RMT_CH3_RX_LIM_REG register + * Channel 3 Rx event configuration register + */ +#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can receive. + */ +#define RMT_RMT_RX_LIM_CH2 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_M (RMT_RMT_RX_LIM_CH2_V << RMT_RMT_RX_LIM_CH2_S) +#define RMT_RMT_RX_LIM_CH2_V 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_S 0 + +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001U +#define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001U +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_RMT_MEM_FORCE_PD_M (RMT_RMT_MEM_FORCE_PD_V << RMT_RMT_MEM_FORCE_PD_S) +#define RMT_RMT_MEM_FORCE_PD_V 0x00000001U +#define RMT_RMT_MEM_FORCE_PD_S 2 +/** RMT_RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_RMT_MEM_FORCE_PU_M (RMT_RMT_MEM_FORCE_PU_V << RMT_RMT_MEM_FORCE_PU_S) +#define RMT_RMT_MEM_FORCE_PU_V 0x00000001U +#define RMT_RMT_MEM_FORCE_PU_S 3 +/** RMT_RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_RMT_SCLK_DIV_NUM 0x000000FFU +#define RMT_RMT_SCLK_DIV_NUM_M (RMT_RMT_SCLK_DIV_NUM_V << RMT_RMT_SCLK_DIV_NUM_S) +#define RMT_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define RMT_RMT_SCLK_DIV_NUM_S 4 +/** RMT_RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_RMT_SCLK_DIV_A 0x0000003FU +#define RMT_RMT_SCLK_DIV_A_M (RMT_RMT_SCLK_DIV_A_V << RMT_RMT_SCLK_DIV_A_S) +#define RMT_RMT_SCLK_DIV_A_V 0x0000003FU +#define RMT_RMT_SCLK_DIV_A_S 12 +/** RMT_RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_RMT_SCLK_DIV_B 0x0000003FU +#define RMT_RMT_SCLK_DIV_B_M (RMT_RMT_SCLK_DIV_B_V << RMT_RMT_SCLK_DIV_B_S) +#define RMT_RMT_SCLK_DIV_B_V 0x0000003FU +#define RMT_RMT_SCLK_DIV_B_S 18 +/** RMT_RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ +#define RMT_RMT_SCLK_SEL 0x00000003U +#define RMT_RMT_SCLK_SEL_M (RMT_RMT_SCLK_SEL_V << RMT_RMT_SCLK_SEL_S) +#define RMT_RMT_SCLK_SEL_V 0x00000003U +#define RMT_RMT_SCLK_SEL_S 24 +/** RMT_RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_RMT_SCLK_ACTIVE_M (RMT_RMT_SCLK_ACTIVE_V << RMT_RMT_SCLK_ACTIVE_S) +#define RMT_RMT_SCLK_ACTIVE_V 0x00000001U +#define RMT_RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001U +#define RMT_CLK_EN_S 31 + +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001U +#define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001U +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_EN : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(2)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001U +#define RMT_TX_SIM_EN_S 2 + +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001U +#define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001U +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001U +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001U +#define RMT_REF_CNT_RST_CH3_S 3 + +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_RMT_DATE : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ +#define RMT_RMT_DATE 0x0FFFFFFFU +#define RMT_RMT_DATE_M (RMT_RMT_DATE_V << RMT_RMT_DATE_S) +#define RMT_RMT_DATE_V 0x0FFFFFFFU +#define RMT_RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rmt_struct.h b/components/soc/esp32h2/include/soc/rmt_struct.h new file mode 100644 index 0000000000..0f67600841 --- /dev/null +++ b/components/soc/esp32h2/include/soc/rmt_struct.h @@ -0,0 +1,808 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chndata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata:32; + }; + uint32_t val; +} rmt_chndata_reg_t; + +/** Type of chmdata register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +typedef union { + struct { + /** chmdata : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ + uint32_t chmdata: 32; + }; + uint32_t val; +} rmt_chmdata_reg_t; + + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_chn : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_chn:1; + /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_chn:1; + /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_chn:1; + /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_chn:1; + /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_chn:1; + /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_chn:1; + /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_chn:1; + /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_chn:1; + /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_chn:8; + /** mem_size_chn : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_chn:3; + uint32_t reserved_19:1; + /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_chn:1; + /** carrier_en_chn : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chn:1; + /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chn:1; + /** afifo_rst_chn : WT; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t afifo_rst_chn:1; + /** conf_update_chn : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +/** Type of chmconf0 register + * Channel m configure register 0 + */ +typedef union { + struct { + /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_chm:8; + /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_chm:15; + /** mem_size_chm : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_chm:3; + uint32_t reserved_26:2; + /** carrier_en_chm : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chm:1; + /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chm:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_chmconf0_reg_t; + +/** Type of chmconf1 register + * Channel m configure register 1 + */ +typedef union { + struct { + /** rx_en_chm : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_chm:1; + /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_chm:1; + /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_chm:1; + /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_chm:1; + /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_chm:1; + /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_chm:8; + /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_chm:1; + /** afifo_rst_chm : WT; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t afifo_rst_chm:1; + /** conf_update_chm : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_chm:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} rmt_chmconf1_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu:1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ + uint32_t sclk_sel:2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active:1; + uint32_t reserved_27:4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0:1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1:1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2:1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_chn:9; + /** state_chn : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_chn:3; + /** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_chn:9; + /** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ + uint32_t apb_mem_rd_err_chn:1; + /** mem_empty_chn : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_chn:1; + /** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_chn:1; + /** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ + uint32_t apb_mem_raddr_chn:8; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_chm:9; + uint32_t reserved_9:3; + /** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_chm:9; + uint32_t reserved_21:1; + /** state_chm : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_chm:3; + /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_chm:1; + /** mem_full_chm : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_chm:1; + /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_chm:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw:1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw:1; + /** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ + uint32_t ch2_rx_end_int_raw:1; + /** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ + uint32_t ch3_rx_end_int_raw:1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw:1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw:1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw:1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw:1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw:1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw:1; + /** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch2_rx_thr_event_int_raw:1; + /** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch3_rx_thr_event_int_raw:1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw:1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st:1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st:1; + /** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_st:1; + /** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_st:1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_st:1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_st:1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_st:1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_st:1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st:1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st:1; + /** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_st:1; + /** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_st:1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st:1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena:1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena:1; + /** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_ena:1; + /** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_ena:1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_ena:1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_ena:1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_ena:1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_ena:1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena:1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena:1; + /** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_ena:1; + /** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_ena:1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena:1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr:1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr:1; + /** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ + uint32_t ch2_rx_end_int_clr:1; + /** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ + uint32_t ch3_rx_end_int_clr:1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr:1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr:1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr:1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr:1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr:1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr:1; + /** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_rx_thr_event_int_clr:1; + /** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_rx_thr_event_int_clr:1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr:1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_clr_reg_t; + + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn:16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn:16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm:16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm:16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn:9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn:10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn:1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn:1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0:1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1:1; + /** tx_sim_en : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** rmt_rx_lim_chm : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t rmt_rx_lim_chm:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** rmt_date : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ + uint32_t rmt_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_date_reg_t; + + +typedef struct rmt_dev_t { + volatile rmt_chndata_reg_t chndata[2]; + volatile rmt_chmdata_reg_t chmdata[2]; + volatile rmt_chnconf0_reg_t chnconf0[2]; + volatile struct { + rmt_chmconf0_reg_t conf0; + rmt_chmconf1_reg_t conf1; + } chmconf[2]; + volatile rmt_chnstatus_reg_t chnstatus[2]; + volatile rmt_chmstatus_reg_t chmstatus[2]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + uint32_t reserved_074[22]; + volatile rmt_date_reg_t date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rsa_reg.h b/components/soc/esp32h2/include/soc/rsa_reg.h new file mode 100644 index 0000000000..4769566cdd --- /dev/null +++ b/components/soc/esp32h2/include/soc/rsa_reg.h @@ -0,0 +1,233 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RSA_M_MEM register + * Represents M + */ +#define RSA_M_MEM_REG (DR_REG_RSA_BASE + 0x0) +#define RSA_M_MEM_SIZE_BYTES 16 + +/** RSA_Z_MEM register + * Represents Z + */ +#define RSA_Z_MEM_REG (DR_REG_RSA_BASE + 0x200) +#define RSA_Z_MEM_SIZE_BYTES 16 + +/** RSA_Y_MEM register + * Represents Y + */ +#define RSA_Y_MEM_REG (DR_REG_RSA_BASE + 0x400) +#define RSA_Y_MEM_SIZE_BYTES 16 + +/** RSA_X_MEM register + * Represents X + */ +#define RSA_X_MEM_REG (DR_REG_RSA_BASE + 0x600) +#define RSA_X_MEM_SIZE_BYTES 16 + +/** RSA_M_PRIME_REG register + * Represents M’ + */ +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) +/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Represents M’ + */ +#define RSA_M_PRIME 0xFFFFFFFFU +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFFU +#define RSA_M_PRIME_S 0 + +/** RSA_MODE_REG register + * Configures RSA length + */ +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) +/** RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ +#define RSA_MODE 0x0000007FU +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007FU +#define RSA_MODE_S 0 + +/** RSA_QUERY_CLEAN_REG register + * RSA clean register + */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) +/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ +#define RSA_QUERY_CLEAN (BIT(0)) +#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) +#define RSA_QUERY_CLEAN_V 0x00000001U +#define RSA_QUERY_CLEAN_S 0 + +/** RSA_SET_START_MODEXP_REG register + * Starts modular exponentiation + */ +#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) +/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODEXP (BIT(0)) +#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) +#define RSA_SET_START_MODEXP_V 0x00000001U +#define RSA_SET_START_MODEXP_S 0 + +/** RSA_SET_START_MODMULT_REG register + * Starts modular multiplication + */ +#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) +/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODMULT (BIT(0)) +#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) +#define RSA_SET_START_MODMULT_V 0x00000001U +#define RSA_SET_START_MODMULT_S 0 + +/** RSA_SET_START_MULT_REG register + * Starts multiplication + */ +#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) +/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MULT (BIT(0)) +#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) +#define RSA_SET_START_MULT_V 0x00000001U +#define RSA_SET_START_MULT_S 0 + +/** RSA_QUERY_IDLE_REG register + * Represents the RSA status + */ +#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) +/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ +#define RSA_QUERY_IDLE (BIT(0)) +#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) +#define RSA_QUERY_IDLE_V 0x00000001U +#define RSA_QUERY_IDLE_S 0 + +/** RSA_INT_CLR_REG register + * Clears RSA interrupt + */ +#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c) +/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001U +#define RSA_CLEAR_INTERRUPT_S 0 + +/** RSA_CONSTANT_TIME_REG register + * Configures the constant_time option + */ +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001U +#define RSA_CONSTANT_TIME_S 0 + +/** RSA_SEARCH_ENABLE_REG register + * Configures the search option + */ +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) +/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001U +#define RSA_SEARCH_ENABLE_S 0 + +/** RSA_SEARCH_POS_REG register + * Configures the search position + */ +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) +/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ +#define RSA_SEARCH_POS 0x00000FFFU +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFFU +#define RSA_SEARCH_POS_S 0 + +/** RSA_INT_ENA_REG register + * Enables the RSA interrupt + */ +#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c) +/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ +#define RSA_INT_ENA (BIT(0)) +#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S) +#define RSA_INT_ENA_V 0x00000001U +#define RSA_INT_ENA_S 0 + +/** RSA_DATE_REG register + * Version control register + */ +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) +/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ +#define RSA_DATE 0x3FFFFFFFU +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFFU +#define RSA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rsa_struct.h b/components/soc/esp32h2/include/soc/rsa_struct.h new file mode 100644 index 0000000000..9e5fea003f --- /dev/null +++ b/components/soc/esp32h2/include/soc/rsa_struct.h @@ -0,0 +1,273 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory */ + +/** Group: Control / Configuration Registers */ +/** Type of m_prime register + * Represents M’ + */ +typedef union { + struct { + /** m_prime : R/W; bitpos: [31:0]; default: 0; + * Represents M’ + */ + uint32_t m_prime:32; + }; + uint32_t val; +} rsa_m_prime_reg_t; + +/** Type of mode register + * Configures RSA length + */ +typedef union { + struct { + /** mode : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ + uint32_t mode:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} rsa_mode_reg_t; + +/** Type of set_start_modexp register + * Starts modular exponentiation + */ +typedef union { + struct { + /** set_start_modexp : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modexp:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modexp_reg_t; + +/** Type of set_start_modmult register + * Starts modular multiplication + */ +typedef union { + struct { + /** set_start_modmult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modmult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modmult_reg_t; + +/** Type of set_start_mult register + * Starts multiplication + */ +typedef union { + struct { + /** set_start_mult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_mult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_mult_reg_t; + +/** Type of query_idle register + * Represents the RSA status + */ +typedef union { + struct { + /** query_idle : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ + uint32_t query_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_idle_reg_t; + +/** Type of constant_time register + * Configures the constant_time option + */ +typedef union { + struct { + /** constant_time : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ + uint32_t constant_time:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_constant_time_reg_t; + +/** Type of search_enable register + * Configures the search option + */ +typedef union { + struct { + /** search_enable : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ + uint32_t search_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_search_enable_reg_t; + +/** Type of search_pos register + * Configures the search position + */ +typedef union { + struct { + /** search_pos : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ + uint32_t search_pos:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} rsa_search_pos_reg_t; + + +/** Group: Status Register */ +/** Type of query_clean register + * RSA clean register + */ +typedef union { + struct { + /** query_clean : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ + uint32_t query_clean:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_clean_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_clr register + * Clears RSA interrupt + */ +typedef union { + struct { + /** clear_interrupt : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_clr_reg_t; + +/** Type of int_ena register + * Enables the RSA interrupt + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_ena_reg_t; + + +/** Group: Version Control Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} rsa_date_reg_t; + + +typedef struct { + volatile uint32_t m[4]; + uint32_t reserved_010[124]; + volatile uint32_t z[4]; + uint32_t reserved_210[124]; + volatile uint32_t y[4]; + uint32_t reserved_410[124]; + volatile uint32_t x[4]; + uint32_t reserved_610[124]; + volatile rsa_m_prime_reg_t m_prime; + volatile rsa_mode_reg_t mode; + volatile rsa_query_clean_reg_t query_clean; + volatile rsa_set_start_modexp_reg_t set_start_modexp; + volatile rsa_set_start_modmult_reg_t set_start_modmult; + volatile rsa_set_start_mult_reg_t set_start_mult; + volatile rsa_query_idle_reg_t query_idle; + volatile rsa_int_clr_reg_t int_clr; + volatile rsa_constant_time_reg_t constant_time; + volatile rsa_search_enable_reg_t search_enable; + volatile rsa_search_pos_reg_t search_pos; + volatile rsa_int_ena_reg_t int_ena; + volatile rsa_date_reg_t date; +} rsa_dev_t; + +extern rsa_dev_t RSA; + +#ifndef __cplusplus +_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h new file mode 100644 index 0000000000..b67768391d --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -0,0 +1,834 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + */ +#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias +#define RTC_CNTL_DBIAS_0V90 13 //digital voltage +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact + +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + */ +#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 +#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 +#define SOC_DELAY_RC_FAST_ENABLE 50 +#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 + +/* Core voltage: + * Currently, ESP32C3 never adjust its wake voltage in runtime + * Only sets dig/rtc voltage dbias at startup time + */ +#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) +#define RTC_CNTL_MIN_SLP_VAL_MIN (2) + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_32M = 32, + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL + RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = RTC_XTAL_FREQ_40M, \ + .cpu_freq_mhz = 80, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +typedef struct { + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t bt_powerup_cycles : 7; + uint16_t bt_wait_cycles : 9; + uint16_t cpu_top_powerup_cycles : 7; + uint16_t cpu_top_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t dg_peri_powerup_cycles : 7; + uint16_t dg_peri_wait_cycles : 9; +} rtc_init_config_t; + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ + .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + +void rtc_clk_divider_set(uint32_t div); + +void rtc_clk_8m_divider_set(uint32_t div); + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(void); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) + */ +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) + */ +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Measure ratio between XTAL frequency and RTC slow clock frequency + * @param cal_clk slow clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average ratio between XTAL frequency and slow clock frequency, + * Q13.19 fixed point format, or 0 if calibration has timed out. + */ +uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +uint64_t rtc_light_slp_time_get(void); + +uint64_t rtc_deep_slp_time_get(void); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(void); + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +void rtc_dig_clk8m_enable(void); + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +void rtc_dig_clk8m_disable(void); + +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +uint32_t rtc_clk_freq_cal(uint32_t cal_val); + +/** + * @brief Power down flags for rtc_sleep_pd function + */ +typedef struct { + uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep + uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep + uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep + uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep + uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep + uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep +} rtc_sleep_pu_config_t; + +/** + * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value + */ +#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ + .sram_fpu = (val), \ + .rom_ram_fpu = (val), \ +} + +void rtc_sleep_pu(rtc_sleep_pu_config_t cfg); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t bt_pd_en : 1; //!< power down BT + uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. + uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator + uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator + uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject +} rtc_sleep_config_t; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU +#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator +#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI +#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT +#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart +#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals +#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator +#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL + +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + +/** + * @brief Low level initialize for rtc state machine waiting cycles after waking up + * + * This function configures the cycles chip need to wait for internal 8MHz + * oscillator and external 40MHz crystal. As we configure fixed time for waiting + * crystal, we need to pass period to calculate cycles. Now this function only + * used in lightsleep mode. + * + * @param slowclk_period re-calibrated slow clock period + */ +void rtc_sleep_low_init(uint32_t slowclk_period); + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_USB_TRIG_EN BIT(14) +#define RTC_BROWNOUT_DET_TRIG_EN BIT(16) + +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_USB_TRIG_EN | \ + RTC_BROWNOUT_DET_TRIG_EN) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); + +/** + * @brief Enter deep sleep mode + * + * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value + * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake + * stub is valid to execute (if a wake address is set). + * + * No RAM is accessed while calculating the CRC and going into deep sleep, which makes + * this function safe to use even if the caller's stack is in RTC FAST memory. + * + * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will + * have the same effect and takes less time as CRC calculation is skipped. + * + * @note This function should only be called after rtc_sleep_init() has been called to + * configure the system for deep sleep. + * + * @param wakeup_opt - same as for rtc_sleep_start + * @param reject_opt - same as for rtc_sleep_start + * + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; + uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise. +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1, \ + .cali_ocode = 0\ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + +/** + * Structure describing vddsdio configuration + */ +typedef struct { + uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. + uint32_t enable : 1; //!< Enable VDDSDIO regulator + uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator +} rtc_vddsdio_config_t; + +/** + * Get current VDDSDIO configuration + * If VDDSDIO configuration is overridden by RTC, get values from RTC + * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE + * Otherwise, use default values and the level of MTDI bootstrapping pin. + * @return currently used VDDSDIO configuration + */ +rtc_vddsdio_config_t rtc_vddsdio_get_config(void); + +/** + * Set new VDDSDIO configuration using RTC registers. + * If config.force == 1, this overrides configuration done using bootstrapping + * pins and EFUSE. + * + * @param config new VDDSDIO configuration + */ +void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + + +// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- +// **WARNING**: The following are only for backwards compatibility. +// Please use the declarations in soc/clk_tree_defs.h instead. +/** + * @brief CPU clock source + */ +typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; +#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL +#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M) +#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; +#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator +#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL +#define RTC_SLOW_FREQ_8MD256 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 //!< Internal 17.5 MHz RC oscillator, divided by 256 + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; +#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 +#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator + +/* Alias of frequency related macros */ +#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_8MD256 SOC_CLK_RC_FAST_D256_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX + +/* Alias of deprecated function names */ +#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) +#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() +#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) +#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/sha_reg.h b/components/soc/esp32h2/include/soc/sha_reg.h new file mode 100644 index 0000000000..b5a4529f4e --- /dev/null +++ b/components/soc/esp32h2/include/soc/sha_reg.h @@ -0,0 +1,172 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Initial configuration register. + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_T_STRING_REG register + * SHA 512/t configuration register 0. + */ +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) +/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ +#define SHA_T_STRING 0xFFFFFFFFU +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFFU +#define SHA_T_STRING_S 0 + +/** SHA_T_LENGTH_REG register + * SHA 512/t configuration register 1. + */ +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) +/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ +#define SHA_T_LENGTH 0x0000003FU +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003FU +#define SHA_T_LENGTH_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * DMA configuration register 0. + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Typical SHA configuration register 0. + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_START 0x7FFFFFFFU +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x7FFFFFFFU +#define SHA_START_S 1 + +/** SHA_CONTINUE_REG register + * Typical SHA configuration register 1. + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x7FFFFFFFU +#define SHA_CONTINUE_S 1 + +/** SHA_BUSY_REG register + * Busy register. + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * DMA configuration register 1. + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * DMA configuration register 2. + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * Interrupt clear register. + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * Interrupt enable register. + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Date register. + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or finial hash. + */ +#define SHA_H_MEM_REG (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM_REG (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 64 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/sha_struct.h b/components/soc/esp32h2/include/soc/sha_struct.h new file mode 100644 index 0000000000..7129b040f0 --- /dev/null +++ b/components/soc/esp32h2/include/soc/sha_struct.h @@ -0,0 +1,216 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of mode register + * Initial configuration register. + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of t_string register + * SHA 512/t configuration register 0. + */ +typedef union { + struct { + /** t_string : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ + uint32_t t_string:32; + }; + uint32_t val; +} sha_t_string_reg_t; + +/** Type of t_length register + * SHA 512/t configuration register 1. + */ +typedef union { + struct { + /** t_length : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ + uint32_t t_length:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_t_length_reg_t; + +/** Type of dma_block_num register + * DMA configuration register 0. + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ + uint32_t dma_block_num:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Typical SHA configuration register 0. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** start : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t start:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Typical SHA configuration register 1. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** continue : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t continue:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * DMA configuration register 1. + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * DMA configuration register 2. + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + + +/** Group: Status Register */ +/** Type of busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Register */ +/** Type of clear_irq register + * Interrupt clear register. + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * Interrupt enable register. + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +typedef struct { + volatile sha_mode_reg_t mode; + volatile sha_t_string_reg_t t_string; + volatile sha_t_length_reg_t t_length; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t continue; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + uint32_t reserved_030[4]; + volatile uint32_t h[16]; + volatile uint32_t m[16]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h new file mode 100644 index 0000000000..80f91da98c --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc.h @@ -0,0 +1,244 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000) + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 32*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ APB_CLK_FREQ +#if CONFIG_IDF_ENV_FPGA +#define APB_CLK_FREQ ( 32*1000000 ) +#else +#define APB_CLK_FREQ ( 80*1000000 ) +#endif +#define REF_CLK_FREQ ( 1000000 ) +#define RTC_CLK_FREQ (20*1000000) +#define XTAL_CLK_FREQ (32*1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 32 +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7)) +#define SOC_DROM_LOW SOC_IROM_HIGH +#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x4004A000 +#define SOC_DROM_MASK_LOW 0x4004A000 +#define SOC_DROM_MASK_HIGH 0x40020000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40850000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40850000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H2 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50001000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50001000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50001000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40850000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40850000 + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40850000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40850000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40850000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40850000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4087c770 + + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt number reserved in riscv/vector.S, not touch this. +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h new file mode 100644 index 0000000000..592b4ce133 --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -0,0 +1,427 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// separate these information into periph_caps.h for each peripheral and +// include them here. + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32h2/include/soc/'` + * + * For more information see `tools/gen_soc_caps_kconfig/README.md` + * +*/ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 // TODO: IDF-6214 +#define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: IDF-6241 +#define SOC_GDMA_SUPPORTED 1 // TODO: IDF-6222 +// #define SOC_PCNT_SUPPORTED 1 // TODO: IDF-6221 +// #define SOC_MCPWM_SUPPORTED 1 // TODO: IDF-6237 +// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-6217 +#define SOC_BT_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: IDF-6239 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: IDF-6229 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 +//#define SOC_RISCV_COPROC_SUPPORTED 1 // TODO: IDF-6272 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_HAS_EFUSE_RST_BUG 1 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-6219 +// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-6224 +// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-6220 +#define SOC_SYSTIMER_SUPPORTED 1 +#define SOC_SUPPORT_COEXISTENCE 1 +// #define SOC_AES_SUPPORTED 1 // TODO: IDF-6280 +#define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 // TODO: IDF-6275 +#define SOC_HMAC_SUPPORTED 1 // TODO: IDF-6279 +// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: IDF-6285 +// #define SOC_FLASH_ENC_SUPPORTED 1 // TODO: IDF-6282 +#define SOC_SECURE_BOOT_SUPPORTED 1 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_32M 1 + +// TODO: IDF-6280 (Copy from esp32c6, need check) +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +// TODO: IDF-6215 (Copy from esp32c6, need check) +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +#define SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define SOC_ADC_ARBITER_SUPPORTED 1 +#define SOC_ADC_FILTER_SUPPORTED 1 +#define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_MAX_CHANNEL_NUM (5) +#define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +#define SOC_ADC_CALIBRATION_V1_SUPPORTED (0) /*!< support HW offset calibration version 1*/ + +// ESP32H2-TODO: Copy from esp32c6, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes + +// TODO: IDF-6370 (Copy from esp32c6, need check) +/*-------------------------- MMU CAPS ----------------------------------------*/ +#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) + +// TODO: IDF-6285 (Copy from esp32c6, need check) +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +// TODO: IDF-6222 (Copy from esp32c6, need check) +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups +#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C6 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1U) +#define SOC_GPIO_PIN_COUNT (31) + +// Target has the full LP IO subsystem +// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) +#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) + +#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated RTCIO subsystem on ESP32-C6. RTC functions are still supported + * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ +#define SOC_RTCIO_PIN_COUNT (0U) + +// TODO: IDF-6284 (Copy from esp32c6, need check) +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +// TODO: IDF-6275 (Copy from esp32c6, need check) +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +// TODO: IDF-6220 +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ +#define SOC_SDM_GROUPS 1U +#define SOC_SDM_CHANNELS_PER_GROUP 4 + +// TODO: IDF-6245 (Copy from esp32c6, need check) +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) + +#define SOC_MEMSPI_SRC_FREQ_48M_SUPPORTED 1 + +// TODO: IDF-6230 (Copy from esp32c6, need check) +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + +// TODO: IDF-6242 (Copy from esp32c6, need check) +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_SUPPORT_APB (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) + +// TODO: IDF-6217 (Copy from esp32c6, need check) +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_CONTROLLER_NUM 1 +#define SOC_TWAI_CLK_SUPPORT_XTAL 1 +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 32768 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +// TODO: IDF-6281 (Copy from esp32c6, need check) +/*-------------------------- Secure Boot CAPS----------------------------*/ +#define SOC_SECURE_BOOT_V2_RSA 1 +#define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +// TODO: IDF-6282 (Copy from esp32c6, need check) +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +// TODO: IDF-6332 (Copy from esp32c6, need check) +/*-------------------------- MEMPROT CAPS ------------------------------------*/ +#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define SOC_MEMPROT_MEM_ALIGN_SIZE 512 + +// TODO: IDF-6249 (Copy from esp32c6, need check) +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-H2 has 2 UARTs +#define SOC_UART_NUM (2) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (0) /*!< Support RTC clock as the clock source */ // TODO: IDF-6249 +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-6249 +#define SOC_UART_REQUIRE_CORE_RESET (1) + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +// TODO: IDF-5679 (Copy from esp32c6, need check) +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +// TODO: IDF-5680 (Copy from esp32c6, need check) +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) +#define SOC_MAC_BB_PD_MEM_SIZE (192*4) + +// TODO: IDF-5679 (Copy from esp32c6, need check) +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +// TODO: IDF-6270 (Copy from esp32c6, need check) +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) + +#define SOC_PM_SUPPORT_BT_WAKEUP (1) + +#define SOC_PM_SUPPORT_CPU_PD (1) + +#define SOC_PM_SUPPORT_WIFI_PD (1) + +#define SOC_PM_SUPPORT_BT_PD (1) + +// TODO: IDF-6229 (Copy from esp32c6, need check) +/*-------------------------- Temperature Sensor CAPS -------------------------------------*/ +#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) +#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) + +/*---------------------------------- Bluetooth CAPS ----------------------------------*/ +#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ diff --git a/components/soc/esp32h2/include/soc/soc_etm_reg.h b/components/soc/esp32h2/include/soc/soc_etm_reg.h new file mode 100644 index 0000000000..07b3cf52ea --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_etm_reg.h @@ -0,0 +1,2320 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SOC_ETM_CH_ENA_AD0_REG register + * channel enable register + */ +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENA0 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch0 enable + */ +#define SOC_ETM_CH_ENA0 (BIT(0)) +#define SOC_ETM_CH_ENA0_M (SOC_ETM_CH_ENA0_V << SOC_ETM_CH_ENA0_S) +#define SOC_ETM_CH_ENA0_V 0x00000001U +#define SOC_ETM_CH_ENA0_S 0 +/** SOC_ETM_CH_ENA1 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch1 enable + */ +#define SOC_ETM_CH_ENA1 (BIT(1)) +#define SOC_ETM_CH_ENA1_M (SOC_ETM_CH_ENA1_V << SOC_ETM_CH_ENA1_S) +#define SOC_ETM_CH_ENA1_V 0x00000001U +#define SOC_ETM_CH_ENA1_S 1 +/** SOC_ETM_CH_ENA2 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch2 enable + */ +#define SOC_ETM_CH_ENA2 (BIT(2)) +#define SOC_ETM_CH_ENA2_M (SOC_ETM_CH_ENA2_V << SOC_ETM_CH_ENA2_S) +#define SOC_ETM_CH_ENA2_V 0x00000001U +#define SOC_ETM_CH_ENA2_S 2 +/** SOC_ETM_CH_ENA3 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch3 enable + */ +#define SOC_ETM_CH_ENA3 (BIT(3)) +#define SOC_ETM_CH_ENA3_M (SOC_ETM_CH_ENA3_V << SOC_ETM_CH_ENA3_S) +#define SOC_ETM_CH_ENA3_V 0x00000001U +#define SOC_ETM_CH_ENA3_S 3 +/** SOC_ETM_CH_ENA4 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch4 enable + */ +#define SOC_ETM_CH_ENA4 (BIT(4)) +#define SOC_ETM_CH_ENA4_M (SOC_ETM_CH_ENA4_V << SOC_ETM_CH_ENA4_S) +#define SOC_ETM_CH_ENA4_V 0x00000001U +#define SOC_ETM_CH_ENA4_S 4 +/** SOC_ETM_CH_ENA5 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch5 enable + */ +#define SOC_ETM_CH_ENA5 (BIT(5)) +#define SOC_ETM_CH_ENA5_M (SOC_ETM_CH_ENA5_V << SOC_ETM_CH_ENA5_S) +#define SOC_ETM_CH_ENA5_V 0x00000001U +#define SOC_ETM_CH_ENA5_S 5 +/** SOC_ETM_CH_ENA6 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch6 enable + */ +#define SOC_ETM_CH_ENA6 (BIT(6)) +#define SOC_ETM_CH_ENA6_M (SOC_ETM_CH_ENA6_V << SOC_ETM_CH_ENA6_S) +#define SOC_ETM_CH_ENA6_V 0x00000001U +#define SOC_ETM_CH_ENA6_S 6 +/** SOC_ETM_CH_ENA7 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch7 enable + */ +#define SOC_ETM_CH_ENA7 (BIT(7)) +#define SOC_ETM_CH_ENA7_M (SOC_ETM_CH_ENA7_V << SOC_ETM_CH_ENA7_S) +#define SOC_ETM_CH_ENA7_V 0x00000001U +#define SOC_ETM_CH_ENA7_S 7 +/** SOC_ETM_CH_ENA8 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch8 enable + */ +#define SOC_ETM_CH_ENA8 (BIT(8)) +#define SOC_ETM_CH_ENA8_M (SOC_ETM_CH_ENA8_V << SOC_ETM_CH_ENA8_S) +#define SOC_ETM_CH_ENA8_V 0x00000001U +#define SOC_ETM_CH_ENA8_S 8 +/** SOC_ETM_CH_ENA9 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch9 enable + */ +#define SOC_ETM_CH_ENA9 (BIT(9)) +#define SOC_ETM_CH_ENA9_M (SOC_ETM_CH_ENA9_V << SOC_ETM_CH_ENA9_S) +#define SOC_ETM_CH_ENA9_V 0x00000001U +#define SOC_ETM_CH_ENA9_S 9 +/** SOC_ETM_CH_ENA10 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch10 enable + */ +#define SOC_ETM_CH_ENA10 (BIT(10)) +#define SOC_ETM_CH_ENA10_M (SOC_ETM_CH_ENA10_V << SOC_ETM_CH_ENA10_S) +#define SOC_ETM_CH_ENA10_V 0x00000001U +#define SOC_ETM_CH_ENA10_S 10 +/** SOC_ETM_CH_ENA11 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch11 enable + */ +#define SOC_ETM_CH_ENA11 (BIT(11)) +#define SOC_ETM_CH_ENA11_M (SOC_ETM_CH_ENA11_V << SOC_ETM_CH_ENA11_S) +#define SOC_ETM_CH_ENA11_V 0x00000001U +#define SOC_ETM_CH_ENA11_S 11 +/** SOC_ETM_CH_ENA12 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch12 enable + */ +#define SOC_ETM_CH_ENA12 (BIT(12)) +#define SOC_ETM_CH_ENA12_M (SOC_ETM_CH_ENA12_V << SOC_ETM_CH_ENA12_S) +#define SOC_ETM_CH_ENA12_V 0x00000001U +#define SOC_ETM_CH_ENA12_S 12 +/** SOC_ETM_CH_ENA13 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch13 enable + */ +#define SOC_ETM_CH_ENA13 (BIT(13)) +#define SOC_ETM_CH_ENA13_M (SOC_ETM_CH_ENA13_V << SOC_ETM_CH_ENA13_S) +#define SOC_ETM_CH_ENA13_V 0x00000001U +#define SOC_ETM_CH_ENA13_S 13 +/** SOC_ETM_CH_ENA14 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch14 enable + */ +#define SOC_ETM_CH_ENA14 (BIT(14)) +#define SOC_ETM_CH_ENA14_M (SOC_ETM_CH_ENA14_V << SOC_ETM_CH_ENA14_S) +#define SOC_ETM_CH_ENA14_V 0x00000001U +#define SOC_ETM_CH_ENA14_S 14 +/** SOC_ETM_CH_ENA15 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch15 enable + */ +#define SOC_ETM_CH_ENA15 (BIT(15)) +#define SOC_ETM_CH_ENA15_M (SOC_ETM_CH_ENA15_V << SOC_ETM_CH_ENA15_S) +#define SOC_ETM_CH_ENA15_V 0x00000001U +#define SOC_ETM_CH_ENA15_S 15 +/** SOC_ETM_CH_ENA16 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch16 enable + */ +#define SOC_ETM_CH_ENA16 (BIT(16)) +#define SOC_ETM_CH_ENA16_M (SOC_ETM_CH_ENA16_V << SOC_ETM_CH_ENA16_S) +#define SOC_ETM_CH_ENA16_V 0x00000001U +#define SOC_ETM_CH_ENA16_S 16 +/** SOC_ETM_CH_ENA17 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch17 enable + */ +#define SOC_ETM_CH_ENA17 (BIT(17)) +#define SOC_ETM_CH_ENA17_M (SOC_ETM_CH_ENA17_V << SOC_ETM_CH_ENA17_S) +#define SOC_ETM_CH_ENA17_V 0x00000001U +#define SOC_ETM_CH_ENA17_S 17 +/** SOC_ETM_CH_ENA18 : R/WTC/WTS; bitpos: [18]; default: 0; + * ch18 enable + */ +#define SOC_ETM_CH_ENA18 (BIT(18)) +#define SOC_ETM_CH_ENA18_M (SOC_ETM_CH_ENA18_V << SOC_ETM_CH_ENA18_S) +#define SOC_ETM_CH_ENA18_V 0x00000001U +#define SOC_ETM_CH_ENA18_S 18 +/** SOC_ETM_CH_ENA19 : R/WTC/WTS; bitpos: [19]; default: 0; + * ch19 enable + */ +#define SOC_ETM_CH_ENA19 (BIT(19)) +#define SOC_ETM_CH_ENA19_M (SOC_ETM_CH_ENA19_V << SOC_ETM_CH_ENA19_S) +#define SOC_ETM_CH_ENA19_V 0x00000001U +#define SOC_ETM_CH_ENA19_S 19 +/** SOC_ETM_CH_ENA20 : R/WTC/WTS; bitpos: [20]; default: 0; + * ch20 enable + */ +#define SOC_ETM_CH_ENA20 (BIT(20)) +#define SOC_ETM_CH_ENA20_M (SOC_ETM_CH_ENA20_V << SOC_ETM_CH_ENA20_S) +#define SOC_ETM_CH_ENA20_V 0x00000001U +#define SOC_ETM_CH_ENA20_S 20 +/** SOC_ETM_CH_ENA21 : R/WTC/WTS; bitpos: [21]; default: 0; + * ch21 enable + */ +#define SOC_ETM_CH_ENA21 (BIT(21)) +#define SOC_ETM_CH_ENA21_M (SOC_ETM_CH_ENA21_V << SOC_ETM_CH_ENA21_S) +#define SOC_ETM_CH_ENA21_V 0x00000001U +#define SOC_ETM_CH_ENA21_S 21 +/** SOC_ETM_CH_ENA22 : R/WTC/WTS; bitpos: [22]; default: 0; + * ch22 enable + */ +#define SOC_ETM_CH_ENA22 (BIT(22)) +#define SOC_ETM_CH_ENA22_M (SOC_ETM_CH_ENA22_V << SOC_ETM_CH_ENA22_S) +#define SOC_ETM_CH_ENA22_V 0x00000001U +#define SOC_ETM_CH_ENA22_S 22 +/** SOC_ETM_CH_ENA23 : R/WTC/WTS; bitpos: [23]; default: 0; + * ch23 enable + */ +#define SOC_ETM_CH_ENA23 (BIT(23)) +#define SOC_ETM_CH_ENA23_M (SOC_ETM_CH_ENA23_V << SOC_ETM_CH_ENA23_S) +#define SOC_ETM_CH_ENA23_V 0x00000001U +#define SOC_ETM_CH_ENA23_S 23 +/** SOC_ETM_CH_ENA24 : R/WTC/WTS; bitpos: [24]; default: 0; + * ch24 enable + */ +#define SOC_ETM_CH_ENA24 (BIT(24)) +#define SOC_ETM_CH_ENA24_M (SOC_ETM_CH_ENA24_V << SOC_ETM_CH_ENA24_S) +#define SOC_ETM_CH_ENA24_V 0x00000001U +#define SOC_ETM_CH_ENA24_S 24 +/** SOC_ETM_CH_ENA25 : R/WTC/WTS; bitpos: [25]; default: 0; + * ch25 enable + */ +#define SOC_ETM_CH_ENA25 (BIT(25)) +#define SOC_ETM_CH_ENA25_M (SOC_ETM_CH_ENA25_V << SOC_ETM_CH_ENA25_S) +#define SOC_ETM_CH_ENA25_V 0x00000001U +#define SOC_ETM_CH_ENA25_S 25 +/** SOC_ETM_CH_ENA26 : R/WTC/WTS; bitpos: [26]; default: 0; + * ch26 enable + */ +#define SOC_ETM_CH_ENA26 (BIT(26)) +#define SOC_ETM_CH_ENA26_M (SOC_ETM_CH_ENA26_V << SOC_ETM_CH_ENA26_S) +#define SOC_ETM_CH_ENA26_V 0x00000001U +#define SOC_ETM_CH_ENA26_S 26 +/** SOC_ETM_CH_ENA27 : R/WTC/WTS; bitpos: [27]; default: 0; + * ch27 enable + */ +#define SOC_ETM_CH_ENA27 (BIT(27)) +#define SOC_ETM_CH_ENA27_M (SOC_ETM_CH_ENA27_V << SOC_ETM_CH_ENA27_S) +#define SOC_ETM_CH_ENA27_V 0x00000001U +#define SOC_ETM_CH_ENA27_S 27 +/** SOC_ETM_CH_ENA28 : R/WTC/WTS; bitpos: [28]; default: 0; + * ch28 enable + */ +#define SOC_ETM_CH_ENA28 (BIT(28)) +#define SOC_ETM_CH_ENA28_M (SOC_ETM_CH_ENA28_V << SOC_ETM_CH_ENA28_S) +#define SOC_ETM_CH_ENA28_V 0x00000001U +#define SOC_ETM_CH_ENA28_S 28 +/** SOC_ETM_CH_ENA29 : R/WTC/WTS; bitpos: [29]; default: 0; + * ch29 enable + */ +#define SOC_ETM_CH_ENA29 (BIT(29)) +#define SOC_ETM_CH_ENA29_M (SOC_ETM_CH_ENA29_V << SOC_ETM_CH_ENA29_S) +#define SOC_ETM_CH_ENA29_V 0x00000001U +#define SOC_ETM_CH_ENA29_S 29 +/** SOC_ETM_CH_ENA30 : R/WTC/WTS; bitpos: [30]; default: 0; + * ch30 enable + */ +#define SOC_ETM_CH_ENA30 (BIT(30)) +#define SOC_ETM_CH_ENA30_M (SOC_ETM_CH_ENA30_V << SOC_ETM_CH_ENA30_S) +#define SOC_ETM_CH_ENA30_V 0x00000001U +#define SOC_ETM_CH_ENA30_S 30 +/** SOC_ETM_CH_ENA31 : R/WTC/WTS; bitpos: [31]; default: 0; + * ch31 enable + */ +#define SOC_ETM_CH_ENA31 (BIT(31)) +#define SOC_ETM_CH_ENA31_M (SOC_ETM_CH_ENA31_V << SOC_ETM_CH_ENA31_S) +#define SOC_ETM_CH_ENA31_V 0x00000001U +#define SOC_ETM_CH_ENA31_S 31 + +/** SOC_ETM_CH_ENA_AD0_SET_REG register + * channel enable set register + */ +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_SET0 : WT; bitpos: [0]; default: 0; + * ch0 set + */ +#define SOC_ETM_CH_SET0 (BIT(0)) +#define SOC_ETM_CH_SET0_M (SOC_ETM_CH_SET0_V << SOC_ETM_CH_SET0_S) +#define SOC_ETM_CH_SET0_V 0x00000001U +#define SOC_ETM_CH_SET0_S 0 +/** SOC_ETM_CH_SET1 : WT; bitpos: [1]; default: 0; + * ch1 set + */ +#define SOC_ETM_CH_SET1 (BIT(1)) +#define SOC_ETM_CH_SET1_M (SOC_ETM_CH_SET1_V << SOC_ETM_CH_SET1_S) +#define SOC_ETM_CH_SET1_V 0x00000001U +#define SOC_ETM_CH_SET1_S 1 +/** SOC_ETM_CH_SET2 : WT; bitpos: [2]; default: 0; + * ch2 set + */ +#define SOC_ETM_CH_SET2 (BIT(2)) +#define SOC_ETM_CH_SET2_M (SOC_ETM_CH_SET2_V << SOC_ETM_CH_SET2_S) +#define SOC_ETM_CH_SET2_V 0x00000001U +#define SOC_ETM_CH_SET2_S 2 +/** SOC_ETM_CH_SET3 : WT; bitpos: [3]; default: 0; + * ch3 set + */ +#define SOC_ETM_CH_SET3 (BIT(3)) +#define SOC_ETM_CH_SET3_M (SOC_ETM_CH_SET3_V << SOC_ETM_CH_SET3_S) +#define SOC_ETM_CH_SET3_V 0x00000001U +#define SOC_ETM_CH_SET3_S 3 +/** SOC_ETM_CH_SET4 : WT; bitpos: [4]; default: 0; + * ch4 set + */ +#define SOC_ETM_CH_SET4 (BIT(4)) +#define SOC_ETM_CH_SET4_M (SOC_ETM_CH_SET4_V << SOC_ETM_CH_SET4_S) +#define SOC_ETM_CH_SET4_V 0x00000001U +#define SOC_ETM_CH_SET4_S 4 +/** SOC_ETM_CH_SET5 : WT; bitpos: [5]; default: 0; + * ch5 set + */ +#define SOC_ETM_CH_SET5 (BIT(5)) +#define SOC_ETM_CH_SET5_M (SOC_ETM_CH_SET5_V << SOC_ETM_CH_SET5_S) +#define SOC_ETM_CH_SET5_V 0x00000001U +#define SOC_ETM_CH_SET5_S 5 +/** SOC_ETM_CH_SET6 : WT; bitpos: [6]; default: 0; + * ch6 set + */ +#define SOC_ETM_CH_SET6 (BIT(6)) +#define SOC_ETM_CH_SET6_M (SOC_ETM_CH_SET6_V << SOC_ETM_CH_SET6_S) +#define SOC_ETM_CH_SET6_V 0x00000001U +#define SOC_ETM_CH_SET6_S 6 +/** SOC_ETM_CH_SET7 : WT; bitpos: [7]; default: 0; + * ch7 set + */ +#define SOC_ETM_CH_SET7 (BIT(7)) +#define SOC_ETM_CH_SET7_M (SOC_ETM_CH_SET7_V << SOC_ETM_CH_SET7_S) +#define SOC_ETM_CH_SET7_V 0x00000001U +#define SOC_ETM_CH_SET7_S 7 +/** SOC_ETM_CH_SET8 : WT; bitpos: [8]; default: 0; + * ch8 set + */ +#define SOC_ETM_CH_SET8 (BIT(8)) +#define SOC_ETM_CH_SET8_M (SOC_ETM_CH_SET8_V << SOC_ETM_CH_SET8_S) +#define SOC_ETM_CH_SET8_V 0x00000001U +#define SOC_ETM_CH_SET8_S 8 +/** SOC_ETM_CH_SET9 : WT; bitpos: [9]; default: 0; + * ch9 set + */ +#define SOC_ETM_CH_SET9 (BIT(9)) +#define SOC_ETM_CH_SET9_M (SOC_ETM_CH_SET9_V << SOC_ETM_CH_SET9_S) +#define SOC_ETM_CH_SET9_V 0x00000001U +#define SOC_ETM_CH_SET9_S 9 +/** SOC_ETM_CH_SET10 : WT; bitpos: [10]; default: 0; + * ch10 set + */ +#define SOC_ETM_CH_SET10 (BIT(10)) +#define SOC_ETM_CH_SET10_M (SOC_ETM_CH_SET10_V << SOC_ETM_CH_SET10_S) +#define SOC_ETM_CH_SET10_V 0x00000001U +#define SOC_ETM_CH_SET10_S 10 +/** SOC_ETM_CH_SET11 : WT; bitpos: [11]; default: 0; + * ch11 set + */ +#define SOC_ETM_CH_SET11 (BIT(11)) +#define SOC_ETM_CH_SET11_M (SOC_ETM_CH_SET11_V << SOC_ETM_CH_SET11_S) +#define SOC_ETM_CH_SET11_V 0x00000001U +#define SOC_ETM_CH_SET11_S 11 +/** SOC_ETM_CH_SET12 : WT; bitpos: [12]; default: 0; + * ch12 set + */ +#define SOC_ETM_CH_SET12 (BIT(12)) +#define SOC_ETM_CH_SET12_M (SOC_ETM_CH_SET12_V << SOC_ETM_CH_SET12_S) +#define SOC_ETM_CH_SET12_V 0x00000001U +#define SOC_ETM_CH_SET12_S 12 +/** SOC_ETM_CH_SET13 : WT; bitpos: [13]; default: 0; + * ch13 set + */ +#define SOC_ETM_CH_SET13 (BIT(13)) +#define SOC_ETM_CH_SET13_M (SOC_ETM_CH_SET13_V << SOC_ETM_CH_SET13_S) +#define SOC_ETM_CH_SET13_V 0x00000001U +#define SOC_ETM_CH_SET13_S 13 +/** SOC_ETM_CH_SET14 : WT; bitpos: [14]; default: 0; + * ch14 set + */ +#define SOC_ETM_CH_SET14 (BIT(14)) +#define SOC_ETM_CH_SET14_M (SOC_ETM_CH_SET14_V << SOC_ETM_CH_SET14_S) +#define SOC_ETM_CH_SET14_V 0x00000001U +#define SOC_ETM_CH_SET14_S 14 +/** SOC_ETM_CH_SET15 : WT; bitpos: [15]; default: 0; + * ch15 set + */ +#define SOC_ETM_CH_SET15 (BIT(15)) +#define SOC_ETM_CH_SET15_M (SOC_ETM_CH_SET15_V << SOC_ETM_CH_SET15_S) +#define SOC_ETM_CH_SET15_V 0x00000001U +#define SOC_ETM_CH_SET15_S 15 +/** SOC_ETM_CH_SET16 : WT; bitpos: [16]; default: 0; + * ch16 set + */ +#define SOC_ETM_CH_SET16 (BIT(16)) +#define SOC_ETM_CH_SET16_M (SOC_ETM_CH_SET16_V << SOC_ETM_CH_SET16_S) +#define SOC_ETM_CH_SET16_V 0x00000001U +#define SOC_ETM_CH_SET16_S 16 +/** SOC_ETM_CH_SET17 : WT; bitpos: [17]; default: 0; + * ch17 set + */ +#define SOC_ETM_CH_SET17 (BIT(17)) +#define SOC_ETM_CH_SET17_M (SOC_ETM_CH_SET17_V << SOC_ETM_CH_SET17_S) +#define SOC_ETM_CH_SET17_V 0x00000001U +#define SOC_ETM_CH_SET17_S 17 +/** SOC_ETM_CH_SET18 : WT; bitpos: [18]; default: 0; + * ch18 set + */ +#define SOC_ETM_CH_SET18 (BIT(18)) +#define SOC_ETM_CH_SET18_M (SOC_ETM_CH_SET18_V << SOC_ETM_CH_SET18_S) +#define SOC_ETM_CH_SET18_V 0x00000001U +#define SOC_ETM_CH_SET18_S 18 +/** SOC_ETM_CH_SET19 : WT; bitpos: [19]; default: 0; + * ch19 set + */ +#define SOC_ETM_CH_SET19 (BIT(19)) +#define SOC_ETM_CH_SET19_M (SOC_ETM_CH_SET19_V << SOC_ETM_CH_SET19_S) +#define SOC_ETM_CH_SET19_V 0x00000001U +#define SOC_ETM_CH_SET19_S 19 +/** SOC_ETM_CH_SET20 : WT; bitpos: [20]; default: 0; + * ch20 set + */ +#define SOC_ETM_CH_SET20 (BIT(20)) +#define SOC_ETM_CH_SET20_M (SOC_ETM_CH_SET20_V << SOC_ETM_CH_SET20_S) +#define SOC_ETM_CH_SET20_V 0x00000001U +#define SOC_ETM_CH_SET20_S 20 +/** SOC_ETM_CH_SET21 : WT; bitpos: [21]; default: 0; + * ch21 set + */ +#define SOC_ETM_CH_SET21 (BIT(21)) +#define SOC_ETM_CH_SET21_M (SOC_ETM_CH_SET21_V << SOC_ETM_CH_SET21_S) +#define SOC_ETM_CH_SET21_V 0x00000001U +#define SOC_ETM_CH_SET21_S 21 +/** SOC_ETM_CH_SET22 : WT; bitpos: [22]; default: 0; + * ch22 set + */ +#define SOC_ETM_CH_SET22 (BIT(22)) +#define SOC_ETM_CH_SET22_M (SOC_ETM_CH_SET22_V << SOC_ETM_CH_SET22_S) +#define SOC_ETM_CH_SET22_V 0x00000001U +#define SOC_ETM_CH_SET22_S 22 +/** SOC_ETM_CH_SET23 : WT; bitpos: [23]; default: 0; + * ch23 set + */ +#define SOC_ETM_CH_SET23 (BIT(23)) +#define SOC_ETM_CH_SET23_M (SOC_ETM_CH_SET23_V << SOC_ETM_CH_SET23_S) +#define SOC_ETM_CH_SET23_V 0x00000001U +#define SOC_ETM_CH_SET23_S 23 +/** SOC_ETM_CH_SET24 : WT; bitpos: [24]; default: 0; + * ch24 set + */ +#define SOC_ETM_CH_SET24 (BIT(24)) +#define SOC_ETM_CH_SET24_M (SOC_ETM_CH_SET24_V << SOC_ETM_CH_SET24_S) +#define SOC_ETM_CH_SET24_V 0x00000001U +#define SOC_ETM_CH_SET24_S 24 +/** SOC_ETM_CH_SET25 : WT; bitpos: [25]; default: 0; + * ch25 set + */ +#define SOC_ETM_CH_SET25 (BIT(25)) +#define SOC_ETM_CH_SET25_M (SOC_ETM_CH_SET25_V << SOC_ETM_CH_SET25_S) +#define SOC_ETM_CH_SET25_V 0x00000001U +#define SOC_ETM_CH_SET25_S 25 +/** SOC_ETM_CH_SET26 : WT; bitpos: [26]; default: 0; + * ch26 set + */ +#define SOC_ETM_CH_SET26 (BIT(26)) +#define SOC_ETM_CH_SET26_M (SOC_ETM_CH_SET26_V << SOC_ETM_CH_SET26_S) +#define SOC_ETM_CH_SET26_V 0x00000001U +#define SOC_ETM_CH_SET26_S 26 +/** SOC_ETM_CH_SET27 : WT; bitpos: [27]; default: 0; + * ch27 set + */ +#define SOC_ETM_CH_SET27 (BIT(27)) +#define SOC_ETM_CH_SET27_M (SOC_ETM_CH_SET27_V << SOC_ETM_CH_SET27_S) +#define SOC_ETM_CH_SET27_V 0x00000001U +#define SOC_ETM_CH_SET27_S 27 +/** SOC_ETM_CH_SET28 : WT; bitpos: [28]; default: 0; + * ch28 set + */ +#define SOC_ETM_CH_SET28 (BIT(28)) +#define SOC_ETM_CH_SET28_M (SOC_ETM_CH_SET28_V << SOC_ETM_CH_SET28_S) +#define SOC_ETM_CH_SET28_V 0x00000001U +#define SOC_ETM_CH_SET28_S 28 +/** SOC_ETM_CH_SET29 : WT; bitpos: [29]; default: 0; + * ch29 set + */ +#define SOC_ETM_CH_SET29 (BIT(29)) +#define SOC_ETM_CH_SET29_M (SOC_ETM_CH_SET29_V << SOC_ETM_CH_SET29_S) +#define SOC_ETM_CH_SET29_V 0x00000001U +#define SOC_ETM_CH_SET29_S 29 +/** SOC_ETM_CH_SET30 : WT; bitpos: [30]; default: 0; + * ch30 set + */ +#define SOC_ETM_CH_SET30 (BIT(30)) +#define SOC_ETM_CH_SET30_M (SOC_ETM_CH_SET30_V << SOC_ETM_CH_SET30_S) +#define SOC_ETM_CH_SET30_V 0x00000001U +#define SOC_ETM_CH_SET30_S 30 +/** SOC_ETM_CH_SET31 : WT; bitpos: [31]; default: 0; + * ch31 set + */ +#define SOC_ETM_CH_SET31 (BIT(31)) +#define SOC_ETM_CH_SET31_M (SOC_ETM_CH_SET31_V << SOC_ETM_CH_SET31_S) +#define SOC_ETM_CH_SET31_V 0x00000001U +#define SOC_ETM_CH_SET31_S 31 + +/** SOC_ETM_CH_ENA_AD0_CLR_REG register + * channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_CLR0 : WT; bitpos: [0]; default: 0; + * ch0 clear + */ +#define SOC_ETM_CH_CLR0 (BIT(0)) +#define SOC_ETM_CH_CLR0_M (SOC_ETM_CH_CLR0_V << SOC_ETM_CH_CLR0_S) +#define SOC_ETM_CH_CLR0_V 0x00000001U +#define SOC_ETM_CH_CLR0_S 0 +/** SOC_ETM_CH_CLR1 : WT; bitpos: [1]; default: 0; + * ch1 clear + */ +#define SOC_ETM_CH_CLR1 (BIT(1)) +#define SOC_ETM_CH_CLR1_M (SOC_ETM_CH_CLR1_V << SOC_ETM_CH_CLR1_S) +#define SOC_ETM_CH_CLR1_V 0x00000001U +#define SOC_ETM_CH_CLR1_S 1 +/** SOC_ETM_CH_CLR2 : WT; bitpos: [2]; default: 0; + * ch2 clear + */ +#define SOC_ETM_CH_CLR2 (BIT(2)) +#define SOC_ETM_CH_CLR2_M (SOC_ETM_CH_CLR2_V << SOC_ETM_CH_CLR2_S) +#define SOC_ETM_CH_CLR2_V 0x00000001U +#define SOC_ETM_CH_CLR2_S 2 +/** SOC_ETM_CH_CLR3 : WT; bitpos: [3]; default: 0; + * ch3 clear + */ +#define SOC_ETM_CH_CLR3 (BIT(3)) +#define SOC_ETM_CH_CLR3_M (SOC_ETM_CH_CLR3_V << SOC_ETM_CH_CLR3_S) +#define SOC_ETM_CH_CLR3_V 0x00000001U +#define SOC_ETM_CH_CLR3_S 3 +/** SOC_ETM_CH_CLR4 : WT; bitpos: [4]; default: 0; + * ch4 clear + */ +#define SOC_ETM_CH_CLR4 (BIT(4)) +#define SOC_ETM_CH_CLR4_M (SOC_ETM_CH_CLR4_V << SOC_ETM_CH_CLR4_S) +#define SOC_ETM_CH_CLR4_V 0x00000001U +#define SOC_ETM_CH_CLR4_S 4 +/** SOC_ETM_CH_CLR5 : WT; bitpos: [5]; default: 0; + * ch5 clear + */ +#define SOC_ETM_CH_CLR5 (BIT(5)) +#define SOC_ETM_CH_CLR5_M (SOC_ETM_CH_CLR5_V << SOC_ETM_CH_CLR5_S) +#define SOC_ETM_CH_CLR5_V 0x00000001U +#define SOC_ETM_CH_CLR5_S 5 +/** SOC_ETM_CH_CLR6 : WT; bitpos: [6]; default: 0; + * ch6 clear + */ +#define SOC_ETM_CH_CLR6 (BIT(6)) +#define SOC_ETM_CH_CLR6_M (SOC_ETM_CH_CLR6_V << SOC_ETM_CH_CLR6_S) +#define SOC_ETM_CH_CLR6_V 0x00000001U +#define SOC_ETM_CH_CLR6_S 6 +/** SOC_ETM_CH_CLR7 : WT; bitpos: [7]; default: 0; + * ch7 clear + */ +#define SOC_ETM_CH_CLR7 (BIT(7)) +#define SOC_ETM_CH_CLR7_M (SOC_ETM_CH_CLR7_V << SOC_ETM_CH_CLR7_S) +#define SOC_ETM_CH_CLR7_V 0x00000001U +#define SOC_ETM_CH_CLR7_S 7 +/** SOC_ETM_CH_CLR8 : WT; bitpos: [8]; default: 0; + * ch8 clear + */ +#define SOC_ETM_CH_CLR8 (BIT(8)) +#define SOC_ETM_CH_CLR8_M (SOC_ETM_CH_CLR8_V << SOC_ETM_CH_CLR8_S) +#define SOC_ETM_CH_CLR8_V 0x00000001U +#define SOC_ETM_CH_CLR8_S 8 +/** SOC_ETM_CH_CLR9 : WT; bitpos: [9]; default: 0; + * ch9 clear + */ +#define SOC_ETM_CH_CLR9 (BIT(9)) +#define SOC_ETM_CH_CLR9_M (SOC_ETM_CH_CLR9_V << SOC_ETM_CH_CLR9_S) +#define SOC_ETM_CH_CLR9_V 0x00000001U +#define SOC_ETM_CH_CLR9_S 9 +/** SOC_ETM_CH_CLR10 : WT; bitpos: [10]; default: 0; + * ch10 clear + */ +#define SOC_ETM_CH_CLR10 (BIT(10)) +#define SOC_ETM_CH_CLR10_M (SOC_ETM_CH_CLR10_V << SOC_ETM_CH_CLR10_S) +#define SOC_ETM_CH_CLR10_V 0x00000001U +#define SOC_ETM_CH_CLR10_S 10 +/** SOC_ETM_CH_CLR11 : WT; bitpos: [11]; default: 0; + * ch11 clear + */ +#define SOC_ETM_CH_CLR11 (BIT(11)) +#define SOC_ETM_CH_CLR11_M (SOC_ETM_CH_CLR11_V << SOC_ETM_CH_CLR11_S) +#define SOC_ETM_CH_CLR11_V 0x00000001U +#define SOC_ETM_CH_CLR11_S 11 +/** SOC_ETM_CH_CLR12 : WT; bitpos: [12]; default: 0; + * ch12 clear + */ +#define SOC_ETM_CH_CLR12 (BIT(12)) +#define SOC_ETM_CH_CLR12_M (SOC_ETM_CH_CLR12_V << SOC_ETM_CH_CLR12_S) +#define SOC_ETM_CH_CLR12_V 0x00000001U +#define SOC_ETM_CH_CLR12_S 12 +/** SOC_ETM_CH_CLR13 : WT; bitpos: [13]; default: 0; + * ch13 clear + */ +#define SOC_ETM_CH_CLR13 (BIT(13)) +#define SOC_ETM_CH_CLR13_M (SOC_ETM_CH_CLR13_V << SOC_ETM_CH_CLR13_S) +#define SOC_ETM_CH_CLR13_V 0x00000001U +#define SOC_ETM_CH_CLR13_S 13 +/** SOC_ETM_CH_CLR14 : WT; bitpos: [14]; default: 0; + * ch14 clear + */ +#define SOC_ETM_CH_CLR14 (BIT(14)) +#define SOC_ETM_CH_CLR14_M (SOC_ETM_CH_CLR14_V << SOC_ETM_CH_CLR14_S) +#define SOC_ETM_CH_CLR14_V 0x00000001U +#define SOC_ETM_CH_CLR14_S 14 +/** SOC_ETM_CH_CLR15 : WT; bitpos: [15]; default: 0; + * ch15 clear + */ +#define SOC_ETM_CH_CLR15 (BIT(15)) +#define SOC_ETM_CH_CLR15_M (SOC_ETM_CH_CLR15_V << SOC_ETM_CH_CLR15_S) +#define SOC_ETM_CH_CLR15_V 0x00000001U +#define SOC_ETM_CH_CLR15_S 15 +/** SOC_ETM_CH_CLR16 : WT; bitpos: [16]; default: 0; + * ch16 clear + */ +#define SOC_ETM_CH_CLR16 (BIT(16)) +#define SOC_ETM_CH_CLR16_M (SOC_ETM_CH_CLR16_V << SOC_ETM_CH_CLR16_S) +#define SOC_ETM_CH_CLR16_V 0x00000001U +#define SOC_ETM_CH_CLR16_S 16 +/** SOC_ETM_CH_CLR17 : WT; bitpos: [17]; default: 0; + * ch17 clear + */ +#define SOC_ETM_CH_CLR17 (BIT(17)) +#define SOC_ETM_CH_CLR17_M (SOC_ETM_CH_CLR17_V << SOC_ETM_CH_CLR17_S) +#define SOC_ETM_CH_CLR17_V 0x00000001U +#define SOC_ETM_CH_CLR17_S 17 +/** SOC_ETM_CH_CLR18 : WT; bitpos: [18]; default: 0; + * ch18 clear + */ +#define SOC_ETM_CH_CLR18 (BIT(18)) +#define SOC_ETM_CH_CLR18_M (SOC_ETM_CH_CLR18_V << SOC_ETM_CH_CLR18_S) +#define SOC_ETM_CH_CLR18_V 0x00000001U +#define SOC_ETM_CH_CLR18_S 18 +/** SOC_ETM_CH_CLR19 : WT; bitpos: [19]; default: 0; + * ch19 clear + */ +#define SOC_ETM_CH_CLR19 (BIT(19)) +#define SOC_ETM_CH_CLR19_M (SOC_ETM_CH_CLR19_V << SOC_ETM_CH_CLR19_S) +#define SOC_ETM_CH_CLR19_V 0x00000001U +#define SOC_ETM_CH_CLR19_S 19 +/** SOC_ETM_CH_CLR20 : WT; bitpos: [20]; default: 0; + * ch20 clear + */ +#define SOC_ETM_CH_CLR20 (BIT(20)) +#define SOC_ETM_CH_CLR20_M (SOC_ETM_CH_CLR20_V << SOC_ETM_CH_CLR20_S) +#define SOC_ETM_CH_CLR20_V 0x00000001U +#define SOC_ETM_CH_CLR20_S 20 +/** SOC_ETM_CH_CLR21 : WT; bitpos: [21]; default: 0; + * ch21 clear + */ +#define SOC_ETM_CH_CLR21 (BIT(21)) +#define SOC_ETM_CH_CLR21_M (SOC_ETM_CH_CLR21_V << SOC_ETM_CH_CLR21_S) +#define SOC_ETM_CH_CLR21_V 0x00000001U +#define SOC_ETM_CH_CLR21_S 21 +/** SOC_ETM_CH_CLR22 : WT; bitpos: [22]; default: 0; + * ch22 clear + */ +#define SOC_ETM_CH_CLR22 (BIT(22)) +#define SOC_ETM_CH_CLR22_M (SOC_ETM_CH_CLR22_V << SOC_ETM_CH_CLR22_S) +#define SOC_ETM_CH_CLR22_V 0x00000001U +#define SOC_ETM_CH_CLR22_S 22 +/** SOC_ETM_CH_CLR23 : WT; bitpos: [23]; default: 0; + * ch23 clear + */ +#define SOC_ETM_CH_CLR23 (BIT(23)) +#define SOC_ETM_CH_CLR23_M (SOC_ETM_CH_CLR23_V << SOC_ETM_CH_CLR23_S) +#define SOC_ETM_CH_CLR23_V 0x00000001U +#define SOC_ETM_CH_CLR23_S 23 +/** SOC_ETM_CH_CLR24 : WT; bitpos: [24]; default: 0; + * ch24 clear + */ +#define SOC_ETM_CH_CLR24 (BIT(24)) +#define SOC_ETM_CH_CLR24_M (SOC_ETM_CH_CLR24_V << SOC_ETM_CH_CLR24_S) +#define SOC_ETM_CH_CLR24_V 0x00000001U +#define SOC_ETM_CH_CLR24_S 24 +/** SOC_ETM_CH_CLR25 : WT; bitpos: [25]; default: 0; + * ch25 clear + */ +#define SOC_ETM_CH_CLR25 (BIT(25)) +#define SOC_ETM_CH_CLR25_M (SOC_ETM_CH_CLR25_V << SOC_ETM_CH_CLR25_S) +#define SOC_ETM_CH_CLR25_V 0x00000001U +#define SOC_ETM_CH_CLR25_S 25 +/** SOC_ETM_CH_CLR26 : WT; bitpos: [26]; default: 0; + * ch26 clear + */ +#define SOC_ETM_CH_CLR26 (BIT(26)) +#define SOC_ETM_CH_CLR26_M (SOC_ETM_CH_CLR26_V << SOC_ETM_CH_CLR26_S) +#define SOC_ETM_CH_CLR26_V 0x00000001U +#define SOC_ETM_CH_CLR26_S 26 +/** SOC_ETM_CH_CLR27 : WT; bitpos: [27]; default: 0; + * ch27 clear + */ +#define SOC_ETM_CH_CLR27 (BIT(27)) +#define SOC_ETM_CH_CLR27_M (SOC_ETM_CH_CLR27_V << SOC_ETM_CH_CLR27_S) +#define SOC_ETM_CH_CLR27_V 0x00000001U +#define SOC_ETM_CH_CLR27_S 27 +/** SOC_ETM_CH_CLR28 : WT; bitpos: [28]; default: 0; + * ch28 clear + */ +#define SOC_ETM_CH_CLR28 (BIT(28)) +#define SOC_ETM_CH_CLR28_M (SOC_ETM_CH_CLR28_V << SOC_ETM_CH_CLR28_S) +#define SOC_ETM_CH_CLR28_V 0x00000001U +#define SOC_ETM_CH_CLR28_S 28 +/** SOC_ETM_CH_CLR29 : WT; bitpos: [29]; default: 0; + * ch29 clear + */ +#define SOC_ETM_CH_CLR29 (BIT(29)) +#define SOC_ETM_CH_CLR29_M (SOC_ETM_CH_CLR29_V << SOC_ETM_CH_CLR29_S) +#define SOC_ETM_CH_CLR29_V 0x00000001U +#define SOC_ETM_CH_CLR29_S 29 +/** SOC_ETM_CH_CLR30 : WT; bitpos: [30]; default: 0; + * ch30 clear + */ +#define SOC_ETM_CH_CLR30 (BIT(30)) +#define SOC_ETM_CH_CLR30_M (SOC_ETM_CH_CLR30_V << SOC_ETM_CH_CLR30_S) +#define SOC_ETM_CH_CLR30_V 0x00000001U +#define SOC_ETM_CH_CLR30_S 30 +/** SOC_ETM_CH_CLR31 : WT; bitpos: [31]; default: 0; + * ch31 clear + */ +#define SOC_ETM_CH_CLR31 (BIT(31)) +#define SOC_ETM_CH_CLR31_M (SOC_ETM_CH_CLR31_V << SOC_ETM_CH_CLR31_S) +#define SOC_ETM_CH_CLR31_V 0x00000001U +#define SOC_ETM_CH_CLR31_S 31 + +/** SOC_ETM_CH_ENA_AD1_REG register + * channel enable register + */ +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENA32 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch32 enable + */ +#define SOC_ETM_CH_ENA32 (BIT(0)) +#define SOC_ETM_CH_ENA32_M (SOC_ETM_CH_ENA32_V << SOC_ETM_CH_ENA32_S) +#define SOC_ETM_CH_ENA32_V 0x00000001U +#define SOC_ETM_CH_ENA32_S 0 +/** SOC_ETM_CH_ENA33 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch33 enable + */ +#define SOC_ETM_CH_ENA33 (BIT(1)) +#define SOC_ETM_CH_ENA33_M (SOC_ETM_CH_ENA33_V << SOC_ETM_CH_ENA33_S) +#define SOC_ETM_CH_ENA33_V 0x00000001U +#define SOC_ETM_CH_ENA33_S 1 +/** SOC_ETM_CH_ENA34 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch34 enable + */ +#define SOC_ETM_CH_ENA34 (BIT(2)) +#define SOC_ETM_CH_ENA34_M (SOC_ETM_CH_ENA34_V << SOC_ETM_CH_ENA34_S) +#define SOC_ETM_CH_ENA34_V 0x00000001U +#define SOC_ETM_CH_ENA34_S 2 +/** SOC_ETM_CH_ENA35 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch35 enable + */ +#define SOC_ETM_CH_ENA35 (BIT(3)) +#define SOC_ETM_CH_ENA35_M (SOC_ETM_CH_ENA35_V << SOC_ETM_CH_ENA35_S) +#define SOC_ETM_CH_ENA35_V 0x00000001U +#define SOC_ETM_CH_ENA35_S 3 +/** SOC_ETM_CH_ENA36 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch36 enable + */ +#define SOC_ETM_CH_ENA36 (BIT(4)) +#define SOC_ETM_CH_ENA36_M (SOC_ETM_CH_ENA36_V << SOC_ETM_CH_ENA36_S) +#define SOC_ETM_CH_ENA36_V 0x00000001U +#define SOC_ETM_CH_ENA36_S 4 +/** SOC_ETM_CH_ENA37 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch37 enable + */ +#define SOC_ETM_CH_ENA37 (BIT(5)) +#define SOC_ETM_CH_ENA37_M (SOC_ETM_CH_ENA37_V << SOC_ETM_CH_ENA37_S) +#define SOC_ETM_CH_ENA37_V 0x00000001U +#define SOC_ETM_CH_ENA37_S 5 +/** SOC_ETM_CH_ENA38 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch38 enable + */ +#define SOC_ETM_CH_ENA38 (BIT(6)) +#define SOC_ETM_CH_ENA38_M (SOC_ETM_CH_ENA38_V << SOC_ETM_CH_ENA38_S) +#define SOC_ETM_CH_ENA38_V 0x00000001U +#define SOC_ETM_CH_ENA38_S 6 +/** SOC_ETM_CH_ENA39 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch39 enable + */ +#define SOC_ETM_CH_ENA39 (BIT(7)) +#define SOC_ETM_CH_ENA39_M (SOC_ETM_CH_ENA39_V << SOC_ETM_CH_ENA39_S) +#define SOC_ETM_CH_ENA39_V 0x00000001U +#define SOC_ETM_CH_ENA39_S 7 +/** SOC_ETM_CH_ENA40 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch40 enable + */ +#define SOC_ETM_CH_ENA40 (BIT(8)) +#define SOC_ETM_CH_ENA40_M (SOC_ETM_CH_ENA40_V << SOC_ETM_CH_ENA40_S) +#define SOC_ETM_CH_ENA40_V 0x00000001U +#define SOC_ETM_CH_ENA40_S 8 +/** SOC_ETM_CH_ENA41 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch41 enable + */ +#define SOC_ETM_CH_ENA41 (BIT(9)) +#define SOC_ETM_CH_ENA41_M (SOC_ETM_CH_ENA41_V << SOC_ETM_CH_ENA41_S) +#define SOC_ETM_CH_ENA41_V 0x00000001U +#define SOC_ETM_CH_ENA41_S 9 +/** SOC_ETM_CH_ENA42 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch42 enable + */ +#define SOC_ETM_CH_ENA42 (BIT(10)) +#define SOC_ETM_CH_ENA42_M (SOC_ETM_CH_ENA42_V << SOC_ETM_CH_ENA42_S) +#define SOC_ETM_CH_ENA42_V 0x00000001U +#define SOC_ETM_CH_ENA42_S 10 +/** SOC_ETM_CH_ENA43 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch43 enable + */ +#define SOC_ETM_CH_ENA43 (BIT(11)) +#define SOC_ETM_CH_ENA43_M (SOC_ETM_CH_ENA43_V << SOC_ETM_CH_ENA43_S) +#define SOC_ETM_CH_ENA43_V 0x00000001U +#define SOC_ETM_CH_ENA43_S 11 +/** SOC_ETM_CH_ENA44 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch44 enable + */ +#define SOC_ETM_CH_ENA44 (BIT(12)) +#define SOC_ETM_CH_ENA44_M (SOC_ETM_CH_ENA44_V << SOC_ETM_CH_ENA44_S) +#define SOC_ETM_CH_ENA44_V 0x00000001U +#define SOC_ETM_CH_ENA44_S 12 +/** SOC_ETM_CH_ENA45 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch45 enable + */ +#define SOC_ETM_CH_ENA45 (BIT(13)) +#define SOC_ETM_CH_ENA45_M (SOC_ETM_CH_ENA45_V << SOC_ETM_CH_ENA45_S) +#define SOC_ETM_CH_ENA45_V 0x00000001U +#define SOC_ETM_CH_ENA45_S 13 +/** SOC_ETM_CH_ENA46 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch46 enable + */ +#define SOC_ETM_CH_ENA46 (BIT(14)) +#define SOC_ETM_CH_ENA46_M (SOC_ETM_CH_ENA46_V << SOC_ETM_CH_ENA46_S) +#define SOC_ETM_CH_ENA46_V 0x00000001U +#define SOC_ETM_CH_ENA46_S 14 +/** SOC_ETM_CH_ENA47 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch47 enable + */ +#define SOC_ETM_CH_ENA47 (BIT(15)) +#define SOC_ETM_CH_ENA47_M (SOC_ETM_CH_ENA47_V << SOC_ETM_CH_ENA47_S) +#define SOC_ETM_CH_ENA47_V 0x00000001U +#define SOC_ETM_CH_ENA47_S 15 +/** SOC_ETM_CH_ENA48 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch48 enable + */ +#define SOC_ETM_CH_ENA48 (BIT(16)) +#define SOC_ETM_CH_ENA48_M (SOC_ETM_CH_ENA48_V << SOC_ETM_CH_ENA48_S) +#define SOC_ETM_CH_ENA48_V 0x00000001U +#define SOC_ETM_CH_ENA48_S 16 +/** SOC_ETM_CH_ENA49 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch49 enable + */ +#define SOC_ETM_CH_ENA49 (BIT(17)) +#define SOC_ETM_CH_ENA49_M (SOC_ETM_CH_ENA49_V << SOC_ETM_CH_ENA49_S) +#define SOC_ETM_CH_ENA49_V 0x00000001U +#define SOC_ETM_CH_ENA49_S 17 + +/** SOC_ETM_CH_ENA_AD1_SET_REG register + * channel enable set register + */ +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_SET32 : WT; bitpos: [0]; default: 0; + * ch32 set + */ +#define SOC_ETM_CH_SET32 (BIT(0)) +#define SOC_ETM_CH_SET32_M (SOC_ETM_CH_SET32_V << SOC_ETM_CH_SET32_S) +#define SOC_ETM_CH_SET32_V 0x00000001U +#define SOC_ETM_CH_SET32_S 0 +/** SOC_ETM_CH_SET33 : WT; bitpos: [1]; default: 0; + * ch33 set + */ +#define SOC_ETM_CH_SET33 (BIT(1)) +#define SOC_ETM_CH_SET33_M (SOC_ETM_CH_SET33_V << SOC_ETM_CH_SET33_S) +#define SOC_ETM_CH_SET33_V 0x00000001U +#define SOC_ETM_CH_SET33_S 1 +/** SOC_ETM_CH_SET34 : WT; bitpos: [2]; default: 0; + * ch34 set + */ +#define SOC_ETM_CH_SET34 (BIT(2)) +#define SOC_ETM_CH_SET34_M (SOC_ETM_CH_SET34_V << SOC_ETM_CH_SET34_S) +#define SOC_ETM_CH_SET34_V 0x00000001U +#define SOC_ETM_CH_SET34_S 2 +/** SOC_ETM_CH_SET35 : WT; bitpos: [3]; default: 0; + * ch35 set + */ +#define SOC_ETM_CH_SET35 (BIT(3)) +#define SOC_ETM_CH_SET35_M (SOC_ETM_CH_SET35_V << SOC_ETM_CH_SET35_S) +#define SOC_ETM_CH_SET35_V 0x00000001U +#define SOC_ETM_CH_SET35_S 3 +/** SOC_ETM_CH_SET36 : WT; bitpos: [4]; default: 0; + * ch36 set + */ +#define SOC_ETM_CH_SET36 (BIT(4)) +#define SOC_ETM_CH_SET36_M (SOC_ETM_CH_SET36_V << SOC_ETM_CH_SET36_S) +#define SOC_ETM_CH_SET36_V 0x00000001U +#define SOC_ETM_CH_SET36_S 4 +/** SOC_ETM_CH_SET37 : WT; bitpos: [5]; default: 0; + * ch37 set + */ +#define SOC_ETM_CH_SET37 (BIT(5)) +#define SOC_ETM_CH_SET37_M (SOC_ETM_CH_SET37_V << SOC_ETM_CH_SET37_S) +#define SOC_ETM_CH_SET37_V 0x00000001U +#define SOC_ETM_CH_SET37_S 5 +/** SOC_ETM_CH_SET38 : WT; bitpos: [6]; default: 0; + * ch38 set + */ +#define SOC_ETM_CH_SET38 (BIT(6)) +#define SOC_ETM_CH_SET38_M (SOC_ETM_CH_SET38_V << SOC_ETM_CH_SET38_S) +#define SOC_ETM_CH_SET38_V 0x00000001U +#define SOC_ETM_CH_SET38_S 6 +/** SOC_ETM_CH_SET39 : WT; bitpos: [7]; default: 0; + * ch39 set + */ +#define SOC_ETM_CH_SET39 (BIT(7)) +#define SOC_ETM_CH_SET39_M (SOC_ETM_CH_SET39_V << SOC_ETM_CH_SET39_S) +#define SOC_ETM_CH_SET39_V 0x00000001U +#define SOC_ETM_CH_SET39_S 7 +/** SOC_ETM_CH_SET40 : WT; bitpos: [8]; default: 0; + * ch40 set + */ +#define SOC_ETM_CH_SET40 (BIT(8)) +#define SOC_ETM_CH_SET40_M (SOC_ETM_CH_SET40_V << SOC_ETM_CH_SET40_S) +#define SOC_ETM_CH_SET40_V 0x00000001U +#define SOC_ETM_CH_SET40_S 8 +/** SOC_ETM_CH_SET41 : WT; bitpos: [9]; default: 0; + * ch41 set + */ +#define SOC_ETM_CH_SET41 (BIT(9)) +#define SOC_ETM_CH_SET41_M (SOC_ETM_CH_SET41_V << SOC_ETM_CH_SET41_S) +#define SOC_ETM_CH_SET41_V 0x00000001U +#define SOC_ETM_CH_SET41_S 9 +/** SOC_ETM_CH_SET42 : WT; bitpos: [10]; default: 0; + * ch42 set + */ +#define SOC_ETM_CH_SET42 (BIT(10)) +#define SOC_ETM_CH_SET42_M (SOC_ETM_CH_SET42_V << SOC_ETM_CH_SET42_S) +#define SOC_ETM_CH_SET42_V 0x00000001U +#define SOC_ETM_CH_SET42_S 10 +/** SOC_ETM_CH_SET43 : WT; bitpos: [11]; default: 0; + * ch43 set + */ +#define SOC_ETM_CH_SET43 (BIT(11)) +#define SOC_ETM_CH_SET43_M (SOC_ETM_CH_SET43_V << SOC_ETM_CH_SET43_S) +#define SOC_ETM_CH_SET43_V 0x00000001U +#define SOC_ETM_CH_SET43_S 11 +/** SOC_ETM_CH_SET44 : WT; bitpos: [12]; default: 0; + * ch44 set + */ +#define SOC_ETM_CH_SET44 (BIT(12)) +#define SOC_ETM_CH_SET44_M (SOC_ETM_CH_SET44_V << SOC_ETM_CH_SET44_S) +#define SOC_ETM_CH_SET44_V 0x00000001U +#define SOC_ETM_CH_SET44_S 12 +/** SOC_ETM_CH_SET45 : WT; bitpos: [13]; default: 0; + * ch45 set + */ +#define SOC_ETM_CH_SET45 (BIT(13)) +#define SOC_ETM_CH_SET45_M (SOC_ETM_CH_SET45_V << SOC_ETM_CH_SET45_S) +#define SOC_ETM_CH_SET45_V 0x00000001U +#define SOC_ETM_CH_SET45_S 13 +/** SOC_ETM_CH_SET46 : WT; bitpos: [14]; default: 0; + * ch46 set + */ +#define SOC_ETM_CH_SET46 (BIT(14)) +#define SOC_ETM_CH_SET46_M (SOC_ETM_CH_SET46_V << SOC_ETM_CH_SET46_S) +#define SOC_ETM_CH_SET46_V 0x00000001U +#define SOC_ETM_CH_SET46_S 14 +/** SOC_ETM_CH_SET47 : WT; bitpos: [15]; default: 0; + * ch47 set + */ +#define SOC_ETM_CH_SET47 (BIT(15)) +#define SOC_ETM_CH_SET47_M (SOC_ETM_CH_SET47_V << SOC_ETM_CH_SET47_S) +#define SOC_ETM_CH_SET47_V 0x00000001U +#define SOC_ETM_CH_SET47_S 15 +/** SOC_ETM_CH_SET48 : WT; bitpos: [16]; default: 0; + * ch48 set + */ +#define SOC_ETM_CH_SET48 (BIT(16)) +#define SOC_ETM_CH_SET48_M (SOC_ETM_CH_SET48_V << SOC_ETM_CH_SET48_S) +#define SOC_ETM_CH_SET48_V 0x00000001U +#define SOC_ETM_CH_SET48_S 16 +/** SOC_ETM_CH_SET49 : WT; bitpos: [17]; default: 0; + * ch49 set + */ +#define SOC_ETM_CH_SET49 (BIT(17)) +#define SOC_ETM_CH_SET49_M (SOC_ETM_CH_SET49_V << SOC_ETM_CH_SET49_S) +#define SOC_ETM_CH_SET49_V 0x00000001U +#define SOC_ETM_CH_SET49_S 17 + +/** SOC_ETM_CH_ENA_AD1_CLR_REG register + * channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_CLR32 : WT; bitpos: [0]; default: 0; + * ch32 clear + */ +#define SOC_ETM_CH_CLR32 (BIT(0)) +#define SOC_ETM_CH_CLR32_M (SOC_ETM_CH_CLR32_V << SOC_ETM_CH_CLR32_S) +#define SOC_ETM_CH_CLR32_V 0x00000001U +#define SOC_ETM_CH_CLR32_S 0 +/** SOC_ETM_CH_CLR33 : WT; bitpos: [1]; default: 0; + * ch33 clear + */ +#define SOC_ETM_CH_CLR33 (BIT(1)) +#define SOC_ETM_CH_CLR33_M (SOC_ETM_CH_CLR33_V << SOC_ETM_CH_CLR33_S) +#define SOC_ETM_CH_CLR33_V 0x00000001U +#define SOC_ETM_CH_CLR33_S 1 +/** SOC_ETM_CH_CLR34 : WT; bitpos: [2]; default: 0; + * ch34 clear + */ +#define SOC_ETM_CH_CLR34 (BIT(2)) +#define SOC_ETM_CH_CLR34_M (SOC_ETM_CH_CLR34_V << SOC_ETM_CH_CLR34_S) +#define SOC_ETM_CH_CLR34_V 0x00000001U +#define SOC_ETM_CH_CLR34_S 2 +/** SOC_ETM_CH_CLR35 : WT; bitpos: [3]; default: 0; + * ch35 clear + */ +#define SOC_ETM_CH_CLR35 (BIT(3)) +#define SOC_ETM_CH_CLR35_M (SOC_ETM_CH_CLR35_V << SOC_ETM_CH_CLR35_S) +#define SOC_ETM_CH_CLR35_V 0x00000001U +#define SOC_ETM_CH_CLR35_S 3 +/** SOC_ETM_CH_CLR36 : WT; bitpos: [4]; default: 0; + * ch36 clear + */ +#define SOC_ETM_CH_CLR36 (BIT(4)) +#define SOC_ETM_CH_CLR36_M (SOC_ETM_CH_CLR36_V << SOC_ETM_CH_CLR36_S) +#define SOC_ETM_CH_CLR36_V 0x00000001U +#define SOC_ETM_CH_CLR36_S 4 +/** SOC_ETM_CH_CLR37 : WT; bitpos: [5]; default: 0; + * ch37 clear + */ +#define SOC_ETM_CH_CLR37 (BIT(5)) +#define SOC_ETM_CH_CLR37_M (SOC_ETM_CH_CLR37_V << SOC_ETM_CH_CLR37_S) +#define SOC_ETM_CH_CLR37_V 0x00000001U +#define SOC_ETM_CH_CLR37_S 5 +/** SOC_ETM_CH_CLR38 : WT; bitpos: [6]; default: 0; + * ch38 clear + */ +#define SOC_ETM_CH_CLR38 (BIT(6)) +#define SOC_ETM_CH_CLR38_M (SOC_ETM_CH_CLR38_V << SOC_ETM_CH_CLR38_S) +#define SOC_ETM_CH_CLR38_V 0x00000001U +#define SOC_ETM_CH_CLR38_S 6 +/** SOC_ETM_CH_CLR39 : WT; bitpos: [7]; default: 0; + * ch39 clear + */ +#define SOC_ETM_CH_CLR39 (BIT(7)) +#define SOC_ETM_CH_CLR39_M (SOC_ETM_CH_CLR39_V << SOC_ETM_CH_CLR39_S) +#define SOC_ETM_CH_CLR39_V 0x00000001U +#define SOC_ETM_CH_CLR39_S 7 +/** SOC_ETM_CH_CLR40 : WT; bitpos: [8]; default: 0; + * ch40 clear + */ +#define SOC_ETM_CH_CLR40 (BIT(8)) +#define SOC_ETM_CH_CLR40_M (SOC_ETM_CH_CLR40_V << SOC_ETM_CH_CLR40_S) +#define SOC_ETM_CH_CLR40_V 0x00000001U +#define SOC_ETM_CH_CLR40_S 8 +/** SOC_ETM_CH_CLR41 : WT; bitpos: [9]; default: 0; + * ch41 clear + */ +#define SOC_ETM_CH_CLR41 (BIT(9)) +#define SOC_ETM_CH_CLR41_M (SOC_ETM_CH_CLR41_V << SOC_ETM_CH_CLR41_S) +#define SOC_ETM_CH_CLR41_V 0x00000001U +#define SOC_ETM_CH_CLR41_S 9 +/** SOC_ETM_CH_CLR42 : WT; bitpos: [10]; default: 0; + * ch42 clear + */ +#define SOC_ETM_CH_CLR42 (BIT(10)) +#define SOC_ETM_CH_CLR42_M (SOC_ETM_CH_CLR42_V << SOC_ETM_CH_CLR42_S) +#define SOC_ETM_CH_CLR42_V 0x00000001U +#define SOC_ETM_CH_CLR42_S 10 +/** SOC_ETM_CH_CLR43 : WT; bitpos: [11]; default: 0; + * ch43 clear + */ +#define SOC_ETM_CH_CLR43 (BIT(11)) +#define SOC_ETM_CH_CLR43_M (SOC_ETM_CH_CLR43_V << SOC_ETM_CH_CLR43_S) +#define SOC_ETM_CH_CLR43_V 0x00000001U +#define SOC_ETM_CH_CLR43_S 11 +/** SOC_ETM_CH_CLR44 : WT; bitpos: [12]; default: 0; + * ch44 clear + */ +#define SOC_ETM_CH_CLR44 (BIT(12)) +#define SOC_ETM_CH_CLR44_M (SOC_ETM_CH_CLR44_V << SOC_ETM_CH_CLR44_S) +#define SOC_ETM_CH_CLR44_V 0x00000001U +#define SOC_ETM_CH_CLR44_S 12 +/** SOC_ETM_CH_CLR45 : WT; bitpos: [13]; default: 0; + * ch45 clear + */ +#define SOC_ETM_CH_CLR45 (BIT(13)) +#define SOC_ETM_CH_CLR45_M (SOC_ETM_CH_CLR45_V << SOC_ETM_CH_CLR45_S) +#define SOC_ETM_CH_CLR45_V 0x00000001U +#define SOC_ETM_CH_CLR45_S 13 +/** SOC_ETM_CH_CLR46 : WT; bitpos: [14]; default: 0; + * ch46 clear + */ +#define SOC_ETM_CH_CLR46 (BIT(14)) +#define SOC_ETM_CH_CLR46_M (SOC_ETM_CH_CLR46_V << SOC_ETM_CH_CLR46_S) +#define SOC_ETM_CH_CLR46_V 0x00000001U +#define SOC_ETM_CH_CLR46_S 14 +/** SOC_ETM_CH_CLR47 : WT; bitpos: [15]; default: 0; + * ch47 clear + */ +#define SOC_ETM_CH_CLR47 (BIT(15)) +#define SOC_ETM_CH_CLR47_M (SOC_ETM_CH_CLR47_V << SOC_ETM_CH_CLR47_S) +#define SOC_ETM_CH_CLR47_V 0x00000001U +#define SOC_ETM_CH_CLR47_S 15 +/** SOC_ETM_CH_CLR48 : WT; bitpos: [16]; default: 0; + * ch48 clear + */ +#define SOC_ETM_CH_CLR48 (BIT(16)) +#define SOC_ETM_CH_CLR48_M (SOC_ETM_CH_CLR48_V << SOC_ETM_CH_CLR48_S) +#define SOC_ETM_CH_CLR48_V 0x00000001U +#define SOC_ETM_CH_CLR48_S 16 +/** SOC_ETM_CH_CLR49 : WT; bitpos: [17]; default: 0; + * ch49 clear + */ +#define SOC_ETM_CH_CLR49 (BIT(17)) +#define SOC_ETM_CH_CLR49_M (SOC_ETM_CH_CLR49_V << SOC_ETM_CH_CLR49_S) +#define SOC_ETM_CH_CLR49_V 0x00000001U +#define SOC_ETM_CH_CLR49_S 17 + +/** SOC_ETM_CH0_EVT_ID_REG register + * channel0 event id register + */ +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) +/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch0_evt_id + */ +#define SOC_ETM_CH0_EVT_ID 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) +#define SOC_ETM_CH0_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_S 0 + +/** SOC_ETM_CH0_TASK_ID_REG register + * channel0 task id register + */ +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) +/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch0_task_id + */ +#define SOC_ETM_CH0_TASK_ID 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) +#define SOC_ETM_CH0_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_S 0 + +/** SOC_ETM_CH1_EVT_ID_REG register + * channel1 event id register + */ +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) +/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch1_evt_id + */ +#define SOC_ETM_CH1_EVT_ID 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) +#define SOC_ETM_CH1_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_S 0 + +/** SOC_ETM_CH1_TASK_ID_REG register + * channel1 task id register + */ +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) +/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch1_task_id + */ +#define SOC_ETM_CH1_TASK_ID 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) +#define SOC_ETM_CH1_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_S 0 + +/** SOC_ETM_CH2_EVT_ID_REG register + * channel2 event id register + */ +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) +/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch2_evt_id + */ +#define SOC_ETM_CH2_EVT_ID 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) +#define SOC_ETM_CH2_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_S 0 + +/** SOC_ETM_CH2_TASK_ID_REG register + * channel2 task id register + */ +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) +/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch2_task_id + */ +#define SOC_ETM_CH2_TASK_ID 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) +#define SOC_ETM_CH2_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_S 0 + +/** SOC_ETM_CH3_EVT_ID_REG register + * channel3 event id register + */ +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) +/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch3_evt_id + */ +#define SOC_ETM_CH3_EVT_ID 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) +#define SOC_ETM_CH3_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_S 0 + +/** SOC_ETM_CH3_TASK_ID_REG register + * channel3 task id register + */ +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) +/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch3_task_id + */ +#define SOC_ETM_CH3_TASK_ID 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) +#define SOC_ETM_CH3_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_S 0 + +/** SOC_ETM_CH4_EVT_ID_REG register + * channel4 event id register + */ +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) +/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch4_evt_id + */ +#define SOC_ETM_CH4_EVT_ID 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) +#define SOC_ETM_CH4_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_S 0 + +/** SOC_ETM_CH4_TASK_ID_REG register + * channel4 task id register + */ +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) +/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch4_task_id + */ +#define SOC_ETM_CH4_TASK_ID 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) +#define SOC_ETM_CH4_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_S 0 + +/** SOC_ETM_CH5_EVT_ID_REG register + * channel5 event id register + */ +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) +/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch5_evt_id + */ +#define SOC_ETM_CH5_EVT_ID 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) +#define SOC_ETM_CH5_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_S 0 + +/** SOC_ETM_CH5_TASK_ID_REG register + * channel5 task id register + */ +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) +/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch5_task_id + */ +#define SOC_ETM_CH5_TASK_ID 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) +#define SOC_ETM_CH5_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_S 0 + +/** SOC_ETM_CH6_EVT_ID_REG register + * channel6 event id register + */ +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) +/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch6_evt_id + */ +#define SOC_ETM_CH6_EVT_ID 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) +#define SOC_ETM_CH6_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_S 0 + +/** SOC_ETM_CH6_TASK_ID_REG register + * channel6 task id register + */ +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) +/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch6_task_id + */ +#define SOC_ETM_CH6_TASK_ID 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) +#define SOC_ETM_CH6_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_S 0 + +/** SOC_ETM_CH7_EVT_ID_REG register + * channel7 event id register + */ +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) +/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch7_evt_id + */ +#define SOC_ETM_CH7_EVT_ID 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) +#define SOC_ETM_CH7_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_S 0 + +/** SOC_ETM_CH7_TASK_ID_REG register + * channel7 task id register + */ +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) +/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch7_task_id + */ +#define SOC_ETM_CH7_TASK_ID 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) +#define SOC_ETM_CH7_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_S 0 + +/** SOC_ETM_CH8_EVT_ID_REG register + * channel8 event id register + */ +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) +/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch8_evt_id + */ +#define SOC_ETM_CH8_EVT_ID 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) +#define SOC_ETM_CH8_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_S 0 + +/** SOC_ETM_CH8_TASK_ID_REG register + * channel8 task id register + */ +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) +/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch8_task_id + */ +#define SOC_ETM_CH8_TASK_ID 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) +#define SOC_ETM_CH8_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_S 0 + +/** SOC_ETM_CH9_EVT_ID_REG register + * channel9 event id register + */ +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) +/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch9_evt_id + */ +#define SOC_ETM_CH9_EVT_ID 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) +#define SOC_ETM_CH9_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_S 0 + +/** SOC_ETM_CH9_TASK_ID_REG register + * channel9 task id register + */ +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) +/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch9_task_id + */ +#define SOC_ETM_CH9_TASK_ID 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) +#define SOC_ETM_CH9_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_S 0 + +/** SOC_ETM_CH10_EVT_ID_REG register + * channel10 event id register + */ +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) +/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch10_evt_id + */ +#define SOC_ETM_CH10_EVT_ID 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) +#define SOC_ETM_CH10_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_S 0 + +/** SOC_ETM_CH10_TASK_ID_REG register + * channel10 task id register + */ +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) +/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch10_task_id + */ +#define SOC_ETM_CH10_TASK_ID 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) +#define SOC_ETM_CH10_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_S 0 + +/** SOC_ETM_CH11_EVT_ID_REG register + * channel11 event id register + */ +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) +/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch11_evt_id + */ +#define SOC_ETM_CH11_EVT_ID 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) +#define SOC_ETM_CH11_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_S 0 + +/** SOC_ETM_CH11_TASK_ID_REG register + * channel11 task id register + */ +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) +/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch11_task_id + */ +#define SOC_ETM_CH11_TASK_ID 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) +#define SOC_ETM_CH11_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_S 0 + +/** SOC_ETM_CH12_EVT_ID_REG register + * channel12 event id register + */ +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) +/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch12_evt_id + */ +#define SOC_ETM_CH12_EVT_ID 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) +#define SOC_ETM_CH12_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_S 0 + +/** SOC_ETM_CH12_TASK_ID_REG register + * channel12 task id register + */ +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) +/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch12_task_id + */ +#define SOC_ETM_CH12_TASK_ID 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) +#define SOC_ETM_CH12_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_S 0 + +/** SOC_ETM_CH13_EVT_ID_REG register + * channel13 event id register + */ +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) +/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch13_evt_id + */ +#define SOC_ETM_CH13_EVT_ID 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) +#define SOC_ETM_CH13_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_S 0 + +/** SOC_ETM_CH13_TASK_ID_REG register + * channel13 task id register + */ +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) +/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch13_task_id + */ +#define SOC_ETM_CH13_TASK_ID 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) +#define SOC_ETM_CH13_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_S 0 + +/** SOC_ETM_CH14_EVT_ID_REG register + * channel14 event id register + */ +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) +/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch14_evt_id + */ +#define SOC_ETM_CH14_EVT_ID 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) +#define SOC_ETM_CH14_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_S 0 + +/** SOC_ETM_CH14_TASK_ID_REG register + * channel14 task id register + */ +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) +/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch14_task_id + */ +#define SOC_ETM_CH14_TASK_ID 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) +#define SOC_ETM_CH14_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_S 0 + +/** SOC_ETM_CH15_EVT_ID_REG register + * channel15 event id register + */ +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) +/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch15_evt_id + */ +#define SOC_ETM_CH15_EVT_ID 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) +#define SOC_ETM_CH15_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_S 0 + +/** SOC_ETM_CH15_TASK_ID_REG register + * channel15 task id register + */ +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) +/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch15_task_id + */ +#define SOC_ETM_CH15_TASK_ID 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) +#define SOC_ETM_CH15_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_S 0 + +/** SOC_ETM_CH16_EVT_ID_REG register + * channel16 event id register + */ +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) +/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch16_evt_id + */ +#define SOC_ETM_CH16_EVT_ID 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) +#define SOC_ETM_CH16_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_S 0 + +/** SOC_ETM_CH16_TASK_ID_REG register + * channel16 task id register + */ +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) +/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch16_task_id + */ +#define SOC_ETM_CH16_TASK_ID 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) +#define SOC_ETM_CH16_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_S 0 + +/** SOC_ETM_CH17_EVT_ID_REG register + * channel17 event id register + */ +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) +/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch17_evt_id + */ +#define SOC_ETM_CH17_EVT_ID 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) +#define SOC_ETM_CH17_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_S 0 + +/** SOC_ETM_CH17_TASK_ID_REG register + * channel17 task id register + */ +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) +/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch17_task_id + */ +#define SOC_ETM_CH17_TASK_ID 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) +#define SOC_ETM_CH17_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_S 0 + +/** SOC_ETM_CH18_EVT_ID_REG register + * channel18 event id register + */ +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) +/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch18_evt_id + */ +#define SOC_ETM_CH18_EVT_ID 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) +#define SOC_ETM_CH18_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_S 0 + +/** SOC_ETM_CH18_TASK_ID_REG register + * channel18 task id register + */ +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) +/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch18_task_id + */ +#define SOC_ETM_CH18_TASK_ID 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) +#define SOC_ETM_CH18_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_S 0 + +/** SOC_ETM_CH19_EVT_ID_REG register + * channel19 event id register + */ +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) +/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch19_evt_id + */ +#define SOC_ETM_CH19_EVT_ID 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) +#define SOC_ETM_CH19_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_S 0 + +/** SOC_ETM_CH19_TASK_ID_REG register + * channel19 task id register + */ +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) +/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch19_task_id + */ +#define SOC_ETM_CH19_TASK_ID 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) +#define SOC_ETM_CH19_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_S 0 + +/** SOC_ETM_CH20_EVT_ID_REG register + * channel20 event id register + */ +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) +/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch20_evt_id + */ +#define SOC_ETM_CH20_EVT_ID 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) +#define SOC_ETM_CH20_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_S 0 + +/** SOC_ETM_CH20_TASK_ID_REG register + * channel20 task id register + */ +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) +/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch20_task_id + */ +#define SOC_ETM_CH20_TASK_ID 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) +#define SOC_ETM_CH20_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_S 0 + +/** SOC_ETM_CH21_EVT_ID_REG register + * channel21 event id register + */ +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) +/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch21_evt_id + */ +#define SOC_ETM_CH21_EVT_ID 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) +#define SOC_ETM_CH21_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_S 0 + +/** SOC_ETM_CH21_TASK_ID_REG register + * channel21 task id register + */ +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) +/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch21_task_id + */ +#define SOC_ETM_CH21_TASK_ID 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) +#define SOC_ETM_CH21_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_S 0 + +/** SOC_ETM_CH22_EVT_ID_REG register + * channel22 event id register + */ +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) +/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch22_evt_id + */ +#define SOC_ETM_CH22_EVT_ID 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) +#define SOC_ETM_CH22_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_S 0 + +/** SOC_ETM_CH22_TASK_ID_REG register + * channel22 task id register + */ +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) +/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch22_task_id + */ +#define SOC_ETM_CH22_TASK_ID 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) +#define SOC_ETM_CH22_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_S 0 + +/** SOC_ETM_CH23_EVT_ID_REG register + * channel23 event id register + */ +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) +/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch23_evt_id + */ +#define SOC_ETM_CH23_EVT_ID 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) +#define SOC_ETM_CH23_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_S 0 + +/** SOC_ETM_CH23_TASK_ID_REG register + * channel23 task id register + */ +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) +/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch23_task_id + */ +#define SOC_ETM_CH23_TASK_ID 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) +#define SOC_ETM_CH23_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_S 0 + +/** SOC_ETM_CH24_EVT_ID_REG register + * channel24 event id register + */ +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) +/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch24_evt_id + */ +#define SOC_ETM_CH24_EVT_ID 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) +#define SOC_ETM_CH24_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_S 0 + +/** SOC_ETM_CH24_TASK_ID_REG register + * channel24 task id register + */ +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) +/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch24_task_id + */ +#define SOC_ETM_CH24_TASK_ID 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) +#define SOC_ETM_CH24_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_S 0 + +/** SOC_ETM_CH25_EVT_ID_REG register + * channel25 event id register + */ +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) +/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch25_evt_id + */ +#define SOC_ETM_CH25_EVT_ID 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) +#define SOC_ETM_CH25_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_S 0 + +/** SOC_ETM_CH25_TASK_ID_REG register + * channel25 task id register + */ +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) +/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch25_task_id + */ +#define SOC_ETM_CH25_TASK_ID 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) +#define SOC_ETM_CH25_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_S 0 + +/** SOC_ETM_CH26_EVT_ID_REG register + * channel26 event id register + */ +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) +/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch26_evt_id + */ +#define SOC_ETM_CH26_EVT_ID 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) +#define SOC_ETM_CH26_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_S 0 + +/** SOC_ETM_CH26_TASK_ID_REG register + * channel26 task id register + */ +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) +/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch26_task_id + */ +#define SOC_ETM_CH26_TASK_ID 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) +#define SOC_ETM_CH26_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_S 0 + +/** SOC_ETM_CH27_EVT_ID_REG register + * channel27 event id register + */ +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) +/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch27_evt_id + */ +#define SOC_ETM_CH27_EVT_ID 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) +#define SOC_ETM_CH27_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_S 0 + +/** SOC_ETM_CH27_TASK_ID_REG register + * channel27 task id register + */ +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) +/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch27_task_id + */ +#define SOC_ETM_CH27_TASK_ID 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) +#define SOC_ETM_CH27_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_S 0 + +/** SOC_ETM_CH28_EVT_ID_REG register + * channel28 event id register + */ +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) +/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch28_evt_id + */ +#define SOC_ETM_CH28_EVT_ID 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) +#define SOC_ETM_CH28_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_S 0 + +/** SOC_ETM_CH28_TASK_ID_REG register + * channel28 task id register + */ +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) +/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch28_task_id + */ +#define SOC_ETM_CH28_TASK_ID 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) +#define SOC_ETM_CH28_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_S 0 + +/** SOC_ETM_CH29_EVT_ID_REG register + * channel29 event id register + */ +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) +/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch29_evt_id + */ +#define SOC_ETM_CH29_EVT_ID 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) +#define SOC_ETM_CH29_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_S 0 + +/** SOC_ETM_CH29_TASK_ID_REG register + * channel29 task id register + */ +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) +/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch29_task_id + */ +#define SOC_ETM_CH29_TASK_ID 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) +#define SOC_ETM_CH29_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_S 0 + +/** SOC_ETM_CH30_EVT_ID_REG register + * channel30 event id register + */ +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) +/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch30_evt_id + */ +#define SOC_ETM_CH30_EVT_ID 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) +#define SOC_ETM_CH30_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_S 0 + +/** SOC_ETM_CH30_TASK_ID_REG register + * channel30 task id register + */ +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) +/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch30_task_id + */ +#define SOC_ETM_CH30_TASK_ID 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) +#define SOC_ETM_CH30_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_S 0 + +/** SOC_ETM_CH31_EVT_ID_REG register + * channel31 event id register + */ +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) +/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch31_evt_id + */ +#define SOC_ETM_CH31_EVT_ID 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) +#define SOC_ETM_CH31_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_S 0 + +/** SOC_ETM_CH31_TASK_ID_REG register + * channel31 task id register + */ +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) +/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch31_task_id + */ +#define SOC_ETM_CH31_TASK_ID 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) +#define SOC_ETM_CH31_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_S 0 + +/** SOC_ETM_CH32_EVT_ID_REG register + * channel32 event id register + */ +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) +/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch32_evt_id + */ +#define SOC_ETM_CH32_EVT_ID 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) +#define SOC_ETM_CH32_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_S 0 + +/** SOC_ETM_CH32_TASK_ID_REG register + * channel32 task id register + */ +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) +/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch32_task_id + */ +#define SOC_ETM_CH32_TASK_ID 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) +#define SOC_ETM_CH32_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_S 0 + +/** SOC_ETM_CH33_EVT_ID_REG register + * channel33 event id register + */ +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) +/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch33_evt_id + */ +#define SOC_ETM_CH33_EVT_ID 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) +#define SOC_ETM_CH33_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_S 0 + +/** SOC_ETM_CH33_TASK_ID_REG register + * channel33 task id register + */ +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) +/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch33_task_id + */ +#define SOC_ETM_CH33_TASK_ID 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) +#define SOC_ETM_CH33_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_S 0 + +/** SOC_ETM_CH34_EVT_ID_REG register + * channel34 event id register + */ +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) +/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch34_evt_id + */ +#define SOC_ETM_CH34_EVT_ID 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) +#define SOC_ETM_CH34_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_S 0 + +/** SOC_ETM_CH34_TASK_ID_REG register + * channel34 task id register + */ +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) +/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch34_task_id + */ +#define SOC_ETM_CH34_TASK_ID 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) +#define SOC_ETM_CH34_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_S 0 + +/** SOC_ETM_CH35_EVT_ID_REG register + * channel35 event id register + */ +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) +/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch35_evt_id + */ +#define SOC_ETM_CH35_EVT_ID 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) +#define SOC_ETM_CH35_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_S 0 + +/** SOC_ETM_CH35_TASK_ID_REG register + * channel35 task id register + */ +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) +/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch35_task_id + */ +#define SOC_ETM_CH35_TASK_ID 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) +#define SOC_ETM_CH35_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_S 0 + +/** SOC_ETM_CH36_EVT_ID_REG register + * channel36 event id register + */ +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) +/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch36_evt_id + */ +#define SOC_ETM_CH36_EVT_ID 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) +#define SOC_ETM_CH36_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_S 0 + +/** SOC_ETM_CH36_TASK_ID_REG register + * channel36 task id register + */ +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) +/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch36_task_id + */ +#define SOC_ETM_CH36_TASK_ID 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) +#define SOC_ETM_CH36_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_S 0 + +/** SOC_ETM_CH37_EVT_ID_REG register + * channel37 event id register + */ +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) +/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch37_evt_id + */ +#define SOC_ETM_CH37_EVT_ID 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) +#define SOC_ETM_CH37_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_S 0 + +/** SOC_ETM_CH37_TASK_ID_REG register + * channel37 task id register + */ +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) +/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch37_task_id + */ +#define SOC_ETM_CH37_TASK_ID 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) +#define SOC_ETM_CH37_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_S 0 + +/** SOC_ETM_CH38_EVT_ID_REG register + * channel38 event id register + */ +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) +/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch38_evt_id + */ +#define SOC_ETM_CH38_EVT_ID 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) +#define SOC_ETM_CH38_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_S 0 + +/** SOC_ETM_CH38_TASK_ID_REG register + * channel38 task id register + */ +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) +/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch38_task_id + */ +#define SOC_ETM_CH38_TASK_ID 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) +#define SOC_ETM_CH38_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_S 0 + +/** SOC_ETM_CH39_EVT_ID_REG register + * channel39 event id register + */ +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) +/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch39_evt_id + */ +#define SOC_ETM_CH39_EVT_ID 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) +#define SOC_ETM_CH39_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_S 0 + +/** SOC_ETM_CH39_TASK_ID_REG register + * channel39 task id register + */ +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) +/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch39_task_id + */ +#define SOC_ETM_CH39_TASK_ID 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) +#define SOC_ETM_CH39_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_S 0 + +/** SOC_ETM_CH40_EVT_ID_REG register + * channel40 event id register + */ +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) +/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch40_evt_id + */ +#define SOC_ETM_CH40_EVT_ID 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) +#define SOC_ETM_CH40_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_S 0 + +/** SOC_ETM_CH40_TASK_ID_REG register + * channel40 task id register + */ +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) +/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch40_task_id + */ +#define SOC_ETM_CH40_TASK_ID 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) +#define SOC_ETM_CH40_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_S 0 + +/** SOC_ETM_CH41_EVT_ID_REG register + * channel41 event id register + */ +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) +/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch41_evt_id + */ +#define SOC_ETM_CH41_EVT_ID 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) +#define SOC_ETM_CH41_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_S 0 + +/** SOC_ETM_CH41_TASK_ID_REG register + * channel41 task id register + */ +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) +/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch41_task_id + */ +#define SOC_ETM_CH41_TASK_ID 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) +#define SOC_ETM_CH41_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_S 0 + +/** SOC_ETM_CH42_EVT_ID_REG register + * channel42 event id register + */ +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) +/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch42_evt_id + */ +#define SOC_ETM_CH42_EVT_ID 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) +#define SOC_ETM_CH42_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_S 0 + +/** SOC_ETM_CH42_TASK_ID_REG register + * channel42 task id register + */ +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) +/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch42_task_id + */ +#define SOC_ETM_CH42_TASK_ID 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) +#define SOC_ETM_CH42_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_S 0 + +/** SOC_ETM_CH43_EVT_ID_REG register + * channel43 event id register + */ +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) +/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch43_evt_id + */ +#define SOC_ETM_CH43_EVT_ID 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) +#define SOC_ETM_CH43_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_S 0 + +/** SOC_ETM_CH43_TASK_ID_REG register + * channel43 task id register + */ +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) +/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch43_task_id + */ +#define SOC_ETM_CH43_TASK_ID 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) +#define SOC_ETM_CH43_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_S 0 + +/** SOC_ETM_CH44_EVT_ID_REG register + * channel44 event id register + */ +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) +/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch44_evt_id + */ +#define SOC_ETM_CH44_EVT_ID 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) +#define SOC_ETM_CH44_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_S 0 + +/** SOC_ETM_CH44_TASK_ID_REG register + * channel44 task id register + */ +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) +/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch44_task_id + */ +#define SOC_ETM_CH44_TASK_ID 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) +#define SOC_ETM_CH44_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_S 0 + +/** SOC_ETM_CH45_EVT_ID_REG register + * channel45 event id register + */ +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) +/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch45_evt_id + */ +#define SOC_ETM_CH45_EVT_ID 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) +#define SOC_ETM_CH45_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_S 0 + +/** SOC_ETM_CH45_TASK_ID_REG register + * channel45 task id register + */ +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) +/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch45_task_id + */ +#define SOC_ETM_CH45_TASK_ID 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) +#define SOC_ETM_CH45_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_S 0 + +/** SOC_ETM_CH46_EVT_ID_REG register + * channel46 event id register + */ +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) +/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch46_evt_id + */ +#define SOC_ETM_CH46_EVT_ID 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) +#define SOC_ETM_CH46_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_S 0 + +/** SOC_ETM_CH46_TASK_ID_REG register + * channel46 task id register + */ +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) +/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch46_task_id + */ +#define SOC_ETM_CH46_TASK_ID 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) +#define SOC_ETM_CH46_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_S 0 + +/** SOC_ETM_CH47_EVT_ID_REG register + * channel47 event id register + */ +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) +/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch47_evt_id + */ +#define SOC_ETM_CH47_EVT_ID 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) +#define SOC_ETM_CH47_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_S 0 + +/** SOC_ETM_CH47_TASK_ID_REG register + * channel47 task id register + */ +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) +/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch47_task_id + */ +#define SOC_ETM_CH47_TASK_ID 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) +#define SOC_ETM_CH47_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_S 0 + +/** SOC_ETM_CH48_EVT_ID_REG register + * channel48 event id register + */ +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) +/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch48_evt_id + */ +#define SOC_ETM_CH48_EVT_ID 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) +#define SOC_ETM_CH48_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_S 0 + +/** SOC_ETM_CH48_TASK_ID_REG register + * channel48 task id register + */ +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) +/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch48_task_id + */ +#define SOC_ETM_CH48_TASK_ID 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) +#define SOC_ETM_CH48_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_S 0 + +/** SOC_ETM_CH49_EVT_ID_REG register + * channel49 event id register + */ +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) +/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch49_evt_id + */ +#define SOC_ETM_CH49_EVT_ID 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) +#define SOC_ETM_CH49_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_S 0 + +/** SOC_ETM_CH49_TASK_ID_REG register + * channel49 task id register + */ +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) +/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch49_task_id + */ +#define SOC_ETM_CH49_TASK_ID 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) +#define SOC_ETM_CH49_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_S 0 + +/** SOC_ETM_CLK_EN_REG register + * etm clock enable register + */ +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1a8) +/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define SOC_ETM_CLK_EN (BIT(0)) +#define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) +#define SOC_ETM_CLK_EN_V 0x00000001U +#define SOC_ETM_CLK_EN_S 0 + +/** SOC_ETM_DATE_REG register + * etm date register + */ +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1ac) +/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 35664018; + * date + */ +#define SOC_ETM_DATE 0x0FFFFFFFU +#define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) +#define SOC_ETM_DATE_V 0x0FFFFFFFU +#define SOC_ETM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/soc_etm_source.h b/components/soc/esp32h2/include/soc/soc_etm_source.h new file mode 100644 index 0000000000..9ecde2c030 --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_etm_source.h @@ -0,0 +1,337 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define LEDC_EVT_DUTY_CHNG_END_CH0 25 +#define LEDC_EVT_DUTY_CHNG_END_CH1 26 +#define LEDC_EVT_DUTY_CHNG_END_CH2 27 +#define LEDC_EVT_DUTY_CHNG_END_CH3 28 +#define LEDC_EVT_DUTY_CHNG_END_CH4 29 +#define LEDC_EVT_DUTY_CHNG_END_CH5 30 +#define LEDC_EVT_OVF_CNT_PLS_CH0 31 +#define LEDC_EVT_OVF_CNT_PLS_CH1 32 +#define LEDC_EVT_OVF_CNT_PLS_CH2 33 +#define LEDC_EVT_OVF_CNT_PLS_CH3 34 +#define LEDC_EVT_OVF_CNT_PLS_CH4 35 +#define LEDC_EVT_OVF_CNT_PLS_CH5 36 +#define LEDC_EVT_TIME_OVF_TIMER0 37 +#define LEDC_EVT_TIME_OVF_TIMER1 38 +#define LEDC_EVT_TIME_OVF_TIMER2 39 +#define LEDC_EVT_TIME_OVF_TIMER3 40 +#define LEDC_EVT_TIMER0_CMP 41 +#define LEDC_EVT_TIMER1_CMP 42 +#define LEDC_EVT_TIMER2_CMP 43 +#define LEDC_EVT_TIMER3_CMP 44 +#define PCNT_EVT_CNT_EQ_THRESH 45 +#define PCNT_EVT_CNT_EQ_LMT 46 +#define PCNT_EVT_CNT_EQ_ZERO 47 +#define TIMER0_EVT_CNT_CMP_TIMER0 48 +#define TIMER1_EVT_CNT_CMP_TIMER0 49 +#define SYSTIMER_EVT_CNT_CMP0 50 +#define SYSTIMER_EVT_CNT_CMP1 51 +#define SYSTIMER_EVT_CNT_CMP2 52 +#define RMT_EVT_TX_END 53 +#define RMT_EVT_TX_LOOP 54 +#define RMT_EVT_RX_END 55 +#define RMT_EVT_TX_THRESH 56 +#define RMT_EVT_RX_THRESH 57 +#define MCPWM_EVT_TIMER0_STOP 58 +#define MCPWM_EVT_TIMER1_STOP 59 +#define MCPWM_EVT_TIMER2_STOP 60 +#define MCPWM_EVT_TIMER0_TEZ 61 +#define MCPWM_EVT_TIMER1_TEZ 62 +#define MCPWM_EVT_TIMER2_TEZ 63 +#define MCPWM_EVT_TIMER0_TEP 64 +#define MCPWM_EVT_TIMER1_TEP 65 +#define MCPWM_EVT_TIMER2_TEP 66 +#define MCPWM_EVT_OP0_TEA 67 +#define MCPWM_EVT_OP1_TEA 68 +#define MCPWM_EVT_OP2_TEA 69 +#define MCPWM_EVT_OP0_TEB 70 +#define MCPWM_EVT_OP1_TEB 71 +#define MCPWM_EVT_OP2_TEB 72 +#define MCPWM_EVT_F0 73 +#define MCPWM_EVT_F1 74 +#define MCPWM_EVT_F2 75 +#define MCPWM_EVT_F0_CLR 76 +#define MCPWM_EVT_F1_CLR 77 +#define MCPWM_EVT_F2_CLR 78 +#define MCPWM_EVT_TZ0_CBC 79 +#define MCPWM_EVT_TZ1_CBC 80 +#define MCPWM_EVT_TZ2_CBC 81 +#define MCPWM_EVT_TZ0_OST 82 +#define MCPWM_EVT_TZ1_OST 83 +#define MCPWM_EVT_TZ2_OST 84 +#define MCPWM_EVT_CAP0 85 +#define MCPWM_EVT_CAP1 86 +#define MCPWM_EVT_CAP2 87 +#define ADC_EVT_CONV_CMPLT0 88 +#define ADC_EVT_EQ_ABOVE_THRESH0 89 +#define ADC_EVT_EQ_ABOVE_THRESH1 90 +#define ADC_EVT_EQ_BELOW_THRESH0 91 +#define ADC_EVT_EQ_BELOW_THRESH1 92 +#define ADC_EVT_RESULT_DONE0 93 +#define ADC_EVT_STOPPED0 94 +#define ADC_EVT_STARTED0 95 +#define REGDMA_EVT_DONE0 96 +#define REGDMA_EVT_DONE1 97 +#define REGDMA_EVT_DONE2 98 +#define REGDMA_EVT_DONE3 99 +#define REGDMA_EVT_ERR0 100 +#define REGDMA_EVT_ERR1 101 +#define REGDMA_EVT_ERR2 102 +#define REGDMA_EVT_ERR3 103 +#define PDMA_EVT_TX_DONE 104 +#define PDMA_EVT_OUT_EOF 105 +#define PDMA_EVT_IN_SUC_EOF 106 +#define PDMA_EVT_FULL_OR_EMPTY 107 +#define PDMA_EVT_ALL_DONE 108 +#define PDMA_EVT_RX_DONE 109 +#define TMPSNSR_EVT_OVER_LIMIT 110 +#define UART_EVT_REC_DATA_OVF0 111 +#define UART_EVT_REC_DATA_OVF1 112 +#define UART_EVT_TX_DONE0 113 +#define UART_EVT_TX_DONE1 114 +#define UART_EVT_TIMEOUT0 115 +#define UART_EVT_TIMEOUT1 116 +#define UART_EVT_ERR0 117 +#define UART_EVT_ERR1 118 +#define UART_EVT_CTS0 119 +#define UART_EVT_CTS1 120 +#define UART_EVT_TX_EMPTY0 121 +#define UART_EVT_TX_EMPTY1 122 +#define UART_EVT_AT_PATTERNS0 123 +#define UART_EVT_AT_PATTERNS1 124 +#define SPI_EVT_STOPPED 125 +#define I2S_EVT_RX_DONE 126 +#define I2S_EVT_TX_DONE 127 +#define I2S_EVT_X_WORDS_RECEIVED 128 +#define I2S_EVT_X_WORDS_SENT 129 +#define I2C_EVT_TRANS_DONE 130 +#define LCDCAM_EVT_TRANS_DONE 131 +#define CAN_EVT_TRANS_DONE 132 +#define ULP_EVT_ERR_INTR 133 +#define ULP_EVT_START_INTR 134 +#define RTC_EVT_TICK 135 +#define RTC_EVT_OVF 136 +#define RTC_EVT_CMP 137 +#define GDMA_EVT_IN_DONE_CH0 138 +#define GDMA_EVT_IN_DONE_CH1 139 +#define GDMA_EVT_IN_DONE_CH2 140 +#define GDMA_EVT_IN_SUC_EOF_CH0 141 +#define GDMA_EVT_IN_SUC_EOF_CH1 142 +#define GDMA_EVT_IN_SUC_EOF_CH2 143 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 144 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 145 +#define GDMA_EVT_IN_FIFO_EMPTY_CH2 146 +#define GDMA_EVT_IN_FIFO_FULL_CH0 147 +#define GDMA_EVT_IN_FIFO_FULL_CH1 148 +#define GDMA_EVT_IN_FIFO_FULL_CH2 149 +#define GDMA_EVT_OUT_DONE_CH0 150 +#define GDMA_EVT_OUT_DONE_CH1 151 +#define GDMA_EVT_OUT_DONE_CH2 152 +#define GDMA_EVT_OUT_EOF_CH0 153 +#define GDMA_EVT_OUT_EOF_CH1 154 +#define GDMA_EVT_OUT_EOF_CH2 155 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 156 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 157 +#define GDMA_EVT_OUT_TOTAL_EOF_CH2 158 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 159 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 160 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 161 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 162 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 163 +#define GDMA_EVT_OUT_FIFO_FULL_CH2 164 +#define PMU_EVT_SLEEP_WEEKUP 165 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_RESERVED0 29 +#define LEDC_TASK_RESERVED1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36 +#define LEDC_TASK_TIMER0_CAP 37 +#define LEDC_TASK_TIMER1_CAP 38 +#define LEDC_TASK_TIMER2_CAP 39 +#define LEDC_TASK_TIMER3_CAP 40 +#define LEDC_TASK_SIG_OUT_DIS_CH0 41 +#define LEDC_TASK_SIG_OUT_DIS_CH1 42 +#define LEDC_TASK_SIG_OUT_DIS_CH2 43 +#define LEDC_TASK_SIG_OUT_DIS_CH3 44 +#define LEDC_TASK_SIG_OUT_DIS_CH4 45 +#define LEDC_TASK_SIG_OUT_DIS_CH5 46 +#define LEDC_TASK_OVF_CNT_RST_CH0 47 +#define LEDC_TASK_OVF_CNT_RST_CH1 48 +#define LEDC_TASK_OVF_CNT_RST_CH2 49 +#define LEDC_TASK_OVF_CNT_RST_CH3 50 +#define LEDC_TASK_OVF_CNT_RST_CH4 51 +#define LEDC_TASK_OVF_CNT_RST_CH5 52 +#define LEDC_TASK_TIMER0_RST 53 +#define LEDC_TASK_TIMER1_RST 54 +#define LEDC_TASK_TIMER2_RST 55 +#define LEDC_TASK_TIMER3_RST 56 +#define LEDC_TASK_TIMER0_RESUME 57 +#define LEDC_TASK_TIMER1_RESUME 58 +#define LEDC_TASK_TIMER2_RESUME 59 +#define LEDC_TASK_TIMER3_RESUME 60 +#define LEDC_TASK_TIMER0_PAUSE 61 +#define LEDC_TASK_TIMER1_PAUSE 62 +#define LEDC_TASK_TIMER2_PAUSE 63 +#define LEDC_TASK_TIMER3_PAUSE 64 +#define LEDC_TASK_GAMMA_RESTART_CH0 65 +#define LEDC_TASK_GAMMA_RESTART_CH1 66 +#define LEDC_TASK_GAMMA_RESTART_CH2 67 +#define LEDC_TASK_GAMMA_RESTART_CH3 68 +#define LEDC_TASK_GAMMA_RESTART_CH4 69 +#define LEDC_TASK_GAMMA_RESTART_CH5 70 +#define LEDC_TASK_GAMMA_PAUSE_CH0 71 +#define LEDC_TASK_GAMMA_PAUSE_CH1 72 +#define LEDC_TASK_GAMMA_PAUSE_CH2 73 +#define LEDC_TASK_GAMMA_PAUSE_CH3 74 +#define LEDC_TASK_GAMMA_PAUSE_CH4 75 +#define LEDC_TASK_GAMMA_PAUSE_CH5 76 +#define LEDC_TASK_GAMMA_RESUME_CH0 77 +#define LEDC_TASK_GAMMA_RESUME_CH1 78 +#define LEDC_TASK_GAMMA_RESUME_CH2 79 +#define LEDC_TASK_GAMMA_RESUME_CH3 80 +#define LEDC_TASK_GAMMA_RESUME_CH4 81 +#define LEDC_TASK_GAMMA_RESUME_CH5 82 +#define PCNT_TASK_START 83 +#define PCNT_TASK_STOP 84 +#define PCNT_TASK_CNT_INC 85 +#define PCNT_TASK_CNT_DEC 86 +#define PCNT_TASK_CNT_RST 87 +#define TIMER0_TASK_CNT_START_TIMER0 88 +#define TIMER1_TASK_CNT_START_TIMER0 89 +#define TIMER0_TASK_ALARM_START_TIMER0 90 +#define TIMER1_TASK_ALARM_START_TIMER0 91 +#define TIMER0_TASK_CNT_STOP_TIMER0 92 +#define TIMER1_TASK_CNT_STOP_TIMER0 93 +#define TIMER0_TASK_CNT_RELOAD_TIMER0 94 +#define TIMER1_TASK_CNT_RELOAD_TIMER0 95 +#define TIMER0_TASK_CNT_CAP_TIMER0 96 +#define TIMER1_TASK_CNT_CAP_TIMER0 97 +#define RMT_TASK_TX_START 98 +#define RMT_TASK_TX_STOP 99 +#define RMT_TASK_RX_DONE 100 +#define RMT_TASK_RX_START 101 +#define MCPWM_TASK_CMPR0_A_UP 102 +#define MCPWM_TASK_CMPR1_A_UP 103 +#define MCPWM_TASK_CMPR2_A_UP 104 +#define MCPWM_TASK_CMPR0_B_UP 105 +#define MCPWM_TASK_CMPR1_B_UP 106 +#define MCPWM_TASK_CMPR2_B_UP 107 +#define MCPWM_TASK_GEN_STOP 108 +#define MCPWM_TASK_TIMER0_SYN 109 +#define MCPWM_TASK_TIMER1_SYN 110 +#define MCPWM_TASK_TIMER2_SYN 111 +#define MCPWM_TASK_TIMER0_PERIOD_UP 112 +#define MCPWM_TASK_TIMER1_PERIOD_UP 113 +#define MCPWM_TASK_TIMER2_PERIOD_UP 114 +#define MCPWM_TASK_TZ0_OST 115 +#define MCPWM_TASK_TZ1_OST 116 +#define MCPWM_TASK_TZ2_OST 117 +#define MCPWM_TASK_CLR0_OST 118 +#define MCPWM_TASK_CLR1_OST 119 +#define MCPWM_TASK_CLR2_OST 120 +#define MCPWM_TASK_CAP0 121 +#define MCPWM_TASK_CAP1 122 +#define MCPWM_TASK_CAP2 123 +#define ADC_TASK_SAMPLE0 124 +#define ADC_TASK_SAMPLE1 125 +#define ADC_TASK_START0 126 +#define ADC_TASK_STOP0 127 +#define REGDMA_TASK_START0 128 +#define REGDMA_TASK_START1 129 +#define REGDMA_TASK_START2 130 +#define REGDMA_TASK_START3 131 +#define PDMA_TASK_START_TX 132 +#define PDMA_TASK_START_RX 133 +#define PDMA_TASK_STOP 134 +#define TMPSNSR_TASK_START_SAMPLE 135 +#define TMPSNSR_TASK_STOP_SAMPLE 136 +#define UART_TASK_TX_START0 137 +#define UART_TASK_TX_START1 138 +#define UART_TASK_TX_STOP0 139 +#define UART_TASK_TX_STOP1 140 +#define UART_TASK_RX_START0 141 +#define UART_TASK_RX_START1 142 +#define UART_TASK_RX_STOP0 143 +#define UART_TASK_RX_STOP1 144 +#define SPI_TASK_TX_START 145 +#define SPI_TASK_SLAVE_HD 146 +#define SPI_TASK_STOP 147 +#define I2S_TASK_START_RX 148 +#define I2S_TASK_START_TX 149 +#define I2S_TASK_STOP_RX 150 +#define I2S_TASK_STOP_TX 151 +#define I2C_TASK_START_TRANS 152 +#define CAN_TASK_TRANS_START 153 +#define ULP_TASK_WAKEUP_CPU 154 +#define RTC_TASK_START 155 +#define RTC_TASK_STOP 156 +#define RTC_TASK_CLR 157 +#define RTC_TASK_TRIGGERFLW 158 +#define GDMA_TASK_IN_START_CH0 159 +#define GDMA_TASK_IN_START_CH1 160 +#define GDMA_TASK_IN_START_CH2 161 +#define GDMA_TASK_OUT_START_CH0 162 +#define GDMA_TASK_OUT_START_CH1 163 +#define GDMA_TASK_OUT_START_CH2 164 +#define PMU_TASK_SLEEP_REQ 165 diff --git a/components/soc/esp32h2/include/soc/soc_etm_struct.h b/components/soc/esp32h2/include/soc/soc_etm_struct.h new file mode 100644 index 0000000000..5e8f2dea6b --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_etm_struct.h @@ -0,0 +1,753 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of ch_ena_ad0 register + * channel enable register + */ +typedef union { + struct { + /** ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch0 enable + */ + uint32_t ch_ena0:1; + /** ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch1 enable + */ + uint32_t ch_ena1:1; + /** ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch2 enable + */ + uint32_t ch_ena2:1; + /** ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch3 enable + */ + uint32_t ch_ena3:1; + /** ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch4 enable + */ + uint32_t ch_ena4:1; + /** ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch5 enable + */ + uint32_t ch_ena5:1; + /** ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch6 enable + */ + uint32_t ch_ena6:1; + /** ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch7 enable + */ + uint32_t ch_ena7:1; + /** ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch8 enable + */ + uint32_t ch_ena8:1; + /** ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch9 enable + */ + uint32_t ch_ena9:1; + /** ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch10 enable + */ + uint32_t ch_ena10:1; + /** ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch11 enable + */ + uint32_t ch_ena11:1; + /** ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch12 enable + */ + uint32_t ch_ena12:1; + /** ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch13 enable + */ + uint32_t ch_ena13:1; + /** ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch14 enable + */ + uint32_t ch_ena14:1; + /** ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch15 enable + */ + uint32_t ch_ena15:1; + /** ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch16 enable + */ + uint32_t ch_ena16:1; + /** ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch17 enable + */ + uint32_t ch_ena17:1; + /** ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0; + * ch18 enable + */ + uint32_t ch_ena18:1; + /** ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0; + * ch19 enable + */ + uint32_t ch_ena19:1; + /** ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0; + * ch20 enable + */ + uint32_t ch_ena20:1; + /** ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0; + * ch21 enable + */ + uint32_t ch_ena21:1; + /** ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0; + * ch22 enable + */ + uint32_t ch_ena22:1; + /** ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0; + * ch23 enable + */ + uint32_t ch_ena23:1; + /** ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0; + * ch24 enable + */ + uint32_t ch_ena24:1; + /** ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0; + * ch25 enable + */ + uint32_t ch_ena25:1; + /** ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0; + * ch26 enable + */ + uint32_t ch_ena26:1; + /** ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0; + * ch27 enable + */ + uint32_t ch_ena27:1; + /** ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0; + * ch28 enable + */ + uint32_t ch_ena28:1; + /** ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0; + * ch29 enable + */ + uint32_t ch_ena29:1; + /** ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0; + * ch30 enable + */ + uint32_t ch_ena30:1; + /** ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0; + * ch31 enable + */ + uint32_t ch_ena31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_reg_t; + +/** Type of ch_ena_ad0_set register + * channel enable set register + */ +typedef union { + struct { + /** ch_set0 : WT; bitpos: [0]; default: 0; + * ch0 set + */ + uint32_t ch_set0:1; + /** ch_set1 : WT; bitpos: [1]; default: 0; + * ch1 set + */ + uint32_t ch_set1:1; + /** ch_set2 : WT; bitpos: [2]; default: 0; + * ch2 set + */ + uint32_t ch_set2:1; + /** ch_set3 : WT; bitpos: [3]; default: 0; + * ch3 set + */ + uint32_t ch_set3:1; + /** ch_set4 : WT; bitpos: [4]; default: 0; + * ch4 set + */ + uint32_t ch_set4:1; + /** ch_set5 : WT; bitpos: [5]; default: 0; + * ch5 set + */ + uint32_t ch_set5:1; + /** ch_set6 : WT; bitpos: [6]; default: 0; + * ch6 set + */ + uint32_t ch_set6:1; + /** ch_set7 : WT; bitpos: [7]; default: 0; + * ch7 set + */ + uint32_t ch_set7:1; + /** ch_set8 : WT; bitpos: [8]; default: 0; + * ch8 set + */ + uint32_t ch_set8:1; + /** ch_set9 : WT; bitpos: [9]; default: 0; + * ch9 set + */ + uint32_t ch_set9:1; + /** ch_set10 : WT; bitpos: [10]; default: 0; + * ch10 set + */ + uint32_t ch_set10:1; + /** ch_set11 : WT; bitpos: [11]; default: 0; + * ch11 set + */ + uint32_t ch_set11:1; + /** ch_set12 : WT; bitpos: [12]; default: 0; + * ch12 set + */ + uint32_t ch_set12:1; + /** ch_set13 : WT; bitpos: [13]; default: 0; + * ch13 set + */ + uint32_t ch_set13:1; + /** ch_set14 : WT; bitpos: [14]; default: 0; + * ch14 set + */ + uint32_t ch_set14:1; + /** ch_set15 : WT; bitpos: [15]; default: 0; + * ch15 set + */ + uint32_t ch_set15:1; + /** ch_set16 : WT; bitpos: [16]; default: 0; + * ch16 set + */ + uint32_t ch_set16:1; + /** ch_set17 : WT; bitpos: [17]; default: 0; + * ch17 set + */ + uint32_t ch_set17:1; + /** ch_set18 : WT; bitpos: [18]; default: 0; + * ch18 set + */ + uint32_t ch_set18:1; + /** ch_set19 : WT; bitpos: [19]; default: 0; + * ch19 set + */ + uint32_t ch_set19:1; + /** ch_set20 : WT; bitpos: [20]; default: 0; + * ch20 set + */ + uint32_t ch_set20:1; + /** ch_set21 : WT; bitpos: [21]; default: 0; + * ch21 set + */ + uint32_t ch_set21:1; + /** ch_set22 : WT; bitpos: [22]; default: 0; + * ch22 set + */ + uint32_t ch_set22:1; + /** ch_set23 : WT; bitpos: [23]; default: 0; + * ch23 set + */ + uint32_t ch_set23:1; + /** ch_set24 : WT; bitpos: [24]; default: 0; + * ch24 set + */ + uint32_t ch_set24:1; + /** ch_set25 : WT; bitpos: [25]; default: 0; + * ch25 set + */ + uint32_t ch_set25:1; + /** ch_set26 : WT; bitpos: [26]; default: 0; + * ch26 set + */ + uint32_t ch_set26:1; + /** ch_set27 : WT; bitpos: [27]; default: 0; + * ch27 set + */ + uint32_t ch_set27:1; + /** ch_set28 : WT; bitpos: [28]; default: 0; + * ch28 set + */ + uint32_t ch_set28:1; + /** ch_set29 : WT; bitpos: [29]; default: 0; + * ch29 set + */ + uint32_t ch_set29:1; + /** ch_set30 : WT; bitpos: [30]; default: 0; + * ch30 set + */ + uint32_t ch_set30:1; + /** ch_set31 : WT; bitpos: [31]; default: 0; + * ch31 set + */ + uint32_t ch_set31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_set_reg_t; + +/** Type of ch_ena_ad0_clr register + * channel enable clear register + */ +typedef union { + struct { + /** ch_clr0 : WT; bitpos: [0]; default: 0; + * ch0 clear + */ + uint32_t ch_clr0:1; + /** ch_clr1 : WT; bitpos: [1]; default: 0; + * ch1 clear + */ + uint32_t ch_clr1:1; + /** ch_clr2 : WT; bitpos: [2]; default: 0; + * ch2 clear + */ + uint32_t ch_clr2:1; + /** ch_clr3 : WT; bitpos: [3]; default: 0; + * ch3 clear + */ + uint32_t ch_clr3:1; + /** ch_clr4 : WT; bitpos: [4]; default: 0; + * ch4 clear + */ + uint32_t ch_clr4:1; + /** ch_clr5 : WT; bitpos: [5]; default: 0; + * ch5 clear + */ + uint32_t ch_clr5:1; + /** ch_clr6 : WT; bitpos: [6]; default: 0; + * ch6 clear + */ + uint32_t ch_clr6:1; + /** ch_clr7 : WT; bitpos: [7]; default: 0; + * ch7 clear + */ + uint32_t ch_clr7:1; + /** ch_clr8 : WT; bitpos: [8]; default: 0; + * ch8 clear + */ + uint32_t ch_clr8:1; + /** ch_clr9 : WT; bitpos: [9]; default: 0; + * ch9 clear + */ + uint32_t ch_clr9:1; + /** ch_clr10 : WT; bitpos: [10]; default: 0; + * ch10 clear + */ + uint32_t ch_clr10:1; + /** ch_clr11 : WT; bitpos: [11]; default: 0; + * ch11 clear + */ + uint32_t ch_clr11:1; + /** ch_clr12 : WT; bitpos: [12]; default: 0; + * ch12 clear + */ + uint32_t ch_clr12:1; + /** ch_clr13 : WT; bitpos: [13]; default: 0; + * ch13 clear + */ + uint32_t ch_clr13:1; + /** ch_clr14 : WT; bitpos: [14]; default: 0; + * ch14 clear + */ + uint32_t ch_clr14:1; + /** ch_clr15 : WT; bitpos: [15]; default: 0; + * ch15 clear + */ + uint32_t ch_clr15:1; + /** ch_clr16 : WT; bitpos: [16]; default: 0; + * ch16 clear + */ + uint32_t ch_clr16:1; + /** ch_clr17 : WT; bitpos: [17]; default: 0; + * ch17 clear + */ + uint32_t ch_clr17:1; + /** ch_clr18 : WT; bitpos: [18]; default: 0; + * ch18 clear + */ + uint32_t ch_clr18:1; + /** ch_clr19 : WT; bitpos: [19]; default: 0; + * ch19 clear + */ + uint32_t ch_clr19:1; + /** ch_clr20 : WT; bitpos: [20]; default: 0; + * ch20 clear + */ + uint32_t ch_clr20:1; + /** ch_clr21 : WT; bitpos: [21]; default: 0; + * ch21 clear + */ + uint32_t ch_clr21:1; + /** ch_clr22 : WT; bitpos: [22]; default: 0; + * ch22 clear + */ + uint32_t ch_clr22:1; + /** ch_clr23 : WT; bitpos: [23]; default: 0; + * ch23 clear + */ + uint32_t ch_clr23:1; + /** ch_clr24 : WT; bitpos: [24]; default: 0; + * ch24 clear + */ + uint32_t ch_clr24:1; + /** ch_clr25 : WT; bitpos: [25]; default: 0; + * ch25 clear + */ + uint32_t ch_clr25:1; + /** ch_clr26 : WT; bitpos: [26]; default: 0; + * ch26 clear + */ + uint32_t ch_clr26:1; + /** ch_clr27 : WT; bitpos: [27]; default: 0; + * ch27 clear + */ + uint32_t ch_clr27:1; + /** ch_clr28 : WT; bitpos: [28]; default: 0; + * ch28 clear + */ + uint32_t ch_clr28:1; + /** ch_clr29 : WT; bitpos: [29]; default: 0; + * ch29 clear + */ + uint32_t ch_clr29:1; + /** ch_clr30 : WT; bitpos: [30]; default: 0; + * ch30 clear + */ + uint32_t ch_clr30:1; + /** ch_clr31 : WT; bitpos: [31]; default: 0; + * ch31 clear + */ + uint32_t ch_clr31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_clr_reg_t; + +/** Type of ch_ena_ad1 register + * channel enable register + */ +typedef union { + struct { + /** ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch32 enable + */ + uint32_t ch_ena32:1; + /** ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch33 enable + */ + uint32_t ch_ena33:1; + /** ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch34 enable + */ + uint32_t ch_ena34:1; + /** ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch35 enable + */ + uint32_t ch_ena35:1; + /** ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch36 enable + */ + uint32_t ch_ena36:1; + /** ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch37 enable + */ + uint32_t ch_ena37:1; + /** ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch38 enable + */ + uint32_t ch_ena38:1; + /** ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch39 enable + */ + uint32_t ch_ena39:1; + /** ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch40 enable + */ + uint32_t ch_ena40:1; + /** ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch41 enable + */ + uint32_t ch_ena41:1; + /** ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch42 enable + */ + uint32_t ch_ena42:1; + /** ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch43 enable + */ + uint32_t ch_ena43:1; + /** ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch44 enable + */ + uint32_t ch_ena44:1; + /** ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch45 enable + */ + uint32_t ch_ena45:1; + /** ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch46 enable + */ + uint32_t ch_ena46:1; + /** ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch47 enable + */ + uint32_t ch_ena47:1; + /** ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch48 enable + */ + uint32_t ch_ena48:1; + /** ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch49 enable + */ + uint32_t ch_ena49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_reg_t; + +/** Type of ch_ena_ad1_set register + * channel enable set register + */ +typedef union { + struct { + /** ch_set32 : WT; bitpos: [0]; default: 0; + * ch32 set + */ + uint32_t ch_set32:1; + /** ch_set33 : WT; bitpos: [1]; default: 0; + * ch33 set + */ + uint32_t ch_set33:1; + /** ch_set34 : WT; bitpos: [2]; default: 0; + * ch34 set + */ + uint32_t ch_set34:1; + /** ch_set35 : WT; bitpos: [3]; default: 0; + * ch35 set + */ + uint32_t ch_set35:1; + /** ch_set36 : WT; bitpos: [4]; default: 0; + * ch36 set + */ + uint32_t ch_set36:1; + /** ch_set37 : WT; bitpos: [5]; default: 0; + * ch37 set + */ + uint32_t ch_set37:1; + /** ch_set38 : WT; bitpos: [6]; default: 0; + * ch38 set + */ + uint32_t ch_set38:1; + /** ch_set39 : WT; bitpos: [7]; default: 0; + * ch39 set + */ + uint32_t ch_set39:1; + /** ch_set40 : WT; bitpos: [8]; default: 0; + * ch40 set + */ + uint32_t ch_set40:1; + /** ch_set41 : WT; bitpos: [9]; default: 0; + * ch41 set + */ + uint32_t ch_set41:1; + /** ch_set42 : WT; bitpos: [10]; default: 0; + * ch42 set + */ + uint32_t ch_set42:1; + /** ch_set43 : WT; bitpos: [11]; default: 0; + * ch43 set + */ + uint32_t ch_set43:1; + /** ch_set44 : WT; bitpos: [12]; default: 0; + * ch44 set + */ + uint32_t ch_set44:1; + /** ch_set45 : WT; bitpos: [13]; default: 0; + * ch45 set + */ + uint32_t ch_set45:1; + /** ch_set46 : WT; bitpos: [14]; default: 0; + * ch46 set + */ + uint32_t ch_set46:1; + /** ch_set47 : WT; bitpos: [15]; default: 0; + * ch47 set + */ + uint32_t ch_set47:1; + /** ch_set48 : WT; bitpos: [16]; default: 0; + * ch48 set + */ + uint32_t ch_set48:1; + /** ch_set49 : WT; bitpos: [17]; default: 0; + * ch49 set + */ + uint32_t ch_set49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_set_reg_t; + +/** Type of ch_ena_ad1_clr register + * channel enable clear register + */ +typedef union { + struct { + /** ch_clr32 : WT; bitpos: [0]; default: 0; + * ch32 clear + */ + uint32_t ch_clr32:1; + /** ch_clr33 : WT; bitpos: [1]; default: 0; + * ch33 clear + */ + uint32_t ch_clr33:1; + /** ch_clr34 : WT; bitpos: [2]; default: 0; + * ch34 clear + */ + uint32_t ch_clr34:1; + /** ch_clr35 : WT; bitpos: [3]; default: 0; + * ch35 clear + */ + uint32_t ch_clr35:1; + /** ch_clr36 : WT; bitpos: [4]; default: 0; + * ch36 clear + */ + uint32_t ch_clr36:1; + /** ch_clr37 : WT; bitpos: [5]; default: 0; + * ch37 clear + */ + uint32_t ch_clr37:1; + /** ch_clr38 : WT; bitpos: [6]; default: 0; + * ch38 clear + */ + uint32_t ch_clr38:1; + /** ch_clr39 : WT; bitpos: [7]; default: 0; + * ch39 clear + */ + uint32_t ch_clr39:1; + /** ch_clr40 : WT; bitpos: [8]; default: 0; + * ch40 clear + */ + uint32_t ch_clr40:1; + /** ch_clr41 : WT; bitpos: [9]; default: 0; + * ch41 clear + */ + uint32_t ch_clr41:1; + /** ch_clr42 : WT; bitpos: [10]; default: 0; + * ch42 clear + */ + uint32_t ch_clr42:1; + /** ch_clr43 : WT; bitpos: [11]; default: 0; + * ch43 clear + */ + uint32_t ch_clr43:1; + /** ch_clr44 : WT; bitpos: [12]; default: 0; + * ch44 clear + */ + uint32_t ch_clr44:1; + /** ch_clr45 : WT; bitpos: [13]; default: 0; + * ch45 clear + */ + uint32_t ch_clr45:1; + /** ch_clr46 : WT; bitpos: [14]; default: 0; + * ch46 clear + */ + uint32_t ch_clr46:1; + /** ch_clr47 : WT; bitpos: [15]; default: 0; + * ch47 clear + */ + uint32_t ch_clr47:1; + /** ch_clr48 : WT; bitpos: [16]; default: 0; + * ch48 clear + */ + uint32_t ch_clr48:1; + /** ch_clr49 : WT; bitpos: [17]; default: 0; + * ch49 clear + */ + uint32_t ch_clr49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_clr_reg_t; + +/** Type of chn_evt_id register + * channeln event id register + */ +typedef union { + struct { + /** evt_id : R/W; bitpos: [7:0]; default: 0; + * chn_evt_id + */ + uint32_t evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_chn_evt_id_reg_t; + +/** Type of chn_task_id register + * channeln task id register + */ +typedef union { + struct { + /** task_id : R/W; bitpos: [7:0]; default: 0; + * chn_task_id + */ + uint32_t task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_chn_task_id_reg_t; + +/** Type of clk_en register + * etm clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} soc_etm_clk_en_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * etm date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35664018; + * date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} soc_etm_date_reg_t; + + +typedef struct soc_etm_dev_t { + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile struct { + soc_etm_chn_evt_id_reg_t evt_id; + soc_etm_chn_task_id_reg_t task_id; + } channel[50]; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; +} soc_etm_dev_t; + +extern soc_etm_dev_t SOC_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(soc_etm_dev_t) == 0x1b0, "Invalid size of soc_etm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/soc_pins.h b/components/soc/esp32h2/include/soc/soc_pins.h new file mode 100644 index 0000000000..05a7c3b416 --- /dev/null +++ b/components/soc/esp32h2/include/soc/soc_pins.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Pin definition header file. The long term plan is to have a single soc_pins.h for all + * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each + * peripheral and include them here to avoid developing conflicts in those header files. + */ + +#pragma once + +#include "soc/gpio_pins.h" +#include "soc/spi_pins.h" diff --git a/components/soc/esp32h2/include/soc/soc_ulp.h b/components/soc/esp32h2/include/soc/soc_ulp.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/soc/esp32h2/include/soc/spi_mem_reg.h b/components/soc/esp32h2/include/soc/spi_mem_reg.h new file mode 100644 index 0000000000..977ed058ee --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_mem_reg.h @@ -0,0 +1,3198 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T +he bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the bit is set. The +bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when the bit is set. The + bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b +e cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered when the bit is + set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will be triggered when t +he bit is set. The bit will be cleared once the operation done.1: enable 0: disa +ble..*/ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera +tion will be triggered when the bit is set. The bit will be cleared once the op +eration done .1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit +is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit + is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T +he bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered when the bit is set +. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat +e or high performance mode and obtains the devices ID. The bit will be cleared o +nce the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operat +ion done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 +/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat +ion will be triggered when the bit is set. The bit will be cleared once the oper +ation done.1: enable 0: disable..*/ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: In user mode, it is set to indicate that program/erase operation will be trigger +ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o +peration done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 +/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta +te, 2: send command state, 3: send address state, 4: wait state, 5: read data st +ate, 6:write data state, 7: done state, 8: read data end state..*/ +#define SPI_MEM_SLV_ST 0x0000000F +#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) +#define SPI_MEM_SLV_ST_V 0xF +#define SPI_MEM_SLV_ST_S 4 +/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT +, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se +nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/ +#define SPI_MEM_MST_ST 0x0000000F +#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) +#define SPI_MEM_MST_ST_V 0xF +#define SPI_MEM_MST_ST_S 0 + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory +address, the bit24-bit31 are the byte length of a transfer..*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a +lways 1. 0: Others..*/ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway +s 1. 0: Others..*/ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is set. 1: enable 0: d +isable..*/ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with +spi_mem_flash_res bit. 1: enable 0: disable..*/ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO +UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 +/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +e.*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 +/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +e low..*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 +/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 8 signals during address phase 1:enable 0: disable.*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 +/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 +/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 +/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] +is output by the MSPI controller in the second half part of dummy phase. It is u +sed to pre-drive flash..*/ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_V 0x1 +#define SPI_MEM_FDUMMY_WOUT_S 3 +/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i +s output by the MSPI controller in the first half part of dummy phase. It is use +d to mask invalid SPI_DQS in the half part of dummy phase..*/ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_V 0x1 +#define SPI_MEM_FDUMMY_RIN_S 2 +/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) +/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + send signals to AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (BIT(31)) +#define SPI_MEM_TXFIFO_RST_V 0x1 +#define SPI_MEM_TXFIFO_RST_S 31 +/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + receive signals from AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 +/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to write data faster, do not wait write data has been stored in tx_ +bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored +in tx_bus_fifo_l2..*/ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_V 0x1 +#define SPI_MEM_FAST_WRITE_EN_S 29 +/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at +the same time..*/ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_V 0x1 +#define SPI_MEM_DUAL_RAM_EN_S 28 +/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac +cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi +ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac +cessed at the same time..*/ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (BIT(27)) +#define SPI_MEM_RAM0_EN_V 0x1 +#define SPI_MEM_RAM0_EN_S 27 +/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Write Splice-transfer..*/ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_V 0x1 +#define SPI_MEM_AW_SPLICE_EN_S 26 +/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Read Splice-transfer..*/ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_V 0x1 +#define SPI_MEM_AR_SPLICE_EN_S 25 +/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + when there is a ECC error in AXI read data. The ECC error information is record +ed in SPI_MEM_ECC_ERR_ADDR_REG..*/ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x1 +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R +eply AXI read data to AXI bus when all the read data is available..*/ +#define SPI_MEM_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_AXI_RDATA_BACK_FAST_M (BIT(23)) +#define SPI_MEM_AXI_RDATA_BACK_FAST_V 0x1 +#define SPI_MEM_AXI_RDATA_BACK_FAST_S 23 +/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M (BIT(22)) +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S 22 +/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl +y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M (BIT(21)) +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S 21 +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ +/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5 +12) SPI_CLK cycles..*/ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is alwasy on..*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The spi0_mst_st and spi0_slv_st will be reset..*/ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core + clock cycles..*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans +fers when one transfer will cross flash or EXT_RAM page corner, valid no matter +whether there is an ECC region or not..*/ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses flash..*/ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */ +/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w +hen accesses flash..*/ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + mode when accessed flash..*/ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ +/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi +th SPI_MEM_CS_HOLD bit..*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ +/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME +M_CS_SETUP bit..*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + clock..*/ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation..*/ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation..*/ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation..*/ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation..*/ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation..*/ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable..*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. +1: enable 0: disable..*/ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1 +: enable 0: disable..*/ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals..*/ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals..*/ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals.*/ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals.*/ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 +/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */ +/*description: SPI0 USR_CMD read or write data byte length -1.*/ +#define SPI_MEM_USR_DBYTELEN 0x00000007 +#define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S)) +#define SPI_MEM_USR_DBYTELEN_V 0x7 +#define SPI_MEM_USR_DBYTELEN_S 6 +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ +/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy +cle_num-1)..*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command..*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b +it..*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/ +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: SPI_CS line keep low when the bit is set..*/ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0, sram is connected to SUBPINs..*/ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 +/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0, flash is connected to SUBPINs..*/ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: For SPI1, the value of crc32..*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) +/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV +_ERR will be replied to BRESP/RRESP..*/ +#define SPI_MEM_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_CLOSE_AXI_INF_EN_M (BIT(31)) +#define SPI_MEM_CLOSE_AXI_INF_EN_V 0x1 +#define SPI_MEM_CLOSE_AXI_INF_EN_S 31 +/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: Set this bit to check AXI read/write the same address region..*/ +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30)) +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V 0x1 +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S 30 +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_qio..*/ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th +e same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_dio..*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the +same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/ +#define SPI_MEM_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_M (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_V 0x1 +#define SPI_MEM_AXI_REQ_EN_S 0 + +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas +e. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 +/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T +he register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase +. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma +nd..*/ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + operations..*/ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ +e operations..*/ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 +/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 +/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en +able, 0:disable..*/ +#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 + +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) +/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0 +] are always 1. 0: Others..*/ +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar +e always 1. 0: Others..*/ +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25)) +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24)) +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM, +the signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_M (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_V 0x1 +#define SPI_MEM_SDUMMY_WOUT_S 23 +/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t +he signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_M (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_V 0x1 +#define SPI_MEM_SDUMMY_RIN_S 22 +/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 +/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 +/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 +/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 +/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 +/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 +/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 +/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 +/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 +/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 +/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 +/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */ +/*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd +_mode bit..*/ +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 +/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is always on..*/ +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 + +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for + sram. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the read command value of command phase + for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram. + The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the write command value of command phas +e for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) +/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c +lk is divided from system clock..*/ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 +/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c +lk frequency is system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 +/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 +/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) +/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ +/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001F +#define SPI_MEM_LOCK_DELAY_TIME_M ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S)) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x1F +#define SPI_MEM_LOCK_DELAY_TIME_S 7 + +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: The command value to wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_CMD 0x0000FFFF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFFFF +#define SPI_MEM_WAITI_CMD_S 16 +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: The dummy cycle length when wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is + 8..*/ +#define SPI_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_M (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_V 0x1 +#define SPI_MEM_WAITI_CMD_2B_S 9 +/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI +_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when +SPI_MEM_WAITI_ADDR_EN is cleared..*/ +#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S)) +#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 +/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out ad +dress in RDSR or read SUS command transfer..*/ +#define SPI_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_M (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_V 0x1 +#define SPI_MEM_WAITI_ADDR_EN_S 2 +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The dummy phase enable when wait flash idle (RDSR).*/ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 +/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto +Suspend/Resume are not supported..*/ +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) +/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ +/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, + it will be treated as check pass..*/ +#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F +#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) +#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F +#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 +/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu +s of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PES_END_EN (BIT(24)) +#define SPI_MEM_PES_END_EN_M (BIT(24)) +#define SPI_MEM_PES_END_EN_V 0x1 +#define SPI_MEM_PES_END_EN_S 24 +/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status + of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PER_END_EN (BIT(23)) +#define SPI_MEM_PER_END_EN_M (BIT(23)) +#define SPI_MEM_PER_END_EN_V 0x1 +#define SPI_MEM_PER_END_EN_S 23 +/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte w +hen check flash SUS/SUS1/SUS2 status bit.*/ +#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_M (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_V 0x1 +#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ +/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is +status_in[15:0](only status_in[7:0] is valid when only one byte of data is read +out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS +2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/ +#define SPI_MEM_PESR_END_MSK 0x0000FFFF +#define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) +#define SPI_MEM_PESR_END_MSK_V 0xFFFF +#define SPI_MEM_PESR_END_MSK_S 6 +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable Auto-suspending function..*/ +#define SPI_MEM_FLASH_PES_EN (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 5 +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a +pplication should send PER after PES is done..*/ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase suspend command is sent. 0: SPI1 does not wait after program erase + suspend command is sent..*/ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase resume command is sent. 0: SPI1 does not wait after program erase +resume command is sent..*/ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program erase suspend bit, program erase suspend operation will be triggered whe +n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +isable..*/ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 +/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: program erase resume bit, program erase suspend operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: di +sable..*/ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) +/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS +/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash +..*/ +#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF +#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) +#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF +#define SPI_MEM_WAIT_PESR_COMMAND_S 16 +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */ +/*description: Program/Erase suspend command..*/ +#define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PES_COMMAND_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */ +/*description: Program/Erase resume command..*/ +#define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PER_COMMAND_S 16 +/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng +th of Program/Erase Suspend/Resume command is 8..*/ +#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1 +#define SPI_MEM_FLASH_PESR_CMD_2B_S 15 +/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/ +#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_V 0x1 +#define SPI_MEM_SPI0_LOCK_EN_S 7 +/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ +#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_128_S 6 +/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ +#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_128_S 5 +/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com +mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles +after DP command is sent..*/ +#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_128_S 4 +/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after RES command is sent..*/ +#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_128_S 3 +/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after HPM command is sent..*/ +#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_128_S 2 +/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/ +#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 +#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status of flash suspend, only used in SPI1..*/ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) +/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ENA_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_V 0x1 +#define SPI_MEM_WPE_END_INT_ENA_S 2 +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 + +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) +/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_CLR_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_V 0x1 +#define SPI_MEM_WPE_END_INT_CLR_S 2 +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 + +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) +/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that +chip is loosing power and RTC module sends out brown out close flash request to +SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + and MSPI returns to idle state. 0: Others..*/ +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_RAW_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr +ite flash request is received. 0: Others..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read +address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access +is rejected. 0: Others..*/ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s +et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error + times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM +. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t +his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq +ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP +I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times +of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E +RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare +d, this bit will not be triggered..*/ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st +is changed from non idle state to idle state. 0: Others..*/ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st +is changed from non idle state to idle state. It means that SPI_CS raises high. +0: Others.*/ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C +E is sent and flash is already idle. 0: Others..*/ +#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_V 0x1 +#define SPI_MEM_WPE_END_INT_RAW_S 2 +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com +mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com +mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 + +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) +/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ST_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_V 0x1 +#define SPI_MEM_WPE_END_INT_ST_S 2 +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) +/* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ +#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_FMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} +..*/ +#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ +#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_FMEM_DQS_CA_IN_S 26 +/* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to flash..*/ +#define SPI_MEM_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to flash..*/ +#define SPI_MEM_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the panda device..*/ +#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_FMEM_OUTMINBYTELEN_M ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_FMEM_VAR_DUMMY_S 1 +/* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD8) +/* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 +]}..*/ +#define SPI_MEM_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] +, 1'b0}..*/ +#define SPI_MEM_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ +#define SPI_MEM_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to external RAM..*/ +#define SPI_MEM_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to external RAM..*/ +#define SPI_MEM_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the DDR psram..*/ +#define SPI_MEM_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS0_ECC_S 2 +/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS0_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS1_ECC_S 2 +/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS1_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS2_ECC_S 2 +/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS2_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) +/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS3_ECC_S 2 +/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS3_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) +/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS0_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS0_ADDR_S_M ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS0_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS0_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) +/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS1_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS1_ADDR_S_M ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS1_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS1_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) +/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS2_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS2_ADDR_S_M ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS2_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS2_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) +/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS3_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS3_ADDR_S_M ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS3_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS3_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS0_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS0_SIZE_M ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S)) +#define SPI_MEM_FMEM_PMS0_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS0_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) +/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS1_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS1_SIZE_M ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S)) +#define SPI_MEM_FMEM_PMS1_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS1_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) +/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS2_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS2_SIZE_M ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S)) +#define SPI_MEM_FMEM_PMS2_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS2_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12C) +/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS3_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS3_SIZE_M ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S)) +#define SPI_MEM_FMEM_PMS3_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS3_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) +/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS0_ECC_S 2 +/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS0_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) +/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS1_ECC_S 2 +/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS1_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) +/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS2_ECC_S 2 +/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS2_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13C) +/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS3_ECC_S 2 +/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS3_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) +/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS0_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS0_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS0_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) +/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS1_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS1_ADDR_S_M ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS1_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS1_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) +/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS2_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS2_ADDR_S_M ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS2_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS2_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14C) +/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS3_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS3_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS3_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) +/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS0_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS0_SIZE_M ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S)) +#define SPI_MEM_SMEM_PMS0_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS0_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) +/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS1_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS1_SIZE_M ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S)) +#define SPI_MEM_SMEM_PMS1_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS1_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) +/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS2_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS2_SIZE_M ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S)) +#define SPI_MEM_SMEM_PMS2_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS2_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15C) +/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS3_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS3_SIZE_M ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S)) +#define SPI_MEM_SMEM_PMS3_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS3_SIZE_S 0 + +#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (BIT(31)) +#define SPI_MEM_PMS_IVD_V 0x1 +#define SPI_MEM_PMS_IVD_S 31 +/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It + is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_V 0x1 +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (BIT(29)) +#define SPI_MEM_PMS_ST_V 0x1 +#define SPI_MEM_PMS_ST_S 29 +/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI +_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (BIT(28)) +#define SPI_MEM_PMS_LD_V 0x1 +#define SPI_MEM_PMS_LD_S 28 +/* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0/1 transfer permission control function..*/ +#define SPI_MEM_PM_EN (BIT(26)) +#define SPI_MEM_PM_EN_M (BIT(26)) +#define SPI_MEM_PM_EN_V 0x1 +#define SPI_MEM_PM_EN_S 26 +/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_REJECT_ADDR 0x03FFFFFF +#define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S)) +#define SPI_MEM_REJECT_ADDR_V 0x3FFFFFF +#define SPI_MEM_REJECT_ADDR_S 0 + +#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) +/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */ +/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding + to byte 0 bit 0 to byte 15 bit 7).*/ +#define SPI_MEM_ECC_ERR_BITS 0x0000007F +#define SPI_MEM_ECC_ERR_BITS_M ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S)) +#define SPI_MEM_ECC_ERR_BITS_V 0x7F +#define SPI_MEM_ECC_ERR_BITS_S 25 +/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd +ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD +R record the first ECC error information..*/ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1 +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_USR_ECC_ADDR_EN_S 21 +/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of flash. If there is no ECC region in flash, th +is bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_FMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_FMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_FMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: +1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_FMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_FMEM_PAGE_SIZE_M ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S)) +#define SPI_MEM_FMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_FMEM_PAGE_SIZE_S 18 +/* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas +h..*/ +#define SPI_MEM_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S 17 +/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */ +/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr +upt..*/ +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM 0x0000003F +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S)) +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V 0x3F +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S 11 + +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16C) +/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */ +/*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_CNT 0x0000003F +#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) +#define SPI_MEM_ECC_ERR_CNT_V 0x3F +#define SPI_MEM_ECC_ERR_CNT_S 26 +/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_ADDR 0x03FFFFFF +#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) +#define SPI_MEM_ECC_ERR_ADDR_V 0x3FFFFFF +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) +/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO +and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31)) +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1 +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 +/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_WBLEN_AFIFO_REMPTY_M (BIT(30)) +#define SPI_MEM_WBLEN_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_WBLEN_AFIFO_REMPTY_S 30 +/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */ +/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_WDATA_AFIFO_REMPTY_M (BIT(29)) +#define SPI_MEM_WDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_WDATA_AFIFO_REMPTY_S 29 +/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */ +/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_RADDR_AFIFO_REMPTY_M (BIT(28)) +#define SPI_MEM_RADDR_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_RADDR_AFIFO_REMPTY_S 28 +/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_RDATA_AFIFO_REMPTY_M (BIT(27)) +#define SPI_MEM_RDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_RDATA_AFIFO_REMPTY_S 27 +/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + and SPI0 transfers are done. 0: Others..*/ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 +/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits show the first AXI write/read invalid error or AXI write flash error a +ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS +H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ +#define SPI_MEM_AXI_ERR_ADDR 0x03FFFFFF +#define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) +#define SPI_MEM_AXI_ERR_ADDR_V 0x3FFFFFF +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) +/* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of external RAM. If there is no ECC region in ex +ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_SMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_SMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */ +/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt +es. 2: 1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_SMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_SMEM_PAGE_SIZE_M ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S)) +#define SPI_MEM_SMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_SMEM_PAGE_SIZE_S 18 +/* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte +rnal RAM..*/ +#define SPI_MEM_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S 17 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x1 +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 +/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f +lash..*/ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable timing auto-calibration for all reading operations..*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable timing adjust clock for all reading operations..*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C) +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_DOUTS_MODE_S 8 +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) +/* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E +XT_RAM..*/ +#define SPI_MEM_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_SMEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_SMEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_SMEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper +ations..*/ +#define SPI_MEM_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SMEM_TIMING_CALI_S 1 +/* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio +ns..*/ +#define SPI_MEM_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SMEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) +/* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SMEM_DINS_MODE_M ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S)) +#define SPI_MEM_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SMEM_DINS_MODE_S 24 +/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN7_MODE_M ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN7_MODE_S 21 +/* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN6_MODE_M ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN6_MODE_S 18 +/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN5_MODE_M ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN5_MODE_S 15 +/* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN4_MODE_M ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN4_MODE_S 12 +/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN3_MODE_M ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN3_MODE_S 9 +/* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN2_MODE_M ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN2_MODE_S 6 +/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN1_MODE_M ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN1_MODE_S 3 +/* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN0_MODE_M ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) +/* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SMEM_DINS_NUM_M ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S)) +#define SPI_MEM_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SMEM_DINS_NUM_S 16 +/* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN7_NUM_M ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN7_NUM_S 14 +/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN6_NUM_M ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN6_NUM_S 12 +/* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN5_NUM_M ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN5_NUM_S 10 +/* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN4_NUM_M ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN4_NUM_S 8 +/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN3_NUM_M ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN3_NUM_S 6 +/* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN2_NUM_M ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN2_NUM_S 4 +/* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN1_NUM_M ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN1_NUM_S 2 +/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN0_NUM_M ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19C) +/* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUTS_MODE_S 8 +/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT7_MODE_S 7 +/* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT6_MODE_S 6 +/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT5_MODE_S 5 +/* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT4_MODE_S 4 +/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT3_MODE_S 3 +/* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT2_MODE_S 2 +/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT1_MODE_S 1 +/* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0) +/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt +er whether there is an ECC region or not..*/ +#define SPI_MEM_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M (BIT(31)) +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S 31 +/* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M +SPI core clock cycles..*/ +#define SPI_MEM_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SMEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses external RAM..*/ +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S 16 +/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh +en accesses external RAM..*/ +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c +ycles in ECC mode when accessed external RAM..*/ +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S 12 +/* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */ +/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a +re combined with spi_mem_cs_hold bit..*/ +#define SPI_MEM_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SMEM_CS_HOLD_TIME_S 7 +/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */ +/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s +pi_mem_cs_setup bit..*/ +#define SPI_MEM_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SMEM_CS_SETUP_TIME_S 2 +/* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab +le..*/ +#define SPI_MEM_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SMEM_CS_HOLD_S 1 +/* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d +isable..*/ +#define SPI_MEM_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* SPI_MEM_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define SPI_MEM_XTS_PLAIN 0xFFFFFFFF +#define SPI_MEM_XTS_PLAIN_M ((SPI_MEM_XTS_PLAIN_V)<<(SPI_MEM_XTS_PLAIN_S)) +#define SPI_MEM_XTS_PLAIN_V 0xFFFFFFFF +#define SPI_MEM_XTS_PLAIN_S 0 + +#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* SPI_MEM_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define SPI_MEM_XTS_LINESIZE 0x00000003 +#define SPI_MEM_XTS_LINESIZE_M ((SPI_MEM_XTS_LINESIZE_V)<<(SPI_MEM_XTS_LINESIZE_S)) +#define SPI_MEM_XTS_LINESIZE_V 0x3 +#define SPI_MEM_XTS_LINESIZE_S 0 + +#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* SPI_MEM_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryptio +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define SPI_MEM_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_XTS_DESTINATION_M (BIT(0)) +#define SPI_MEM_XTS_DESTINATION_V 0x1 +#define SPI_MEM_XTS_DESTINATION_S 0 + +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* SPI_MEM_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS 0x03FFFFFF +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_XTS_PHYSICAL_ADDRESS_S)) +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_S 0 + +#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* SPI_MEM_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryptio +n status becomes 2..*/ +#define SPI_MEM_XTS_TRIGGER (BIT(0)) +#define SPI_MEM_XTS_TRIGGER_M (BIT(0)) +#define SPI_MEM_XTS_TRIGGER_V 0x1 +#define SPI_MEM_XTS_TRIGGER_S 0 + +#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* SPI_MEM_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define SPI_MEM_XTS_RELEASE (BIT(0)) +#define SPI_MEM_XTS_RELEASE_M (BIT(0)) +#define SPI_MEM_XTS_RELEASE_V 0x1 +#define SPI_MEM_XTS_RELEASE_S 0 + +#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* SPI_MEM_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define SPI_MEM_XTS_DESTROY (BIT(0)) +#define SPI_MEM_XTS_DESTROY_M (BIT(0)) +#define SPI_MEM_XTS_DESTROY_V 0x1 +#define SPI_MEM_XTS_DESTROY_S 0 + +#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* SPI_MEM_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define SPI_MEM_XTS_STATE 0x00000003 +#define SPI_MEM_XTS_STATE_M ((SPI_MEM_XTS_STATE_V)<<(SPI_MEM_XTS_STATE_S)) +#define SPI_MEM_XTS_STATE_V 0x3 +#define SPI_MEM_XTS_STATE_S 0 + +#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* SPI_MEM_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define SPI_MEM_XTS_DATE 0x3FFFFFFF +#define SPI_MEM_XTS_DATE_M ((SPI_MEM_XTS_DATE_V)<<(SPI_MEM_XTS_DATE_S)) +#define SPI_MEM_XTS_DATE_V 0x3FFFFFFF +#define SPI_MEM_XTS_DATE_S 0 + +#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C) +/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: MSPI-MMU item content.*/ +#define SPI_MEM_MMU_ITEM_CONTENT 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_CONTENT_M ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S)) +#define SPI_MEM_MMU_ITEM_CONTENT_V 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_CONTENT_S 0 + +#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) +/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: MSPI-MMU item index.*/ +#define SPI_MEM_MMU_ITEM_INDEX 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_INDEX_M ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S)) +#define SPI_MEM_MMU_ITEM_INDEX_V 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_INDEX_S 0 + +#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) +/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/ +#define SPI_MEM_RDN_RESULT (BIT(31)) +#define SPI_MEM_RDN_RESULT_M (BIT(31)) +#define SPI_MEM_RDN_RESULT_V 0x1 +#define SPI_MEM_RDN_RESULT_S 31 +/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: ECO register enable bit.*/ +#define SPI_MEM_RDN_ENA (BIT(30)) +#define SPI_MEM_RDN_ENA_M (BIT(30)) +#define SPI_MEM_RDN_ENA_V 0x1 +#define SPI_MEM_RDN_ENA_S 30 +/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */ +/*description: MMU PSRAM aux control register.*/ +#define SPI_MEM_AUX_CTRL 0x00003FFF +#define SPI_MEM_AUX_CTRL_M ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S)) +#define SPI_MEM_AUX_CTRL_V 0x3FFF +#define SPI_MEM_AUX_CTRL_S 16 +/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/ +#define SPI_MEM_MMU_PAGE_SIZE 0x00000003 +#define SPI_MEM_MMU_PAGE_SIZE_M ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S)) +#define SPI_MEM_MMU_PAGE_SIZE_V 0x3 +#define SPI_MEM_MMU_PAGE_SIZE_S 3 +/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be + controlled by rtc..*/ +#define SPI_MEM_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_MMU_MEM_FORCE_PU_M (BIT(2)) +#define SPI_MEM_MMU_MEM_FORCE_PU_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_PU_S 2 +/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to force mmu-memory powerdown.*/ +#define SPI_MEM_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_MMU_MEM_FORCE_PD_M (BIT(1)) +#define SPI_MEM_MMU_MEM_FORCE_PD_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_PD_S 1 +/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable mmu-memory clock force on.*/ +#define SPI_MEM_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_MMU_MEM_FORCE_ON_M (BIT(0)) +#define SPI_MEM_MMU_MEM_FORCE_ON_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_ON_S 0 + +#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* SPI_MEM_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_S 4 +/* SPI_MEM_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define SPI_MEM_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_V 0x1 +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_S 3 +/* SPI_MEM_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define SPI_MEM_CRYPT_SECURITY_LEVEL 0x00000007 +#define SPI_MEM_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_CRYPT_SECURITY_LEVEL_S)) +#define SPI_MEM_CRYPT_SECURITY_LEVEL_V 0x7 +#define SPI_MEM_CRYPT_SECURITY_LEVEL_S 0 + +#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0) +/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO high register.*/ +#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S)) +#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 + +#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F4) +/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO low register.*/ +#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_M ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S)) +#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2203030 ; */ +/*description: SPI0 register version..*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/spi_mem_struct.h b/components/soc/esp32h2/include/soc/spi_mem_struct.h new file mode 100644 index 0000000000..9557848458 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_mem_struct.h @@ -0,0 +1,1076 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +typedef volatile struct spi_mem_dev_s { + union { + struct { + uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/ + uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/ + uint32_t reserved8 : 9; /*reserved*/ + uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */ + uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + }; + uint32_t val; + } cmd; + uint32_t addr; + union { + struct { + uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t fdummy_rin : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/ + uint32_t fdummy_wout : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/ + uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ + uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ + uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ + uint32_t reserved7 : 1; /*reserved*/ + uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12 : 1; /*reserved*/ + uint32_t fastrd_mode : 1; /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ + uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ + uint32_t reserved16 : 2; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/ + uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */ + uint32_t wrsr_2b : 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */ + uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t reserved25 : 5; /*reserved*/ + uint32_t dqs_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t data_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ + uint32_t reserved2 : 9; /*reserved*/ + uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_axi_rdata_back_fast : 1; /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/ + uint32_t rresp_ecc_err_en : 1; /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/ + uint32_t ar_splice_en : 1; /*Set this bit to enable AXI Read Splice-transfer.*/ + uint32_t aw_splice_en : 1; /*Set this bit to enable AXI Write Splice-transfer.*/ + uint32_t ram0_en : 1; /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t dual_ram_en : 1; /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t fast_write_en : 1; /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.*/ + uint32_t rxfifo_rst : 1; /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO.*/ + uint32_t txfifo_rst : 1; /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/ + uint32_t cs_hold_time : 5; /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/ + uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/ + uint32_t ecc_skip_page_corner : 1; /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ + uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ + uint32_t reserved15 : 9; /*reserved*/ + uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset : 1; /*The spi0_mst_st and spi0_slv_st will be reset.*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. */ + uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */ + uint32_t clk_equ_sysclk : 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reserved8 : 1; /*reserved*/ + uint32_t ck_out_edge : 1; /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t reserved16 : 8; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t usr_dbytelen : 3; /*SPI0 USR_CMD read or write data byte length -1*/ + uint32_t reserved9 : 17; /*reserved*/ + uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value : 16; /*The value of command.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_bit_len : 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + union { + struct { + uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ + uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t reserved24 : 8; /*reserved*/ + }; + uint32_t val; + } rd_status; + uint32_t reserved_30; + union { + struct { + uint32_t cs0_dis : 1; /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t reserved0 : 5; /*reserved*/ + uint32_t fsub_pin : 1; /*For SPI0, flash is connected to SUBPINs.*/ + uint32_t ssub_pin : 1; /*For SPI0, sram is connected to SUBPINs.*/ + uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ + uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } misc; + uint32_t tx_crc; + union { + struct { + uint32_t axi_req_en : 1; /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/ + uint32_t usr_addr_4byte : 1; /*For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.*/ + uint32_t flash_usr_cmd : 1; /*For SPI0, cache read flash for user define command, 1: enable, 0:disable.*/ + uint32_t fdin_dual : 1; /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdout_dual : 1; /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t faddr_dual : 1; /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t fdout_quad : 1; /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t reserved9 : 21; /*reserved*/ + uint32_t reg_same_aw_ar_addr_chk_en : 1; /*Set this bit to check AXI read/write the same address region.*/ + uint32_t reg_close_axi_inf_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t usr_saddr_4byte : 1; /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/ + uint32_t usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_wr_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/ + uint32_t sram_usr_rcmd : 1; /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/ + uint32_t sram_rdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved12 : 2; /*reserved*/ + uint32_t sram_addr_bitlen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/ + uint32_t sram_oct : 1; /*reserved*/ + uint32_t sram_wdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ + uint32_t swb_mode : 8; /*Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t sdin_dual : 1; /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t sdout_dual : 1; /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t saddr_dual : 1; /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t reserved13 : 1; /*reserved*/ + uint32_t sdin_quad : 1; /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdout_quad : 1; /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t saddr_quad : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t scmd_quad : 1; /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdin_oct : 1; /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdout_oct : 1; /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */ + uint32_t saddr_oct : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */ + uint32_t scmd_oct : 1; /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdummy_rin : 1; /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t sdummy_wout : 1; /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t reg_smem_wdummy_dqs_always_out: 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t reg_smem_wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t reserved26 : 4; /*reserved*/ + uint32_t reg_smem_dqs_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t reg_smem_data_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t sram_usr_rd_cmd_value : 16; /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_rd_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t sram_usr_wr_cmd_value : 16; /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_wr_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t sclkcnt_l : 8; /*For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.*/ + uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t sclkcnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*reserved*/ + uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + }; + uint32_t val; + } sram_clk; + union { + struct { + uint32_t reserved0 : 7; /*reserved*/ + uint32_t lock_delay_time : 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } fsm; + uint32_t data_buf[16]; + union { + struct { + uint32_t waiti_en : 1; /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/ + uint32_t waiti_dummy : 1; /*The dummy phase enable when wait flash idle (RDSR)*/ + uint32_t waiti_addr_en : 1; /*1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/ + uint32_t waiti_addr_cyclelen : 2; /*When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/ + uint32_t reserved5 : 4; /*reserved*/ + uint32_t waiti_cmd_2b : 1; /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/ + uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/ + uint32_t waiti_cmd : 16; /*The command value to wait flash idle(RDSR).*/ + }; + uint32_t val; + } flash_waiti_ctrl; + union { + struct { + uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_per_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */ + uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */ + uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/ + uint32_t flash_pes_en : 1; /*Set this bit to enable Auto-suspending function.*/ + uint32_t pesr_end_msk : 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ + uint32_t frd_sus_2b : 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ + uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ + uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ + uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/ + }; + uint32_t val; + } flash_sus_ctrl; + union { + struct { + uint32_t flash_pes_command : 16; /*Program/Erase suspend command.*/ + uint32_t wait_pesr_command : 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ + }; + uint32_t val; + } flash_sus_cmd; + union { + struct { + uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/ + uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/ + uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ + uint32_t flash_res_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ + uint32_t flash_dp_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ + uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ + uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ + uint32_t spi0_lock_en : 1; /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/ + uint32_t reserved8 : 7; /*reserved*/ + uint32_t flash_pesr_cmd_2b : 1; /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/ + uint32_t flash_per_command : 16; /*Program/Erase resume command.*/ + }; + uint32_t val; + } sus_status; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + union { + struct { + uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end_en : 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject_en : 1; /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err_en : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t per_end : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t per_end : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ + uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ + uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ + uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ + uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/ + uint32_t ecc_err : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ + uint32_t pms_reject : 1; /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/ + uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ + uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t per_end : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_st; + uint32_t reserved_d0; + union { + struct { + uint32_t reg_fmem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t reg_fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t reg_fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t reg_fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t reg_fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t reg_fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ + uint32_t reg_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/ + uint32_t reg_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/ + uint32_t reg_fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t reg_fmem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t reg_fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t reg_fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t reg_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t reg_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ + uint32_t reg_fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t reg_fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } ddr; + union { + struct { + uint32_t reg_smem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t reg_smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t reg_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t reg_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t reg_smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t reg_smem_outminbytelen : 7; /*It is the minimum output data length in the DDR psram.*/ + uint32_t reg_smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/ + uint32_t reg_smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/ + uint32_t reg_smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t reg_smem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t reg_smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t reg_smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t reg_smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t reg_smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ + uint32_t reg_smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t reg_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } spi_smem_ddr; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + union { + struct { + uint32_t reg_fmem_pms0_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms0_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms0_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_attr; + union { + struct { + uint32_t reg_fmem_pms1_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms1_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms1_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_attr; + union { + struct { + uint32_t reg_fmem_pms2_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms2_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms2_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_attr; + union { + struct { + uint32_t reg_fmem_pms3_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms3_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms3_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_attr; + union { + struct { + uint32_t reg_fmem_pms0_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_addr; + union { + struct { + uint32_t reg_fmem_pms1_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_addr; + union { + struct { + uint32_t reg_fmem_pms2_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_addr; + union { + struct { + uint32_t reg_fmem_pms3_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_addr; + union { + struct { + uint32_t reg_fmem_pms0_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_size; + union { + struct { + uint32_t reg_fmem_pms1_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_size; + union { + struct { + uint32_t reg_fmem_pms2_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_size; + union { + struct { + uint32_t reg_fmem_pms3_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_size; + union { + struct { + uint32_t reg_smem_pms0_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms0_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms0_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_attr; + union { + struct { + uint32_t reg_smem_pms1_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms1_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms1_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_attr; + union { + struct { + uint32_t reg_smem_pms2_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms2_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms2_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_attr; + union { + struct { + uint32_t reg_smem_pms3_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms3_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms3_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_attr; + union { + struct { + uint32_t reg_smem_pms0_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_addr; + union { + struct { + uint32_t reg_smem_pms1_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_addr; + union { + struct { + uint32_t reg_smem_pms2_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_addr; + union { + struct { + uint32_t reg_smem_pms3_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_addr; + union { + struct { + uint32_t reg_smem_pms0_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_size; + union { + struct { + uint32_t reg_smem_pms1_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_size; + union { + struct { + uint32_t reg_smem_pms2_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_size; + union { + struct { + uint32_t reg_smem_pms3_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_size; + uint32_t reserved_160; + union { + struct { + uint32_t reject_addr : 26; /*This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/ + uint32_t reserved27 : 1; /*reserved*/ + uint32_t pms_ld : 1; /*1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_st : 1; /*1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_multi_hit : 1; /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_ivd : 1; /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + }; + uint32_t val; + } pms_reject; + union { + struct { + uint32_t reserved0 : 11; /*reserved*/ + uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t reg_fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/ + uint32_t reg_fmem_page_size : 2; /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reg_fmem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t usr_ecc_addr_en : 1; /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/ + uint32_t ecc_err_bits : 7; /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/ + }; + uint32_t val; + } ecc_ctrl; + union { + struct { + uint32_t ecc_err_addr : 26; /*This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t ecc_err_cnt : 6; /*This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + }; + uint32_t val; + } ecc_err_addr; + union { + struct { + uint32_t axi_err_addr : 26; /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ + uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/ + uint32_t reg_rdata_afifo_rempty : 1; /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_raddr_afifo_rempty : 1; /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_wdata_afifo_rempty : 1; /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_wblen_afifo_rempty : 1; /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_all_axi_trans_afifo_empty : 1; /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/ + }; + uint32_t val; + } axi_err_addr; + union { + struct { + uint32_t reserved0 : 17; /*reserved*/ + uint32_t reg_smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/ + uint32_t reg_smem_page_size : 2; /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reg_smem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } spi_smem_ecc_ctrl; + uint32_t reserved_178; + uint32_t reserved_17c; + union { + struct { + uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/ + uint32_t timing_cali_update : 1; /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/ + uint32_t reserved7 : 25; /*reserved*/ + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } dout_mode; + union { + struct { + uint32_t reg_smem_timing_clk_ena : 1; /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t reg_smem_timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t reg_smem_extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reg_smem_dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/ + uint32_t reserved6 : 26; /*reserved*/ + }; + uint32_t val; + } spi_smem_timing_cali; + union { + struct { + uint32_t reg_smem_din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_mode; + union { + struct { + uint32_t reg_smem_din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_dins_num : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_num; + union { + struct { + uint32_t reg_smem_dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_mode; + union { + struct { + uint32_t reg_smem_cs_setup : 1; /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reg_smem_cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t reg_smem_cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t reg_smem_cs_hold_time : 5; /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t reg_smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/ + uint32_t reg_smem_ecc_skip_page_corner : 1; /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/ + uint32_t reg_smem_ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/ + uint32_t reserved17 : 8; /*reserved*/ + uint32_t reg_smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t reg_smem_split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + }; + uint32_t val; + } spi_smem_ac; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + union { + struct { + uint32_t reg_clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t xts_plain_base; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + union { + struct { + uint32_t reg_xts_linesize : 2; /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_linesize; + union { + struct { + uint32_t reg_xts_destination : 1; /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destination; + union { + struct { + uint32_t reg_xts_physical_address : 26; /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } xts_physical_address; + union { + struct { + uint32_t reg_xts_trigger : 1; /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_trigger; + union { + struct { + uint32_t reg_xts_release : 1; /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_release; + union { + struct { + uint32_t reg_xts_destroy : 1; /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destroy; + union { + struct { + uint32_t reg_xts_state : 2; /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_state; + union { + struct { + uint32_t reg_xts_date : 30; /*This bits stores the last modified-time of manual encryption feature.*/ + uint32_t reserved30 : 2; /*reserved*/ + }; + uint32_t val; + } xts_date; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t mmu_item_content; + uint32_t mmu_item_index; + union { + struct { + uint32_t reg_mmu_mem_force_on : 1; /*Set this bit to enable mmu-memory clock force on*/ + uint32_t reg_mmu_mem_force_pd : 1; /*Set this bit to force mmu-memory powerdown*/ + uint32_t reg_mmu_mem_force_pu : 1; /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/ + uint32_t reg_mmu_page_size : 2; /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/ + uint32_t reserved5 : 11; /*reserved*/ + uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/ + uint32_t rdn_ena : 1; /*ECO register enable bit*/ + uint32_t rdn_result : 1; /*MSPI module clock domain and AXI clock domain ECO register result register*/ + }; + uint32_t val; + } mmu_power_ctrl; + union { + struct { + uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ + uint32_t reg_crypt_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ + uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } dpa_ctrl; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t spi_memisterrnd_eco_high; + uint32_t spi_memisterrnd_eco_low; + uint32_t reserved_3f8; + union { + struct { + uint32_t date : 28; /*SPI0 register version.*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_mem_dev_t; +extern spi_mem_dev_t SPIMEM0; +extern spi_mem_dev_t SPIMEM1; +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/spi_pins.h b/components/soc/esp32h2/include/soc/spi_pins.h new file mode 100644 index 0000000000..0921353333 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_pins.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_SPI_PINS_H_ +#define _SOC_SPI_PINS_H_ + +#define SPI_FUNC_NUM 0 +#define SPI_IOMUX_PIN_NUM_HD 12 +#define SPI_IOMUX_PIN_NUM_CS 14 +#define SPI_IOMUX_PIN_NUM_MOSI 16 +#define SPI_IOMUX_PIN_NUM_CLK 15 +#define SPI_IOMUX_PIN_NUM_MISO 17 +#define SPI_IOMUX_PIN_NUM_WP 13 + +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 10 + +#endif diff --git a/components/soc/esp32h2/include/soc/spi_reg.h b/components/soc/esp32h2/include/soc/spi_reg.h new file mode 100644 index 0000000000..126b6b5324 --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_reg.h @@ -0,0 +1,2114 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_CMD_REG register + * Command control register + */ +#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0) +/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ +#define SPI_CONF_BITLEN 0x0003FFFFU +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFFU +#define SPI_CONF_BITLEN_S 0 +/** SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001U +#define SPI_UPDATE_S 23 +/** SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001U +#define SPI_USR_S 24 + +/** SPI_ADDR_REG register + * Address value register + */ +#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4) +/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_S 0 + +/** SPI_CTRL_REG register + * SPI control register + */ +#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8) +/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001U +#define SPI_DUMMY_OUT_S 3 +/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001U +#define SPI_FADDR_DUAL_S 5 +/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001U +#define SPI_FADDR_QUAD_S 6 +/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001U +#define SPI_FADDR_OCT_S 7 +/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001U +#define SPI_FCMD_DUAL_S 8 +/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001U +#define SPI_FCMD_QUAD_S 9 +/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001U +#define SPI_FCMD_OCT_S 10 +/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001U +#define SPI_FREAD_DUAL_S 14 +/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001U +#define SPI_FREAD_QUAD_S 15 +/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001U +#define SPI_FREAD_OCT_S 16 +/** SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001U +#define SPI_Q_POL_S 18 +/** SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001U +#define SPI_D_POL_S 19 +/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001U +#define SPI_HOLD_POL_S 20 +/** SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001U +#define SPI_WP_POL_S 21 +/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ +#define SPI_RD_BIT_ORDER 0x00000003U +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000003U +#define SPI_RD_BIT_ORDER_S 23 +/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ +#define SPI_WR_BIT_ORDER 0x00000003U +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000003U +#define SPI_WR_BIT_ORDER_S 25 + +/** SPI_CLOCK_REG register + * SPI clock control register + */ +#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc) +/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_L 0x0000003FU +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003FU +#define SPI_CLKCNT_L_S 0 +/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_H 0x0000003FU +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003FU +#define SPI_CLKCNT_H_S 6 +/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ +#define SPI_CLKCNT_N 0x0000003FU +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003FU +#define SPI_CLKCNT_N_S 12 +/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ +#define SPI_CLKDIV_PRE 0x0000000FU +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000FU +#define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_CLK_EQU_SYSCLK_S 31 + +/** SPI_USER_REG register + * SPI USER control register + */ +#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10) +/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001U +#define SPI_DOUTDIN_S 0 +/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001U +#define SPI_QPI_MODE_S 3 +/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001U +#define SPI_OPI_MODE_S 4 +/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001U +#define SPI_TSCK_I_EDGE_S 5 +/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001U +#define SPI_CS_HOLD_S 6 +/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001U +#define SPI_CS_SETUP_S 7 +/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001U +#define SPI_RSCK_I_EDGE_S 8 +/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001U +#define SPI_CK_OUT_EDGE_S 9 +/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001U +#define SPI_FWRITE_DUAL_S 12 +/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001U +#define SPI_FWRITE_QUAD_S 13 +/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001U +#define SPI_FWRITE_OCT_S 14 +/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001U +#define SPI_USR_CONF_NXT_S 15 +/** SPI_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001U +#define SPI_SIO_S 17 +/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_USR_MISO_HIGHPART_S 24 +/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_USR_MOSI_HIGHPART_S 25 +/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_USR_DUMMY_IDLE_S 26 +/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001U +#define SPI_USR_MOSI_S 27 +/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001U +#define SPI_USR_MISO_S 28 +/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001U +#define SPI_USR_DUMMY_S 29 +/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001U +#define SPI_USR_ADDR_S 30 +/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001U +#define SPI_USR_COMMAND_S 31 + +/** SPI_USER1_REG register + * SPI USER control register 1 + */ +#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14) +/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001U +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ +#define SPI_CS_SETUP_TIME 0x0000001FU +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001FU +#define SPI_CS_SETUP_TIME_S 17 +/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ +#define SPI_CS_HOLD_TIME 0x0000001FU +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001FU +#define SPI_CS_HOLD_TIME_S 22 +/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_ADDR_BITLEN 0x0000001FU +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001FU +#define SPI_USR_ADDR_BITLEN_S 27 + +/** SPI_USER2_REG register + * SPI USER control register 2 + */ +#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18) +/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_S 0 +/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_S 28 + +/** SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c) +/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ +#define SPI_MS_DATA_BITLEN 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_S 0 + +/** SPI_MISC_REG register + * SPI misc register + */ +#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20) +/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001U +#define SPI_CS0_DIS_S 0 +/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001U +#define SPI_CS1_DIS_S 1 +/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001U +#define SPI_CS2_DIS_S 2 +/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001U +#define SPI_CS3_DIS_S 3 +/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001U +#define SPI_CS4_DIS_S 4 +/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001U +#define SPI_CS5_DIS_S 5 +/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001U +#define SPI_CK_DIS_S 6 +/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ +#define SPI_MASTER_CS_POL 0x0000003FU +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003FU +#define SPI_MASTER_CS_POL_S 7 +/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S) +#define SPI_CLK_DATA_DTR_EN_V 0x00000001U +#define SPI_CLK_DATA_DTR_EN_S 16 +/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S) +#define SPI_DATA_DTR_EN_V 0x00000001U +#define SPI_DATA_DTR_EN_S 17 +/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S) +#define SPI_ADDR_DTR_EN_V 0x00000001U +#define SPI_ADDR_DTR_EN_S 18 +/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S) +#define SPI_CMD_DTR_EN_V 0x00000001U +#define SPI_CMD_DTR_EN_S 19 +/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001U +#define SPI_SLAVE_CS_POL_S 23 +/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001U +#define SPI_DQS_IDLE_EDGE_S 24 +/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001U +#define SPI_CK_IDLE_EDGE_S 29 +/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_CS_KEEP_ACTIVE_S 30 +/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001U +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/** SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24) +/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN0_MODE 0x00000003U +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003U +#define SPI_DIN0_MODE_S 0 +/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN1_MODE 0x00000003U +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003U +#define SPI_DIN1_MODE_S 2 +/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN2_MODE 0x00000003U +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003U +#define SPI_DIN2_MODE_S 4 +/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN3_MODE 0x00000003U +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003U +#define SPI_DIN3_MODE_S 6 +/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN4_MODE 0x00000003U +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000003U +#define SPI_DIN4_MODE_S 8 +/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the + * (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, + * 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle. Can be configured in CONF state. + */ +#define SPI_DIN5_MODE 0x00000003U +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000003U +#define SPI_DIN5_MODE_S 10 +/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the + * (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, + * 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle. Can be configured in CONF state. + */ +#define SPI_DIN6_MODE 0x00000003U +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000003U +#define SPI_DIN6_MODE_S 12 +/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the + * (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, + * 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle. Can be configured in CONF state. + */ +#define SPI_DIN7_MODE 0x00000003U +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000003U +#define SPI_DIN7_MODE_S 14 +/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001U +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/** SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28) +/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN0_NUM 0x00000003U +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003U +#define SPI_DIN0_NUM_S 0 +/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN1_NUM 0x00000003U +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003U +#define SPI_DIN1_NUM_S 2 +/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN2_NUM 0x00000003U +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003U +#define SPI_DIN2_NUM_S 4 +/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN3_NUM 0x00000003U +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003U +#define SPI_DIN3_NUM_S 6 +/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN4_NUM 0x00000003U +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003U +#define SPI_DIN4_NUM_S 8 +/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN5_NUM 0x00000003U +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003U +#define SPI_DIN5_NUM_S 10 +/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN6_NUM 0x00000003U +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003U +#define SPI_DIN6_NUM_S 12 +/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN7_NUM 0x00000003U +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003U +#define SPI_DIN7_NUM_S 14 + +/** SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c) +/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001U +#define SPI_DOUT0_MODE_S 0 +/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001U +#define SPI_DOUT1_MODE_S 1 +/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001U +#define SPI_DOUT2_MODE_S 2 +/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001U +#define SPI_DOUT3_MODE_S 3 +/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000001U +#define SPI_DOUT4_MODE_S 4 +/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000001U +#define SPI_DOUT5_MODE_S 5 +/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000001U +#define SPI_DOUT6_MODE_S 6 +/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000001U +#define SPI_DOUT7_MODE_S 7 +/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000001U +#define SPI_D_DQS_MODE_S 8 + +/** SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30) +/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_S 0 +/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_S 1 +/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001U +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001U +#define SPI_RX_EOF_EN_S 21 +/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001U +#define SPI_DMA_RX_ENA_S 27 +/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001U +#define SPI_DMA_TX_ENA_S 28 +/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001U +#define SPI_RX_AFIFO_RST_S 29 +/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001U +#define SPI_BUF_AFIFO_RST_S 30 +/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001U +#define SPI_DMA_AFIFO_RST_S 31 + +/** SPI_DMA_INT_ENA_REG register + * SPI interrupt enable register + */ +#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD7_INT_ENA_S 4 +/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD8_INT_ENA_S 5 +/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD9_INT_ENA_S 6 +/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001U +#define SPI_SLV_CMDA_INT_ENA_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_TRANS_DONE_INT_ENA_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001U +#define SPI_APP2_INT_ENA_S 19 +/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001U +#define SPI_APP1_INT_ENA_S 20 + +/** SPI_DMA_INT_CLR_REG register + * SPI interrupt clear register + */ +#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38) +/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD7_INT_CLR_S 4 +/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD8_INT_CLR_S 5 +/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD9_INT_CLR_S 6 +/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001U +#define SPI_SLV_CMDA_INT_CLR_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_TRANS_DONE_INT_CLR_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001U +#define SPI_APP2_INT_CLR_S 19 +/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001U +#define SPI_APP1_INT_CLR_S 20 + +/** SPI_DMA_INT_RAW_REG register + * SPI interrupt raw register + */ +#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c) +/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD7_INT_RAW_S 4 +/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD8_INT_RAW_S 5 +/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD9_INT_RAW_S 6 +/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001U +#define SPI_SLV_CMDA_INT_RAW_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_TRANS_DONE_INT_RAW_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001U +#define SPI_APP2_INT_RAW_S 19 +/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001U +#define SPI_APP1_INT_RAW_S 20 + +/** SPI_DMA_INT_ST_REG register + * SPI interrupt status register + */ +#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001U +#define SPI_SLV_CMD7_INT_ST_S 4 +/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001U +#define SPI_SLV_CMD8_INT_ST_S 5 +/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001U +#define SPI_SLV_CMD9_INT_ST_S 6 +/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001U +#define SPI_SLV_CMDA_INT_ST_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_TRANS_DONE_INT_ST_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001U +#define SPI_APP2_INT_ST_S 19 +/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001U +#define SPI_APP1_INT_ST_S 20 + +/** SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44) +/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S) +#define SPI_SLV_EX_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S) +#define SPI_SLV_EN_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S) +#define SPI_SLV_CMD7_INT_SET_V 0x00000001U +#define SPI_SLV_CMD7_INT_SET_S 4 +/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S) +#define SPI_SLV_CMD8_INT_SET_V 0x00000001U +#define SPI_SLV_CMD8_INT_SET_S 5 +/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S) +#define SPI_SLV_CMD9_INT_SET_V 0x00000001U +#define SPI_SLV_CMD9_INT_SET_S 6 +/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S) +#define SPI_SLV_CMDA_INT_SET_V 0x00000001U +#define SPI_SLV_CMDA_INT_SET_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S) +#define SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_TRANS_DONE_INT_SET_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S) +#define SPI_APP2_INT_SET_V 0x00000001U +#define SPI_APP2_INT_SET_S 19 +/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S) +#define SPI_APP1_INT_SET_V 0x00000001U +#define SPI_APP1_INT_SET_S 20 + +/** SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98) +/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF0 0xFFFFFFFFU +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFFU +#define SPI_BUF0_S 0 + +/** SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c) +/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF1 0xFFFFFFFFU +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFFU +#define SPI_BUF1_S 0 + +/** SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0) +/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF2 0xFFFFFFFFU +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFFU +#define SPI_BUF2_S 0 + +/** SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4) +/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF3 0xFFFFFFFFU +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFFU +#define SPI_BUF3_S 0 + +/** SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8) +/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF4 0xFFFFFFFFU +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFFU +#define SPI_BUF4_S 0 + +/** SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac) +/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF5 0xFFFFFFFFU +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFFU +#define SPI_BUF5_S 0 + +/** SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0) +/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF6 0xFFFFFFFFU +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFFU +#define SPI_BUF6_S 0 + +/** SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4) +/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF7 0xFFFFFFFFU +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFFU +#define SPI_BUF7_S 0 + +/** SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8) +/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF8 0xFFFFFFFFU +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFFU +#define SPI_BUF8_S 0 + +/** SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc) +/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF9 0xFFFFFFFFU +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFFU +#define SPI_BUF9_S 0 + +/** SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0) +/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF10 0xFFFFFFFFU +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFFU +#define SPI_BUF10_S 0 + +/** SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4) +/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF11 0xFFFFFFFFU +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFFU +#define SPI_BUF11_S 0 + +/** SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8) +/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF12 0xFFFFFFFFU +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFFU +#define SPI_BUF12_S 0 + +/** SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc) +/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF13 0xFFFFFFFFU +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFFU +#define SPI_BUF13_S 0 + +/** SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0) +/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF14 0xFFFFFFFFU +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFFU +#define SPI_BUF14_S 0 + +/** SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4) +/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF15 0xFFFFFFFFU +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFFU +#define SPI_BUF15_S 0 + +/** SPI_SLAVE_REG register + * SPI slave control register + */ +#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0) +/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ +#define SPI_CLK_MODE 0x00000003U +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003U +#define SPI_CLK_MODE_S 0 +/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001U +#define SPI_CLK_MODE_13_S 2 +/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001U +#define SPI_RSCK_DATA_OUT_S 3 +/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001U +#define SPI_SLAVE_MODE_S 26 +/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001U +#define SPI_SOFT_RESET_S 27 +/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001U +#define SPI_USR_CONF_S 28 +/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ +#define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_V 0x00000001U +#define SPI_MST_FD_WAIT_DMA_TX_DATA_S 29 + +/** SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4) +/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ +#define SPI_SLV_DATA_BITLEN 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_S 0 +/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ +#define SPI_SLV_LAST_COMMAND 0x000000FFU +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FFU +#define SPI_SLV_LAST_COMMAND_S 18 +/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ +#define SPI_SLV_LAST_ADDR 0x0000003FU +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003FU +#define SPI_SLV_LAST_ADDR_S 26 + +/** SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001U +#define SPI_MST_CLK_ACTIVE_S 1 +/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001U +#define SPI_MST_CLK_SEL_S 2 + +/** SPI_DATE_REG register + * Version control + */ +#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0) +/** SPI_DATE : R/W; bitpos: [27:0]; default: 35656448; + * SPI register version. + */ +#define SPI_DATE 0x0FFFFFFFU +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFFU +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/spi_struct.h b/components/soc/esp32h2/include/soc/spi_struct.h new file mode 100644 index 0000000000..de7705f92c --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_struct.h @@ -0,0 +1,1406 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + uint32_t reserved_12:10; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the + * (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, + * 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the + * (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, + * 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the + * (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, + * 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst + * falling edge cycle. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + + +/** Group: CPU-controlled data buffer */ +/** Type of w0 register + * SPI CPU-controlled buffer0 + */ +typedef union { + struct { + /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi_wn_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35656448; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_wn_reg_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/system_reg.h b/components/soc/esp32h2/include/soc/system_reg.h new file mode 100644 index 0000000000..6a52d2da70 --- /dev/null +++ b/components/soc/esp32h2/include/soc/system_reg.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/hp_system_reg.h" +#include "intpri_reg.h" + +// ESP32H2-TODO : TODO: IDF-5720 +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG +#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32h2/include/soc/systimer_reg.h b/components/soc/esp32h2/include/soc/systimer_reg.h new file mode 100644 index 0000000000..9cccb760cc --- /dev/null +++ b/components/soc/esp32h2/include/soc/systimer_reg.h @@ -0,0 +1,637 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ +#define SYSTIMER_ETM_EN (BIT(1)) +#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) +#define SYSTIMER_ETM_EN_V 0x00000001U +#define SYSTIMER_ETM_EN_S 1 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/systimer_struct.h b/components/soc/esp32h2/include/soc/systimer_struct.h new file mode 100644 index 0000000000..0e0e1f8f34 --- /dev/null +++ b/components/soc/esp32h2/include/soc/systimer_struct.h @@ -0,0 +1,379 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo:1; + /** etm_en : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_2:20; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en:1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en:1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en:1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en:1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en:1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en:1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en:1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en:1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en:1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit_op register + * system timer unit value update register + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit + */ + uint32_t timer_unit_update: 1; + uint32_t reserved31: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * system timer unit value high and low load register + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 20 bit + */ + uint32_t timer_unit_load_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of unit_value_hi register + * system timer unit value high and low register + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20 bit + */ + uint32_t timer_unit_value_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32 bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + +/** Type of unit_load register + * system timer unit conf sync register + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_unit_load_reg_t; + + +/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */ +/** Type of target register + * system timer comp value high and low register + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 20 bit + */ + uint32_t timer_target_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * system timer comp target mode register + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of comp_load register + * system timer comp conf sync register + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp sync enable signal + */ + uint32_t timer_comp_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_comp_load_reg_t; + + +/** Group: SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena:1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena:1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw:1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw:1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr:1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr:1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st:1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st:1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Group: SYSTEM TIMER COMP STATUS REGISTER */ +/** Type of real_target_hi/lo register + * system timer comp actual target value low register + */ +typedef struct { + union { + struct { + /** target_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32 bits + */ + uint32_t target_lo_ro: 32; + }; + uint32_t val; + } lo; + union { + struct { + /** target_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20 bits + */ + uint32_t target_hi_ro: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; +} systimer_real_target_reg_t; + + +/** Group: VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct systimer_dev_t { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target_reg_t real_target[3]; + uint32_t reserved_08c[28]; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/tee_reg.h b/components/soc/esp32h2/include/soc/tee_reg.h new file mode 100644 index 0000000000..fd340089ee --- /dev/null +++ b/components/soc/esp32h2/include/soc/tee_reg.h @@ -0,0 +1,456 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 + +/** TEE_M1_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 + +/** TEE_M2_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 + +/** TEE_M3_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 + +/** TEE_M4_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 + +/** TEE_M5_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 + +/** TEE_M6_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 + +/** TEE_M7_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 + +/** TEE_M8_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 + +/** TEE_M9_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 + +/** TEE_M10_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 + +/** TEE_M11_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 + +/** TEE_M12_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 + +/** TEE_M13_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 + +/** TEE_M14_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 + +/** TEE_M15_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 + +/** TEE_M16_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 + +/** TEE_M17_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 + +/** TEE_M18_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 + +/** TEE_M19_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 + +/** TEE_M20_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 + +/** TEE_M21_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 + +/** TEE_M22_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 + +/** TEE_M23_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 + +/** TEE_M24_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 + +/** TEE_M25_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 + +/** TEE_M26_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 + +/** TEE_M27_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 + +/** TEE_M28_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 + +/** TEE_M29_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 + +/** TEE_M30_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 + +/** TEE_M31_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706; + * reg_tee_date + */ +#define TEE_DATE_REG 0x0FFFFFFFU +#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) +#define TEE_DATE_REG_V 0x0FFFFFFFU +#define TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/tee_struct.h b/components/soc/esp32h2/include/soc/tee_struct.h new file mode 100644 index 0000000000..974ff22188 --- /dev/null +++ b/components/soc/esp32h2/include/soc/tee_struct.h @@ -0,0 +1,573 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m0_mode_ctrl_reg_t; + +/** Type of m1_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m1_mode : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m1_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m1_mode_ctrl_reg_t; + +/** Type of m2_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m2_mode : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m2_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m2_mode_ctrl_reg_t; + +/** Type of m3_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m3_mode : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m3_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m3_mode_ctrl_reg_t; + +/** Type of m4_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m4_mode : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m4_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m4_mode_ctrl_reg_t; + +/** Type of m5_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m5_mode : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m5_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m5_mode_ctrl_reg_t; + +/** Type of m6_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m6_mode : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m6_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m6_mode_ctrl_reg_t; + +/** Type of m7_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m7_mode : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m7_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m7_mode_ctrl_reg_t; + +/** Type of m8_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m8_mode : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m8_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m8_mode_ctrl_reg_t; + +/** Type of m9_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m9_mode : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m9_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m9_mode_ctrl_reg_t; + +/** Type of m10_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m10_mode : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m10_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m10_mode_ctrl_reg_t; + +/** Type of m11_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m11_mode : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m11_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m11_mode_ctrl_reg_t; + +/** Type of m12_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m12_mode : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m12_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m12_mode_ctrl_reg_t; + +/** Type of m13_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m13_mode : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m13_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m13_mode_ctrl_reg_t; + +/** Type of m14_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m14_mode : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m14_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m14_mode_ctrl_reg_t; + +/** Type of m15_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m15_mode : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m15_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m15_mode_ctrl_reg_t; + +/** Type of m16_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m16_mode : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m16_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m16_mode_ctrl_reg_t; + +/** Type of m17_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m17_mode : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m17_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m17_mode_ctrl_reg_t; + +/** Type of m18_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m18_mode : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m18_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m18_mode_ctrl_reg_t; + +/** Type of m19_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m19_mode : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m19_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m19_mode_ctrl_reg_t; + +/** Type of m20_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m20_mode : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m20_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m20_mode_ctrl_reg_t; + +/** Type of m21_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m21_mode : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m21_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m21_mode_ctrl_reg_t; + +/** Type of m22_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m22_mode : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m22_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m22_mode_ctrl_reg_t; + +/** Type of m23_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m23_mode : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m23_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m23_mode_ctrl_reg_t; + +/** Type of m24_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m24_mode : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m24_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m24_mode_ctrl_reg_t; + +/** Type of m25_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m25_mode : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m25_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m25_mode_ctrl_reg_t; + +/** Type of m26_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m26_mode : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m26_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m26_mode_ctrl_reg_t; + +/** Type of m27_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m27_mode : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m27_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m27_mode_ctrl_reg_t; + +/** Type of m28_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m28_mode : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m28_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m28_mode_ctrl_reg_t; + +/** Type of m29_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m29_mode : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m29_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m29_mode_ctrl_reg_t; + +/** Type of m30_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m30_mode : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m30_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m30_mode_ctrl_reg_t; + +/** Type of m31_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m31_mode : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m31_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m31_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35672706; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct { + volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl; + volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl; + volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl; + volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl; + volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl; + volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl; + volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl; + volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl; + volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl; + volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl; + volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl; + volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl; + volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl; + volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl; + volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl; + volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl; + volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl; + volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl; + volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl; + volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl; + volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl; + volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl; + volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl; + volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl; + volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl; + volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl; + volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl; + volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl; + volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl; + volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl; + volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl; + volatile tee_clock_gate_reg_t clock_gate; + uint32_t reserved_084[990]; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/include/soc/timer_group_reg.h new file mode 100644 index 0000000000..df5c8ffb32 --- /dev/null +++ b/components/soc/esp32h2/include/soc/timer_group_reg.h @@ -0,0 +1,591 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) +/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) +#define TIMG_T0_USE_XTAL_V 0x00000001U +#define TIMG_T0_USE_XTAL_S 9 +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0; + * choose WDT clock:0-apb_clk, 1-xtal_clk. + */ +#define TIMG_WDT_USE_XTAL (BIT(21)) +#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S) +#define TIMG_WDT_USE_XTAL_V 0x00000001U +#define TIMG_WDT_USE_XTAL_S 21 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(1)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 1 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(1)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 1 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(1)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 1 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(1)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 1 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35676274; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1; + * enable WDT's clock + */ +#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S) +#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U +#define TIMG_WDT_CLK_IS_ACTIVE_S 29 +/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1; + * enable Timer $x's clock + */ +#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S) +#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U +#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/timer_group_struct.h b/components/soc/esp32h2/include/soc/timer_group_struct.h new file mode 100644 index 0000000000..15e16e6d2e --- /dev/null +++ b/components/soc/esp32h2/include/soc/timer_group_struct.h @@ -0,0 +1,568 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_use_xtal : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ + uint32_t tx_use_xtal:1; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_use_xtal : R/W; bitpos: [21]; default: 0; + * choose WDT clock:0-apb_clk, 1-xtal_clk. + */ + uint32_t wdt_use_xtal:1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en:1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3:2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2:2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1:2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0:2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale:16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed:32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling:1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel:2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy:1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max:15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start:1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value:25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena:1; + /** wdt_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw:1; + /** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st:1; + /** wdt_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr:1; + /** wdt_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35676274; + * Timer version control register + */ + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en:1; + /** wdt_clk_is_active : R/W; bitpos: [29]; default: 1; + * enable WDT's clock + */ + uint32_t wdt_clk_is_active:1; + /** timer_clk_is_active : R/W; bitpos: [30]; default: 1; + * enable Timer $x's clock + */ + uint32_t timer_clk_is_active:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} timg_regclk_reg_t; + + +typedef struct { + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; + + +typedef struct timg_dev_t { + volatile timg_hwtimer_reg_t hw_timer[1]; + uint32_t reserved_024[9]; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/trace_reg.h b/components/soc/esp32h2/include/soc/trace_reg.h new file mode 100644 index 0000000000..a5c3eda9dc --- /dev/null +++ b/components/soc/esp32h2/include/soc/trace_reg.h @@ -0,0 +1,219 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * mem start addr + */ +#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ +#define TRACE_MEM_STAET_ADDR 0xFFFFFFFFU +#define TRACE_MEM_STAET_ADDR_M (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S) +#define TRACE_MEM_STAET_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_STAET_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * mem end addr + */ +#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * mem current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * mem addr update + */ +#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * when set this reg, the current_mem_addr will update to start_addr + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * fifo status register + */ +#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * 1 indicate that fifo is empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_WORK_STATUS (BIT(1)) +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000001U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * interrupt enable register + */ +#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * interrupt status register + */ +#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * interrupt clear register + */ +#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Set 1 clr fifo overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Set 1 clr mem full interrupt + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * trigger register + */ +#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * [0] set 1 start trace. + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * set 1 stop trace. + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * at mem_end_addr, it will stop at the mem_end_addr + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * enable encoder auto-restart, when lost package, the encoder will end, if enable + * auto-restart, when fifo empty, encoder will restart and send a sync package. + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_RESYNC_PROLONGED_REG register + * resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0; + * resyc mode sel: 0: default, cycle count 1: package num count + */ +#define TRACE_RESYNC_MODE (BIT(24)) +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000001U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/trace_struct.h b/components/soc/esp32h2/include/soc/trace_struct.h new file mode 100644 index 0000000000..41677de428 --- /dev/null +++ b/components/soc/esp32h2/include/soc/trace_struct.h @@ -0,0 +1,249 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Trace memory configuration registers */ +/** Type of mem_start_addr register + * mem start addr + */ +typedef union { + struct { + /** mem_staet_addr : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ + uint32_t mem_staet_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * mem end addr + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * mem current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * mem addr update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * when set this reg, the current_mem_addr will update to start_addr + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * fifo status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * 1 indicate that fifo is empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t work_status:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Trace interrupt configuration registers */ +/** Type of intr_ena register + * interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * interrupt status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Set 1 clr fifo overflow interrupt + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Set 1 clr mem full interrupt + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * trigger register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * [0] set 1 start trace. + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * set 1 stop trace. + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * at mem_end_addr, it will stop at the mem_end_addr + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * enable encoder auto-restart, when lost package, the encoder will end, if enable + * auto-restart, when fifo empty, encoder will restart and send a sync package. + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of resync_prolonged register + * resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [24]; default: 0; + * resyc mode sel: 0: default, cycle count 1: package num count + */ + uint32_t resync_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35663920; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_02c[244]; + volatile trace_date_reg_t date; +} trace_dev_t; + +extern trace_dev_t TRACE; + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/twai_reg.h b/components/soc/esp32h2/include/soc/twai_reg.h new file mode 100644 index 0000000000..6e87c1267d --- /dev/null +++ b/components/soc/esp32h2/include/soc/twai_reg.h @@ -0,0 +1,740 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TWAI_MODE_REG register + * TWAI mode register. + */ +#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0) +/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ +#define TWAI_RESET_MODE (BIT(0)) +#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) +#define TWAI_RESET_MODE_V 0x00000001U +#define TWAI_RESET_MODE_S 0 +/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ +#define TWAI_LISTEN_ONLY_MODE (BIT(1)) +#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) +#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U +#define TWAI_LISTEN_ONLY_MODE_S 1 +/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ +#define TWAI_SELF_TEST_MODE (BIT(2)) +#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) +#define TWAI_SELF_TEST_MODE_V 0x00000001U +#define TWAI_SELF_TEST_MODE_S 2 +/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ +#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3)) +#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S) +#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U +#define TWAI_ACCEPTANCE_FILTER_MODE_S 3 + +/** TWAI_CMD_REG register + * TWAI command register. + */ +#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4) +/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ +#define TWAI_TX_REQUEST (BIT(0)) +#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S) +#define TWAI_TX_REQUEST_V 0x00000001U +#define TWAI_TX_REQUEST_S 0 +/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ +#define TWAI_ABORT_TX (BIT(1)) +#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) +#define TWAI_ABORT_TX_V 0x00000001U +#define TWAI_ABORT_TX_S 1 +/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ +#define TWAI_RELEASE_BUFFER (BIT(2)) +#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S) +#define TWAI_RELEASE_BUFFER_V 0x00000001U +#define TWAI_RELEASE_BUFFER_S 2 +/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ +#define TWAI_CLEAR_DATA_OVERRUN (BIT(3)) +#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S) +#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U +#define TWAI_CLEAR_DATA_OVERRUN_S 3 +/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ +#define TWAI_SELF_RX_REQUEST (BIT(4)) +#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S) +#define TWAI_SELF_RX_REQUEST_V 0x00000001U +#define TWAI_SELF_RX_REQUEST_S 4 + +/** TWAI_STATUS_REG register + * TWAI status register. + */ +#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8) +/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ +#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0)) +#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S) +#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U +#define TWAI_STATUS_RECEIVE_BUFFER_S 0 +/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ +#define TWAI_STATUS_OVERRUN (BIT(1)) +#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S) +#define TWAI_STATUS_OVERRUN_V 0x00000001U +#define TWAI_STATUS_OVERRUN_S 1 +/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ +#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2)) +#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S) +#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_BUFFER_S 2 +/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ +#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3)) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U +#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3 +/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ +#define TWAI_STATUS_RECEIVE (BIT(4)) +#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S) +#define TWAI_STATUS_RECEIVE_V 0x00000001U +#define TWAI_STATUS_RECEIVE_S 4 +/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ +#define TWAI_STATUS_TRANSMIT (BIT(5)) +#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S) +#define TWAI_STATUS_TRANSMIT_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_S 5 +/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ +#define TWAI_STATUS_ERR (BIT(6)) +#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S) +#define TWAI_STATUS_ERR_V 0x00000001U +#define TWAI_STATUS_ERR_S 6 +/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ +#define TWAI_STATUS_NODE_BUS_OFF (BIT(7)) +#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S) +#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U +#define TWAI_STATUS_NODE_BUS_OFF_S 7 +/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ +#define TWAI_STATUS_MISS (BIT(8)) +#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S) +#define TWAI_STATUS_MISS_V 0x00000001U +#define TWAI_STATUS_MISS_S 8 + +/** TWAI_INTERRUPT_REG register + * Interrupt signals' register. + */ +#define TWAI_INTERRUPT_REG (DR_REG_TWAI_BASE + 0xc) +/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ +#define TWAI_RECEIVE_INT_ST (BIT(0)) +#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S) +#define TWAI_RECEIVE_INT_ST_V 0x00000001U +#define TWAI_RECEIVE_INT_ST_S 0 +/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_TRANSMIT_INT_ST (BIT(1)) +#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S) +#define TWAI_TRANSMIT_INT_ST_V 0x00000001U +#define TWAI_TRANSMIT_INT_ST_S 1 +/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ +#define TWAI_ERR_WARNING_INT_ST (BIT(2)) +#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S) +#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U +#define TWAI_ERR_WARNING_INT_ST_S 2 +/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_DATA_OVERRUN_INT_ST (BIT(3)) +#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S) +#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U +#define TWAI_DATA_OVERRUN_INT_ST_S 3 +/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) +#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ST_S 5 +/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S) +#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ST_S 6 +/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_BUS_ERR_INT_ST (BIT(7)) +#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) +#define TWAI_BUS_ERR_INT_ST_V 0x00000001U +#define TWAI_BUS_ERR_INT_ST_S 7 +/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_IDLE_INT_ST (BIT(8)) +#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S) +#define TWAI_IDLE_INT_ST_V 0x00000001U +#define TWAI_IDLE_INT_ST_S 8 + +/** TWAI_INTERRUPT_ENABLE_REG register + * Interrupt enable register. + */ +#define TWAI_INTERRUPT_ENABLE_REG (DR_REG_TWAI_BASE + 0x10) +/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ +#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0)) +#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S) +#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U +#define TWAI_EXT_RECEIVE_INT_ENA_S 0 +/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ +#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1)) +#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S) +#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U +#define TWAI_EXT_TRANSMIT_INT_ENA_S 1 +/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2)) +#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S) +#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U +#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2 +/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3)) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3 +/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ +#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) +#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ENA_S 5 +/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ +#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S) +#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ENA_S 6 +/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_BUS_ERR_INT_ENA (BIT(7)) +#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) +#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U +#define TWAI_BUS_ERR_INT_ENA_S 7 +/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_IDLE_INT_ENA (BIT(8)) +#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S) +#define TWAI_IDLE_INT_ENA_V 0x00000001U +#define TWAI_IDLE_INT_ENA_S 8 + +/** TWAI_BUS_TIMING_0_REG register + * Bit timing configuration register 0. + */ +#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18) +/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ +#define TWAI_BAUD_PRESC 0x00003FFFU +#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) +#define TWAI_BAUD_PRESC_V 0x00003FFFU +#define TWAI_BAUD_PRESC_S 0 +/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ +#define TWAI_SYNC_JUMP_WIDTH 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) +#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_S 14 + +/** TWAI_BUS_TIMING_1_REG register + * Bit timing configuration register 1. + */ +#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c) +/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT1 0x0000000FU +#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S) +#define TWAI_TIME_SEGMENT1_V 0x0000000FU +#define TWAI_TIME_SEGMENT1_S 0 +/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT2 0x00000007U +#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S) +#define TWAI_TIME_SEGMENT2_V 0x00000007U +#define TWAI_TIME_SEGMENT2_S 4 +/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TIME_SAMPLING (BIT(7)) +#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S) +#define TWAI_TIME_SAMPLING_V 0x00000001U +#define TWAI_TIME_SAMPLING_S 7 + +/** TWAI_ARB_LOST_CAP_REG register + * TWAI arbiter lost capture register. + */ +#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c) +/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ +#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S) +#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_S 0 + +/** TWAI_ERR_CODE_CAP_REG register + * TWAI error info capture register. + */ +#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30) +/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ +#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S) +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0 +/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ +#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5)) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5 +/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ +#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S) +#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6 + +/** TWAI_ERR_WARNING_LIMIT_REG register + * TWAI error threshold configuration register. + */ +#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34) +/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_ERR_WARNING_LIMIT 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) +#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_S 0 + +/** TWAI_RX_ERR_CNT_REG register + * Rx error counter register. + */ +#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38) +/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_RX_ERR_CNT 0x000000FFU +#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) +#define TWAI_RX_ERR_CNT_V 0x000000FFU +#define TWAI_RX_ERR_CNT_S 0 + +/** TWAI_TX_ERR_CNT_REG register + * Tx error counter register. + */ +#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c) +/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TX_ERR_CNT 0x000000FFU +#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) +#define TWAI_TX_ERR_CNT_V 0x000000FFU +#define TWAI_TX_ERR_CNT_S 0 + +/** TWAI_DATA_0_REG register + * Data register 0. + */ +#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40) +/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ +#define TWAI_DATA_0 0x000000FFU +#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S) +#define TWAI_DATA_0_V 0x000000FFU +#define TWAI_DATA_0_S 0 + +/** TWAI_DATA_1_REG register + * Data register 1. + */ +#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44) +/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ +#define TWAI_DATA_1 0x000000FFU +#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S) +#define TWAI_DATA_1_V 0x000000FFU +#define TWAI_DATA_1_S 0 + +/** TWAI_DATA_2_REG register + * Data register 2. + */ +#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48) +/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ +#define TWAI_DATA_2 0x000000FFU +#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S) +#define TWAI_DATA_2_V 0x000000FFU +#define TWAI_DATA_2_S 0 + +/** TWAI_DATA_3_REG register + * Data register 3. + */ +#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c) +/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ +#define TWAI_DATA_3 0x000000FFU +#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S) +#define TWAI_DATA_3_V 0x000000FFU +#define TWAI_DATA_3_S 0 + +/** TWAI_DATA_4_REG register + * Data register 4. + */ +#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50) +/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ +#define TWAI_DATA_4 0x000000FFU +#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S) +#define TWAI_DATA_4_V 0x000000FFU +#define TWAI_DATA_4_S 0 + +/** TWAI_DATA_5_REG register + * Data register 5. + */ +#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54) +/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ +#define TWAI_DATA_5 0x000000FFU +#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S) +#define TWAI_DATA_5_V 0x000000FFU +#define TWAI_DATA_5_S 0 + +/** TWAI_DATA_6_REG register + * Data register 6. + */ +#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58) +/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ +#define TWAI_DATA_6 0x000000FFU +#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S) +#define TWAI_DATA_6_V 0x000000FFU +#define TWAI_DATA_6_S 0 + +/** TWAI_DATA_7_REG register + * Data register 7. + */ +#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c) +/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ +#define TWAI_DATA_7 0x000000FFU +#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S) +#define TWAI_DATA_7_V 0x000000FFU +#define TWAI_DATA_7_S 0 + +/** TWAI_DATA_8_REG register + * Data register 8. + */ +#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60) +/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ +#define TWAI_DATA_8 0x000000FFU +#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S) +#define TWAI_DATA_8_V 0x000000FFU +#define TWAI_DATA_8_S 0 + +/** TWAI_DATA_9_REG register + * Data register 9. + */ +#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64) +/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ +#define TWAI_DATA_9 0x000000FFU +#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S) +#define TWAI_DATA_9_V 0x000000FFU +#define TWAI_DATA_9_S 0 + +/** TWAI_DATA_10_REG register + * Data register 10. + */ +#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68) +/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ +#define TWAI_DATA_10 0x000000FFU +#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S) +#define TWAI_DATA_10_V 0x000000FFU +#define TWAI_DATA_10_S 0 + +/** TWAI_DATA_11_REG register + * Data register 11. + */ +#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c) +/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ +#define TWAI_DATA_11 0x000000FFU +#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S) +#define TWAI_DATA_11_V 0x000000FFU +#define TWAI_DATA_11_S 0 + +/** TWAI_DATA_12_REG register + * Data register 12. + */ +#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70) +/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ +#define TWAI_DATA_12 0x000000FFU +#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S) +#define TWAI_DATA_12_V 0x000000FFU +#define TWAI_DATA_12_S 0 + +/** TWAI_RX_MESSAGE_COUNTER_REG register + * Received message counter register. + */ +#define TWAI_RX_MESSAGE_COUNTER_REG (DR_REG_TWAI_BASE + 0x74) +/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ +#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) +#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_S 0 + +/** TWAI_CLOCK_DIVIDER_REG register + * Clock divider register. + */ +#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c) +/** TWAI_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ +#define TWAI_CD 0x000000FFU +#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) +#define TWAI_CD_V 0x000000FFU +#define TWAI_CD_S 0 +/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_CLOCK_OFF (BIT(8)) +#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) +#define TWAI_CLOCK_OFF_V 0x00000001U +#define TWAI_CLOCK_OFF_S 8 + +/** TWAI_SW_STANDBY_CFG_REG register + * Software configure standby pin directly. + */ +#define TWAI_SW_STANDBY_CFG_REG (DR_REG_TWAI_BASE + 0x80) +/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ +#define TWAI_SW_STANDBY_EN (BIT(0)) +#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S) +#define TWAI_SW_STANDBY_EN_V 0x00000001U +#define TWAI_SW_STANDBY_EN_S 0 +/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ +#define TWAI_SW_STANDBY_CLR (BIT(1)) +#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S) +#define TWAI_SW_STANDBY_CLR_V 0x00000001U +#define TWAI_SW_STANDBY_CLR_S 1 + +/** TWAI_HW_CFG_REG register + * Hardware configure standby pin. + */ +#define TWAI_HW_CFG_REG (DR_REG_TWAI_BASE + 0x84) +/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ +#define TWAI_HW_STANDBY_EN (BIT(0)) +#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S) +#define TWAI_HW_STANDBY_EN_V 0x00000001U +#define TWAI_HW_STANDBY_EN_S 0 + +/** TWAI_HW_STANDBY_CNT_REG register + * Configure standby counter. + */ +#define TWAI_HW_STANDBY_CNT_REG (DR_REG_TWAI_BASE + 0x88) +/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ +#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S) +#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_S 0 + +/** TWAI_IDLE_INTR_CNT_REG register + * Configure idle interrupt counter. + */ +#define TWAI_IDLE_INTR_CNT_REG (DR_REG_TWAI_BASE + 0x8c) +/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ +#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S) +#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_S 0 + +/** TWAI_ECO_CFG_REG register + * ECO configuration register. + */ +#define TWAI_ECO_CFG_REG (DR_REG_TWAI_BASE + 0x90) +/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ +#define TWAI_RDN_ENA (BIT(0)) +#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S) +#define TWAI_RDN_ENA_V 0x00000001U +#define TWAI_RDN_ENA_S 0 +/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ +#define TWAI_RDN_RESULT (BIT(1)) +#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S) +#define TWAI_RDN_RESULT_V 0x00000001U +#define TWAI_RDN_RESULT_S 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/twai_struct.h b/components/soc/esp32h2/include/soc/twai_struct.h new file mode 100644 index 0000000000..ca4f281fad --- /dev/null +++ b/components/soc/esp32h2/include/soc/twai_struct.h @@ -0,0 +1,565 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + uint32_t reserved_4:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + uint32_t reserved_4:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of buffer register + * TX RX Buffer. + */ +typedef union { + struct { + /** byte : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_rx_buffer_reg_t; + +typedef struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; +} acceptance_filter_reg_t; + + +typedef struct twai_dev_s { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_reg_t interrupt; + volatile twai_interrupt_enable_reg_t interrupt_enable; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile union { + acceptance_filter_reg_t acceptance_filter; + twai_tx_rx_buffer_reg_t tx_rx_buffer[13]; + }; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; +} twai_dev_t; + +extern twai_dev_t TWAI0; + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0x94, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/uart_channel.h b/components/soc/esp32h2/include/soc/uart_channel.h new file mode 100644 index 0000000000..9977264f21 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_channel.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3. + +#ifndef _SOC_UART_CHANNEL_H +#define _SOC_UART_CHANNEL_H + +//UART channels +#define UART_GPIO24_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 24 +#define UART_GPIO23_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 23 + +#define UART_TXD_GPIO24_DIRECT_CHANNEL UART_GPIO24_DIRECT_CHANNEL +#define UART_RXD_GPIO23_DIRECT_CHANNEL UART_GPIO23_DIRECT_CHANNEL + +#endif diff --git a/components/soc/esp32h2/include/soc/uart_pins.h b/components/soc/esp32h2/include/soc/uart_pins.h new file mode 100644 index 0000000000..51c9edba01 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_pins.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/io_mux_reg.h" + +/* Specify the number of pins for UART */ +#define SOC_UART_PINS_COUNT (4) + +/* Specify the GPIO pin number for each UART signal in the IOMUX */ +#define U0RXD_GPIO_NUM 23 +#define U0TXD_GPIO_NUM 24 + +#define U0RTS_GPIO_NUM (-1) +#define U0CTS_GPIO_NUM (-1) + +#define U1RXD_GPIO_NUM (-1) +#define U1TXD_GPIO_NUM (-1) +#define U1RTS_GPIO_NUM (-1) +#define U1CTS_GPIO_NUM (-1) + +/* The following defines are necessary for reconfiguring the UART + * to use IOMUX, at runtime. */ +#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD) +#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD) +/* No func for the following pins, they shall not be used */ +#define U0RTS_MUX_FUNC (-1) +#define U0CTS_MUX_FUNC (-1) +/* Same goes for UART1 */ +#define U1TXD_MUX_FUNC (-1) +#define U1RXD_MUX_FUNC (-1) +#define U1RTS_MUX_FUNC (-1) +#define U1CTS_MUX_FUNC (-1) diff --git a/components/soc/esp32h2/include/soc/uart_reg.h b/components/soc/esp32h2/include/soc/uart_reg.h new file mode 100644 index 0000000000..164b55603f --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_reg.h @@ -0,0 +1,1579 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UART_FIFO_REG(i) register + * FIFO data register + */ +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG(i) register + * Raw interrupt status + */ +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG(i) register + * Masked interrupt status + */ +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG(i) register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG(i) register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG(i) register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG(i) register + * Rx Filter configuration + */ +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG(i) register + * UART status register + */ +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG(i) register + * a + */ +#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG(i) register + * Configuration register 1 + */ +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG(i) register + * Hardware flow-control configuration + */ +#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG(i) register + * UART sleep configure register 0 + */ +#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG(i) register + * UART sleep configure register 1 + */ +#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG(i) register + * UART sleep configure register 2 + */ +#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG(i) register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG(i) register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG(i) register + * Tx Break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG(i) register + * Frame-end idle configuration + */ +#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG(i) register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG(i) register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG(i) register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG(i) register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG(i) register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG(i) register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG(i) register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG(i) register + * Tx-SRAM write and read offset address. + */ +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG(i) register + * Rx-SRAM write and read offset address. + */ +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG(i) register + * UART transmit and receive status. + */ +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG(i) register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG(i) register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG(i) register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG(i) register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG(i) register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG(i) register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG(i) register + * UART Version register + */ +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848; + * This is the version register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG(i) register + * UART AFIFO Status + */ +#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG(i) register + * UART Registers Configuration Update register + */ +#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG(i) register + * UART ID register + */ +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/uart_struct.h b/components/soc/esp32h2/include/soc/uart_struct.h new file mode 100644 index 0000000000..2315f5c1ad --- /dev/null +++ b/components/soc/esp32h2/include/soc/uart_struct.h @@ -0,0 +1,1293 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:32; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty:1; + /** parity_err : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err:1; + /** frm_err : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err:1; + /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg:1; + /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg:1; + /** brk_det : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det:1; + /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout:1; + /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon:1; + /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff:1; + /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det:1; + /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done:1; + /** rs485_parity_err : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det:1; + /** wakeup : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty:1; + /** parity_err : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err:1; + /** frm_err : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err:1; + /** rxfifo_ovf : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg:1; + /** cts_chg : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg:1; + /** brk_det : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det:1; + /** rxfifo_tout : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout:1; + /** sw_xon : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon:1; + /** sw_xoff : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff:1; + /** glitch_det : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det:1; + /** tx_brk_done : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done:1; + /** rs485_parity_err : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det:1; + /** wakeup : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full: R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty: R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty:1; + /** parity_err: R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err:1; + /** frm_err: R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err:1; + /** rxfifo_ovf: R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg: R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg:1; + /** cts_chg: R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg:1; + /** brk_det: R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det:1; + /** rxfifo_tout: R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout:1; + /** sw_xon: R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon:1; + /** sw_xoff: R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff:1; + /** glitch_det: R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det:1; + /** tx_brk_done: R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done: R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done: R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done:1; + /** rs485_parity_err: R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err: R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash: R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det: R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det:1; + /** wakeup: R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full: WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty: WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty:1; + /** parity_err: WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err:1; + /** frm_err: WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err:1; + /** rxfifo_ovf: WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg: WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg:1; + /** cts_chg: WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg:1; + /** brk_det: WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det:1; + /** rxfifo_tout: WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout:1; + /** sw_xon: WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon:1; + /** sw_xoff: WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff:1; + /** glitch_det: WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det:1; + /** tx_brk_done: WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done: WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done: WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done:1; + /** rs485_parity_err: WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err: WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash: WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det: WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det:1; + /** wakeup: WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv_int : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv_int:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ + uint32_t sclk_div_b:6; + /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ + uint32_t sclk_div_a:6; + /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ + uint32_t sclk_div_num:8; + /** sclk_sel : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ + uint32_t sclk_sel:2; + /** sclk_en : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ + uint32_t sclk_en:1; + /** rst_core : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ + uint32_t rst_core:1; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** data : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t data:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct uart_dev_s { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/uhci_reg.h b/components/soc/esp32h2/include/soc/uhci_reg.h new file mode 100644 index 0000000000..8271133451 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uhci_reg.h @@ -0,0 +1,945 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UHCI_CONF0_REG register + * a + */ +#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0) +/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S) +#define UHCI_TX_RST_V 0x00000001U +#define UHCI_TX_RST_S 0 +/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S) +#define UHCI_RX_RST_V 0x00000001U +#define UHCI_RX_RST_S 1 +/** UHCI_UART0_CE : R/W; bitpos: [2]; default: 0; + * Set this bit to link up HCI and UART0. + */ +#define UHCI_UART0_CE (BIT(2)) +#define UHCI_UART0_CE_M (UHCI_UART0_CE_V << UHCI_UART0_CE_S) +#define UHCI_UART0_CE_V 0x00000001U +#define UHCI_UART0_CE_S 2 +/** UHCI_UART1_CE : R/W; bitpos: [3]; default: 0; + * Set this bit to link up HCI and UART1. + */ +#define UHCI_UART1_CE (BIT(3)) +#define UHCI_UART1_CE_M (UHCI_UART1_CE_V << UHCI_UART1_CE_S) +#define UHCI_UART1_CE_V 0x00000001U +#define UHCI_UART1_CE_S 3 +/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001U +#define UHCI_SEPER_EN_S 5 +/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001U +#define UHCI_HEAD_EN_S 6 +/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001U +#define UHCI_CRC_REC_EN_S 7 +/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U +#define UHCI_UART_IDLE_EOF_EN_S 8 +/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001U +#define UHCI_LEN_EOF_EN_S 9 +/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001U +#define UHCI_ENCODE_CRC_EN_S 10 +/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001U +#define UHCI_CLK_EN_S 11 +/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U +#define UHCI_UART_RX_BRK_EOF_EN_S 12 + +/** UHCI_INT_RAW_REG register + * a + */ +#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4) +/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001U +#define UHCI_RX_START_INT_RAW_S 0 +/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001U +#define UHCI_TX_START_INT_RAW_S 1 +/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_RX_HUNG_INT_RAW_S 2 +/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_TX_HUNG_INT_RAW_S 3 +/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S) +#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_RAW_S 4 +/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S) +#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_RAW_S 5 +/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This is the interrupt raw bit. Triggered when there are some errors in EOF in the + */ +#define UHCI_OUT_EOF_INT_RAW (BIT(6)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U +#define UHCI_OUT_EOF_INT_RAW_S 6 +/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0; + * Soft control int raw bit. + */ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S) +#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0; + * Soft control int raw bit. + */ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S) +#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL1_INT_RAW_S 8 + +/** UHCI_INT_ST_REG register + * a + */ +#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8) +/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001U +#define UHCI_RX_START_INT_ST_S 0 +/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001U +#define UHCI_TX_START_INT_ST_S 1 +/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001U +#define UHCI_RX_HUNG_INT_ST_S 2 +/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001U +#define UHCI_TX_HUNG_INT_ST_S 3 +/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S) +#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ST_S 4 +/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S) +#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ST_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * a + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0; + * a + */ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S) +#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ST_S 7 +/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0; + * a + */ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S) +#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ST_S 8 + +/** UHCI_INT_ENA_REG register + * a + */ +#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc) +/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001U +#define UHCI_RX_START_INT_ENA_S 0 +/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001U +#define UHCI_TX_START_INT_ENA_S 1 +/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_RX_HUNG_INT_ENA_S 2 +/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_TX_HUNG_INT_ENA_S 3 +/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S) +#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ENA_S 4 +/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S) +#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ENA_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * a + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S) +#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0; + * a + */ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S) +#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ENA_S 8 + +/** UHCI_INT_CLR_REG register + * a + */ +#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10) +/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001U +#define UHCI_RX_START_INT_CLR_S 0 +/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001U +#define UHCI_TX_START_INT_CLR_S 1 +/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_RX_HUNG_INT_CLR_S 2 +/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_TX_HUNG_INT_CLR_S 3 +/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S) +#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_CLR_S 4 +/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S) +#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_CLR_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * a + */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0; + * a + */ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S) +#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0; + * a + */ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S) +#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL1_INT_CLR_S 8 + +/** UHCI_CONF1_REG register + * a + */ +#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14) +/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; + * a + */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001U +#define UHCI_CHECK_SUM_EN_S 0 +/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; + * a + */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001U +#define UHCI_CHECK_SEQ_EN_S 1 +/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; + * a + */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001U +#define UHCI_CRC_DISABLE_S 2 +/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; + * a + */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001U +#define UHCI_SAVE_HEAD_S 3 +/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; + * a + */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U +#define UHCI_TX_CHECK_SUM_RE_S 4 +/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; + * a + */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001U +#define UHCI_TX_ACK_NUM_RE_S 5 +/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001U +#define UHCI_WAIT_SW_START_S 7 +/** UHCI_SW_START : WT; bitpos: [8]; default: 0; + * a + */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001U +#define UHCI_SW_START_S 8 + +/** UHCI_STATE0_REG register + * a + */ +#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18) +/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_RX_ERR_CAUSE 0x00000007U +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007U +#define UHCI_RX_ERR_CAUSE_S 0 +/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0; + * a + */ +#define UHCI_DECODE_STATE 0x00000007U +#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S) +#define UHCI_DECODE_STATE_V 0x00000007U +#define UHCI_DECODE_STATE_S 3 + +/** UHCI_STATE1_REG register + * a + */ +#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c) +/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_ENCODE_STATE 0x00000007U +#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S) +#define UHCI_ENCODE_STATE_V 0x00000007U +#define UHCI_ENCODE_STATE_S 0 + +/** UHCI_ESCAPE_CONF_REG register + * a + */ +#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20) +/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; + * a + */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001U +#define UHCI_TX_C0_ESC_EN_S 0 +/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; + * a + */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001U +#define UHCI_TX_DB_ESC_EN_S 1 +/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; + * a + */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001U +#define UHCI_TX_11_ESC_EN_S 2 +/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001U +#define UHCI_TX_13_ESC_EN_S 3 +/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; + * a + */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001U +#define UHCI_RX_C0_ESC_EN_S 4 +/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; + * a + */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001U +#define UHCI_RX_DB_ESC_EN_S 5 +/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; + * a + */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001U +#define UHCI_RX_11_ESC_EN_S 6 +/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001U +#define UHCI_RX_13_ESC_EN_S 7 + +/** UHCI_HUNG_CONF_REG register + * a + */ +#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24) +/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * a + */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_S 0 +/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * a + */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * a + */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; + * a + */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_S 12 +/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0; + * a + */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; + * a + */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/** UHCI_ACK_NUM_REG register + * a + */ +#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28) +/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_ACK_NUM 0x00000007U +#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S) +#define UHCI_ACK_NUM_V 0x00000007U +#define UHCI_ACK_NUM_S 0 +/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; + * a + */ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) +#define UHCI_ACK_NUM_LOAD_V 0x00000001U +#define UHCI_ACK_NUM_LOAD_S 3 + +/** UHCI_RX_HEAD_REG register + * a + */ +#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c) +/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_RX_HEAD 0xFFFFFFFFU +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFFU +#define UHCI_RX_HEAD_S 0 + +/** UHCI_QUICK_SENT_REG register + * a + */ +#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30) +/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_SINGLE_SEND_NUM 0x00000007U +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007U +#define UHCI_SINGLE_SEND_NUM_S 0 +/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0; + * a + */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001U +#define UHCI_SINGLE_SEND_EN_S 3 +/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; + * a + */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_S 4 +/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001U +#define UHCI_ALWAYS_SEND_EN_S 7 + +/** UHCI_REG_Q0_WORD0_REG register + * a + */ +#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34) +/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_S 0 + +/** UHCI_REG_Q0_WORD1_REG register + * a + */ +#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38) +/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_S 0 + +/** UHCI_REG_Q1_WORD0_REG register + * a + */ +#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c) +/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_S 0 + +/** UHCI_REG_Q1_WORD1_REG register + * a + */ +#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40) +/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_S 0 + +/** UHCI_REG_Q2_WORD0_REG register + * a + */ +#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44) +/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_S 0 + +/** UHCI_REG_Q2_WORD1_REG register + * a + */ +#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48) +/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_S 0 + +/** UHCI_REG_Q3_WORD0_REG register + * a + */ +#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c) +/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_S 0 + +/** UHCI_REG_Q3_WORD1_REG register + * a + */ +#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50) +/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_S 0 + +/** UHCI_REG_Q4_WORD0_REG register + * a + */ +#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54) +/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_S 0 + +/** UHCI_REG_Q4_WORD1_REG register + * a + */ +#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58) +/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_S 0 + +/** UHCI_REG_Q5_WORD0_REG register + * a + */ +#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c) +/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_S 0 + +/** UHCI_REG_Q5_WORD1_REG register + * a + */ +#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60) +/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_S 0 + +/** UHCI_REG_Q6_WORD0_REG register + * a + */ +#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64) +/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_S 0 + +/** UHCI_REG_Q6_WORD1_REG register + * a + */ +#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68) +/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_S 0 + +/** UHCI_ESC_CONF0_REG register + * a + */ +#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c) +/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; + * a + */ +#define UHCI_SEPER_CHAR 0x000000FFU +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FFU +#define UHCI_SEPER_CHAR_S 0 +/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_S 8 +/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220; + * a + */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/** UHCI_ESC_CONF1_REG register + * a + */ +#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70) +/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; + * a + */ +#define UHCI_ESC_SEQ0 0x000000FFU +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FFU +#define UHCI_ESC_SEQ0_S 0 +/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221; + * a + */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/** UHCI_ESC_CONF2_REG register + * a + */ +#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74) +/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; + * a + */ +#define UHCI_ESC_SEQ1 0x000000FFU +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FFU +#define UHCI_ESC_SEQ1_S 0 +/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222; + * a + */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/** UHCI_ESC_CONF3_REG register + * a + */ +#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78) +/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; + * a + */ +#define UHCI_ESC_SEQ2 0x000000FFU +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FFU +#define UHCI_ESC_SEQ2_S 0 +/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223; + * a + */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/** UHCI_PKT_THRES_REG register + * a + */ +#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c) +/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; + * a + */ +#define UHCI_PKT_THRS 0x00001FFFU +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFFU +#define UHCI_PKT_THRS_S 0 + +/** UHCI_DATE_REG register + * a + */ +#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80) +/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; + * a + */ +#define UHCI_DATE 0xFFFFFFFFU +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFFU +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/uhci_struct.h b/components/soc/esp32h2/include/soc/uhci_struct.h new file mode 100644 index 0000000000..29a488af67 --- /dev/null +++ b/components/soc/esp32h2/include/soc/uhci_struct.h @@ -0,0 +1,655 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of conf0 register + * a + */ +typedef union { + struct { + /** tx_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ + uint32_t tx_rst:1; + /** rx_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ + uint32_t rx_rst:1; + /** uart0_ce : R/W; bitpos: [2]; default: 0; + * Set this bit to link up HCI and UART0. + */ + uint32_t uart0_ce:1; + /** uart1_ce : R/W; bitpos: [3]; default: 0; + * Set this bit to link up HCI and UART1. + */ + uint32_t uart1_ce:1; + uint32_t reserved_4:1; + /** seper_en : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ + uint32_t seper_en:1; + /** head_en : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ + uint32_t head_en:1; + /** crc_rec_en : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ + uint32_t crc_rec_en:1; + /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ + uint32_t uart_idle_eof_en:1; + /** len_eof_en : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ + uint32_t len_eof_en:1; + /** encode_crc_en : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ + uint32_t encode_crc_en:1; + /** clk_en : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ + uint32_t uart_rx_brk_eof_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_conf0_reg_t; + +/** Type of conf1 register + * a + */ +typedef union { + struct { + /** check_sum_en : R/W; bitpos: [0]; default: 1; + * a + */ + uint32_t check_sum_en:1; + /** check_seq_en : R/W; bitpos: [1]; default: 1; + * a + */ + uint32_t check_seq_en:1; + /** crc_disable : R/W; bitpos: [2]; default: 0; + * a + */ + uint32_t crc_disable:1; + /** save_head : R/W; bitpos: [3]; default: 0; + * a + */ + uint32_t save_head:1; + /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; + * a + */ + uint32_t tx_check_sum_re:1; + /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; + * a + */ + uint32_t tx_ack_num_re:1; + uint32_t reserved_6:1; + /** wait_sw_start : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t wait_sw_start:1; + /** sw_start : WT; bitpos: [8]; default: 0; + * a + */ + uint32_t sw_start:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_conf1_reg_t; + +/** Type of escape_conf register + * a + */ +typedef union { + struct { + /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; + * a + */ + uint32_t tx_c0_esc_en:1; + /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; + * a + */ + uint32_t tx_db_esc_en:1; + /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; + * a + */ + uint32_t tx_11_esc_en:1; + /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_13_esc_en:1; + /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; + * a + */ + uint32_t rx_c0_esc_en:1; + /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; + * a + */ + uint32_t rx_db_esc_en:1; + /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; + * a + */ + uint32_t rx_11_esc_en:1; + /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t rx_13_esc_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_escape_conf_reg_t; + +/** Type of hung_conf register + * a + */ +typedef union { + struct { + /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; + * a + */ + uint32_t txfifo_timeout:8; + /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * a + */ + uint32_t txfifo_timeout_shift:3; + /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * a + */ + uint32_t txfifo_timeout_ena:1; + /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; + * a + */ + uint32_t rxfifo_timeout:8; + /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; + * a + */ + uint32_t rxfifo_timeout_shift:3; + /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; + * a + */ + uint32_t rxfifo_timeout_ena:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_hung_conf_reg_t; + +/** Type of ack_num register + * a + */ +typedef union { + struct { + /** ack_num : R/W; bitpos: [2:0]; default: 0; + * a + */ + uint32_t ack_num:3; + /** ack_num_load : WT; bitpos: [3]; default: 0; + * a + */ + uint32_t ack_num_load:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uhci_ack_num_reg_t; + +/** Type of quick_sent register + * a + */ +typedef union { + struct { + /** single_send_num : R/W; bitpos: [2:0]; default: 0; + * a + */ + uint32_t single_send_num:3; + /** single_send_en : WT; bitpos: [3]; default: 0; + * a + */ + uint32_t single_send_en:1; + /** always_send_num : R/W; bitpos: [6:4]; default: 0; + * a + */ + uint32_t always_send_num:3; + /** always_send_en : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t always_send_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_quick_sent_reg_t; + +/** Type of reg_qn_word0 register + * a + */ +typedef union { + struct { + /** send_word0 : R/W; bitpos: [31:0]; default: 0; + * a + */ + uint32_t send_word0:32; + }; + uint32_t val; +} uhci_reg_qn_word0_reg_t; + +/** Type of reg_qn_word1 register + * a + */ +typedef union { + struct { + /** send_word1 : R/W; bitpos: [31:0]; default: 0; + * a + */ + uint32_t send_word1:32; + }; + uint32_t val; +} uhci_reg_qn_word1_reg_t; + +/** Type of esc_conf0 register + * a + */ +typedef union { + struct { + /** seper_char : R/W; bitpos: [7:0]; default: 192; + * a + */ + uint32_t seper_char:8; + /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t seper_esc_char0:8; + /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; + * a + */ + uint32_t seper_esc_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf0_reg_t; + +/** Type of esc_conf1 register + * a + */ +typedef union { + struct { + /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; + * a + */ + uint32_t esc_seq0:8; + /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t esc_seq0_char0:8; + /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; + * a + */ + uint32_t esc_seq0_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf1_reg_t; + +/** Type of esc_conf2 register + * a + */ +typedef union { + struct { + /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; + * a + */ + uint32_t esc_seq1:8; + /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t esc_seq1_char0:8; + /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; + * a + */ + uint32_t esc_seq1_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf2_reg_t; + +/** Type of esc_conf3 register + * a + */ +typedef union { + struct { + /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; + * a + */ + uint32_t esc_seq2:8; + /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t esc_seq2_char0:8; + /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; + * a + */ + uint32_t esc_seq2_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf3_reg_t; + +/** Type of pkt_thres register + * a + */ +typedef union { + struct { + /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; + * a + */ + uint32_t pkt_thrs:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_pkt_thres_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * a + */ +typedef union { + struct { + /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_raw:1; + /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_raw:1; + /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_raw:1; + /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_raw:1; + /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This is the interrupt raw bit. Triggered when there are some errors in EOF in the + */ + uint32_t out_eof_int_raw:1; + /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; + * Soft control int raw bit. + */ + uint32_t app_ctrl0_int_raw:1; + /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; + * Soft control int raw bit. + */ + uint32_t app_ctrl1_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_raw_reg_t; + +/** Type of int_st register + * a + */ +typedef union { + struct { + /** rx_start_int_st : RO; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_st:1; + /** tx_start_int_st : RO; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_st:1; + /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_st:1; + /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_st:1; + /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; + * a + */ + uint32_t outlink_eof_err_int_st:1; + /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; + * a + */ + uint32_t app_ctrl0_int_st:1; + /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; + * a + */ + uint32_t app_ctrl1_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_st_reg_t; + +/** Type of int_ena register + * a + */ +typedef union { + struct { + /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_ena:1; + /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_ena:1; + /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_ena:1; + /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_ena:1; + /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; + * a + */ + uint32_t outlink_eof_err_int_ena:1; + /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t app_ctrl0_int_ena:1; + /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; + * a + */ + uint32_t app_ctrl1_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_ena_reg_t; + +/** Type of int_clr register + * a + */ +typedef union { + struct { + /** rx_start_int_clr : WT; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_clr:1; + /** tx_start_int_clr : WT; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_clr:1; + /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_clr:1; + /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_clr:1; + /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; + * a + */ + uint32_t outlink_eof_err_int_clr:1; + /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; + * a + */ + uint32_t app_ctrl0_int_clr:1; + /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; + * a + */ + uint32_t app_ctrl1_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_clr_reg_t; + + +/** Group: UHCI Status Register */ +/** Type of state0 register + * a + */ +typedef union { + struct { + /** rx_err_cause : RO; bitpos: [2:0]; default: 0; + * a + */ + uint32_t rx_err_cause:3; + /** decode_state : RO; bitpos: [5:3]; default: 0; + * a + */ + uint32_t decode_state:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} uhci_state0_reg_t; + +/** Type of state1 register + * a + */ +typedef union { + struct { + /** encode_state : RO; bitpos: [2:0]; default: 0; + * a + */ + uint32_t encode_state:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} uhci_state1_reg_t; + +/** Type of rx_head register + * a + */ +typedef union { + struct { + /** rx_head : RO; bitpos: [31:0]; default: 0; + * a + */ + uint32_t rx_head:32; + }; + uint32_t val; +} uhci_rx_head_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * a + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655936; + * a + */ + uint32_t date:32; + }; + uint32_t val; +} uhci_date_reg_t; + + +typedef struct uhci_dev_s { + volatile uhci_conf0_reg_t conf0; + volatile uhci_int_raw_reg_t int_raw; + volatile uhci_int_st_reg_t int_st; + volatile uhci_int_ena_reg_t int_ena; + volatile uhci_int_clr_reg_t int_clr; + volatile uhci_conf1_reg_t conf1; + volatile uhci_state0_reg_t state0; + volatile uhci_state1_reg_t state1; + volatile uhci_escape_conf_reg_t escape_conf; + volatile uhci_hung_conf_reg_t hung_conf; + volatile uhci_ack_num_reg_t ack_num; + volatile uhci_rx_head_reg_t rx_head; + volatile uhci_quick_sent_reg_t quick_sent; + volatile struct { + uhci_reg_qn_word0_reg_t word0; + uhci_reg_qn_word1_reg_t word1; + } q_data[7]; + volatile uhci_esc_conf0_reg_t esc_conf0; + volatile uhci_esc_conf1_reg_t esc_conf1; + volatile uhci_esc_conf2_reg_t esc_conf2; + volatile uhci_esc_conf3_reg_t esc_conf3; + volatile uhci_pkt_thres_reg_t pkt_thres; + volatile uhci_date_reg_t date; +} uhci_dev_t; + +extern uhci_dev_t UHCI0; + +#ifndef __cplusplus +_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..eb4b8a1e03 --- /dev/null +++ b/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1188 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..f9dc6fa69f --- /dev/null +++ b/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,941 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t test_enable:1; + /** test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t test_usb_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t usb_mem_pd:1; + /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t rts:1; + /** dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t dtr:1; + /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bdata_bits:8; + /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bparity_type:8; + /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_in_afifo_reset_wr:1; + /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_in_afifo_reset_rd:1; + /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_out_afifo_reset_wr:1; + /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_out_afifo_reset_rd:1; + /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_out_afifo_rempty:1; + /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t jtag_in_flush_int_raw:1; + /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t sof_int_raw:1; + /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_out_recv_pkt_int_raw:1; + /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_in_empty_int_raw:1; + /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t pid_err_int_raw:1; + /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t crc5_err_int_raw:1; + /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t crc16_err_int_raw:1; + /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t stuff_err_int_raw:1; + /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t in_token_rec_in_ep1_int_raw:1; + /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t usb_bus_reset_int_raw:1; + /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t out_ep1_zero_payload_int_raw:1; + /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t out_ep2_zero_payload_int_raw:1; + /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t rts_chg_int_raw:1; + /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t dtr_chg_int_raw:1; + /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t get_line_code_int_raw:1; + /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_st:1; + /** sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_st:1; + /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ + uint32_t serial_out_recv_pkt_int_st:1; + /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_st:1; + /** pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_st:1; + /** crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_st:1; + /** crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_st:1; + /** stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_st:1; + /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ + uint32_t in_token_rec_in_ep1_int_st:1; + /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_st:1; + /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep1_zero_payload_int_st:1; + /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep2_zero_payload_int_st:1; + /** rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_st:1; + /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_st:1; + /** get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_st:1; + /** set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_ena:1; + /** sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_ena:1; + /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_ena:1; + /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_ena:1; + /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_ena:1; + /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_ena:1; + /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_ena:1; + /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_ena:1; + /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_ena:1; + /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_ena:1; + /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_ena:1; + /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_ena:1; + /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_ena:1; + /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_ena:1; + /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_ena:1; + /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_clr:1; + /** sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_clr:1; + /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_clr:1; + /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_clr:1; + /** pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_clr:1; + /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_clr:1; + /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_clr:1; + /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_clr:1; + /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_clr:1; + /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_clr:1; + /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_clr:1; + /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_clr:1; + /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_clr:1; + /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_clr:1; + /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_clr:1; + /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t in_fifo_cnt:2; + /** in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t in_fifo_empty:1; + /** in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t in_fifo_full:1; + /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t out_fifo_cnt:2; + /** out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t out_fifo_empty:1; + /** out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t out_fifo_full:1; + /** in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t in_fifo_reset:1; + /** out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t in_ep0_state:2; + /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t in_ep0_wr_addr:7; + /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t in_ep1_state:2; + /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t in_ep1_wr_addr:7; + /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t in_ep2_state:2; + /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t in_ep2_wr_addr:7; + /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t in_ep3_state:2; + /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t in_ep3_wr_addr:7; + /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t out_ep0_state:2; + /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t out_ep0_wr_addr:7; + /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t out_ep1_state:2; + /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t out_ep1_wr_addr:7; + /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t out_ep1_rd_addr:7; + /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t out_ep2_state:2; + /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t out_ep2_wr_addr:7; + /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t bchar_format:8; + /** bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t bparity_type:8; + /** bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + uint32_t reserved_06c[5]; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/wdev_reg.h b/components/soc/esp32h2/include/soc/wdev_reg.h new file mode 100644 index 0000000000..a26b914a29 --- /dev/null +++ b/components/soc/esp32h2/include/soc/wdev_reg.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc.h" +#include "soc/lpperi_reg.h" + +/* Hardware random number generator register */ +#define WDEV_RND_REG LPPERI_RNG_DATA_REG diff --git a/components/soc/esp32h2/interrupts.c b/components/soc/esp32h2/interrupts.c new file mode 100644 index 0000000000..c64a2247ad --- /dev/null +++ b/components/soc/esp32h2/interrupts.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "PMU", + [1] = "EFUSE", + [2] = "LP_RTC_TIMER", + [3] = "LP_BLE_TIMER", + [4] = "LP_WDT", + [5] = "LP_PERI_TIMEOUT", + [6] = "LP_APM_M0", + [7] = "CPUFROM_CPU_0", + [8] = "CPUFROM_CPU_1", + [9] = "CPUFROM_CPU_2", + [10] = "CPUFROM_CPU_3", + [11] = "ASSIST_DEBUG", + [12] = "TRACE", + [13] = "CACHE", + [14] = "CPU_PERI_TIMEOUT", + [15] = "BT_MAC", + [16] = "BT_BB", + [17] = "BT_BB_NMI_", + [18] = "COEX", + [19] = "BLE_TIMER", + [20] = "BLE_SEC", + [21] = "ZB_MAC", + [22] = "GPIO_INTERRUPT_PRO_", + [23] = "GPIO_INTERRUPT_PRO_NMI", + [24] = "PAU", + [25] = "HP_PERI_TIMEOUT", + [26] = "HP_APM_M0", + [27] = "HP_APM_M1", + [28] = "HP_APM_M2", + [29] = "HP_APM_M3", + [30] = "MSPI", + [31] = "I2S1", + [32] = "UHCI0", + [33] = "UART0", + [34] = "UART1", + [35] = "LEDC", + [36] = "CAN0", + [37] = "USB", + [38] = "RMT", + [39] = "I2C_EXT0", + [40] = "I2C_EXT1", + [41] = "TG0_T0", + [42] = "TG0_WDT", + [43] = "TG1_T0", + [44] = "TG1_WDT", + [45] = "SYSTIMER_TARGET0", + [46] = "SYSTIMER_TARGET1", + [47] = "SYSTIMER_TARGET2", + [48] = "APB_ADC", + [49] = "PWM", + [50] = "PCNT", + [51] = "PARL_IO_TX", + [52] = "PARL_IO_RX", + [53] = "DMA_IN_CH0", + [54] = "DMA_IN_CH1", + [55] = "DMA_IN_CH2", + [56] = "DMA_OUT_CH0", + [57] = "DMA_OUT_CH1", + [58] = "DMA_OUT_CH2", + [59] = "GPSPI2", + [60] = "AES", + [61] = "SHA", + [62] = "RSA", + [63] = "ECC", + [64] = "ECDSA", +}; diff --git a/components/soc/esp32h2/ld/esp32h2.peripherals.ld b/components/soc/esp32h2/ld/esp32h2.peripherals.ld new file mode 100644 index 0000000000..0167d1583c --- /dev/null +++ b/components/soc/esp32h2/ld/esp32h2.peripherals.ld @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C0 = 0x60004000 ); +PROVIDE ( I2C1 = 0x60005000 ); +PROVIDE ( UHCI0 = 0x60006000 ); +PROVIDE ( RMT = 0x60007000 ); +PROVIDE ( RMTMEM = 0x60007400 ); +PROVIDE ( LEDC = 0x60008000 ); +PROVIDE ( TIMERG0 = 0x60009000 ); +PROVIDE ( TIMERG1 = 0x6000A000 ); +PROVIDE ( SYSTIMER = 0x6000B000 ); +PROVIDE ( TWAI0 = 0x6000C000 ); +PROVIDE ( I2S0 = 0x6000D000 ); +PROVIDE ( APB_ADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); + +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( ATOMIC_LOCKER = 0x60011000 ); +PROVIDE ( PCNT = 0x60012000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( MCPWM = 0x60014000 ); +PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( PVT_MONITOR = 0x60019000 ); + +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); + +PROVIDE ( AES = 0x60088000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( RSA = 0x6008A000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( DS = 0x6008C000 ); +PROVIDE ( HMAC = 0x6008D000 ); + +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091f00 ); +PROVIDE ( SDM = 0x60091f00 ); /*ESP32H2-TODO*/ + +PROVIDE ( MEM_ACS_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); + +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( EFUSE = 0x600B0800 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( I2C_ANA_MST = 0x600B2400 ); +PROVIDE ( LP_PERI = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( OTP_DEBUG = 0x600B3C00 ); diff --git a/components/soc/esp32h2/ledc_periph.c b/components/soc/esp32h2/ledc_periph.c new file mode 100644 index 0000000000..b150f9bc99 --- /dev/null +++ b/components/soc/esp32h2/ledc_periph.c @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; diff --git a/components/soc/esp32h2/rmt_periph.c b/components/soc/esp32h2/rmt_periph.c new file mode 100644 index 0000000000..0c5a55871e --- /dev/null +++ b/components/soc/esp32h2/rmt_periph.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/rmt_periph.h" +#include "soc/gpio_sig_map.h" + +const rmt_signal_conn_t rmt_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = -1 + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = -1 + }, + [2] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN0_IDX + }, + [3] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN1_IDX + }, + } + } + } +}; diff --git a/components/soc/esp32h2/sdm_periph.c b/components/soc/esp32h2/sdm_periph.c new file mode 100644 index 0000000000..6d41dc98f1 --- /dev/null +++ b/components/soc/esp32h2/sdm_periph.c @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/sdm_periph.h" +#include "soc/gpio_sig_map.h" + +const sigma_delta_signal_conn_t sigma_delta_periph_signals = { + .channels = { + [0] = { + GPIO_SD0_OUT_IDX + }, + [1] = { + GPIO_SD1_OUT_IDX + }, + [2] = { + GPIO_SD2_OUT_IDX + }, + [3] = { + GPIO_SD3_OUT_IDX + } + } +}; diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c new file mode 100644 index 0000000000..bcb26e851f --- /dev/null +++ b/components/soc/esp32h2/spi_periph.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/spi_periph.h" +#include "stddef.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + {// ESP32H2-TODO: IDF-6245 Need check + .spiclk_in = 0,/* SPI clock is not an input signal*/ + .spics_in = 0,/* SPI cs is not an input signal*/ + .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, + .irq = ETS_MSPI_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI_MODULE, + .hw = (spi_dev_t *) &SPIMEM1, + .func = SPI_FUNC_NUM, + }, { + .spiclk_out = FSPICLK_OUT_IDX, + .spiclk_in = FSPICLK_IN_IDX, + .spid_out = FSPID_OUT_IDX, + .spiq_out = FSPIQ_OUT_IDX, + .spiwp_out = FSPIWP_OUT_IDX, + .spihd_out = FSPIHD_OUT_IDX, + .spid_in = FSPID_IN_IDX, + .spiq_in = FSPIQ_IN_IDX, + .spiwp_in = FSPIWP_IN_IDX, + .spihd_in = FSPIHD_IN_IDX, + .spics_out = {FSPICS0_OUT_IDX}, + .spics_in = FSPICS0_IN_IDX, + .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, + .irq = ETS_MSPI_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI2_MODULE, + .hw = &GPSPI2, + .func = SPI2_FUNC_NUM, + } +}; diff --git a/components/soc/esp32h2/temperature_sensor_periph.c b/components/soc/esp32h2/temperature_sensor_periph.c new file mode 100644 index 0000000000..e75c60b317 --- /dev/null +++ b/components/soc/esp32h2/temperature_sensor_periph.c @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/temperature_sensor_periph.h" + +const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { + /*Offset reg_val min max error */ + {-2, 5, 50, 125, 3}, + {-1, 7, 20, 100, 2}, + { 0, 15, -10, 80, 1}, + { 1, 11, -30, 50, 2}, + { 2, 10, -40, 20, 3}, +}; diff --git a/components/soc/esp32h2/timer_periph.c b/components/soc/esp32h2/timer_periph.c new file mode 100644 index 0000000000..e2be270b18 --- /dev/null +++ b/components/soc/esp32h2/timer_periph.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/timer_periph.h" + +const timer_group_signal_conn_t timer_group_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_TIMG0_MODULE, + .timer_irq_id = { + [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE, + } + }, + [1] = { + .module = PERIPH_TIMG1_MODULE, + .timer_irq_id = { + [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE, + } + } + } +}; diff --git a/components/soc/esp32h2/uart_periph.c b/components/soc/esp32h2/uart_periph.c new file mode 100644 index 0000000000..a23ff14937 --- /dev/null +++ b/components/soc/esp32h2/uart_periph.c @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/uart_periph.h" + +/* + Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { + { + .pins = { + [SOC_UART_TX_PIN_IDX] = { + .default_gpio = U0TXD_GPIO_NUM, + .iomux_func = U0TXD_MUX_FUNC, + .input = 0, + .signal = U0TXD_OUT_IDX, + }, + + [SOC_UART_RX_PIN_IDX] = { + .default_gpio = U0RXD_GPIO_NUM, + .iomux_func = U0RXD_MUX_FUNC, + .input = 1, + .signal = U0RXD_IN_IDX, + }, + + [SOC_UART_RTS_PIN_IDX] = { + .default_gpio = U0RTS_GPIO_NUM, + .iomux_func = U0RTS_MUX_FUNC, + .input = 0, + .signal = U0RTS_OUT_IDX, + }, + + [SOC_UART_CTS_PIN_IDX] = { + .default_gpio = U0CTS_GPIO_NUM, + .iomux_func = U0CTS_MUX_FUNC, + .input = 1, + .signal = U0CTS_IN_IDX, + } + }, + .irq = ETS_UART0_INTR_SOURCE, + .module = PERIPH_UART0_MODULE, + }, + + { + .pins = { + [SOC_UART_TX_PIN_IDX] = { + .default_gpio = U1TXD_GPIO_NUM, + .iomux_func = U1TXD_MUX_FUNC, + .input = 0, + .signal = U1TXD_OUT_IDX, + }, + + [SOC_UART_RX_PIN_IDX] = { + .default_gpio = U1RXD_GPIO_NUM, + .iomux_func = U1RXD_MUX_FUNC, + .input = 1, + .signal = U1RXD_IN_IDX, + }, + + [SOC_UART_RTS_PIN_IDX] = { + .default_gpio = U1RTS_GPIO_NUM, + .iomux_func = U1RTS_MUX_FUNC, + .input = 0, + .signal = U1RTS_OUT_IDX, + }, + + [SOC_UART_CTS_PIN_IDX] = { + .default_gpio = U1CTS_GPIO_NUM, + .iomux_func = U1CTS_MUX_FUNC, + .input = 1, + .signal = U1CTS_IN_IDX, + }, + }, + .irq = ETS_UART1_INTR_SOURCE, + .module = PERIPH_UART1_MODULE, + }, +}; diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h index e9ed87c7ce..5580c2b276 100644 --- a/components/soc/include/soc/rtc_cntl_periph.h +++ b/components/soc/include/soc/rtc_cntl_periph.h @@ -22,6 +22,16 @@ #include "soc/lp_uart_struct.h" #include "soc/lp_wdt_reg.h" #include "soc/lp_wdt_struct.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +// ESP32H2-TODO: IDF-6327 +#include "soc/lp_aon_reg.h" +#include "soc/lp_analog_peri_reg.h" +#include "soc/lp_clkrst_reg.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/lp_timer_reg.h" +#include "soc/lp_timer_struct.h" +#include "soc/lp_wdt_reg.h" +#include "soc/lp_wdt_struct.h" #else #include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_struct.h" diff --git a/components/soc/include/soc/syscon_periph.h b/components/soc/include/soc/syscon_periph.h index 01f12e297f..4f96aec6e5 100644 --- a/components/soc/include/soc/syscon_periph.h +++ b/components/soc/include/soc/syscon_periph.h @@ -6,8 +6,8 @@ #pragma once -// TODO: IDF-5721 -#if !CONFIG_IDF_TARGET_ESP32C6 +// ESP32-C6 ESP32-H2 TODO: IDF-5721 +#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 #include "soc/syscon_reg.h" #include "soc/syscon_struct.h" #endif