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Merge branch 'feature/esp32c5_regi2c_support' into 'master'

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feat(regi2c): support REGI2C for ESP32C5 MP

Closes IDF-8824

See merge request espressif/esp-idf!31411
This commit is contained in:
Song Ruo Jing 2024-06-17 11:10:26 +08:00
commit b4b1906d2c
11 changed files with 1415 additions and 26 deletions
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10
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
View File

@ -42,9 +42,8 @@
#include "soc/lp_wdt_reg.h"
#include "hal/efuse_hal.h"
#include "hal/lpwdt_ll.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "modem/modem_lpcon_reg.h"
#endif
#include "modem/modem_syscon_reg.h"
static const char *TAG = "boot.esp32c5";
@ -88,9 +87,12 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
/* Enable analog i2c master clock */
#if SOC_MODEM_CLOCK_SUPPORTED
SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-8667 Remove this?
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
#else // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M);
#endif
}
@ -163,7 +165,7 @@ esp_err_t bootloader_init(void)
}
#endif // !CONFIG_APP_BUILD_TYPE_RAM
// check whether a WDT reset happend
// check whether a WDT reset happened
bootloader_check_wdt_reset();
// config WDT
bootloader_config_wdt();

3
components/esp_rom/CMakeLists.txt
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@ -36,10 +36,7 @@ else()
# Override regi2c implementation in ROM
if(CONFIG_ESP_ROM_HAS_REGI2C_BUG OR CONFIG_ESP_ROM_WITHOUT_REGI2C)
if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5")
# TODO: [ESP32C5] IDF-8824
if(NOT CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
list(APPEND sources "patches/esp_rom_hp_regi2c_${target}.c")
endif()
else()
list(APPEND sources "patches/esp_rom_regi2c_${target}.c")
endif()

2
components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in
View File

@ -55,7 +55,7 @@ config ESP_ROM_HAS_SPI_FLASH
bool
default y
config ESP_ROM_HAS_REGI2C_BUG
config ESP_ROM_WITHOUT_REGI2C
bool
default y

2
components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h
View File

@ -19,7 +19,7 @@
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver
#define ESP_ROM_HAS_REGI2C_BUG (1) // ROM has the regi2c bug
#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor
#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included
#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock

15
components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c
View File

@ -7,17 +7,7 @@
#include "esp_attr.h"
#include "soc/i2c_ana_mst_reg.h"
#include "modem/modem_lpcon_reg.h"
/**
* BB - 0x67 - BIT0
* TXRF - 0x6B - BIT1
* SDM - 0x63 - BIT2
* PLL - 0x62 - BIT3
* BIAS - 0x6A - BIT4
* BBPLL - 0x66 - BIT5
* ULP - 0x61 - BIT6
* SAR - 0x69 - BIT7
* PMU - 0x6d - BIT8
*/
#include "soc/pmu_reg.h"
#define REGI2C_BIAS_MST_SEL (BIT(8))
#define REGI2C_BBPLL_MST_SEL (BIT(9))
@ -87,7 +77,8 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
uint32_t i2c_sel = 0;
REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
REG_SET_BIT(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); // TODO: IDF-8642 Move to pmu_init()
REG_SET_BIT(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); // TODO: IDF-8642 Move to pmu_init()
/* Before config I2C register, enable corresponding slave. */
switch (block) {

378
components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h Normal file
View File

@ -0,0 +1,378 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_EN (BIT(0))
#define MODEM_LPCON_CLK_EN_M (BIT(0))
#define MODEM_LPCON_CLK_EN_V 0x1
#define MODEM_LPCON_CLK_EN_S 0
#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S))
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4
/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3
/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1
/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0
#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S))
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC)
/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S))
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0
#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2))
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2))
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2
/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S))
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003
#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S))
#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3
#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3
/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1))
#define MODEM_LPCON_CLK_COEX_EN_V 0x1
#define MODEM_LPCON_CLK_COEX_EN_S 1
/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C)
/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4))
#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4))
#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1
#define MODEM_LPCON_CLK_FE_MEM_FO_S 4
/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1))
#define MODEM_LPCON_CLK_COEX_FO_V 0x1
#define MODEM_LPCON_CLK_COEX_FO_S 1
/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1
#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0
#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S))
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S))
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24
/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F
#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S))
#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF
#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20
/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S))
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_RST_LP_TIMER (BIT(3))
#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3))
#define MODEM_LPCON_RST_LP_TIMER_V 0x1
#define MODEM_LPCON_RST_LP_TIMER_S 3
/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
#define MODEM_LPCON_RST_I2C_MST_M (BIT(2))
#define MODEM_LPCON_RST_I2C_MST_V 0x1
#define MODEM_LPCON_RST_I2C_MST_S 2
/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_RST_COEX (BIT(1))
#define MODEM_LPCON_RST_COEX_M (BIT(1))
#define MODEM_LPCON_RST_COEX_V 0x1
#define MODEM_LPCON_RST_COEX_S 1
/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_RST_WIFIPWR (BIT(0))
#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0))
#define MODEM_LPCON_RST_WIFIPWR_V 0x1
#define MODEM_LPCON_RST_WIFIPWR_S 0
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */
/*description: .*/
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S))
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C)
/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23
/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
/*description: .*/
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S))
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20
/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19))
#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19))
#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1
#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19
/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
/*description: .*/
#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007
#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S))
#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7
#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16
/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_LPCON_BC_MEM_FORCE (BIT(15))
#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15))
#define MODEM_LPCON_BC_MEM_FORCE_V 0x1
#define MODEM_LPCON_BC_MEM_FORCE_S 15
/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */
/*description: .*/
#define MODEM_LPCON_BC_MEM_MODE 0x00000007
#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S))
#define MODEM_LPCON_BC_MEM_MODE_V 0x7
#define MODEM_LPCON_BC_MEM_MODE_S 12
/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11))
#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11))
#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1
#define MODEM_LPCON_PBUS_MEM_FORCE_S 11
/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
/*description: .*/
#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007
#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S))
#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7
#define MODEM_LPCON_PBUS_MEM_MODE_S 8
/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7))
#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7))
#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1
#define MODEM_LPCON_AGC_MEM_FORCE_S 7
/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */
/*description: .*/
#define MODEM_LPCON_AGC_MEM_MODE 0x00000007
#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S))
#define MODEM_LPCON_AGC_MEM_MODE_V 0x7
#define MODEM_LPCON_AGC_MEM_MODE_S 4
/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_LPCON_DC_MEM_FORCE (BIT(3))
#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3))
#define MODEM_LPCON_DC_MEM_FORCE_V 0x1
#define MODEM_LPCON_DC_MEM_FORCE_S 3
/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: .*/
#define MODEM_LPCON_DC_MEM_MODE 0x00000007
#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S))
#define MODEM_LPCON_DC_MEM_MODE_V 0x7
#define MODEM_LPCON_DC_MEM_MODE_S 0
#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30)
/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */
/*description: .*/
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S))
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0
#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34)
/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S))
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0
#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38)
/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_AGC_MEM_EN (BIT(2))
#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2))
#define MODEM_LPCON_AGC_MEM_EN_V 0x1
#define MODEM_LPCON_AGC_MEM_EN_S 2
/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */
/*description: .*/
#define MODEM_LPCON_PBUS_MEM_EN (BIT(1))
#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1))
#define MODEM_LPCON_PBUS_MEM_EN_V 0x1
#define MODEM_LPCON_PBUS_MEM_EN_S 1
/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0))
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0))
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C)
/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */
/*description: .*/
#define MODEM_LPCON_DATE 0x0FFFFFFF
#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S))
#define MODEM_LPCON_DATE_V 0xFFFFFFF
#define MODEM_LPCON_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h Normal file
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t reg_clk_en : 1;
uint32_t reserved1 : 1;
uint32_t reserved2 : 30;
};
uint32_t val;
} test_conf;
union {
struct {
uint32_t reg_clk_lp_timer_sel_osc_slow : 1;
uint32_t reg_clk_lp_timer_sel_osc_fast : 1;
uint32_t reg_clk_lp_timer_sel_xtal : 1;
uint32_t reg_clk_lp_timer_sel_xtal32k : 1;
uint32_t reg_clk_lp_timer_div_num : 12;
uint32_t reserved16 : 16;
};
uint32_t val;
} lp_timer_conf;
union {
struct {
uint32_t reg_clk_coex_lp_sel_osc_slow : 1;
uint32_t reg_clk_coex_lp_sel_osc_fast : 1;
uint32_t reg_clk_coex_lp_sel_xtal : 1;
uint32_t reg_clk_coex_lp_sel_xtal32k : 1;
uint32_t reg_clk_coex_lp_div_num : 12;
uint32_t reserved16 : 16;
};
uint32_t val;
} coex_lp_clk_conf;
union {
struct {
uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1;
uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1;
uint32_t reg_clk_wifipwr_lp_sel_xtal : 1;
uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1;
uint32_t reg_clk_wifipwr_lp_div_num : 12;
uint32_t reserved16 : 16;
};
uint32_t val;
} wifi_lp_clk_conf;
union {
struct {
uint32_t reg_clk_modem_aon_force : 2;
uint32_t reg_modem_pwr_clk_src_fo : 1;
uint32_t reserved3 : 29;
};
uint32_t val;
} modem_src_clk_conf;
union {
struct {
uint32_t reg_clk_modem_32k_sel : 2;
uint32_t reserved2 : 30;
};
uint32_t val;
} modem_32k_clk_conf;
union {
struct {
uint32_t reg_clk_wifipwr_en : 1;
uint32_t reg_clk_coex_en : 1;
uint32_t reg_clk_i2c_mst_en : 1;
uint32_t reg_clk_lp_timer_en : 1;
uint32_t reserved4 : 1;
uint32_t reserved5 : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t reserved8 : 1;
uint32_t reserved9 : 1;
uint32_t reserved10 : 1;
uint32_t reserved11 : 1;
uint32_t reserved12 : 1;
uint32_t reserved13 : 1;
uint32_t reserved14 : 1;
uint32_t reserved15 : 1;
uint32_t reserved16 : 1;
uint32_t reserved17 : 1;
uint32_t reserved18 : 1;
uint32_t reserved19 : 1;
uint32_t reserved20 : 1;
uint32_t reserved21 : 1;
uint32_t reserved22 : 1;
uint32_t reserved23 : 1;
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t reserved28 : 1;
uint32_t reserved29 : 1;
uint32_t reserved30 : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reg_clk_wifipwr_fo : 1;
uint32_t reg_clk_coex_fo : 1;
uint32_t reg_clk_i2c_mst_fo : 1;
uint32_t reg_clk_lp_timer_fo : 1;
uint32_t reg_clk_fe_mem_fo : 1;
uint32_t reserved5 : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t reserved8 : 1;
uint32_t reserved9 : 1;
uint32_t reserved10 : 1;
uint32_t reserved11 : 1;
uint32_t reserved12 : 1;
uint32_t reserved13 : 1;
uint32_t reserved14 : 1;
uint32_t reserved15 : 1;
uint32_t reserved16 : 1;
uint32_t reserved17 : 1;
uint32_t reserved18 : 1;
uint32_t reserved19 : 1;
uint32_t reserved20 : 1;
uint32_t reserved21 : 1;
uint32_t reserved22 : 1;
uint32_t reserved23 : 1;
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t reserved28 : 1;
uint32_t reserved29 : 1;
uint32_t reserved30 : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} clk_conf_force_on;
union {
struct {
uint32_t reserved0 : 16;
uint32_t reg_clk_wifipwr_st_map : 4;
uint32_t reg_clk_coex_st_map : 4;
uint32_t reg_clk_i2c_mst_st_map : 4;
uint32_t reg_clk_lp_apb_st_map : 4;
};
uint32_t val;
} clk_conf_power_st;
union {
struct {
uint32_t reg_rst_wifipwr : 1;
uint32_t reg_rst_coex : 1;
uint32_t reg_rst_i2c_mst : 1;
uint32_t reg_rst_lp_timer : 1;
uint32_t reserved4 : 1;
uint32_t reserved5 : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t reserved8 : 1;
uint32_t reserved9 : 1;
uint32_t reserved10 : 1;
uint32_t reserved11 : 1;
uint32_t reserved12 : 1;
uint32_t reserved13 : 1;
uint32_t reserved14 : 1;
uint32_t reserved15 : 1;
uint32_t reserved16 : 1;
uint32_t reserved17 : 1;
uint32_t reserved18 : 1;
uint32_t reserved19 : 1;
uint32_t reserved20 : 1;
uint32_t reserved21 : 1;
uint32_t reserved22 : 1;
uint32_t reserved23 : 1;
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t reserved28 : 1;
uint32_t reserved29 : 1;
uint32_t reserved30 : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} rst_conf;
union {
struct {
uint32_t reg_modem_pwr_tick_target : 6;
uint32_t reserved6 : 26;
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t reg_dc_mem_mode : 3;
uint32_t reg_dc_mem_force : 1;
uint32_t reg_agc_mem_mode : 3;
uint32_t reg_agc_mem_force : 1;
uint32_t reg_pbus_mem_mode : 3;
uint32_t reg_pbus_mem_force : 1;
uint32_t reg_bc_mem_mode : 3;
uint32_t reg_bc_mem_force : 1;
uint32_t reg_i2c_mst_mem_mode : 3;
uint32_t reg_i2c_mst_mem_force : 1;
uint32_t reg_chan_freq_mem_mode : 3;
uint32_t reg_chan_freq_mem_force : 1;
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t reserved28 : 1;
uint32_t reserved29 : 1;
uint32_t reserved30 : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} mem_conf;
uint32_t mem_rf1_aux_ctrl;
uint32_t mem_rf2_aux_ctrl;
union {
struct {
uint32_t reg_chan_freq_mem_en : 1;
uint32_t reg_pbus_mem_en : 1;
uint32_t reg_agc_mem_en : 1;
uint32_t reserved3 : 29;
};
uint32_t val;
} apb_mem_sel;
union {
struct {
uint32_t reg_date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
} modem_lpcon_dev_t;
extern modem_lpcon_dev_t MODEM_LPCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8))
#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8))
#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1
#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8
/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7))
#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7))
#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1
#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7
/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6))
#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6))
#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1
#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6
/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5))
#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5))
#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1
#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5
/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4))
#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4))
#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1
#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4
/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3))
#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3))
#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1
#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3
/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2))
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2))
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2
/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1))
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1))
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1
#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1
/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_EN (BIT(0))
#define MODEM_SYSCON_CLK_EN_M (BIT(0))
#define MODEM_SYSCON_CLK_EN_V 0x1
#define MODEM_SYSCON_CLK_EN_S 0
#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31
/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30
/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29
/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28))
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28))
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28
/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27
/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26))
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26))
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26
/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25))
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25))
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25
/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24))
#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24))
#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1
#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24
/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23))
#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23))
#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23
/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ETM_EN (BIT(22))
#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22))
#define MODEM_SYSCON_CLK_ETM_EN_V 0x1
#define MODEM_SYSCON_CLK_ETM_EN_S 22
/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21))
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21))
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21
/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12))
#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12))
#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1
#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12
/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11))
#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11))
#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1
#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11
/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10))
#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10))
#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1
#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10
/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9))
#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9))
#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1
#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9
/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */
/*description: .*/
#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF
#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S))
#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF
#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1
/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0))
#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0))
#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1
#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0
#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8)
/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31
/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30
/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29
/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ETM_FO (BIT(28))
#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28))
#define MODEM_SYSCON_CLK_ETM_FO_V 0x1
#define MODEM_SYSCON_CLK_ETM_FO_S 28
/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9))
#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9))
#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1
#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9
/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8))
#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8))
#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1
#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8
/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7))
#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7))
#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1
#define MODEM_SYSCON_CLK_BT_APB_FO_S 7
/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6))
#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6))
#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1
#define MODEM_SYSCON_CLK_BTMAC_FO_S 6
/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5))
#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5))
#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1
#define MODEM_SYSCON_CLK_BTBB_FO_S 5
/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4))
#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4))
#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1
#define MODEM_SYSCON_CLK_FE_APB_FO_S 4
/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_FO (BIT(3))
#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3))
#define MODEM_SYSCON_CLK_FE_FO_V 0x1
#define MODEM_SYSCON_CLK_FE_FO_S 3
/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2))
#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2))
#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1
#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2
/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1))
#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1))
#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1
#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1
/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0
#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC)
/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S))
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28
/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S))
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24
/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S))
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20
/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S))
#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16
/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S))
#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12
/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F
#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S))
#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF
#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8
#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31))
#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31))
#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1
#define MODEM_SYSCON_RST_DATA_DUMP_S 31
/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30))
#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30))
#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1
#define MODEM_SYSCON_RST_BLE_TIMER_S 30
/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29))
#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29))
#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1
#define MODEM_SYSCON_RST_MODEM_SEC_S 29
/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27))
#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27))
#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1
#define MODEM_SYSCON_RST_MODEM_BAH_S 27
/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26))
#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26))
#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1
#define MODEM_SYSCON_RST_MODEM_CCM_S 26
/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25))
#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25))
#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1
#define MODEM_SYSCON_RST_MODEM_ECB_S 25
/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_ZBMAC (BIT(24))
#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24))
#define MODEM_SYSCON_RST_ZBMAC_V 0x1
#define MODEM_SYSCON_RST_ZBMAC_S 24
/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23))
#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23))
#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1
#define MODEM_SYSCON_RST_ZBMAC_APB_S 23
/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_ETM (BIT(22))
#define MODEM_SYSCON_RST_ETM_M (BIT(22))
#define MODEM_SYSCON_RST_ETM_V 0x1
#define MODEM_SYSCON_RST_ETM_S 22
/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BTBB (BIT(18))
#define MODEM_SYSCON_RST_BTBB_M (BIT(18))
#define MODEM_SYSCON_RST_BTBB_V 0x1
#define MODEM_SYSCON_RST_BTBB_S 18
/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BTBB_APB (BIT(17))
#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17))
#define MODEM_SYSCON_RST_BTBB_APB_V 0x1
#define MODEM_SYSCON_RST_BTBB_APB_S 17
/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BTMAC (BIT(16))
#define MODEM_SYSCON_RST_BTMAC_M (BIT(16))
#define MODEM_SYSCON_RST_BTMAC_V 0x1
#define MODEM_SYSCON_RST_BTMAC_S 16
/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15))
#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15))
#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1
#define MODEM_SYSCON_RST_BTMAC_APB_S 15
/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_FE (BIT(14))
#define MODEM_SYSCON_RST_FE_M (BIT(14))
#define MODEM_SYSCON_RST_FE_V 0x1
#define MODEM_SYSCON_RST_FE_S 14
/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_FE_AHB (BIT(13))
#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13))
#define MODEM_SYSCON_RST_FE_AHB_V 0x1
#define MODEM_SYSCON_RST_FE_AHB_S 13
/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_FE_ADC (BIT(12))
#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12))
#define MODEM_SYSCON_RST_FE_ADC_V 0x1
#define MODEM_SYSCON_RST_FE_ADC_S 12
/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_FE_DAC (BIT(11))
#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11))
#define MODEM_SYSCON_RST_FE_DAC_V 0x1
#define MODEM_SYSCON_RST_FE_DAC_S 11
/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10))
#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10))
#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1
#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10
/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_WIFIMAC (BIT(9))
#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9))
#define MODEM_SYSCON_RST_WIFIMAC_V 0x1
#define MODEM_SYSCON_RST_WIFIMAC_S 9
/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_RST_WIFIBB (BIT(8))
#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8))
#define MODEM_SYSCON_RST_WIFIBB_V 0x1
#define MODEM_SYSCON_RST_WIFIBB_S 8
#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14)
/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21))
#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21))
#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21
/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20))
#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20))
#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20
/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19))
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19))
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19
/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18))
#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18))
#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1
#define MODEM_SYSCON_CLK_BTMAC_EN_S 18
/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17))
#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17))
#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1
#define MODEM_SYSCON_CLK_BTBB_EN_S 17
/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16))
#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16))
#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_BT_APB_EN_S 16
/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15))
#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15))
#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_APB_EN_S 15
/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14))
#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14))
#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_160M_EN_S 14
/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13))
#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13))
#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_80M_EN_S 13
/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12))
#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12))
#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_40M_EN_S 12
/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11))
#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11))
#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1
#define MODEM_SYSCON_CLK_FE_20M_EN_S 11
/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10))
#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10))
#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10
/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9))
#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9))
#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9
/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8))
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8))
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8
/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7))
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7))
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7
/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6))
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6))
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6
/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5))
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5))
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5
/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4))
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4))
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4
/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3))
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3))
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3
/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2))
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2))
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2
/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1))
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1))
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1
/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0
#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18)
/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S))
#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define MODEM_SYSCON_WIFI_BB_CFG_S 0
#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C)
/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */
/*description: .*/
#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF
#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S))
#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF
#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0
#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20)
/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */
/*description: .*/
#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF
#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S))
#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF
#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0
#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24)
/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2312050 ; */
/*description: .*/
#define MODEM_SYSCON_DATE 0x0FFFFFFF
#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S))
#define MODEM_SYSCON_DATE_V 0xFFFFFFF
#define MODEM_SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif

174
components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h Normal file
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@ -0,0 +1,174 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t reg_clk_en : 1;
uint32_t reg_modem_ant_force_sel_bt : 1;
uint32_t reg_modem_ant_force_sel_wifi : 1;
uint32_t reg_fpga_debug_clkswitch : 1;
uint32_t reg_fpga_debug_clk80 : 1;
uint32_t reg_fpga_debug_clk40 : 1;
uint32_t reg_fpga_debug_clk20 : 1;
uint32_t reg_fpga_debug_clk10 : 1;
uint32_t reg_modem_mem_mode_force : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} test_conf;
union {
struct {
uint32_t reg_pwdet_sar_clock_ena : 1;
uint32_t reg_pwdet_clk_div_num : 8;
uint32_t reg_clk_tx_dac_inv_ena : 1;
uint32_t reg_clk_rx_adc_inv_ena : 1;
uint32_t reg_clk_pwdet_adc_inv_ena : 1;
uint32_t reg_clk_i2c_mst_sel_160m : 1;
uint32_t reserved13 : 8;
uint32_t reg_clk_data_dump_mux : 1;
uint32_t reg_clk_etm_en : 1;
uint32_t reg_clk_zb_apb_en : 1;
uint32_t reg_clk_zbmac_en : 1;
uint32_t reg_clk_modem_sec_ecb_en : 1;
uint32_t reg_clk_modem_sec_ccm_en : 1;
uint32_t reg_clk_modem_sec_bah_en : 1;
uint32_t reg_clk_modem_sec_apb_en : 1;
uint32_t reg_clk_modem_sec_en : 1;
uint32_t reg_clk_ble_timer_en : 1;
uint32_t reg_clk_data_dump_en : 1;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reg_clk_wifibb_fo : 1;
uint32_t reg_clk_wifimac_fo : 1;
uint32_t reg_clk_wifi_apb_fo : 1;
uint32_t reg_clk_fe_fo : 1;
uint32_t reg_clk_fe_apb_fo : 1;
uint32_t reg_clk_btbb_fo : 1;
uint32_t reg_clk_btmac_fo : 1;
uint32_t reg_clk_bt_apb_fo : 1;
uint32_t reg_clk_zbmac_fo : 1;
uint32_t reg_clk_zbmac_apb_fo : 1;
uint32_t reserved10 : 13;
uint32_t reserved23 : 1;
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t reg_clk_etm_fo : 1;
uint32_t reg_clk_modem_sec_fo : 1;
uint32_t reg_clk_ble_timer_fo : 1;
uint32_t reg_clk_data_dump_fo : 1;
};
uint32_t val;
} clk_conf_force_on;
union {
struct {
uint32_t reserved0 : 8;
uint32_t reg_clk_zb_st_map : 4;
uint32_t reg_clk_fe_st_map : 4;
uint32_t reg_clk_bt_st_map : 4;
uint32_t reg_clk_wifi_st_map : 4;
uint32_t reg_clk_modem_peri_st_map : 4;
uint32_t reg_clk_modem_apb_st_map : 4;
};
uint32_t val;
} clk_conf_power_st;
union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
uint32_t reserved2 : 1;
uint32_t reserved3 : 1;
uint32_t reserved4 : 1;
uint32_t reserved5 : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t reg_rst_wifibb : 1;
uint32_t reg_rst_wifimac : 1;
uint32_t reg_rst_fe_pwdet_adc : 1;
uint32_t reg_rst_fe_dac : 1;
uint32_t reg_rst_fe_adc : 1;
uint32_t reg_rst_fe_ahb : 1;
uint32_t reg_rst_fe : 1;
uint32_t reg_rst_btmac_apb : 1;
uint32_t reg_rst_btmac : 1;
uint32_t reg_rst_btbb_apb : 1;
uint32_t reg_rst_btbb : 1;
uint32_t reserved19 : 3;
uint32_t reg_rst_etm : 1;
uint32_t reg_rst_zbmac_apb : 1;
uint32_t reg_rst_zbmac : 1;
uint32_t reg_rst_modem_ecb : 1;
uint32_t reg_rst_modem_ccm : 1;
uint32_t reg_rst_modem_bah : 1;
uint32_t reserved28 : 1;
uint32_t reg_rst_modem_sec : 1;
uint32_t reg_rst_ble_timer : 1;
uint32_t reg_rst_data_dump : 1;
};
uint32_t val;
} modem_rst_conf;
union {
struct {
uint32_t reg_clk_wifibb_22m_en : 1;
uint32_t reg_clk_wifibb_40m_en : 1;
uint32_t reg_clk_wifibb_44m_en : 1;
uint32_t reg_clk_wifibb_80m_en : 1;
uint32_t reg_clk_wifibb_40x_en : 1;
uint32_t reg_clk_wifibb_80x_en : 1;
uint32_t reg_clk_wifibb_40x1_en : 1;
uint32_t reg_clk_wifibb_80x1_en : 1;
uint32_t reg_clk_wifibb_160x1_en : 1;
uint32_t reg_clk_wifimac_en : 1;
uint32_t reg_clk_wifi_apb_en : 1;
uint32_t reg_clk_fe_20m_en : 1;
uint32_t reg_clk_fe_40m_en : 1;
uint32_t reg_clk_fe_80m_en : 1;
uint32_t reg_clk_fe_160m_en : 1;
uint32_t reg_clk_fe_apb_en : 1;
uint32_t reg_clk_bt_apb_en : 1;
uint32_t reg_clk_btbb_en : 1;
uint32_t reg_clk_btmac_en : 1;
uint32_t reg_clk_fe_pwdet_adc_en : 1;
uint32_t reg_clk_fe_adc_en : 1;
uint32_t reg_clk_fe_dac_en : 1;
uint32_t reserved22 : 1;
uint32_t reserved23 : 1;
uint32_t reserved24 : 8;
};
uint32_t val;
} clk_conf1;
uint32_t wifi_bb_cfg;
uint32_t mem_rf1_conf;
uint32_t mem_rf2_conf;
union {
struct {
uint32_t reg_date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
} modem_syscon_dev_t;
extern modem_syscon_dev_t MODEM_SYSCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

9
components/soc/esp32c5/mp/include/modem/reg_base.h Normal file
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@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A9C00
#define DR_REG_MODEM_LPCON_BASE 0x600AF000

5
components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
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@ -52,9 +52,8 @@ PROVIDE ( HP_APM = 0x60099000 );
PROVIDE ( LP_APM0 = 0x60099800 );
PROVIDE ( MISC = 0x6009F000 );
/* TODO: [ESP32C5] IDF-8845 Check the address */
PROVIDE ( IEEE802154 = 0x600A3000 );
PROVIDE ( MODEM_SYSCON = 0x600A9800 );
PROVIDE ( IEEE802154 = 0x600A3000 ); /* TODO: [ESP32C5] IDF-9140 Check the address */
PROVIDE ( MODEM_SYSCON = 0x600A9C00 );
PROVIDE ( MODEM_LPCON = 0x600AF000 );
PROVIDE ( MODEM0 = 0x600A0000 );