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bootloader, esp32: add workaround for Tensilica erratum 572

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If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
This commit is contained in:
Ivan Grokhotkov 2018-11-01 11:30:48 +08:00
parent 8c1d9e70b5
commit b4939b1121
4 changed files with 23 additions and 0 deletions
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1
components/bootloader_support/src/bootloader_init.c
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@ -71,6 +71,7 @@ static void wdt_reset_check(void);
esp_err_t bootloader_init() esp_err_t bootloader_init()
{ {
cpu_configure_region_protection(); cpu_configure_region_protection();
cpu_init_memctl();
/* Sanity check that static RAM is after the stack */ /* Sanity check that static RAM is after the stack */
#ifndef NDEBUG #ifndef NDEBUG

2
components/esp32/cpu_start.c
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@ -119,6 +119,7 @@ void IRAM_ATTR call_start_cpu0()
RESET_REASON rst_reas[2]; RESET_REASON rst_reas[2];
#endif #endif
cpu_configure_region_protection(); cpu_configure_region_protection();
cpu_init_memctl();
//Move exception vectors to IRAM //Move exception vectors to IRAM
asm volatile (\ asm volatile (\
@ -235,6 +236,7 @@ void IRAM_ATTR call_start_cpu1()
ets_set_appcpu_boot_addr(0); ets_set_appcpu_boot_addr(0);
cpu_configure_region_protection(); cpu_configure_region_protection();
cpu_init_memctl();
#if CONFIG_CONSOLE_UART_NONE #if CONFIG_CONSOLE_UART_NONE
ets_install_putc1(NULL); ets_install_putc1(NULL);

11
components/esp32/include/xtensa/config/core.h
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@ -1401,5 +1401,16 @@ extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
#define XCHAL_ERRATUM_497 0 #define XCHAL_ERRATUM_497 0
#endif #endif
/*
* Erratum 572 (releases TBD, but present in ESP32)
* Disable zero-overhead loop buffer to prevent rare illegal instruction
* exceptions while executing zero-overhead loops.
*/
#if ( XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 )
#define XCHAL_ERRATUM_572 1
#else
#define XCHAL_ERRATUM_572 0
#endif
#endif /*XTENSA_CONFIG_CORE_H*/ #endif /*XTENSA_CONFIG_CORE_H*/

9
components/soc/esp32/include/soc/cpu.h
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@ -19,6 +19,7 @@
#include <stdbool.h> #include <stdbool.h>
#include <stddef.h> #include <stddef.h>
#include "xtensa/corebits.h" #include "xtensa/corebits.h"
#include "xtensa/config/core.h"
/* C macros for xtensa special register read/write/exchange */ /* C macros for xtensa special register read/write/exchange */
@ -51,6 +52,14 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
} }
static inline void cpu_init_memctl()
{
#if XCHAL_ERRATUM_572
uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
WSR(MEMCTL, memctl);
#endif // XCHAL_ERRATUM_572
}
/** /**
* @brief Configure memory region protection * @brief Configure memory region protection
* *