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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Add support for esp32h2 beta2
This commit is contained in:
GengYuchao
parent
e1d07c0cf2
commit
b474c83840
@ -697,7 +697,11 @@ if(CONFIG_BT_ENABLED)
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"-L${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
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target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
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elseif(CONFIG_IDF_TARGET_ESP32H2)
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add_prebuilt_library(nimblelib "controller/lib_esp32h2/esp32h2-bt-lib/libble_app.a")
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if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
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add_prebuilt_library(nimblelib "controller/lib_esp32h2/esp32h2-bt-lib/beta1/libble_app.a")
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elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
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add_prebuilt_library(nimblelib "controller/lib_esp32h2/esp32h2-bt-lib/beta2/libble_app.a")
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endif()
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target_link_libraries(${COMPONENT_LIB} PRIVATE nimblelib)
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elseif(CONFIG_IDF_TARGET_ESP32C2)
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add_prebuilt_library(nimblelib "controller/lib_esp32c2/esp32c2-bt-lib/libble_app.a")
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@ -35,6 +35,7 @@
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#include "esp_pm.h"
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#include "esp_phy_init.h"
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#include "soc/system_reg.h"
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#include "soc/clkrst_reg.h"
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#include "hci_uart.h"
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#include "bt_osi_mem.h"
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@ -57,9 +58,13 @@
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#define OSI_COEX_VERSION 0x00010006
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#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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#define EXT_FUNC_VERSION 0x20220125
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#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
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#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
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#define EXT_FUNC_VERSION 0xE0000001
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#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
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#endif
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/* Types definition
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************************************************************************
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*/
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@ -89,9 +94,11 @@ struct ext_funcs_t {
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void (* _task_delete)(void *task_handle);
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void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
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uint32_t (* _os_random)(void);
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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int (* _ecc_gen_key_pair)(uint8_t *pub, uint8_t *priv);
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int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y, const uint8_t *local_priv_key, uint8_t *dhkey);
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int (* _esp_reset_rpa_moudle)(void);
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#endif
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uint32_t magic;
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};
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@ -207,9 +214,11 @@ struct ext_funcs_t ext_funcs_ro = {
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._task_delete = task_delete_wrapper,
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._osi_assert = osi_assert_wrapper,
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._os_random = osi_random_wrapper,
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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._ecc_gen_key_pair = ble_sm_alg_gen_key_pair,
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._ecc_gen_dh_key = ble_sm_alg_gen_dhkey,
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._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
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#endif
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.magic = EXT_FUNC_MAGIC_VALUE,
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};
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@ -566,8 +575,17 @@ void controller_sleep_deinit(void)
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}
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
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void periph_module_etm_active()
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{
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/*This part for esp32h2 beta2*/
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REG_SET_BIT(SYSTEM_MODCLK_CONF_REG, SYSTEM_ETM_CLK_SEL | SYSTEM_ETM_CLK_ACTIVE ); //Active ETM clock
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}
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#endif
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esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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{
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if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
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ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
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return ESP_FAIL;
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@ -613,7 +631,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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/* Initialize default event queue */
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ble_npl_eventq_init(nimble_port_get_dflt_eventq());
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#endif
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periph_module_enable(PERIPH_BT_MODULE);
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
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// only use for esp32h2 beta2
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periph_module_etm_active();
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#endif
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// init phy
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esp_phy_enable();
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@ -8,6 +8,7 @@
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#include "esp_heap_caps.h"
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#include "sdkconfig.h"
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#include "esp_nimble_mem.h"
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#include "nimble/nimble_port.h"
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#include "host/ble_hs.h"
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static TaskHandle_t host_task_h;
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@ -19,6 +20,21 @@ static struct ble_npl_eventq g_eventq_dflt;
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static struct ble_npl_sem ble_hs_stop_sem;
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static struct ble_npl_event ble_hs_ev_stop;
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/**
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* Called when the host stop procedure has completed.
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*/
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static void
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ble_hs_stop_cb(int status, void *arg)
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{
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ble_npl_sem_release(&ble_hs_stop_sem);
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}
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static void
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nimble_port_stop_cb(struct ble_npl_event *ev)
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{
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ble_npl_sem_release(&ble_hs_stop_sem);
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}
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esp_err_t esp_nimble_init(void)
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{
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#if !SOC_ESP_NIMBLE_CONTROLLER
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@ -63,11 +79,11 @@ esp_err_t esp_nimble_disable(void)
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ble_npl_sem_init(&ble_hs_stop_sem, 0);
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/* Initiate a host stop procedure. */
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rc = ble_hs_stop(&stop_listener, ble_hs_stop_cb,
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err = ble_hs_stop(&stop_listener, ble_hs_stop_cb,
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NULL);
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if (rc != 0) {
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if (err != 0) {
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ble_npl_sem_deinit(&ble_hs_stop_sem);
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return rc;
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return err;
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}
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/* Wait till the host stop procedure is complete */
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@ -118,9 +118,13 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_
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*/
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esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type);
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#define CONFIG_VERSION 0x20220409
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#define CONFIG_MAGIC 0x5A5AA5A5
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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#define CONFIG_VERSION 0x20220409
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#define CONFIG_MAGIC 0x5A5AA5A5
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#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
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#define CONFIG_VERSION 0x20211021
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#define CONFIG_MAGIC 0x5A5AA5A5
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#endif
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/**
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* @brief Controller config options, depend on config mask.
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* Config mask indicate which functions enabled, this means
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@ -169,12 +173,16 @@ typedef struct {
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uint8_t ble_hci_uart_uart_parity;
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uint8_t enable_tx_cca;
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uint8_t cca_rssi_thresh;
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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uint8_t cca_drop_mode;
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int8_t cca_low_tx_pwr;
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#endif
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uint8_t sleep_en;
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uint8_t coex_phy_coded_tx_rx_time_limit;
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uint8_t dis_scan_backoff;
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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uint8_t scan_classify_filter_enable;
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#endif
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uint32_t config_magic;
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} esp_bt_controller_config_t;
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@ -196,7 +196,10 @@ extern "C" {
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#if CONFIG_RTC_CLK_SRC_EXT_CRYS
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#define RTC_FREQ_N (32768) /* in Hz */
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#else
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#pragma message "RTC clock source not available"
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#define RTC_FREQ_N (32000) /* in Hz */
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#if CONFIG_RTC_CLK_SRC_EXT_OSC || CONFIG_RTC_CLK_SRC_INT_RC32K
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#pragma message "RTC clock source may not available"
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#endif
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#endif
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