From b4727a87651a26736b8eb046a2a9ea06b94b35d6 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 29 Nov 2018 15:15:21 +0800 Subject: [PATCH] =?UTF-8?q?soc/rtc=5Fclk:=20don=E2=80=99t=20clear=20DPORT?= =?UTF-8?q?=5FCPUPERIOD=5FSEL=20when=20switching=20to=20XTAL?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this. --- components/soc/esp32/rtc_clk.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 8c2948553d..3a96c75e20 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -395,7 +395,6 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div) REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1); /* switch clock source */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); /* clear DPORT_CPUPERIOD_SEL */ rtc_clk_apb_freq_update(freq * MHZ); /* lower the voltage */ if (freq <= 2) { @@ -411,7 +410,6 @@ static void rtc_clk_cpu_freq_to_8m() REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M); - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); }