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i2s: fix apll bugs introduced in 'refactor/i2s_driver'
Closes https://github.com/espressif/esp-idf/issues/7529
This commit is contained in:
laokaiyao
parent
df1b524d07
commit
b3193e233c
@ -155,7 +155,7 @@ static int _i2s_adc_channel = -1;
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-------------------------------------------------------------
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I2S clock operation
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-------------------------------------------------------------
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- [helper] i2s_get_source_clock
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- [helper] i2s_config_source_clock
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- [helper] i2s_calculate_adc_dac_clock
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- [helper] i2s_calculate_pdm_tx_clock
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- [helper] i2s_calculate_pdm_rx_clock
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@ -889,6 +889,28 @@ esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num)
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I2S clock operation
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-------------------------------------------------------------*/
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#if SOC_I2S_SUPPORTS_APLL
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/**
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* @brief Get APLL frequency
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*/
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static float i2s_apll_get_freq(int bits_per_sample, int sdm0, int sdm1, int sdm2, int odir)
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{
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int f_xtal = (int)rtc_clk_xtal_freq_get() * 1000000;
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#if CONFIG_IDF_TARGET_ESP32
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/* ESP32 rev0 silicon issue for APLL range/accuracy, please see ESP32 ECO document for more information on this */
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if (esp_efuse_get_chip_ver() == 0) {
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sdm0 = 0;
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sdm1 = 0;
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}
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#endif
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float fout = f_xtal * (sdm2 + sdm1 / 256.0f + sdm0 / 65536.0f + 4);
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if (fout < SOC_I2S_APLL_MIN_FREQ || fout > SOC_I2S_APLL_MAX_FREQ) {
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return SOC_I2S_APLL_MAX_FREQ;
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}
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float fpll = fout / (2 * (odir + 2)); //== fi2s (N=1, b=0, a=1)
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return fpll / 2;
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}
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/**
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* @brief APLL calculate function, was described by following:
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* APLL Output frequency is given by the formula:
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@ -919,30 +941,6 @@ esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num)
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* @param[out] sdm1 The sdm 1
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* @param[out] sdm2 The sdm 2
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* @param[out] odir The odir
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*
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* @return ESP_ERR_INVALID_ARG or ESP_OK
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*/
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static float i2s_apll_get_division_coefficient(int bits_per_sample, int sdm0, int sdm1, int sdm2, int odir)
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{
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int f_xtal = (int)rtc_clk_xtal_freq_get() * 1000000;
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#if CONFIG_IDF_TARGET_ESP32
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/* ESP32 rev0 silicon issue for APLL range/accuracy, please see ESP32 ECO document for more information on this */
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if (esp_efuse_get_chip_ver() == 0) {
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sdm0 = 0;
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sdm1 = 0;
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}
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#endif
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float fout = f_xtal * (sdm2 + sdm1 / 256.0f + sdm0 / 65536.0f + 4);
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if (fout < SOC_I2S_APLL_MIN_FREQ || fout > SOC_I2S_APLL_MAX_FREQ) {
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return SOC_I2S_APLL_MAX_FREQ;
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}
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float fpll = fout / (2 * (odir + 2)); //== fi2s (N=1, b=0, a=1)
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return fpll / 2;
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}
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/**
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* @brief Calculate APLL parameters to get a closest frequency
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*/
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static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, int *sdm1, int *sdm2, int *odir)
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{
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@ -957,8 +955,8 @@ static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, in
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min_diff = SOC_I2S_APLL_MAX_FREQ;
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for (_sdm2 = 4; _sdm2 < 9; _sdm2 ++) {
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max_rate = i2s_apll_get_division_coefficient(bits_per_sample, 255, 255, _sdm2, 0);
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min_rate = i2s_apll_get_division_coefficient(bits_per_sample, 0, 0, _sdm2, 31);
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max_rate = i2s_apll_get_freq(bits_per_sample, 255, 255, _sdm2, 0);
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min_rate = i2s_apll_get_freq(bits_per_sample, 0, 0, _sdm2, 31);
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avg = (max_rate + min_rate) / 2;
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if (abs(avg - rate) < min_diff) {
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min_diff = abs(avg - rate);
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@ -967,8 +965,8 @@ static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, in
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}
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min_diff = SOC_I2S_APLL_MAX_FREQ;
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for (_odir = 0; _odir < 32; _odir ++) {
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max_rate = i2s_apll_get_division_coefficient(bits_per_sample, 255, 255, *sdm2, _odir);
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min_rate = i2s_apll_get_division_coefficient(bits_per_sample, 0, 0, *sdm2, _odir);
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max_rate = i2s_apll_get_freq(bits_per_sample, 255, 255, *sdm2, _odir);
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min_rate = i2s_apll_get_freq(bits_per_sample, 0, 0, *sdm2, _odir);
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avg = (max_rate + min_rate) / 2;
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if (abs(avg - rate) < min_diff) {
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min_diff = abs(avg - rate);
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@ -977,8 +975,8 @@ static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, in
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}
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min_diff = SOC_I2S_APLL_MAX_FREQ;
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for (_sdm2 = 4; _sdm2 < 9; _sdm2 ++) {
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max_rate = i2s_apll_get_division_coefficient(bits_per_sample, 255, 255, _sdm2, *odir);
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min_rate = i2s_apll_get_division_coefficient(bits_per_sample, 0, 0, _sdm2, *odir);
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max_rate = i2s_apll_get_freq(bits_per_sample, 255, 255, _sdm2, *odir);
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min_rate = i2s_apll_get_freq(bits_per_sample, 0, 0, _sdm2, *odir);
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avg = (max_rate + min_rate) / 2;
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if (abs(avg - rate) < min_diff) {
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min_diff = abs(avg - rate);
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@ -988,8 +986,8 @@ static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, in
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min_diff = SOC_I2S_APLL_MAX_FREQ;
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for (_sdm1 = 0; _sdm1 < 256; _sdm1 ++) {
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max_rate = i2s_apll_get_division_coefficient(bits_per_sample, 255, _sdm1, *sdm2, *odir);
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min_rate = i2s_apll_get_division_coefficient(bits_per_sample, 0, _sdm1, *sdm2, *odir);
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max_rate = i2s_apll_get_freq(bits_per_sample, 255, _sdm1, *sdm2, *odir);
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min_rate = i2s_apll_get_freq(bits_per_sample, 0, _sdm1, *sdm2, *odir);
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avg = (max_rate + min_rate) / 2;
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if (abs(avg - rate) < min_diff) {
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min_diff = abs(avg - rate);
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@ -999,7 +997,7 @@ static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, in
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min_diff = SOC_I2S_APLL_MAX_FREQ;
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for (_sdm0 = 0; _sdm0 < 256; _sdm0 ++) {
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avg = i2s_apll_get_division_coefficient(bits_per_sample, _sdm0, *sdm1, *sdm2, *odir);
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avg = i2s_apll_get_freq(bits_per_sample, _sdm0, *sdm1, *sdm2, *odir);
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if (abs(avg - rate) < min_diff) {
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min_diff = abs(avg - rate);
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*sdm0 = _sdm0;
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@ -1009,15 +1007,17 @@ static void i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm0, in
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#endif
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/**
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* @brief Get I2S source clock
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* @brief Config I2S source clock and get its frequency
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*
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* @param i2s_num I2S device number
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* @param use_apll Whether use apll, only take effect when chip supports
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* @param fixed_mclk Whether use apll, only take effect when 'use_apll' is true
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* @param mclk module clock
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*
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* @return
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* - Clock frequency
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* - 0 use I2S_CLK_APLL as clock source, no I2S system clock to set
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* - I2S_LL_BASE_CLK use I2S_CLK_D2CLK as clock source, return APB clock frequency
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*/
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static uint32_t i2s_get_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t fixed_mclk)
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static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
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{
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#if SOC_I2S_SUPPORTS_APLL
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if (use_apll) {
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@ -1025,20 +1025,18 @@ static uint32_t i2s_get_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t
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int sdm1 = 0;
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int sdm2 = 0;
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int odir = 0;
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if (fixed_mclk == 0) {
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ESP_LOGI(TAG, "fixed_mclk is not set, set to 128 MHz as default");
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fixed_mclk = 128000000;
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}else if ((fixed_mclk / p_i2s[i2s_num]->hal_cfg.chan_bits / 16) < SOC_I2S_APLL_MIN_RATE) {
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ESP_LOGW(TAG, "fixed_mclk is too small, use I2S_CLK_D2CLK as default clock source");
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goto err;
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if ((mclk / p_i2s[i2s_num]->hal_cfg.chan_bits / p_i2s[i2s_num]->hal_cfg.total_chan) < SOC_I2S_APLL_MIN_RATE) {
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ESP_LOGE(TAG, "mclk is too small");
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return 0;
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}
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i2s_apll_calculate_fi2s(p_i2s[i2s_num]->hal_cfg.sample_rate, p_i2s[i2s_num]->hal_cfg.sample_bits,
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&sdm0, &sdm1, &sdm2, &odir);
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i2s_apll_calculate_fi2s(mclk, p_i2s[i2s_num]->hal_cfg.sample_bits, &sdm0, &sdm1, &sdm2, &odir);
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ESP_LOGI(TAG, "APLL Enabled, coefficient: sdm0=%d, sdm1=%d, sdm2=%d, odir=%d", sdm0, sdm1, sdm2, odir);
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rtc_clk_apll_enable(true, sdm0, sdm1, sdm2, odir);
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return fixed_mclk;
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/* Set I2S_APLL as I2S module clock source */
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i2s_hal_set_clock_src(&(p_i2s[i2s_num]->hal), I2S_CLK_APLL);
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/* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */
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return 0;
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}
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err:
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/* Set I2S_D2CLK (160M) as default I2S module clock source */
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i2s_hal_set_clock_src(&(p_i2s[i2s_num]->hal), I2S_CLK_D2CLK);
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return I2S_LL_BASE_CLK;
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@ -1067,20 +1065,22 @@ static esp_err_t i2s_calculate_adc_dac_clock(int i2s_num, i2s_hal_clock_cfg_t *c
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ESP_RETURN_ON_FALSE(clk_cfg, ESP_ERR_INVALID_ARG, TAG, "input clk_cfg is NULL");
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ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->hal_cfg.mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN), ESP_ERR_INVALID_ARG, TAG, "current mode is not built-in ADC/DAC");
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/* Set I2S module clock */
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clk_cfg->sclk = i2s_get_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, p_i2s[i2s_num]->fixed_mclk);
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR;
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/* Set I2S bit clock */
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clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR * 2;
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/* Get I2S master clock, mclk = bclk * bclk_div */
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clk_cfg->mclk = clk_cfg->bclk * clk_cfg->bclk_div;
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR;
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/* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */
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clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
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p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div;
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/* Calculate bclk_div = mclk / bclk */
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clk_cfg->bclk_div = clk_cfg->mclk / clk_cfg->bclk;
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/* Get I2S system clock by config source clock */
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clk_cfg->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_cfg->mclk);
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/* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
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clk_cfg->mclk_div = clk_cfg->sclk / clk_cfg->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "I2S module get clock failed");
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ESP_RETURN_ON_FALSE(clk_cfg->bclk * clk_cfg->bclk_div <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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ESP_RETURN_ON_FALSE(!clk_cfg->sclk || clk_cfg->mclk <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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return ESP_OK;
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}
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@ -1101,23 +1101,24 @@ static esp_err_t i2s_calculate_pdm_tx_clock(int i2s_num, i2s_hal_clock_cfg_t *cl
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ESP_RETURN_ON_FALSE(clk_cfg, ESP_ERR_INVALID_ARG, TAG, "input clk_cfg is NULL");
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ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_PDM, ESP_ERR_INVALID_ARG, TAG, "current mode is not PDM");
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/* Set I2S module clock */
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clk_cfg->sclk = i2s_get_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, p_i2s[i2s_num]->fixed_mclk);
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = 8;
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int fp = i2s_hal_get_tx_pdm_fp(&(p_i2s[i2s_num]->hal));
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int fs = i2s_hal_get_tx_pdm_fs(&(p_i2s[i2s_num]->hal));
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/* Set I2S bit clock */
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clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_PDM_BCK_FACTOR * fp / fs;
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/* Get I2S master clock, mclk = bclk * bclk_div */
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clk_cfg->mclk = clk_cfg->bclk * clk_cfg->bclk_div;
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = 8;
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/* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */
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clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
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p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div;
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/* Calculate bclk_div = mclk / bclk */
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clk_cfg->bclk_div = clk_cfg->mclk / clk_cfg->bclk;
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/* Get I2S system clock by config source clock */
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clk_cfg->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_cfg->mclk);
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/* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
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clk_cfg->mclk_div = clk_cfg->sclk / clk_cfg->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "I2S module clock is 0");
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ESP_RETURN_ON_FALSE(clk_cfg->bclk * clk_cfg->bclk_div <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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ESP_RETURN_ON_FALSE(!clk_cfg->sclk || clk_cfg->mclk <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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return ESP_OK;
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}
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@ -1138,23 +1139,24 @@ static esp_err_t i2s_calculate_pdm_rx_clock(int i2s_num, i2s_hal_clock_cfg_t *cl
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ESP_RETURN_ON_FALSE(clk_cfg, ESP_ERR_INVALID_ARG, TAG, "input clk_cfg is NULL");
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ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_PDM, ESP_ERR_INVALID_ARG, TAG, "current mode is not PDM");
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/* Set I2S module clock */
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clk_cfg->sclk = i2s_get_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, p_i2s[i2s_num]->fixed_mclk);
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = 8;
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i2s_pdm_dsr_t dsr;
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i2s_hal_get_rx_pdm_dsr(&(p_i2s[i2s_num]->hal), &dsr);
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/* Set I2S bit clock */
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clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_PDM_BCK_FACTOR * (dsr == I2S_PDM_DSR_16S ? 2 : 1);
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/* Get I2S master clock, mclk = bclk * bclk_div */
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clk_cfg->mclk = clk_cfg->bclk * clk_cfg->bclk_div;
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = 8;
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/* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */
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clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
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p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div;
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/* Calculate bclk_div = mclk / bclk */
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clk_cfg->bclk_div = clk_cfg->mclk / clk_cfg->bclk;
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/* Get I2S system clock by config source clock */
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clk_cfg->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_cfg->mclk);
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/* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
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clk_cfg->mclk_div = clk_cfg->sclk / clk_cfg->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "I2S module clock is 0");
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ESP_RETURN_ON_FALSE(clk_cfg->bclk * clk_cfg->bclk_div <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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ESP_RETURN_ON_FALSE(!clk_cfg->sclk || clk_cfg->mclk <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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return ESP_OK;
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}
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@ -1177,10 +1179,8 @@ static esp_err_t i2s_calculate_common_clock(int i2s_num, i2s_hal_clock_cfg_t *cl
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uint32_t chan_num = p_i2s[i2s_num]->hal_cfg.total_chan < 2 ? 2 : p_i2s[i2s_num]->hal_cfg.total_chan;
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uint32_t chan_bit = p_i2s[i2s_num]->hal_cfg.chan_bits;
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uint32_t multi;
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/* Set I2S module clock */
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clk_cfg->sclk = i2s_get_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, p_i2s[i2s_num]->fixed_mclk);
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/* Calculate multiple */
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if (p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_MASTER) {
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if (p_i2s[i2s_num]->hal_cfg.mode & I2S_MODE_MASTER || p_i2s[i2s_num]->use_apll) {
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multi = p_i2s[i2s_num]->mclk_multiple ? p_i2s[i2s_num]->mclk_multiple : I2S_MCLK_MULTIPLE_256;
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} else {
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||||
/* Only need to set the multiple of mclk to sample rate for MASTER mode,
|
||||
@ -1201,16 +1201,18 @@ static esp_err_t i2s_calculate_common_clock(int i2s_num, i2s_hal_clock_cfg_t *cl
|
||||
}
|
||||
/* Set I2S bit clock */
|
||||
clk_cfg->bclk = rate * chan_num * chan_bit;
|
||||
/* Set I2S bit clock division according to the sample rate and multiple of mclk */
|
||||
clk_cfg->bclk_div = rate * multi / clk_cfg->bclk;
|
||||
/* Get I2S master clock, mclk = bclk * bclk_div = rate * multiple */
|
||||
clk_cfg->mclk = clk_cfg->bclk * clk_cfg->bclk_div;
|
||||
/* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */
|
||||
clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
|
||||
p_i2s[i2s_num]->fixed_mclk : (rate * multi);
|
||||
/* Calculate bclk_div = mclk / bclk */
|
||||
clk_cfg->bclk_div = clk_cfg->mclk / clk_cfg->bclk;
|
||||
/* Get I2S system clock by config source clock */
|
||||
clk_cfg->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_cfg->mclk);
|
||||
/* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */
|
||||
clk_cfg->mclk_div = clk_cfg->sclk / clk_cfg->mclk;
|
||||
|
||||
/* Check if the configuration is correct */
|
||||
ESP_RETURN_ON_FALSE(clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "I2S module clock is 0");
|
||||
ESP_RETURN_ON_FALSE(clk_cfg->bclk * clk_cfg->bclk_div <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
|
||||
ESP_RETURN_ON_FALSE(!clk_cfg->sclk || clk_cfg->mclk <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1965,7 +1967,6 @@ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config,
|
||||
/* Step 6: Initialise i2s event queue if user needs */
|
||||
if (i2s_queue) {
|
||||
pre_alloc_i2s_obj->i2s_queue = xQueueCreate(queue_size, sizeof(i2s_event_t));
|
||||
printf("queue handle %p\n", pre_alloc_i2s_obj->i2s_queue);
|
||||
ESP_GOTO_ON_FALSE(pre_alloc_i2s_obj->i2s_queue, ESP_ERR_NO_MEM, err, TAG, "I2S queue create failed");
|
||||
*((QueueHandle_t *) i2s_queue) = pre_alloc_i2s_obj->i2s_queue;
|
||||
ESP_LOGI(TAG, "queue free spaces: %d", uxQueueSpacesAvailable(pre_alloc_i2s_obj->i2s_queue));
|
||||
|
||||
@ -34,7 +34,9 @@ static void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mc
|
||||
cal->mclk_div = clk_cfg->mclk_div;
|
||||
cal->a = 1;
|
||||
cal->b = 0;
|
||||
/* If sclk = 0 means APLL clock applied, mclk_div should set to 1 */
|
||||
if (!clk_cfg->sclk) {
|
||||
cal->mclk_div = 1;
|
||||
return;
|
||||
}
|
||||
uint32_t freq_diff = clk_cfg->sclk - clk_cfg->mclk * cal->mclk_div;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user