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https://github.com/espressif/esp-idf.git
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rtc_clk: Fix wrong RC_FAST and RC_SLOW clock frequency values on ESP32C3 and ESP32S3
This commit is contained in:
Song Ruo Jing
parent
4c550fd79f
commit
b2f4fc022a
@ -15,7 +15,10 @@
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#define DPORT_SOC_CLK_SEL_PLL 1
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#define DPORT_SOC_CLK_SEL_8M 2
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#define RTC_FAST_CLK_FREQ_8M 8500000
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// On esp32c3, RC_FAST_CLK has a freq of ~17.5MHz
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#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000
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// '8M' does not mean the actual freq, it only represents the clock source is RC_FAST_CLK.
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#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
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#ifdef __cplusplus
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extern "C" {
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@ -19,7 +19,10 @@
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#define DPORT_SOC_CLK_SEL_PLL 1
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#define DPORT_SOC_CLK_SEL_8M 2
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#define RTC_FAST_CLK_FREQ_8M 8500000
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// On esp32s3, RC_FAST_CLK has a freq of ~17.5MHz
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#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000
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// '8M' does not mean the actual freq, it only represents the clock source is RC_FAST_CLK.
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#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
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#ifdef __cplusplus
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extern "C" {
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@ -49,7 +49,10 @@ extern "C" {
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#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
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#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
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#define RTC_SLOW_CLK_FREQ_150K 150000
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// On esp32c3, RC_SLOW_CLK has a freq of ~136kHz
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000
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// '150K' does not mean the actual freq, it represents the clock source is RC_SLOW_CLK. RC_SLOW_CLK has a freq of ~150kHz only on esp32.
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#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
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#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256)
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#define RTC_SLOW_CLK_FREQ_32K 32768
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@ -74,7 +77,7 @@ extern "C" {
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#define DELAY_SLOW_CLK_SWITCH 300
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#define DELAY_8M_ENABLE 50
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/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
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/* Number of RC_FAST_D256 clock cycles to use for XTAL frequency estimation.
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* 10 cycles will take approximately 300 microseconds.
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*/
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#define XTAL_FREQ_EST_CYCLES 10
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@ -155,7 +158,7 @@ typedef enum {
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typedef enum {
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RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
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RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
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RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
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RTC_CPU_FREQ_SRC_8M, //!< Internal 17.5M RC oscillator
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RTC_CPU_FREQ_SRC_APLL //!< APLL
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} rtc_cpu_freq_src_t;
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@ -173,9 +176,9 @@ typedef struct rtc_cpu_freq_config_s {
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* @brief RTC SLOW_CLK frequency values
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*/
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typedef enum {
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RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
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RTC_SLOW_FREQ_RTC = 0, //!< Internal 136 kHz RC oscillator
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RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
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RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
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RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 17.5 MHz RC oscillator, divided by 256
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} rtc_slow_freq_t;
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/**
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@ -183,11 +186,11 @@ typedef enum {
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*/
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typedef enum {
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RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
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RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
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RTC_FAST_FREQ_8M = 1, //!< Internal 17.5 MHz RC oscillator
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} rtc_fast_freq_t;
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/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
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#define RTC_FAST_CLK_FREQ_APPROX 8500000
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/* With the default value of CK8M_DFREQ, RTC_FAST clock frequency is 17.5 MHz +/- 7% */
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#define RTC_FAST_CLK_FREQ_APPROX 17500000
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#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
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@ -199,9 +202,9 @@ typedef enum {
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*/
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typedef enum {
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RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
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RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
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RTC_CAL_8MD256 = 1, //!< Internal 17.5 MHz RC oscillator, divided by 256
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RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
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RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
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RTC_CAL_INTERNAL_OSC = 3 //!< Internal 136 kHz oscillator
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} rtc_cal_sel_t;
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/**
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@ -213,9 +216,9 @@ typedef struct {
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rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
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rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
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uint32_t clk_rtc_clk_div : 8;
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uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
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uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
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uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
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uint32_t clk_8m_clk_div : 3; //!< RTC_FAST_CLK source RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~17.5MHz frequency)
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uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
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uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
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} rtc_clk_config_t;
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/**
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@ -333,31 +336,31 @@ bool rtc_clk_32k_enabled(void);
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void rtc_clk_32k_bootstrap(uint32_t cycle);
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/**
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* @brief Enable or disable 8 MHz internal oscillator
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* @brief Enable or disable 17.5 MHz internal oscillator
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*
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* Output from 8 MHz internal oscillator is passed into a configurable
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* Output from 17.5 MHz internal oscillator is passed into a configurable
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* divider, which by default divides the input clock frequency by 256.
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* Output of the divider may be used as RTC_SLOW_CLK source.
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* Output of the divider is referred to in register descriptions and code as
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* 8md256 or simply d256. Divider values other than 256 may be configured, but
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* this facility is not currently needed, so is not exposed in the code.
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*
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* When 8MHz/256 divided output is not needed, the divider should be disabled
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* When RC_FAST_D256 divided output is not needed, the divider should be disabled
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* to reduce power consumption.
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*
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* @param clk_8m_en true to enable 8MHz generator
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* @param clk_8m_en true to enable 17.5MHz generator
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* @param d256_en true to enable /256 divider
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*/
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void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
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/**
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* @brief Get the state of 8 MHz internal oscillator
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* @brief Get the state of 17.5 MHz internal oscillator
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* @return true if the oscillator is enabled
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*/
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bool rtc_clk_8m_enabled(void);
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/**
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* @brief Get the state of /256 divider which is applied to 8MHz clock
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* @brief Get the state of /256 divider which is applied to 17.5MHz clock
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* @return true if the divided output is enabled
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*/
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bool rtc_clk_8md256_enabled(void);
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@ -395,9 +398,9 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void);
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/**
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* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
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*
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* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
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* - if RTC_SLOW_FREQ_RTC is selected, returns 136000
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* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
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* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
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* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~68000
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*
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* rtc_clk_cal function can be used to get more precise value by comparing
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* RTC_SLOW_CLK frequency to the frequency of main XTAL.
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@ -568,22 +571,22 @@ uint64_t rtc_deep_slp_time_get(void);
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void rtc_clk_wait_for_slow_cycle(void);
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/**
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* @brief Enable the rtc digital 8M clock
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* @brief Enable the digital RC_FAST_CLK
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*
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* This function is used to enable the digital rtc 8M clock to support peripherals.
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* For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
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* This function is used to enable the digital RC_FAST clock to support peripherals.
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* For enabling the analog 17.5M clock, using `rtc_clk_8M_enable` function above.
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*/
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void rtc_dig_clk8m_enable(void);
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/**
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* @brief Disable the rtc digital 8M clock
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* @brief Disable the digital RC_FAST_CLK
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*
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* This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
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* This function is used to disable the digital RC_FAST clock, which is only used to support peripherals.
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*/
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void rtc_dig_clk8m_disable(void);
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/**
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* @brief Get whether the rtc digital 8M clock is enabled
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* @brief Get whether the digital RC_FAST_CLK is enabled
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*/
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bool rtc_dig_8m_enabled(void);
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@ -639,7 +642,7 @@ typedef struct {
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uint32_t wifi_pd_en : 1; //!< power down WiFi
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uint32_t bt_pd_en : 1; //!< power down BT
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uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
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uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
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uint32_t int_8m_pd_en : 1; //!< Power down Internal 17.5M oscillator
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uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
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uint32_t deep_slp : 1; //!< power down digital domain
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uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
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@ -669,7 +672,7 @@ typedef struct {
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#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
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#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
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#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
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#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
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#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 17.5M oscillator
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#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
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//These flags are not power domains, but will affect some sleep parameters
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@ -785,7 +788,7 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
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* RTC power and clock control initialization settings
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*/
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typedef struct {
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uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
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uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 17.5M clock to be ready
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uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
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uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
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uint32_t clkctl_init : 1; //!< Perform clock control related initialization
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@ -50,7 +50,10 @@ extern "C" {
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#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
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#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
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#define RTC_SLOW_CLK_FREQ_150K 150000
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// On esp32s3, RC_SLOW_CLK has a freq of ~136kHz
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000
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// '150K' does not mean the actual freq, it represents the clock source is RC_SLOW_CLK. RC_SLOW_CLK has a freq of ~150kHz only on esp32.
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#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
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#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256)
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#define RTC_SLOW_CLK_FREQ_32K 32768
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@ -75,7 +78,7 @@ extern "C" {
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#define DELAY_SLOW_CLK_SWITCH 300
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#define DELAY_8M_ENABLE 50
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/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
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/* Number of RC_FAST_D256 clock cycles to use for XTAL frequency estimation.
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* 10 cycles will take approximately 300 microseconds.
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*/
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#define XTAL_FREQ_EST_CYCLES 10
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@ -160,7 +163,7 @@ typedef enum {
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typedef enum {
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RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
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RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
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RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
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RTC_CPU_FREQ_SRC_8M, //!< Internal 17.5M RC oscillator
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RTC_CPU_FREQ_SRC_APLL //!< APLL
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} rtc_cpu_freq_src_t;
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@ -178,9 +181,9 @@ typedef struct rtc_cpu_freq_config_s {
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* @brief RTC SLOW_CLK frequency values
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*/
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typedef enum {
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RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
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RTC_SLOW_FREQ_RTC = 0, //!< Internal 136 kHz RC oscillator
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RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
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RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
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RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 17.5 MHz RC oscillator, divided by 256
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} rtc_slow_freq_t;
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/**
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@ -188,11 +191,11 @@ typedef enum {
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*/
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typedef enum {
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RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
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RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
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RTC_FAST_FREQ_8M = 1, //!< Internal 17.5 MHz RC oscillator
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} rtc_fast_freq_t;
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/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
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#define RTC_FAST_CLK_FREQ_APPROX 8500000
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/* With the default value of CK8M_DFREQ, RTC_FAST clock frequency is 17.5 MHz +/- 7% */
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#define RTC_FAST_CLK_FREQ_APPROX 17500000
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#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
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@ -204,9 +207,9 @@ typedef enum {
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*/
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typedef enum {
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RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
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RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
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RTC_CAL_8MD256 = 1, //!< Internal 17.5 MHz RC oscillator, divided by 256
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RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
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RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
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RTC_CAL_INTERNAL_OSC = 3 //!< Internal 136 kHz oscillator
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} rtc_cal_sel_t;
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/**
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@ -218,9 +221,9 @@ typedef struct {
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rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
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rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
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uint32_t clk_rtc_clk_div : 8;
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uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
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uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
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uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
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uint32_t clk_8m_clk_div : 3; //!< RTC_FAST_CLK source RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ～17.5MHz frequency)
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uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
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uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
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} rtc_clk_config_t;
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/**
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@ -346,31 +349,31 @@ bool rtc_clk_32k_enabled(void);
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void rtc_clk_32k_bootstrap(uint32_t cycle);
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/**
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* @brief Enable or disable 8 MHz internal oscillator
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* @brief Enable or disable 17.5 MHz internal oscillator
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*
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* Output from 8 MHz internal oscillator is passed into a configurable
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* Output from 17.5 MHz internal oscillator is passed into a configurable
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* divider, which by default divides the input clock frequency by 256.
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* Output of the divider may be used as RTC_SLOW_CLK source.
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* Output of the divider is referred to in register descriptions and code as
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* 8md256 or simply d256. Divider values other than 256 may be configured, but
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* this facility is not currently needed, so is not exposed in the code.
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*
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* When 8MHz/256 divided output is not needed, the divider should be disabled
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* When RC_FAST_D256 divided output is not needed, the divider should be disabled
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* to reduce power consumption.
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*
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* @param clk_8m_en true to enable 8MHz generator
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* @param clk_8m_en true to enable 17.5MHz generator
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* @param d256_en true to enable /256 divider
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*/
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void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
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/**
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* @brief Get the state of 8 MHz internal oscillator
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* @brief Get the state of 17.5 MHz internal oscillator
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* @return true if the oscillator is enabled
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*/
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bool rtc_clk_8m_enabled(void);
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/**
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* @brief Get the state of /256 divider which is applied to 8MHz clock
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* @brief Get the state of /256 divider which is applied to 17.5MHz clock
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* @return true if the divided output is enabled
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*/
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bool rtc_clk_8md256_enabled(void);
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@ -408,9 +411,9 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void);
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/**
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* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
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*
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* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
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* - if RTC_SLOW_FREQ_RTC is selected, returns 136000
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* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
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* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
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* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~68000
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*
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* rtc_clk_cal function can be used to get more precise value by comparing
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* RTC_SLOW_CLK frequency to the frequency of main XTAL.
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@ -580,22 +583,22 @@ uint64_t rtc_deep_slp_time_get(void);
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void rtc_clk_wait_for_slow_cycle(void);
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/**
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* @brief Enable the rtc digital 8M clock
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* @brief Enable the digital RC_FAST_CLK
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*
|
||||
* This function is used to enable the digital rtc 8M clock to support peripherals.
|
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* For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
|
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* This function is used to enable the digital RC_FAST clock to support peripherals.
|
||||
* For enabling the analog 17.5M clock, using `rtc_clk_8M_enable` function above.
|
||||
*/
|
||||
void rtc_dig_clk8m_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable the rtc digital 8M clock
|
||||
* @brief Disable the digital RC_FAST_CLK
|
||||
*
|
||||
* This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
|
||||
* This function is used to disable the digital RC_FAST clock, which is only used to support peripherals.
|
||||
*/
|
||||
void rtc_dig_clk8m_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Get whether the rtc digital 8M clock is enabled
|
||||
* @brief Get whether the digital RC_FAST_CLK is enabled
|
||||
*/
|
||||
bool rtc_dig_8m_enabled(void);
|
||||
|
||||
@ -651,7 +654,7 @@ typedef struct {
|
||||
uint32_t wifi_pd_en : 1; //!< power down WiFi
|
||||
uint32_t bt_pd_en : 1; //!< power down BT
|
||||
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
|
||||
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
|
||||
uint32_t int_8m_pd_en : 1; //!< Power down Internal 17.5M oscillator
|
||||
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
|
||||
uint32_t deep_slp : 1; //!< power down digital domain
|
||||
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
|
||||
@ -680,7 +683,7 @@ typedef struct {
|
||||
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
|
||||
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
|
||||
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
|
||||
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
|
||||
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 17.5M oscillator
|
||||
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
|
||||
|
||||
//These flags are not power domains, but will affect some sleep parameters
|
||||
@ -807,7 +810,7 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
|
||||
* RTC power and clock control initialization settings
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
|
||||
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 17.5M clock to be ready
|
||||
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
|
||||
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
|
||||
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
|
||||
|
||||
Loading…
Reference in New Issue
Block a user