diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c index 1ed38cc5c1..9f3d416b04 100644 --- a/components/driver/test/test_gpio.c +++ b/components/driver/test/test_gpio.c @@ -57,7 +57,7 @@ #define TEST_GPIO_EXT_OUT_IO 2 // default output GPIO #define TEST_GPIO_EXT_IN_IO 3 // default input GPIO #define TEST_GPIO_OUTPUT_PIN 1 -#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_21 +#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX #define TEST_GPIO_USB_DM_IO 18 // USB D- GPIO #define TEST_GPIO_USB_DP_IO 19 // USB D+ GPIO #define TEST_GPIO_INPUT_LEVEL_HIGH_PIN 10 @@ -756,11 +756,11 @@ static void gpio_isr_handler(void *arg) */ TEST_CASE("GPIO ISR service test", "[gpio][ignore]") { - static gpio_isr_param_t io9_param = { + gpio_isr_param_t io9_param = { .gpio_num = TEST_IO_9, .isr_cnt = 0, }; - static gpio_isr_param_t io10_param = { + gpio_isr_param_t io10_param = { .gpio_num = TEST_IO_10, .isr_cnt = 0, }; diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index 59639ef150..804e94a7b4 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -18,6 +18,7 @@ #include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/rtc_cntl_reg.h" +#include "soc/usb_serial_jtag_reg.h" #include "hal/gpio_types.h" #include "stdlib.h" @@ -25,17 +26,6 @@ extern "C" { #endif -/* - * The following defines are used to disable USB JTAG when pins 18 and pins 19 - * are set to be used as GPIO. - * See gpio_pad_select_gpio() below. - * - * TODO: Delete these definitions once the USB device registers definition is - * merged. - */ -#define USB_DEVICE_CONF0_REG (0x60043018) -#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) - // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -392,8 +382,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign */ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) { + // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { - CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(pin_name, func); } diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index a9b56f7c6a..1678689961 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -302,7 +302,6 @@ typedef enum { GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ GPIO_NUM_MAX, /** @endcond */ } gpio_num_t; diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/include/soc/io_mux_reg.h index e9a0795167..618f8fa5d3 100644 --- a/components/soc/esp32c3/include/soc/io_mux_reg.h +++ b/components/soc/esp32c3/include/soc/io_mux_reg.h @@ -138,9 +138,9 @@ #define SD_DATA2_GPIO_NUM 9 #define SD_DATA3_GPIO_NUM 10 -#define MAX_RTC_GPIO_NUM 0 -#define MAX_PAD_GPIO_NUM 22 -#define MAX_GPIO_NUM 22 +#define MAX_RTC_GPIO_NUM 5 +#define MAX_PAD_GPIO_NUM 21 +#define MAX_GPIO_NUM 25 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE #define PIN_CTRL (REG_IO_MUX_BASE +0x00) diff --git a/components/soc/esp32s2/gpio_periph.c b/components/soc/esp32s2/gpio_periph.c index 346984b57c..0e7fa4661b 100644 --- a/components/soc/esp32s2/gpio_periph.c +++ b/components/soc/esp32s2/gpio_periph.c @@ -62,7 +62,6 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { IO_MUX_GPIO44_REG, IO_MUX_GPIO45_REG, IO_MUX_GPIO46_REG, - 0, }; const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { @@ -113,5 +112,4 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { BIT(23), BIT(24), BIT(25), - BIT(26), }; diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 99911fac6c..1fe364aa5a 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -98,18 +98,18 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-S2 has 1 GPIO peripheral #define SOC_GPIO_PORT (1) -#define SOC_GPIO_PIN_COUNT (48) +#define SOC_GPIO_PIN_COUNT (47) -// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. +// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register. // On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // Force hold is a new function of ESP32-S2 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// 0~47 except from 22~25, 47 are valid -#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47)) -// GPIO 46, 47 are input only -#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47)) +// 0~46 except from 22~25 are valid +#define SOC_GPIO_VALID_GPIO_MASK (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) +// GPIO 46 is input only +#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46)) // Support to configure slept status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) diff --git a/components/soc/esp32s2/rtc_io_periph.c b/components/soc/esp32s2/rtc_io_periph.c index 63828d8d25..217361070b 100644 --- a/components/soc/esp32s2/rtc_io_periph.c +++ b/components/soc/esp32s2/rtc_io_periph.c @@ -62,7 +62,6 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { -1,//GPIO44 -1,//GPIO45 -1,//GPIO46 - -1,//GPIO47 }; //Reg,Mux,Fun,IE,Up,Down,Rtc_number