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set fosc div to 1 to make chip run stablly for C2

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chaijie@espressif.com 2022-07-25 17:18:18 +08:00 committed by cje
parent 0f08d4050d
commit b250589f2f
1 changed files with 1 additions and 1 deletions
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2
components/soc/esp32c2/include/soc/rtc.h
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@ -179,7 +179,7 @@ typedef struct {
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.clk_8m_clk_div = 1, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
}