add esp32s2beta component

components/esp32/CMakeLists.txt

@@ -76,7 +76,7 @@ else()
     add_custom_command(
         OUTPUT esp32_out.ld
         COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32_out.ld -I ${config_dir} ${LD_DIR}/esp32.ld
-        MAIN_DEPENDENCY ${LD_DIR}/esp32.ld ${SDKCONFIG_H}
+        MAIN_DEPENDENCY ${LD_DIR}/esp32.ld ${sdkconfig_header}
         COMMENT "Generating linker script..."
         VERBATIM)
 

components/esp32s2beta/CMakeLists.txt

@@ -0,0 +1,81 @@
+if(BOOTLOADER_BUILD AND CONFIG_IDF_TARGET_ESP32S2BETA)
+    # For bootloader, all we need from esp32s2beta is headers
+    set(COMPONENT_ADD_INCLUDEDIRS include)
+    set(COMPONENT_REQUIRES ${IDF_COMPONENTS} soc) #unfortunately rom/uart uses SOC registers directly
+    set(COMPONENT_SRCS )
+    register_component()
+elseif(CONFIG_IDF_TARGET_ESP32S2BETA)
+    # Regular app build
+
+    set(COMPONENT_SRCS "brownout.c"
+                   "cache_err_int.c"
+                   "clk.c"
+                   "cpu_start.c"
+                   "crosscore_int.c"
+                   "dport_access.c"
+                   "dport_panic_highint_hdl.S"
+                   "esp_timer_esp32s2beta.c"
+                   "gdbstub.c"
+                   "hw_random.c"
+                   "int_wdt.c"
+                   "intr_alloc.c"
+                   "panic.c"
+                   "pm_esp32s2beta.c"
+                   "pm_trace.c"
+                   "sleep_modes.c"
+                   "spiram.c"
+                   "spiram_psram.c"
+                   "system_api.c"
+                   "task_wdt.c")
+    set(COMPONENT_ADD_INCLUDEDIRS "include")
+
+    set(COMPONENT_REQUIRES driver esp_event efuse soc) #unfortunately rom/uart uses SOC registers directly
+
+    # driver is a public requirement because esp_sleep.h uses gpio_num_t & touch_pad_t
+    # app_update is added here because cpu_start.c uses esp_ota_get_app_description() function.
+    set(COMPONENT_PRIV_REQUIRES
+        app_trace app_update bootloader_support log mbedtls nvs_flash
+        pthread smartconfig_ack spi_flash vfs wpa_supplicant espcoredump esp_common esp_wifi)
+
+    set(COMPONENT_ADD_LDFRAGMENTS linker.lf ld/esp32s2beta_fragments.lf)
+
+    register_component()
+
+    target_linker_script(${COMPONENT_LIB} "${CMAKE_CURRENT_BINARY_DIR}/esp32s2beta_out.ld")
+
+    # Process the template file through the linker script generation mechanism, and use the output for linking the
+    # final binary
+    target_linker_script(${COMPONENT_LIB} "${CMAKE_CURRENT_LIST_DIR}/ld/esp32s2beta.project.ld.in" PROCESS)
+
+    target_linker_script(${COMPONENT_LIB} "ld/esp32s2beta.peripherals.ld")
+
+    target_link_libraries(${COMPONENT_LIB} gcc)
+    target_link_libraries(${COMPONENT_LIB} "-u call_user_start_cpu0")
+
+    #ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
+    #linker will ignore panic_highint_hdl.S as it has no other files depending on any
+    #symbols in it.
+    target_link_libraries(${COMPONENT_LIB} "-u ld_include_panic_highint_hdl")
+
+    idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER)
+    get_filename_component(config_dir ${sdkconfig_header} DIRECTORY)
+    # Preprocess esp32s2beta.ld linker script to include configuration, becomes esp32s2beta_out.ld
+    set(LD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/ld)
+    add_custom_command(
+        OUTPUT esp32s2beta_out.ld
+        COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32s2beta_out.ld -I ${config_dir} ${LD_DIR}/esp32s2beta.ld
+        MAIN_DEPENDENCY ${LD_DIR}/esp32s2beta.ld ${sdkconfig_header}
+        COMMENT "Generating linker script..."
+        VERBATIM)
+
+    add_custom_target(esp32s2beta_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32s2beta_out.ld)
+    add_dependencies(${COMPONENT_LIB} esp32s2beta_linker_script)
+
+    # disable stack protection in files which are involved in initialization of that feature
+    set_source_files_properties(
+        cpu_start.c
+        PROPERTIES COMPILE_FLAGS
+        -fno-stack-protector)
+else()
+    register_config_only_component()
+endif()

components/esp32s2beta/Makefile.projbuild

@@ -0,0 +1,44 @@
+ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+
+PHY_INIT_DATA_OBJ = $(BUILD_DIR_BASE)/phy_init_data.o
+PHY_INIT_DATA_BIN = $(BUILD_DIR_BASE)/phy_init_data.bin
+
+# Command to flash PHY init data partition
+PHY_INIT_DATA_FLASH_CMD = $(ESPTOOLPY_SERIAL) write_flash $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
+ESPTOOL_ALL_FLASH_ARGS += $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
+
+ESP32_COMPONENT_PATH := $(COMPONENT_PATH)
+
+$(PHY_INIT_DATA_OBJ): $(ESP32_COMPONENT_PATH)/phy_init_data.h $(BUILD_DIR_BASE)/include/sdkconfig.h
+	$(summary) CC $(notdir $@)
+	printf "#include \"phy_init_data.h\"\n" | $(CC) -I $(BUILD_DIR_BASE)/include -I $(ESP32_COMPONENT_PATH) -I $(ESP32_COMPONENT_PATH)/include -c -o $@ -xc -
+
+$(PHY_INIT_DATA_BIN): $(PHY_INIT_DATA_OBJ)
+	$(summary) BIN $(notdir $@)
+	$(OBJCOPY) -O binary $< $@
+
+phy_init_data: $(PHY_INIT_DATA_BIN)
+
+phy_init_data-flash: $(BUILD_DIR_BASE)/phy_init_data.bin
+	@echo "Flashing PHY init data..."
+	$(PHY_INIT_DATA_FLASH_CMD)
+
+phy_init_data-clean:
+	rm -f $(PHY_INIT_DATA_BIN) $(PHY_INIT_DATA_OBJ)
+
+all: phy_init_data
+flash: phy_init_data
+
+endif # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+
+
+# Enable psram cache bug workaround in compiler if selected
+ifdef CONFIG_SPIRAM_CACHE_WORKAROUND
+CFLAGS+=-mfix-esp32-psram-cache-issue
+CXXFLAGS+=-mfix-esp32-psram-cache-issue
+endif
+
+# Enable dynamic esp_timer overflow value if building unit tests
+ifneq ("$(TEST_COMPONENTS_LIST)","")
+CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL
+endif

components/esp32s2beta/brownout.c

@@ -0,0 +1,56 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "soc/cpu.h"
+#include "soc/rtc_cntl_reg.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp_private/system_internal.h"
+#include "driver/rtc_cntl.h"
+#include "freertos/FreeRTOS.h"
+
+#ifdef CONFIG_BROWNOUT_DET_LVL
+#define BROWNOUT_DET_LVL CONFIG_BROWNOUT_DET_LVL
+#else
+#define BROWNOUT_DET_LVL 0
+#endif //CONFIG_BROWNOUT_DET_LVL
+
+static void rtc_brownout_isr_handler()
+{
+    /* Normally RTC ISR clears the interrupt flag after the application-supplied
+     * handler returns. Since restart is called here, the flag needs to be
+     * cleared manually.
+     */
+    REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_BROWN_OUT_INT_CLR);
+    /* Stall the other CPU to make sure the code running there doesn't use UART
+     * at the same time as the following ets_printf.
+     */
+    esp_cpu_stall(!xPortGetCoreID());
+    ets_printf("\r\nBrownout detector was triggered\r\n\r\n");
+    esp_restart_noos();
+}
+
+void esp_brownout_init()
+{
+    //TODO, chip7.2.2 will use i2c inteface to configure brown out threshold
+
+    ESP_ERROR_CHECK( rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M) );
+
+    REG_SET_BIT(RTC_CNTL_INT_ENA_REG, RTC_CNTL_BROWN_OUT_INT_ENA_M);
+}

components/esp32s2beta/cache_err_int.c

@@ -0,0 +1,69 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ The cache has an interrupt that can be raised as soon as an access to a cached
+ region (flash, psram) is done without the cache being enabled. We use that here
+ to panic the CPU, which from a debugging perspective is better than grabbing bad
+ data from the bus.
+*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "freertos/FreeRTOS.h"
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+#include "esp_attr.h"
+#include "soc/dport_reg.h"
+#include "soc/periph_defs.h"
+#include "sdkconfig.h"
+#include "esp32s2beta/dport_access.h"
+
+void esp_cache_err_int_init()
+{
+    uint32_t core_id = xPortGetCoreID();
+    ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
+
+    // We do not register a handler for the interrupt because it is interrupt
+    // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
+    // a call to the panic handler for
+    // this interrupt.
+    intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
+
+    // Enable invalid cache access interrupt when the cache is disabled.
+    // When the interrupt happens, we can not determine the CPU where the
+    // invalid cache access has occurred. We enable the interrupt to catch
+    // invalid access on both CPUs, but the interrupt is connected to the
+    // CPU which happens to call this function.
+    // For this reason, panic handler backtrace will not be correct if the
+    // interrupt is connected to PRO CPU and invalid access happens on the APP
+    // CPU.
+#if 0
+    DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_IA_INT_EN_REG,
+        DPORT_CACHE_IA_INT_PRO_DRAM1 |
+        DPORT_CACHE_IA_INT_PRO_DROM0 |
+        DPORT_CACHE_IA_INT_PRO_IROM0 |
+        DPORT_CACHE_IA_INT_PRO_IRAM0 |
+        DPORT_CACHE_IA_INT_PRO_IRAM1);
+#endif
+    ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
+}
+
+int IRAM_ATTR esp_cache_err_get_cpuid()
+{
+    esp_dport_access_int_pause();
+    return PRO_CPU_NUM;
+}

components/esp32s2beta/clk.c

@@ -0,0 +1,307 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <sys/cdefs.h>
+#include <sys/time.h>
+#include <sys/param.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp32s2beta/clk.h"
+#include "esp_clk_internal.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/uart.h"
+#include "esp32s2beta/rom/rtc.h"
+#include "soc/soc.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/i2s_reg.h"
+#include "driver/periph_ctrl.h"
+#include "xtensa/core-macros.h"
+#include "bootloader_clock.h"
+#include "soc/syscon_reg.h"
+
+/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
+ * Larger values increase startup delay. Smaller values may cause false positive
+ * detection (i.e. oscillator runs for a few cycles and then stops).
+ */
+#define SLOW_CLK_CAL_CYCLES     CONFIG_ESP32_RTC_CLK_CAL_CYCLES
+
+#define MHZ (1000000)
+
+static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
+
+// g_ticks_us defined in ROMs for PRO and APP CPU
+extern uint32_t g_ticks_per_us_pro;
+#if !CONFIG_FREERTOS_UNICORE
+extern uint32_t g_ticks_per_us_app;
+#endif //!CONFIG_FREERTOS_UNICORE
+
+static const char* TAG = "clk";
+
+
+void esp_clk_init(void)
+{
+    rtc_config_t cfg = RTC_CONFIG_DEFAULT();
+    rtc_init(cfg);
+
+#ifdef CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS
+    /* Check the bootloader set the XTAL frequency.
+
+       Bootloaders pre-v2.1 don't do this.
+    */
+    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+    if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
+        ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader");
+        bootloader_clock_configure();
+    }
+#else
+    /* If this assertion fails, either upgrade the bootloader or enable CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
+    assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
+#endif
+
+    rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
+
+#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+    select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
+#else
+    select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
+#endif
+
+    uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
+    rtc_cpu_freq_t freq = RTC_CPU_FREQ_80M;
+    switch(freq_mhz) {
+        case 240:
+            freq = RTC_CPU_FREQ_240M;
+            break;
+        case 160:
+            freq = RTC_CPU_FREQ_160M;
+            break;
+        default:
+            freq_mhz = 80;
+            /* no break */
+        case 80:
+            freq = RTC_CPU_FREQ_80M;
+            break;
+    }
+
+    // Wait for UART TX to finish, otherwise some UART output will be lost
+    // when switching APB frequency
+    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+
+    uint32_t freq_before = rtc_clk_cpu_freq_value(rtc_clk_cpu_freq_get()) / MHZ ;
+
+    rtc_clk_cpu_freq_set(freq);
+
+    // Re calculate the ccount to make time calculation correct.
+    uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
+    XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
+}
+
+int IRAM_ATTR esp_clk_cpu_freq(void)
+{
+    return g_ticks_per_us_pro * 1000000;
+}
+
+int IRAM_ATTR esp_clk_apb_freq(void)
+{
+    return MIN(g_ticks_per_us_pro, 80) * 1000000;
+}
+
+void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
+{
+    /* Update scale factors used by ets_delay_us */
+    g_ticks_per_us_pro = ticks_per_us;
+#if !CONFIG_FREERTOS_UNICORE
+    g_ticks_per_us_app = ticks_per_us;
+#endif //!CONFIG_FREERTOS_UNICORE
+}
+
+static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
+{
+    uint32_t cal_val = 0;
+    uint32_t wait = 0;
+    const uint32_t warning_timeout = 3 /* sec */ * 32768 /* Hz */ / (2 * SLOW_CLK_CAL_CYCLES);
+    bool changing_clock_to_150k = false;
+    do {
+        if (slow_clk == RTC_SLOW_FREQ_32K_XTAL) {
+            /* 32k XTAL oscillator needs to be enabled and running before it can
+             * be used. Hardware doesn't have a direct way of checking if the
+             * oscillator is running. Here we use rtc_clk_cal function to count
+             * the number of main XTAL cycles in the given number of 32k XTAL
+             * oscillator cycles. If the 32k XTAL has not started up, calibration
+             * will time out, returning 0.
+             */
+            ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
+            rtc_clk_32k_enable(true);
+            cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
+            if(cal_val == 0 || cal_val < 15000000L){
+                ESP_EARLY_LOGE(TAG, "RTC: Not found External 32 kHz XTAL. Switching to Internal 150 kHz RC chain");
+                slow_clk = RTC_SLOW_FREQ_RTC;
+                changing_clock_to_150k = true;
+            }
+        }
+        rtc_clk_slow_freq_set(slow_clk);
+        if (changing_clock_to_150k == true && wait > 1){
+            // This helps when there are errors when switching the clock from External 32 kHz XTAL to Internal 150 kHz RC chain.
+            rtc_clk_32k_enable(false);
+            uint32_t min_bootstrap = 5; // Min bootstrapping for continue switching the clock.
+            rtc_clk_32k_bootstrap(min_bootstrap);
+            rtc_clk_32k_enable(true);
+        }
+
+        if (SLOW_CLK_CAL_CYCLES > 0) {
+            /* TODO: 32k XTAL oscillator has some frequency drift at startup.
+             * Improve calibration routine to wait until the frequency is stable.
+             */
+            cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
+        } else {
+            const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
+            cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
+        }
+        if (++wait % warning_timeout == 0) {
+            ESP_EARLY_LOGW(TAG, "still waiting for source selection RTC");
+        }
+    } while (cal_val == 0);
+    ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
+    esp_clk_slowclk_cal_set(cal_val);
+}
+
+void rtc_clk_select_rtc_slow_clk()
+{
+    select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
+}
+
+/* This function is not exposed as an API at this point.
+ * All peripheral clocks are default enabled after chip is powered on.
+ * This function disables some peripheral clocks when cpu starts.
+ * These peripheral clocks are enabled when the peripherals are initialized
+ * and disabled when they are de-initialized.
+ */
+void esp_perip_clk_init(void)
+{
+    uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
+    uint32_t common_perip_clk1 = 0;
+
+#if CONFIG_FREERTOS_UNICORE
+    RESET_REASON rst_reas[1];
+#else
+    RESET_REASON rst_reas[2];
+#endif
+
+    rst_reas[0] = rtc_get_reset_reason(0);
+
+#if !CONFIG_FREERTOS_UNICORE
+    rst_reas[1] = rtc_get_reset_reason(1);
+#endif
+
+    /* For reason that only reset CPU, do not disable the clocks
+     * that have been enabled before reset.
+     */
+    if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
+#if !CONFIG_FREERTOS_UNICORE
+        || (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
+#endif
+    ) {
+        common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
+        hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
+        wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
+    }
+    else {
+        common_perip_clk = DPORT_WDG_CLK_EN |
+                              DPORT_I2S0_CLK_EN |
+#if CONFIG_CONSOLE_UART_NUM != 0
+                              DPORT_UART_CLK_EN |
+#endif
+#if CONFIG_CONSOLE_UART_NUM != 1
+                              DPORT_UART1_CLK_EN |
+#endif
+                              DPORT_USB_CLK_EN |
+                              DPORT_SPI2_CLK_EN |
+                              DPORT_I2C_EXT0_CLK_EN |
+                              DPORT_UHCI0_CLK_EN |
+                              DPORT_RMT_CLK_EN |
+                              DPORT_PCNT_CLK_EN |
+                              DPORT_LEDC_CLK_EN |
+                              DPORT_TIMERGROUP1_CLK_EN |
+                              DPORT_SPI3_CLK_EN |
+                              DPORT_SPI4_CLK_EN |
+                              DPORT_PWM0_CLK_EN |
+                              DPORT_CAN_CLK_EN |
+                              DPORT_PWM1_CLK_EN |
+                              DPORT_I2S1_CLK_EN |
+                              DPORT_SPI2_DMA_CLK_EN |
+                              DPORT_SPI3_DMA_CLK_EN |
+                              DPORT_PWM2_CLK_EN |
+                              DPORT_PWM3_CLK_EN;
+        common_perip_clk1 = DPORT_SPI_SHARED_DMA_CLK_EN;
+        hwcrypto_perip_clk = DPORT_PERI_EN_AES |
+                                DPORT_PERI_EN_SHA |
+                                DPORT_PERI_EN_RSA |
+                                DPORT_PERI_EN_SECUREBOOT;
+        wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
+                              DPORT_WIFI_CLK_BT_EN_M |
+                              DPORT_WIFI_CLK_UNUSED_BIT5 |
+                              DPORT_WIFI_CLK_UNUSED_BIT12 |
+                              DPORT_WIFI_CLK_SDIOSLAVE_EN |
+                              DPORT_WIFI_CLK_SDIO_HOST_EN |
+                              DPORT_WIFI_CLK_EMAC_EN;
+    }
+
+    //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
+    common_perip_clk |= DPORT_I2S0_CLK_EN |
+#if CONFIG_CONSOLE_UART_NUM != 0
+                        DPORT_UART_CLK_EN |
+#endif
+#if CONFIG_CONSOLE_UART_NUM != 1
+                        DPORT_UART1_CLK_EN |
+#endif
+                        DPORT_USB_CLK_EN |
+                        DPORT_SPI2_CLK_EN |
+                        DPORT_I2C_EXT0_CLK_EN |
+                        DPORT_UHCI0_CLK_EN |
+                        DPORT_RMT_CLK_EN |
+                        DPORT_UHCI1_CLK_EN |
+                        DPORT_SPI3_CLK_EN |
+                        DPORT_SPI4_CLK_EN |
+                        DPORT_I2C_EXT1_CLK_EN |
+                        DPORT_I2S1_CLK_EN |
+                        DPORT_SPI2_DMA_CLK_EN |
+                        DPORT_SPI3_DMA_CLK_EN;
+    common_perip_clk1 = DPORT_SPI_SHARED_DMA_CLK_EN;
+
+    /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
+     * the current is not reduced when disable I2S clock.
+     */
+    REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
+    REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
+
+    /* Disable some peripheral clocks. */
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
+
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
+
+    /* Disable hardware crypto clocks. */
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
+    DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
+
+    /* Disable WiFi/BT/SDIO clocks. */
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
+
+    /* Enable RNG clock. */
+    periph_module_enable(PERIPH_RNG_MODULE);
+}

components/esp32s2beta/component.mk

@@ -0,0 +1,4 @@
+#
+# Component Makefile
+#
+COMPONENT_CONFIG_ONLY := 1

components/esp32s2beta/cpu_start.c

@@ -0,0 +1,523 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <string.h>
+
+#include "esp_attr.h"
+#include "esp_err.h"
+
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/uart.h"
+#include "esp32s2beta/rom/rtc.h"
+#include "esp32s2beta/rom/cache.h"
+
+#include "soc/cpu.h"
+#include "soc/rtc.h"
+#include "soc/dport_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/timer_group_reg.h"
+#include "soc/periph_defs.h"
+
+#include "driver/rtc_io.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+#include "freertos/portmacro.h"
+
+#include "esp_heap_caps_init.h"
+#include "sdkconfig.h"
+#include "esp_system.h"
+#include "esp_spi_flash.h"
+#include "nvs_flash.h"
+#include "esp_event.h"
+#include "esp_spi_flash.h"
+#include "esp_ipc.h"
+#include "esp32s2beta/dport_access.h"
+#include "esp_private/crosscore_int.h"
+#include "esp_log.h"
+#include "esp_vfs_dev.h"
+#include "esp_newlib.h"
+#include "esp32s2beta/brownout.h"
+#include "esp_int_wdt.h"
+#include "esp_task.h"
+#include "esp_task_wdt.h"
+#include "esp_phy_init.h"
+#include "esp32s2beta/cache_err_int.h"
+#include "esp_coexist_internal.h"
+#include "esp_debug_helpers.h"
+#include "esp_core_dump.h"
+#include "esp_app_trace.h"
+#include "esp_private/dbg_stubs.h"
+#include "esp_efuse.h"
+#include "esp32s2beta/spiram.h"
+#include "esp_clk_internal.h"
+#include "esp_timer.h"
+#include "esp_pm.h"
+#include "esp_private/pm_impl.h"
+#include "trax.h"
+
+#define STRINGIFY(s) STRINGIFY2(s)
+#define STRINGIFY2(s) #s
+
+void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
+void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
+#if !CONFIG_FREERTOS_UNICORE
+static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
+void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
+void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
+static bool app_cpu_started = false;
+#endif //!CONFIG_FREERTOS_UNICORE
+
+static void do_global_ctors(void);
+static void main_task(void* args);
+extern void app_main(void);
+extern esp_err_t esp_pthread_init(void);
+
+extern int _bss_start;
+extern int _bss_end;
+extern int _rtc_bss_start;
+extern int _rtc_bss_end;
+extern int _init_start;
+extern void (*__init_array_start)(void);
+extern void (*__init_array_end)(void);
+extern volatile int port_xSchedulerRunning[2];
+
+static const char* TAG = "cpu_start";
+
+struct object { long placeholder[ 10 ]; };
+void __register_frame_info (const void *begin, struct object *ob);
+extern char __eh_frame[];
+
+//If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
+static bool s_spiram_okay=true;
+
+/*
+ * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
+ * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
+ */
+
+void IRAM_ATTR call_start_cpu0()
+{
+#if CONFIG_FREERTOS_UNICORE
+    RESET_REASON rst_reas[1];
+#else
+    RESET_REASON rst_reas[2];
+#endif
+    cpu_configure_region_protection();
+
+    //Move exception vectors to IRAM
+    asm volatile (\
+                  "wsr    %0, vecbase\n" \
+                  ::"r"(&_init_start));
+
+    rst_reas[0] = rtc_get_reset_reason(0);
+
+#if !CONFIG_FREERTOS_UNICORE
+    rst_reas[1] = rtc_get_reset_reason(1);
+#endif
+
+    // from panic handler we can be reset by RWDT or TG0WDT
+    if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
+#if !CONFIG_FREERTOS_UNICORE
+        || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
+#endif
+    ) {
+        esp_panic_wdt_stop();
+    }
+
+    //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
+    memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
+
+    /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
+    if (rst_reas[0] != DEEPSLEEP_RESET) {
+        memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
+    }
+
+    /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
+extern void esp_config_instruction_cache_mode(void);
+    esp_config_instruction_cache_mode();
+
+    /* copy MMU table from ICache to DCache, so we can use DCache to access rodata later. */
+#if CONFIG_RODATA_USE_DATA_CACHE
+    MMU_Drom0_I2D_Copy();
+#endif
+
+    /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache.
+       Configure the mode of data : cache size, cache associated ways, cache line size.
+       Enable data cache, so if we don't use SPIRAM, it just works. */
+#if CONFIG_SPIRAM_BOOT_INIT || CONFIG_RODATA_USE_DATA_CACHE
+extern void esp_config_data_cache_mode(void);
+    esp_config_data_cache_mode();
+    Cache_Enable_DCache(0);
+#endif
+
+    /* In SPIRAM code, we will reconfigure data cache, as well as instruction cache, so that we can:
+       1. make data buses works with SPIRAM
+       2. make instruction and rodata work with SPIRAM, still through instruction cache */
+#if CONFIG_SPIRAM_BOOT_INIT
+    esp_spiram_init_cache();
+    if (esp_spiram_init() != ESP_OK) {
+#if CONFIG_SPIRAM_IGNORE_NOTFOUND
+        ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
+        s_spiram_okay = false;
+#else
+        ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
+        abort();
+#endif
+    }
+#endif
+
+    /* Start to use data cache to access rodata. */
+#if CONFIG_RODATA_USE_DATA_CACHE
+extern void esp_switch_rodata_to_dcache(void);
+    esp_switch_rodata_to_dcache();
+#endif
+
+    ESP_EARLY_LOGI(TAG, "Pro cpu up.");
+
+#if !CONFIG_FREERTOS_UNICORE
+    ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
+    //Flush and enable icache for APP CPU
+    Cache_Flush(1);
+    Cache_Read_Enable(1);
+    esp_cpu_unstall(1);
+    // Enable clock and reset APP CPU. Note that OpenOCD may have already
+    // enabled clock and taken APP CPU out of reset. In this case don't reset
+    // APP CPU again, as that will clear the breakpoints which may have already
+    // been set.
+    if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
+        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
+        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
+    }
+    ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
+
+    while (!app_cpu_started) {
+        ets_delay_us(100);
+    }
+#else
+    ESP_EARLY_LOGI(TAG, "Single core mode");
+#endif
+
+
+#if CONFIG_SPIRAM_MEMTEST
+    if (s_spiram_okay) {
+        bool ext_ram_ok=esp_spiram_test();
+        if (!ext_ram_ok) {
+            ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
+            abort();
+        }
+    }
+#endif
+
+#if CONFIG_INSTRUCTION_USE_SPIRAM
+extern void esp_spiram_enable_instruction_access(void);
+    esp_spiram_enable_instruction_access();
+#endif
+#if CONFIG_RODATA_USE_SPIRAM
+extern void esp_spiram_enable_rodata_access(void);
+    esp_spiram_enable_rodata_access();
+#endif
+
+#if CONFIG_ENABLE_INSTRUCTION_CACHE_WRAP || CONFIG_ENABLE_DATA_CACHE_WRAP
+uint32_t icache_wrap_enable = 0,dcache_wrap_enable = 0;
+#if CONFIG_ENABLE_INSTRUCTION_CACHE_WRAP
+    icache_wrap_enable = 1;
+#endif
+#if CONFIG_ENABLE_DATA_CACHE_WRAP
+    dcache_wrap_enable = 1;
+#endif
+extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
+    esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
+#endif
+
+    /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
+       If the heap allocator is initialized first, it will put free memory linked list items into
+       memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
+       corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
+       works around this problem.
+       With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
+       app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
+       fail initializing it properly. */
+    heap_caps_init();
+
+    ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
+    start_cpu0();
+}
+
+#if !CONFIG_FREERTOS_UNICORE
+
+static void wdt_reset_cpu1_info_enable(void)
+{
+    DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
+    DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
+}
+
+void IRAM_ATTR call_start_cpu1()
+{
+    asm volatile (\
+                  "wsr    %0, vecbase\n" \
+                  ::"r"(&_init_start));
+
+    ets_set_appcpu_boot_addr(0);
+    cpu_configure_region_protection();
+
+#if CONFIG_CONSOLE_UART_NONE
+    ets_install_putc1(NULL);
+    ets_install_putc2(NULL);
+#else // CONFIG_CONSOLE_UART_NONE
+    uartAttach();
+    ets_install_uart_printf();
+    uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
+#endif
+
+    wdt_reset_cpu1_info_enable();
+    ESP_EARLY_LOGI(TAG, "App cpu up.");
+    app_cpu_started = 1;
+    start_cpu1();
+}
+#endif //!CONFIG_FREERTOS_UNICORE
+
+static void intr_matrix_clear(void)
+{
+    //Clear all the interrupt matrix register
+    for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
+        intr_matrix_set(0, i, ETS_INVALID_INUM);
+#if !CONFIG_FREERTOS_UNICORE
+        intr_matrix_set(1, i, ETS_INVALID_INUM);
+#endif
+    }
+}
+
+void start_cpu0_default(void)
+{
+    esp_err_t err;
+    esp_setup_syscall_table();
+
+    if (s_spiram_okay) {
+#if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
+        esp_err_t r=esp_spiram_add_to_heapalloc();
+        if (r != ESP_OK) {
+            ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
+            abort();
+        }
+#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
+        r=esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
+        if (r != ESP_OK) {
+            ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool!");
+            abort();
+        }
+#endif
+#if CONFIG_SPIRAM_USE_MALLOC
+        heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
+#endif
+#endif
+    }
+
+//Enable trace memory and immediately start trace.
+#if CONFIG_ESP32_TRAX
+#if CONFIG_ESP32_TRAX_TWOBANKS
+    trax_enable(TRAX_ENA_PRO_APP);
+#else
+    trax_enable(TRAX_ENA_PRO);
+#endif
+    trax_start_trace(TRAX_DOWNCOUNT_WORDS);
+#endif
+    esp_clk_init();
+    esp_perip_clk_init();
+    intr_matrix_clear();
+
+#ifndef CONFIG_CONSOLE_UART_NONE
+#ifdef CONFIG_PM_ENABLE
+    const int uart_clk_freq = REF_CLK_FREQ;
+    /* When DFS is enabled, use REFTICK as UART clock source */
+    CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
+#else
+    const int uart_clk_freq = APB_CLK_FREQ;
+#endif // CONFIG_PM_DFS_ENABLE
+    uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
+#endif // CONFIG_CONSOLE_UART_NONE
+
+#if CONFIG_BROWNOUT_DET
+    esp_brownout_init();
+#endif
+#if CONFIG_DISABLE_BASIC_ROM_CONSOLE
+    esp_efuse_disable_basic_rom_console();
+#endif
+    rtc_gpio_force_hold_dis_all();
+    esp_vfs_dev_uart_register();
+    esp_reent_init(_GLOBAL_REENT);
+#ifndef CONFIG_CONSOLE_UART_NONE
+    const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
+    _GLOBAL_REENT->_stdin  = fopen(default_uart_dev, "r");
+    _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
+    _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
+#else
+    _GLOBAL_REENT->_stdin  = (FILE*) &__sf_fake_stdin;
+    _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
+    _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
+#endif
+    esp_timer_init();
+    esp_set_time_from_rtc();
+#if CONFIG_ESP32_APPTRACE_ENABLE
+    err = esp_apptrace_init();
+    assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
+#endif
+#if CONFIG_SYSVIEW_ENABLE
+    SEGGER_SYSVIEW_Conf();
+#endif
+#if CONFIG_ESP32_DEBUG_STUBS_ENABLE
+    esp_dbg_stubs_init();
+#endif
+    err = esp_pthread_init();
+    assert(err == ESP_OK && "Failed to init pthread module!");
+
+    do_global_ctors();
+#if CONFIG_INT_WDT
+    //esp_int_wdt_init();
+    //Initialize the interrupt watch dog for CPU0.
+    //esp_int_wdt_cpu_init();
+#endif
+    //esp_cache_err_int_init();
+    esp_crosscore_int_init();
+    esp_ipc_init();
+#ifndef CONFIG_FREERTOS_UNICORE
+    esp_dport_access_int_init();
+#endif
+    spi_flash_init();
+    /* init default OS-aware flash access critical section */
+    spi_flash_guard_set(&g_flash_guard_default_ops);
+#ifdef CONFIG_PM_ENABLE
+    esp_pm_impl_init();
+#ifdef CONFIG_PM_DFS_INIT_AUTO
+    rtc_cpu_freq_t max_freq;
+    rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, &max_freq);
+    esp_pm_config_esp32_t cfg = {
+            .max_cpu_freq = max_freq,
+            .min_cpu_freq = RTC_CPU_FREQ_XTAL
+    };
+    esp_pm_configure(&cfg);
+#endif //CONFIG_PM_DFS_INIT_AUTO
+#endif //CONFIG_PM_ENABLE
+
+#if CONFIG_ESP32_ENABLE_COREDUMP
+    esp_core_dump_init();
+#endif
+
+    portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
+                                                ESP_TASK_MAIN_STACK, NULL,
+                                                ESP_TASK_MAIN_PRIO, NULL, 0);
+    assert(res == pdTRUE);
+    ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
+    vTaskStartScheduler();
+    abort(); /* Only get to here if not enough free heap to start scheduler */
+}
+
+#if !CONFIG_FREERTOS_UNICORE
+void start_cpu1_default(void)
+{
+    // Wait for FreeRTOS initialization to finish on PRO CPU
+    while (port_xSchedulerRunning[0] == 0) {
+        ;
+    }
+#if CONFIG_ESP32_TRAX_TWOBANKS
+    trax_start_trace(TRAX_DOWNCOUNT_WORDS);
+#endif
+#if CONFIG_ESP32_APPTRACE_ENABLE
+    esp_err_t err = esp_apptrace_init();
+    assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
+#endif
+#if CONFIG_INT_WDT
+    //Initialize the interrupt watch dog for CPU1.
+    //esp_int_wdt_cpu_init();
+#endif
+    //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
+    //has started, but it isn't active *on this CPU* yet.
+    esp_cache_err_int_init();
+    esp_crosscore_int_init();
+    esp_dport_access_int_init();
+
+    ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
+    xPortStartScheduler();
+    abort(); /* Only get to here if FreeRTOS somehow very broken */
+}
+#endif //!CONFIG_FREERTOS_UNICORE
+
+#ifdef CONFIG_CXX_EXCEPTIONS
+size_t __cxx_eh_arena_size_get()
+{
+    return CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE;
+}
+#endif
+
+static void do_global_ctors(void)
+{
+#ifdef CONFIG_CXX_EXCEPTIONS
+    static struct object ob;
+    __register_frame_info( __eh_frame, &ob );
+#endif
+
+    void (**p)(void);
+    for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
+        (*p)();
+    }
+}
+
+static void main_task(void* args)
+{
+    // Now that the application is about to start, disable boot watchdogs
+    REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
+    REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
+#if !CONFIG_FREERTOS_UNICORE
+    // Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
+    while (port_xSchedulerRunning[1] == 0) {
+        ;
+    }
+#endif
+    //Enable allocation in region where the startup stacks were located.
+    heap_caps_enable_nonos_stack_heaps();
+
+    //Initialize task wdt if configured to do so
+#ifdef CONFIG_TASK_WDT_PANIC
+    //ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, true))
+#elif CONFIG_TASK_WDT
+    //ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, false))
+#endif
+
+    //Add IDLE 0 to task wdt
+#if 0
+#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0
+    TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
+    if(idle_0 != NULL){
+        ESP_ERROR_CHECK(esp_task_wdt_add(idle_0))
+    }
+#endif
+    //Add IDLE 1 to task wdt
+#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1
+    TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
+    if(idle_1 != NULL){
+        ESP_ERROR_CHECK(esp_task_wdt_add(idle_1))
+    }
+#endif
+#endif
+
+    app_main();
+    vTaskDelete(NULL);
+}
+

components/esp32s2beta/crosscore_int.c

@@ -0,0 +1,119 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stdint.h>
+#include <string.h>
+
+#include "esp_attr.h"
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/uart.h"
+
+#include "soc/cpu.h"
+#include "soc/dport_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/periph_defs.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+#include "freertos/portmacro.h"
+
+
+#define REASON_YIELD            BIT(0)
+#define REASON_FREQ_SWITCH      BIT(1)
+
+static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
+static volatile uint32_t reason[ portNUM_PROCESSORS ];
+
+/*
+ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
+the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
+*/
+static inline void IRAM_ATTR esp_crosscore_isr_handle_yield()
+{
+    portYIELD_FROM_ISR();
+}
+
+static void IRAM_ATTR esp_crosscore_isr(void *arg) {
+    uint32_t my_reason_val;
+    //A pointer to the correct reason array item is passed to this ISR.
+    volatile uint32_t *my_reason=arg;
+
+    //Clear the interrupt first.
+    if (xPortGetCoreID()==0) {
+        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
+    } else {
+        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
+    }
+    //Grab the reason and clear it.
+    portENTER_CRITICAL_ISR(&reason_spinlock);
+    my_reason_val=*my_reason;
+    *my_reason=0;
+    portEXIT_CRITICAL_ISR(&reason_spinlock);
+
+    //Check what we need to do.
+    if (my_reason_val & REASON_YIELD) {
+        esp_crosscore_isr_handle_yield();
+    }
+    if (my_reason_val & REASON_FREQ_SWITCH) {
+        /* Nothing to do here; the frequency switch event was already
+         * handled by a hook in xtensa_vectors.S. Could be used in the future
+         * to allow DFS features without the extra latency of the ISR hook.
+         */
+    }
+}
+
+//Initialize the crosscore interrupt on this core. Call this once
+//on each active core.
+void esp_crosscore_int_init() {
+    portENTER_CRITICAL(&reason_spinlock);
+    reason[xPortGetCoreID()]=0;
+    portEXIT_CRITICAL(&reason_spinlock);
+    esp_err_t err;
+    if (xPortGetCoreID()==0) {
+        err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
+    } else {
+        err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
+    }
+    assert(err == ESP_OK);
+}
+
+static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
+    assert(core_id<portNUM_PROCESSORS);
+    //Mark the reason we interrupt the other CPU
+    portENTER_CRITICAL(&reason_spinlock);
+    reason[core_id] |= reason_mask;
+    portEXIT_CRITICAL(&reason_spinlock);
+    //Poke the other CPU.
+    if (core_id==0) {
+        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
+    } else {
+        DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
+    }
+}
+
+void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
+{
+    esp_crosscore_int_send(core_id, REASON_YIELD);
+}
+
+void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
+{
+    esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
+}
+

components/esp32s2beta/dport_access.c

@@ -0,0 +1,312 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
+ * This function will be initialize after FreeRTOS startup.
+ * When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
+ * cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <sdkconfig.h>
+#include "esp_attr.h"
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/uart.h"
+
+#include "soc/cpu.h"
+#include "soc/dport_reg.h"
+#include "soc/spi_mem_reg.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+#include "freertos/portmacro.h"
+
+#include "xtensa/core-macros.h"
+
+#ifndef CONFIG_FREERTOS_UNICORE
+static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
+
+#define DPORT_CORE_STATE_IDLE        0
+#define DPORT_CORE_STATE_RUNNING     1
+static uint32_t volatile dport_core_state[portNUM_PROCESSORS];      //cpu is already run
+
+/* these global variables are accessed from interrupt vector, hence not declared as static */
+uint32_t volatile dport_access_start[portNUM_PROCESSORS];      //dport register could be accessed
+uint32_t volatile dport_access_end[portNUM_PROCESSORS];        //dport register is accessed over
+
+static uint32_t volatile dport_access_ref[portNUM_PROCESSORS];        //dport access reference
+
+#ifdef DPORT_ACCESS_BENCHMARK
+#define DPORT_ACCESS_BENCHMARK_STORE_NUM
+static uint32_t ccount_start[portNUM_PROCESSORS];
+static uint32_t ccount_end[portNUM_PROCESSORS];
+static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM];
+static uint32_t ccount_margin_cnt;
+#endif
+
+
+static BaseType_t oldInterruptLevel[2];
+#endif // CONFIG_FREERTOS_UNICORE
+
+/* stall other cpu that this cpu is pending to access dport register start */
+void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
+{
+#ifndef CONFIG_FREERTOS_UNICORE
+    if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
+        || dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
+        return;
+    }
+
+    BaseType_t intLvl = portENTER_CRITICAL_NESTED();
+
+    int cpu_id = xPortGetCoreID();
+
+#ifdef DPORT_ACCESS_BENCHMARK
+    ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
+#endif
+
+    if (dport_access_ref[cpu_id] == 0) {
+        portENTER_CRITICAL_ISR(&g_dport_mux);
+
+        oldInterruptLevel[cpu_id]=intLvl;
+
+        dport_access_start[cpu_id] = 0;
+        dport_access_end[cpu_id] = 0;
+
+        if (cpu_id == 0) {
+            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
+        } else {
+            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
+        }
+
+        while (!dport_access_start[cpu_id]) {};
+
+        REG_READ(SPI_DATE_REG(3));  //just read a APB register sure that the APB-bus is idle
+    }
+
+    dport_access_ref[cpu_id]++;
+
+    if (dport_access_ref[cpu_id] > 1) {
+        /* Interrupts are already disabled by the parent, we're nested here. */
+        portEXIT_CRITICAL_NESTED(intLvl);
+    }
+#endif /* CONFIG_FREERTOS_UNICORE */
+}
+
+/* stall other cpu that this cpu is pending to access dport register end */
+void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
+{
+#ifndef CONFIG_FREERTOS_UNICORE
+    int cpu_id = xPortGetCoreID();
+
+    if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
+            || dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
+        return;
+    }
+
+    if (dport_access_ref[cpu_id] == 0) {
+        assert(0);
+    }
+
+    dport_access_ref[cpu_id]--;
+
+    if (dport_access_ref[cpu_id] == 0) {
+        dport_access_end[cpu_id] = 1;
+
+        portEXIT_CRITICAL_ISR(&g_dport_mux);
+
+        portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
+    }
+
+#ifdef DPORT_ACCESS_BENCHMARK
+    ccount_end[cpu_id] = XTHAL_GET_CCOUNT();
+    ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
+    ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
+#endif
+#endif /* CONFIG_FREERTOS_UNICORE */
+}
+
+void IRAM_ATTR esp_dport_access_stall_other_cpu_start_wrap(void)
+{
+    DPORT_STALL_OTHER_CPU_START();
+}
+
+void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
+{
+    DPORT_STALL_OTHER_CPU_END();
+}
+
+#ifndef CONFIG_FREERTOS_UNICORE
+static void dport_access_init_core(void *arg)
+{
+    int core_id = 0;
+    uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
+
+
+    core_id = xPortGetCoreID();
+    if (core_id == 1) {
+        intr_source = ETS_FROM_CPU_INTR3_SOURCE;
+    }
+
+    ESP_INTR_DISABLE(ETS_DPORT_INUM);
+    intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
+    ESP_INTR_ENABLE(ETS_DPORT_INUM);
+
+    dport_access_ref[core_id] = 0;
+    dport_access_start[core_id] = 0;
+    dport_access_end[core_id] = 0;
+    dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
+
+    vTaskDelete(NULL);
+}
+#endif
+
+/*  Defer initialisation until after scheduler is running */
+void esp_dport_access_int_init(void)
+{
+#ifndef CONFIG_FREERTOS_UNICORE
+    portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
+    assert(res == pdTRUE);
+#endif
+}
+
+void IRAM_ATTR esp_dport_access_int_pause(void)
+{
+#ifndef CONFIG_FREERTOS_UNICORE
+    portENTER_CRITICAL_ISR(&g_dport_mux);
+    dport_core_state[0] = DPORT_CORE_STATE_IDLE;
+    dport_core_state[1] = DPORT_CORE_STATE_IDLE;
+    portEXIT_CRITICAL_ISR(&g_dport_mux);
+#endif
+}
+
+//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
+void IRAM_ATTR esp_dport_access_int_abort(void)
+{
+#ifndef CONFIG_FREERTOS_UNICORE
+    dport_core_state[0] = DPORT_CORE_STATE_IDLE;
+    dport_core_state[1] = DPORT_CORE_STATE_IDLE;
+#endif
+}
+
+void IRAM_ATTR esp_dport_access_int_resume(void)
+{
+#ifndef CONFIG_FREERTOS_UNICORE
+    portENTER_CRITICAL_ISR(&g_dport_mux);
+    dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
+    dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
+    portEXIT_CRITICAL_ISR(&g_dport_mux);
+#endif
+}
+
+/**
+ * @brief Read a sequence of DPORT registers to the buffer, SMP-safe version.
+ *
+ * This implementation uses a method of the pre-reading of the APB register
+ * before reading the register of the DPORT, without stall other CPU.
+ * There is disable/enable interrupt.
+ *
+ * @param[out] buff_out  Contains the read data.
+ * @param[in]  address   Initial address for reading registers.
+ * @param[in]  num_words The number of words.
+ */
+void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
+{
+    DPORT_INTERRUPT_DISABLE();
+    for (uint32_t i = 0;  i < num_words; ++i) {
+        buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4);
+    }
+    DPORT_INTERRUPT_RESTORE();
+}
+
+/**
+ * @brief Read value from register, SMP-safe version.
+ *
+ * This method uses the pre-reading of the APB register before reading the register of the DPORT.
+ * This implementation is useful for reading DORT registers for single reading without stall other CPU.
+ * There is disable/enable interrupt.
+ *
+ * @param reg Register address
+ * @return Value
+ */
+uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
+{
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
+    return _DPORT_REG_READ(reg);
+#else
+    uint32_t apb;
+    unsigned int intLvl;
+    __asm__ __volatile__ (\
+                  "movi %[APB], "XTSTR(0x3f400078)"\n"\
+                  "rsil %[LVL], "XTSTR(3)"\n"\
+                  "l32i %[APB], %[APB], 0\n"\
+                  "l32i %[REG], %[REG], 0\n"\
+                  "wsr  %[LVL], "XTSTR(PS)"\n"\
+                  "rsync\n"\
+                  : [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
+                  : \
+                  : "memory" \
+                  );
+    return reg;
+#endif
+}
+
+/**
+ * @brief Read value from register, NOT SMP-safe version.
+ *
+ * This method uses the pre-reading of the APB register before reading the register of the DPORT.
+ * There is not disable/enable interrupt.
+ * The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading.
+ * This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example.
+ * The recommended way to read registers sequentially without stall other CPU
+ * is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer.
+ *
+ * \code{c}
+ * // This example shows how to use it.
+ * { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE.
+ *     DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
+ *     for (i = 0; i < max; ++i) {
+ *        array[i] = esp_dport_access_sequence_reg_read(Address + i * 4); // reading DPORT registers
+ *     }
+ *     DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
+ * }
+ * \endcode
+ *
+ * @param reg Register address
+ * @return Value
+ */
+uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
+{
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
+    return _DPORT_REG_READ(reg);
+#else
+    uint32_t apb;
+    __asm__ __volatile__ (\
+                  "movi %[APB], "XTSTR(0x3f400078)"\n"\
+                  "l32i %[APB], %[APB], 0\n"\
+                  "l32i %[REG], %[REG], 0\n"\
+                  : [APB]"=a"(apb), [REG]"+a"(reg)\
+                  : \
+                  : "memory" \
+                  );
+    return reg;
+#endif
+}

components/esp32s2beta/dport_panic_highint_hdl.S

@@ -0,0 +1,203 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <xtensa/coreasm.h>
+#include <xtensa/corebits.h>
+#include <xtensa/config/system.h>
+#include "freertos/xtensa_context.h"
+#include "esp_private/panic_reason.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "soc/dport_reg.h"
+
+/*
+
+Interrupt , a high-priority interrupt, is used for several things:
+- Dport access mediation
+- Cache error panic handler
+- Interrupt watchdog panic handler
+
+*/
+
+#define L4_INTR_STACK_SIZE  8
+#define L4_INTR_A2_OFFSET   0
+#define L4_INTR_A3_OFFSET   4
+    .data
+_l4_intr_stack:
+    .space      L4_INTR_STACK_SIZE
+
+    .section .iram1,"ax"
+    .global     xt_highint4
+    .type       xt_highint4,@function
+    .align      4
+xt_highint4:
+
+#ifndef CONFIG_FREERTOS_UNICORE
+    /* See if we're here for the dport access interrupt */
+    rsr     a0, INTERRUPT
+    extui   a0, a0, ETS_DPORT_INUM, 1
+    bnez    a0, .handle_dport_access_int
+#endif // CONFIG_FREERTOS_UNICORE
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save vaddr into exception frame */
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* Figure out reason, save into EXCCAUSE reg */
+
+    rsr     a0, INTERRUPT
+    extui   a0, a0, ETS_CACHEERR_INUM, 1 /* get cacheerr int bit */
+    beqz    a0, 1f
+    /* Kill this interrupt; we cannot reset it. */
+    rsr     a0, INTENABLE
+    movi    a4, ~(1<<ETS_CACHEERR_INUM)
+    and     a0, a4, a0
+    wsr     a0, INTENABLE
+    movi    a0, PANIC_RSN_CACHEERR
+    j 9f
+1:
+#if CONFIG_INT_WDT_CHECK_CPU1
+    /* Check if the cause is the app cpu failing to tick.*/
+    movi    a0, int_wdt_app_cpu_ticked
+    l32i    a0, a0, 0
+    bnez    a0, 2f
+    /* It is. Modify cause. */
+    movi    a0,PANIC_RSN_INTWDT_CPU1
+    j 9f
+2:
+#endif
+    /* Set EXCCAUSE to reflect cause of the wdt int trigger */
+    movi    a0,PANIC_RSN_INTWDT_CPU0
+9:
+    /* Found the reason, now save it. */
+    s32i    a0, sp, XT_STK_EXCCAUSE
+
+    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+
+    s32i    a0, sp, XT_STK_A0
+
+    /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    wsr     a0, PS
+
+    //Call panic handler
+    mov     a6,sp
+    call4   panicHandler
+
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+
+
+
+#ifndef CONFIG_FREERTOS_UNICORE
+
+    .align      4
+.handle_dport_access_int:
+    /* This section is for dport access register protection */
+    /* Allocate exception frame and save minimal context. */
+    /* Because the interrupt cause code has protection that only
+       allows one cpu to enter in the dport section of the L4
+       interrupt at one time, there's no need to have two
+       _l4_intr_stack for each cpu */
+
+    /* This int is edge-triggered and needs clearing. */
+    movi    a0, (1<<ETS_DPORT_INUM)
+    wsr     a0, INTCLEAR
+
+    /* Save A2, A3 so we can use those registers */
+    movi    a0, _l4_intr_stack
+    s32i    a2, a0, L4_INTR_A2_OFFSET
+    s32i    a3, a0, L4_INTR_A3_OFFSET
+
+    /* handle dport interrupt */
+    /* get CORE_ID */
+    getcoreid   a0
+    beqz    a0, 2f
+
+    /* current cpu is 1 */
+    movi    a0, DPORT_CPU_INTR_FROM_CPU_3_REG
+    movi    a2, 0
+    s32i    a2, a0, 0   /* clear intr */
+    movi    a0, 0       /* other cpu id */
+    j       3f
+2:
+    /* current cpu is 0 */
+    movi    a0, DPORT_CPU_INTR_FROM_CPU_2_REG
+    movi    a2, 0
+    s32i    a2, a0, 0   /* clear intr */
+    movi    a0, 1       /* other cpu id */
+3:
+    /* set and wait flag */
+    movi    a2, dport_access_start
+    addx4   a2, a0, a2
+    movi    a3, 1
+    s32i    a3, a2, 0
+    memw
+    movi    a2, dport_access_end
+    addx4   a2, a0, a2
+.check_dport_access_end:
+    l32i    a3, a2, 0
+    beqz    a3, .check_dport_access_end
+
+    /* Done. Restore registers and return. */
+    movi    a0, _l4_intr_stack
+    l32i    a2, a0, L4_INTR_A2_OFFSET
+    l32i    a3, a0, L4_INTR_A3_OFFSET
+    rsync                                   /* ensure register restored */
+
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif // CONFIG_FREERTOS_UNICORE
+
+/* The linker has no reason to link in this file; all symbols it exports are already defined
+   (weakly!) in the default int handler. Define a symbol here so we can use it to have the
+   linker inspect this anyway. */
+
+    .global ld_include_panic_highint_hdl
+ld_include_panic_highint_hdl:
+
+
+
+

components/esp32s2beta/esp_clk_internal.h

@@ -0,0 +1,44 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file esp_clk_internal.h
+ *
+ * Private clock-related functions
+ */
+
+/**
+ * @brief Initialize clock-related settings
+ *
+ * Called from cpu_start.c, not intended to be called from other places.
+ * This function configures the CPU clock, RTC slow and fast clocks, and
+ * performs RTC slow clock calibration.
+ */
+void esp_clk_init(void);
+
+
+/**
+ * @brief Disables clock of some peripherals
+ *
+ * Called from cpu_start.c, not intended to be called from other places.
+ * This function disables clock of useless peripherals when cpu starts.
+ */
+void esp_perip_clk_init(void);
+
+/* Selects an external clock source (32 kHz) for RTC.
+ * Only internal use in unit test.
+ */
+void rtc_clk_select_rtc_slow_clk();

components/esp32s2beta/esp_timer_esp32s2beta.c

@@ -0,0 +1,407 @@
+// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "esp_err.h"
+#include "esp_timer.h"
+#include "esp_system.h"
+#include "esp_task.h"
+#include "esp_attr.h"
+#include "esp_intr_alloc.h"
+#include "esp_log.h"
+#include "esp32s2beta/clk.h"
+#include "esp_private/esp_timer_impl.h"
+#include "soc/frc_timer_reg.h"
+#include "soc/rtc.h"
+#include "soc/periph_defs.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+
+/**
+ * @file esp_timer_esp32.c
+ * @brief Implementation of chip-specific part of esp_timer
+ *
+ * This implementation uses FRC2 (legacy) timer of the ESP32. This timer is
+ * a 32-bit up-counting timer, with a programmable compare value (called 'alarm'
+ * hereafter). When the timer reaches compare value, interrupt is raised.
+ * The timer can be configured to produce an edge or a level interrupt.
+ *
+ * In this implementation the timer is used for two purposes:
+ * 1. To generate interrupts at certain moments — the upper layer of esp_timer
+ *    uses this to trigger callbacks of esp_timer objects.
+ *
+ * 2. To keep track of time relative to application start. This facility is
+ *    used both by the upper layer of esp_timer and by time functions, such as
+ *    gettimeofday.
+ *
+ * Whenever an esp_timer timer is armed (configured to fire once or
+ * periodically), timer_insert function of the upper layer calls
+ * esp_timer_impl_set_alarm to enable the interrupt at the required moment.
+ * This implementation sets up the timer interrupt to fire at the earliest of
+ * two moments:
+ * a) the time requested by upper layer
+ * b) the time when the timer count reaches 0xffffffff (i.e. is about to overflow)
+ *
+ * Whenever the interrupt fires and timer overflow is detected, interrupt hander
+ * increments s_time_base_us variable, which is used for timekeeping.
+ *
+ * When the interrupt fires, the upper layer is notified, and it dispatches
+ * the callbacks (if any timers have expired) and sets new alarm value (if any
+ * timers are still active).
+ *
+ * At any point in time, esp_timer_impl_get_time will return the current timer
+ * value (expressed in microseconds) plus s_time_base_us. To account for the
+ * case when the timer counter has overflown, but the interrupt has not fired
+ * yet (for example, because interupts are temporarily disabled),
+ * esp_timer_impl_get_time will also check timer overflow flag, and will add
+ * s_timer_us_per_overflow to the returned value.
+ *
+ */
+
+/* Timer is clocked from APB. To allow for integer scaling factor between ticks
+ * and microseconds, divider 1 is used. 16 or 256 would not work for APB
+ * frequencies such as 40 or 26 or 2 MHz.
+ */
+#define TIMER_DIV           1
+#define TIMER_DIV_CFG       FRC_TIMER_PRESCALER_1
+
+/* ALARM_OVERFLOW_VAL is used as timer alarm value when there are not timers
+ * enabled which need to fire within the next timer overflow period. This alarm
+ * is used to perform timekeeping (i.e. to track timer overflows).
+ * Due to the 0xffffffff cannot recognize the real overflow or the scenario that
+ * ISR happens follow set_alarm, so change the ALARM_OVERFLOW_VAL to resolve this problem.
+ * Set it to 0xefffffffUL. The remain 0x10000000UL(about 3 second) is enough to handle ISR.
+ */
+#define DEFAULT_ALARM_OVERFLOW_VAL 0xefffffffUL
+
+/* Provision to set lower overflow value for unit testing. Lowering the
+ * overflow value helps check for race conditions which occur near overflow
+ * moment.
+ */
+#ifndef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
+#define ALARM_OVERFLOW_VAL  DEFAULT_ALARM_OVERFLOW_VAL
+#else
+static uint32_t s_alarm_overflow_val = DEFAULT_ALARM_OVERFLOW_VAL;
+#define ALARM_OVERFLOW_VAL (s_alarm_overflow_val)
+#endif
+
+static const char* TAG = "esp_timer_impl";
+
+// Interrupt handle returned by the interrupt allocator
+static intr_handle_t s_timer_interrupt_handle;
+
+// Function from the upper layer to be called when the interrupt happens.
+// Registered in esp_timer_impl_init.
+static intr_handler_t s_alarm_handler;
+
+// Time in microseconds from startup to the moment
+// when timer counter was last equal to 0. This variable is updated each time
+// when timer overflows, and when APB frequency switch is performed.
+static uint64_t s_time_base_us;
+
+// Number of timer ticks per microsecond. Calculated from APB frequency.
+static uint32_t s_timer_ticks_per_us;
+
+// Period between timer overflows, in microseconds.
+// Equal to 2^32 / s_timer_ticks_per_us.
+static uint32_t s_timer_us_per_overflow;
+
+// When frequency switch happens, timer counter is reset to 0, s_time_base_us
+// is updated, and alarm value is re-calculated based on the new APB frequency.
+// However because the frequency switch can happen before the final
+// interrupt handler is invoked, interrupt handler may see a different alarm
+// value than the one which caused an interrupt. This can cause interrupt handler
+// to consider that the interrupt has happened due to timer overflow, incrementing
+// s_time_base_us. To avoid this, frequency switch hook sets this flag if
+// it needs to set timer alarm value to ALARM_OVERFLOW_VAL. Interrupt handler
+// will not increment s_time_base_us if this flag is set.
+static bool s_mask_overflow;
+
+//The timer_overflow_happened read alarm register to tell if overflow happened.
+//However, there is a monent that overflow happens, and before ISR function called
+//alarm register is set to another value, then you call timer_overflow_happened,
+//it will return false.
+//So we store the overflow value when new alarm is to be set.
+static bool s_overflow_happened;
+
+#ifdef CONFIG_PM_DFS_USE_RTC_TIMER_REF
+// If DFS is enabled, upon the first frequency change this value is set to the
+// difference between esp_timer value and RTC timer value. On every subsequent
+// frequency change, s_time_base_us is adjusted to maintain the same difference
+// between esp_timer and RTC timer. (All mentioned values are in microseconds.)
+static uint64_t s_rtc_time_diff = 0;
+#endif
+
+// Spinlock used to protect access to static variables above and to the hardware
+// registers.
+portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED;
+
+//Use FRC_TIMER_LOAD_VALUE(1) instead of UINT32_MAX, convenience to change FRC TIMER for future
+#define TIMER_IS_AFTER_OVERFLOW(a) (ALARM_OVERFLOW_VAL < (a) && (a) <= FRC_TIMER_LOAD_VALUE(1))
+
+// Check if timer overflow has happened (but was not handled by ISR yet)
+static inline bool IRAM_ATTR timer_overflow_happened()
+{
+    if (s_overflow_happened) {
+        return true;
+    }
+
+    return ((REG_READ(FRC_TIMER_CTRL_REG(1)) & FRC_TIMER_INT_STATUS) != 0 &&
+              ((REG_READ(FRC_TIMER_ALARM_REG(1)) == ALARM_OVERFLOW_VAL && TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1))) && !s_mask_overflow) ||
+               (!TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_ALARM_REG(1))) && TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1))))));
+}
+
+static inline void IRAM_ATTR timer_count_reload(void)
+{
+    //this function should be only called the real overflow happened. And the count cannot be very approach to 0xffffffff.
+    assert(TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1))));
+
+    /* Restart the timer count by current time count minus ALARM_OVERFLOW_VAL(0xefffffff), it may cause error, if current tick is near boundary.
+     * But even if the error happen 100% per overflow(the distance of each real overflow is about 50 second),
+     * the error is 0.0125us*N per 50s(the FRC time clock is 80MHz), the N is the ticks run by the line following,
+     * Normally, N is less than 10, assume N is 10, so the error accumulation is only 6.48ms per month.
+     * In fact, if the CPU frequency is large than 80MHz. The error accumulation will be more less than 6.48ms per month.
+     * so It can be adopted.
+     */
+    REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL);
+}
+
+void esp_timer_impl_lock()
+{
+    portENTER_CRITICAL(&s_time_update_lock);
+}
+
+void esp_timer_impl_unlock()
+{
+    portEXIT_CRITICAL(&s_time_update_lock);
+}
+
+uint64_t IRAM_ATTR esp_timer_impl_get_time()
+{
+    uint32_t timer_val;
+    uint64_t time_base;
+    uint32_t ticks_per_us;
+    bool overflow;
+
+    do {
+        /* Read all values needed to calculate current time */
+        timer_val = REG_READ(FRC_TIMER_COUNT_REG(1));
+        time_base = s_time_base_us;
+        overflow = timer_overflow_happened();
+        ticks_per_us = s_timer_ticks_per_us;
+
+        /* Read them again and compare */
+        /* In this function, do not call timer_count_reload() when overflow is true.
+         * Because there's remain count enough to allow FRC_TIMER_COUNT_REG grow
+         */
+        if (REG_READ(FRC_TIMER_COUNT_REG(1)) > timer_val &&
+                time_base == *((volatile uint64_t*) &s_time_base_us) &&
+                ticks_per_us == *((volatile uint32_t*) &s_timer_ticks_per_us) &&
+                overflow == timer_overflow_happened()) {
+            break;
+        }
+
+        /* If any value has changed (other than the counter increasing), read again */
+    } while(true);
+
+    uint64_t result = time_base
+                        + timer_val / ticks_per_us;
+    return result;
+}
+
+void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp)
+{
+    portENTER_CRITICAL(&s_time_update_lock);
+    // Alarm time relative to the moment when counter was 0
+    uint64_t time_after_timebase_us = timestamp - s_time_base_us;
+    // Adjust current time if overflow has happened
+    bool overflow = timer_overflow_happened();
+    uint64_t cur_count = REG_READ(FRC_TIMER_COUNT_REG(1));
+
+    if (overflow) {
+        assert(time_after_timebase_us > s_timer_us_per_overflow);
+        time_after_timebase_us -= s_timer_us_per_overflow;
+        s_overflow_happened = true;
+    }
+    // Calculate desired timer compare value (may exceed 2^32-1)
+    uint64_t compare_val = time_after_timebase_us * s_timer_ticks_per_us;
+    uint32_t alarm_reg_val = ALARM_OVERFLOW_VAL;
+    // Use calculated alarm value if it is less than ALARM_OVERFLOW_VAL.
+    // Note that if by the time we update ALARM_REG, COUNT_REG value is higher,
+    // interrupt will not happen for another ALARM_OVERFLOW_VAL timer ticks,
+    // so need to check if alarm value is too close in the future (e.g. <2 us away).
+    const uint32_t offset = s_timer_ticks_per_us * 2;
+    if (compare_val < ALARM_OVERFLOW_VAL) {
+        if (compare_val < cur_count + offset) {
+            compare_val = cur_count + offset;
+            if (compare_val > ALARM_OVERFLOW_VAL) {
+                compare_val = ALARM_OVERFLOW_VAL;
+            }
+        }
+        alarm_reg_val = (uint32_t) compare_val;
+    }
+    REG_WRITE(FRC_TIMER_ALARM_REG(1), alarm_reg_val);
+    portEXIT_CRITICAL(&s_time_update_lock);
+}
+
+static void IRAM_ATTR timer_alarm_isr(void *arg)
+{
+    portENTER_CRITICAL_ISR(&s_time_update_lock);
+    // Timekeeping: adjust s_time_base_us if counter has passed ALARM_OVERFLOW_VAL
+    if (timer_overflow_happened()) {
+        timer_count_reload();
+        s_time_base_us += s_timer_us_per_overflow;
+        s_overflow_happened = false;
+    }
+    s_mask_overflow = false;
+    // Clear interrupt status
+    REG_WRITE(FRC_TIMER_INT_REG(1), FRC_TIMER_INT_CLR);
+    // Set alarm to the next overflow moment. Later, upper layer function may
+    // call esp_timer_impl_set_alarm to change this to an earlier value.
+    REG_WRITE(FRC_TIMER_ALARM_REG(1), ALARM_OVERFLOW_VAL);
+    portEXIT_CRITICAL_ISR(&s_time_update_lock);
+    // Call the upper layer handler
+    (*s_alarm_handler)(arg);
+}
+
+void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
+{
+    portENTER_CRITICAL_ISR(&s_time_update_lock);
+    /* Bail out if the timer is not initialized yet */
+    if (s_timer_interrupt_handle == NULL) {
+        portEXIT_CRITICAL_ISR(&s_time_update_lock);
+        return;
+    }
+
+    uint32_t new_ticks_per_us = apb_ticks_per_us / TIMER_DIV;
+    uint32_t alarm = REG_READ(FRC_TIMER_ALARM_REG(1));
+    uint32_t count = REG_READ(FRC_TIMER_COUNT_REG(1));
+    uint64_t ticks_to_alarm = alarm - count;
+    uint64_t new_ticks = (ticks_to_alarm * new_ticks_per_us) / s_timer_ticks_per_us;
+    uint32_t new_alarm_val;
+    if (alarm > count && new_ticks <= ALARM_OVERFLOW_VAL) {
+        new_alarm_val = new_ticks;
+    } else {
+        new_alarm_val = ALARM_OVERFLOW_VAL;
+        if (alarm != ALARM_OVERFLOW_VAL) {
+            s_mask_overflow = true;
+        }
+    }
+    REG_WRITE(FRC_TIMER_ALARM_REG(1), new_alarm_val);
+    REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
+
+    s_time_base_us += count / s_timer_ticks_per_us;
+
+#ifdef CONFIG_PM_DFS_USE_RTC_TIMER_REF
+    // Due to the extra time required to read RTC time, don't attempt this
+    // adjustment when switching to a higher frequency (which usually
+    // happens in an interrupt).
+    if (new_ticks_per_us < s_timer_ticks_per_us) {
+        uint64_t rtc_time = esp_clk_rtc_time();
+        uint64_t new_rtc_time_diff = s_time_base_us - rtc_time;
+        if (s_rtc_time_diff != 0) {
+            uint64_t correction = new_rtc_time_diff - s_rtc_time_diff;
+            s_time_base_us -= correction;
+        } else {
+            s_rtc_time_diff = new_rtc_time_diff;
+        }
+    }
+#endif // CONFIG_PM_DFS_USE_RTC_TIMER_REF
+
+    s_timer_ticks_per_us = new_ticks_per_us;
+    s_timer_us_per_overflow = ALARM_OVERFLOW_VAL / new_ticks_per_us;
+
+    portEXIT_CRITICAL_ISR(&s_time_update_lock);
+}
+
+void esp_timer_impl_advance(int64_t time_us)
+{
+    assert(time_us > 0 && "negative adjustments not supported yet");
+
+    portENTER_CRITICAL(&s_time_update_lock);
+    uint64_t count = REG_READ(FRC_TIMER_COUNT_REG(1));
+    /* Trigger an ISR to handle past alarms and set new one.
+     * ISR handler will run once we exit the critical section.
+     */
+    REG_WRITE(FRC_TIMER_ALARM_REG(1), 0);
+    REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
+    s_time_base_us += count / s_timer_ticks_per_us + time_us;
+    s_overflow_happened = false;
+    portEXIT_CRITICAL(&s_time_update_lock);
+}
+
+esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
+{
+    s_alarm_handler = alarm_handler;
+
+    esp_err_t err = esp_intr_alloc(ETS_TIMER2_INTR_SOURCE,
+            ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM,
+            &timer_alarm_isr, NULL, &s_timer_interrupt_handle);
+
+    if (err != ESP_OK) {
+        ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (0x%0x)", err);
+        return err;
+    }
+
+    uint32_t apb_freq = rtc_clk_apb_freq_get();
+    s_timer_ticks_per_us = apb_freq / 1000000 / TIMER_DIV;
+    assert(s_timer_ticks_per_us > 0
+            && apb_freq % TIMER_DIV == 0
+            && "APB frequency does not result in a valid ticks_per_us value");
+    s_timer_us_per_overflow = ALARM_OVERFLOW_VAL / s_timer_ticks_per_us;
+    s_time_base_us = 0;
+
+    REG_WRITE(FRC_TIMER_ALARM_REG(1), ALARM_OVERFLOW_VAL);
+    REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
+    REG_WRITE(FRC_TIMER_CTRL_REG(1),
+            TIMER_DIV_CFG | FRC_TIMER_ENABLE | FRC_TIMER_LEVEL_INT);
+    REG_WRITE(FRC_TIMER_INT_REG(1), FRC_TIMER_INT_CLR);
+    ESP_ERROR_CHECK( esp_intr_enable(s_timer_interrupt_handle) );
+
+    return ESP_OK;
+}
+
+void esp_timer_impl_deinit()
+{
+    esp_intr_disable(s_timer_interrupt_handle);
+
+    REG_WRITE(FRC_TIMER_CTRL_REG(1), 0);
+    REG_WRITE(FRC_TIMER_ALARM_REG(1), 0);
+    REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
+
+    esp_intr_free(s_timer_interrupt_handle);
+    s_timer_interrupt_handle = NULL;
+}
+
+// FIXME: This value is safe for 80MHz APB frequency.
+// Should be modified to depend on clock frequency.
+
+uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us()
+{
+    return 50;
+}
+
+#ifdef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
+uint32_t esp_timer_impl_get_overflow_val()
+{
+    return s_alarm_overflow_val;
+}
+
+void esp_timer_impl_set_overflow_val(uint32_t overflow_val)
+{
+    s_alarm_overflow_val = overflow_val;
+    /* update alarm value */
+    esp_timer_impl_update_apb_freq(esp_clk_apb_freq() / 1000000);
+}
+#endif // ESP_TIMER_DYNAMIC_OVERFLOW_VAL

components/esp32s2beta/gdbstub.c

@@ -0,0 +1,356 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/******************************************************************************
+ * Description: A stub to make the ESP32 debuggable by GDB over the serial
+ * port, at least enough to do a backtrace on panic. This gdbstub is read-only:
+ * it allows inspecting the ESP32 state
+ *******************************************************************************/
+
+#include "esp32s2beta/rom/ets_sys.h"
+#include "soc/uart_reg.h"
+#include "soc/io_mux_reg.h"
+#include "esp_private/gdbstub.h"
+#include "driver/gpio.h"
+
+//Length of buffer used to reserve GDB commands. Has to be at least able to fit the G command, which
+//implies a minimum size of about 320 bytes.
+#define PBUFLEN 512
+
+static unsigned char cmd[PBUFLEN];		//GDB command input buffer
+static char chsum;						//Running checksum of the output packet
+
+#define ATTR_GDBFN
+
+//Receive a char from the uart. Uses polling and feeds the watchdog.
+static int ATTR_GDBFN gdbRecvChar() {
+	int i;
+	while (((READ_PERI_REG(UART_STATUS_REG(0))>>UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT)==0) ;
+	i=READ_PERI_REG(UART_FIFO_AHB_REG(0));
+	return i;
+}
+
+//Send a char to the uart.
+static void ATTR_GDBFN gdbSendChar(char c) {
+	while (((READ_PERI_REG(UART_STATUS_REG(0))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT)>=126) ;
+	WRITE_PERI_REG(UART_FIFO_AHB_REG(0), c);
+}
+
+//Send the start of a packet; reset checksum calculation.
+static void ATTR_GDBFN gdbPacketStart() {
+	chsum=0;
+	gdbSendChar('$');
+}
+
+//Send a char as part of a packet
+static void ATTR_GDBFN gdbPacketChar(char c) {
+	if (c=='#' || c=='$' || c=='}' || c=='*') {
+		gdbSendChar('}');
+		gdbSendChar(c^0x20);
+		chsum+=(c^0x20)+'}';
+	} else {
+		gdbSendChar(c);
+		chsum+=c;
+	}
+}
+
+//Send a string as part of a packet
+static void ATTR_GDBFN gdbPacketStr(const char *c) {
+	while (*c!=0) {
+		gdbPacketChar(*c);
+		c++;
+	}
+}
+
+//Send a hex val as part of a packet. 'bits'/4 dictates the number of hex chars sent.
+static void ATTR_GDBFN gdbPacketHex(int val, int bits) {
+	char hexChars[]="0123456789abcdef";
+	int i;
+	for (i=bits; i>0; i-=4) {
+		gdbPacketChar(hexChars[(val>>(i-4))&0xf]);
+	}
+}
+
+//Finish sending a packet.
+static void ATTR_GDBFN gdbPacketEnd() {
+	gdbSendChar('#');
+	gdbPacketHex(chsum, 8);
+}
+
+//Error states used by the routines that grab stuff from the incoming gdb packet
+#define ST_ENDPACKET -1
+#define ST_ERR -2
+#define ST_OK -3
+#define ST_CONT -4
+
+//Grab a hex value from the gdb packet. Ptr will get positioned on the end
+//of the hex string, as far as the routine has read into it. Bits/4 indicates
+//the max amount of hex chars it gobbles up. Bits can be -1 to eat up as much
+//hex chars as possible.
+static long ATTR_GDBFN gdbGetHexVal(unsigned char **ptr, int bits) {
+	int i;
+	int no;
+	unsigned int v=0;
+	char c;
+	no=bits/4;
+	if (bits==-1) no=64;
+	for (i=0; i<no; i++) {
+		c=**ptr;
+		(*ptr)++;
+		if (c>='0' && c<='9') {
+			v<<=4;
+			v|=(c-'0');
+		} else if (c>='A' && c<='F') {
+			v<<=4;
+			v|=(c-'A')+10;
+		} else if (c>='a' && c<='f') {
+			v<<=4;
+			v|=(c-'a')+10;
+		} else if (c=='#') {
+			if (bits==-1) {
+				(*ptr)--;
+				return v;
+			}
+			return ST_ENDPACKET;
+		} else {
+			if (bits==-1) {
+				(*ptr)--;
+				return v;
+			}
+			return ST_ERR;
+		}
+	}
+	return v;
+}
+
+//Swap an int into the form gdb wants it
+static int ATTR_GDBFN iswap(int i) {
+	int r;
+	r=((i>>24)&0xff);
+	r|=((i>>16)&0xff)<<8;
+	r|=((i>>8)&0xff)<<16;
+	r|=((i>>0)&0xff)<<24;
+	return r;
+}
+
+//Read a byte from ESP32 memory.
+static unsigned char ATTR_GDBFN readbyte(unsigned int p) {
+	int *i=(int*)(p&(~3));
+	if (p<0x20000000 || p>=0x80000000) return -1;
+	return *i>>((p&3)*8);
+}
+
+
+//Register file in the format exp108 gdb port expects it.
+//Inspired by gdb/regformats/reg-xtensa.dat
+typedef struct {
+	uint32_t pc;
+	uint32_t a[64];
+	uint32_t lbeg;
+	uint32_t lend;
+	uint32_t lcount;
+	uint32_t sar;
+	uint32_t windowbase;
+	uint32_t windowstart;
+	uint32_t configid0;
+	uint32_t configid1;
+	uint32_t ps;
+	uint32_t threadptr;
+	uint32_t br;
+	uint32_t scompare1;
+	uint32_t acclo;
+	uint32_t acchi;
+	uint32_t m0;
+	uint32_t m1;
+	uint32_t m2;
+	uint32_t m3;
+	uint32_t expstate;  //I'm going to assume this is exccause...
+	uint32_t f64r_lo;
+	uint32_t f64r_hi;
+	uint32_t f64s;
+	uint32_t f[16];
+	uint32_t fcr;
+	uint32_t fsr;
+} GdbRegFile;
+
+
+GdbRegFile gdbRegFile;
+
+/*
+//Register format as the Xtensa HAL has it:
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit)
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+[..]
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+// Temporary space for saving stuff during window spill
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+#endif
+STRUCT_END(XtExcFrame)
+*/
+
+
+static void dumpHwToRegfile(XtExcFrame *frame) {
+	int i;
+	long *frameAregs=&frame->a0;
+	gdbRegFile.pc=frame->pc;
+	for (i=0; i<16; i++) gdbRegFile.a[i]=frameAregs[i];
+	for (i=16; i<64; i++) gdbRegFile.a[i]=0xDEADBEEF;
+	gdbRegFile.sar=frame->sar;
+	//All windows have been spilled to the stack by the ISR routines. The following values should indicate that.
+	gdbRegFile.sar=frame->sar;
+	gdbRegFile.windowbase=0; //0
+	gdbRegFile.windowstart=0x1; //1
+	gdbRegFile.configid0=0xdeadbeef; //ToDo
+	gdbRegFile.configid1=0xdeadbeef; //ToDo
+	gdbRegFile.ps=frame->ps-PS_EXCM_MASK;
+	gdbRegFile.threadptr=0xdeadbeef; //ToDo
+	gdbRegFile.br=0xdeadbeef; //ToDo
+	gdbRegFile.scompare1=0xdeadbeef; //ToDo
+	gdbRegFile.acclo=0xdeadbeef; //ToDo
+	gdbRegFile.acchi=0xdeadbeef; //ToDo
+	gdbRegFile.m0=0xdeadbeef; //ToDo
+	gdbRegFile.m1=0xdeadbeef; //ToDo
+	gdbRegFile.m2=0xdeadbeef; //ToDo
+	gdbRegFile.m3=0xdeadbeef; //ToDo
+	gdbRegFile.expstate=frame->exccause; //ToDo
+}
+
+
+//Send the reason execution is stopped to GDB.
+static void sendReason() {
+	//exception-to-signal mapping
+	char exceptionSignal[]={4,31,11,11,2,6,8,0,6,7,0,0,7,7,7,7};
+	int i=0;
+	gdbPacketStart();
+	gdbPacketChar('T');
+	i=gdbRegFile.expstate&0x7f;
+	if (i<sizeof(exceptionSignal)) {
+		gdbPacketHex(exceptionSignal[i], 8);
+	} else {
+		gdbPacketHex(11, 8);
+	}
+	gdbPacketEnd();
+}
+
+//Handle a command as received from GDB.
+static int gdbHandleCommand(unsigned char *cmd, int len) {
+	//Handle a command
+	int i, j, k;
+	unsigned char *data=cmd+1;
+	if (cmd[0]=='g') {		//send all registers to gdb
+		int *p=(int*)&gdbRegFile;
+		gdbPacketStart();
+		for (i=0; i<sizeof(GdbRegFile)/4; i++) gdbPacketHex(iswap(*p++), 32);
+		gdbPacketEnd();
+	} else if (cmd[0]=='G') {	//receive content for all registers from gdb
+		int *p=(int*)&gdbRegFile;
+		for (i=0; i<sizeof(GdbRegFile)/4; i++) *p++=iswap(gdbGetHexVal(&data, 32));;
+		gdbPacketStart();
+		gdbPacketStr("OK");
+		gdbPacketEnd();
+	} else if (cmd[0]=='m') {	//read memory to gdb
+		i=gdbGetHexVal(&data, -1);
+		data++;
+		j=gdbGetHexVal(&data, -1);
+		gdbPacketStart();
+		for (k=0; k<j; k++) {
+			gdbPacketHex(readbyte(i++), 8);
+		}
+		gdbPacketEnd();
+	} else if (cmd[0]=='?') {	//Reply with stop reason
+		sendReason();
+	} else {
+		//We don't recognize or support whatever GDB just sent us.
+		gdbPacketStart();
+		gdbPacketEnd();
+		return ST_ERR;
+	}
+	return ST_OK;
+}
+
+
+//Lower layer: grab a command packet and check the checksum
+//Calls gdbHandleCommand on the packet if the checksum is OK
+//Returns ST_OK on success, ST_ERR when checksum fails, a
+//character if it is received instead of the GDB packet
+//start char.
+static int gdbReadCommand() {
+	unsigned char c;
+	unsigned char chsum=0, rchsum;
+	unsigned char sentchs[2];
+	int p=0;
+	unsigned char *ptr;
+	c=gdbRecvChar();
+	if (c!='$') return c;
+	while(1) {
+		c=gdbRecvChar();
+		if (c=='#') {	//end of packet, checksum follows
+			cmd[p]=0;
+			break;
+		}
+		chsum+=c;
+		if (c=='$') {
+			//Wut, restart packet?
+			chsum=0;
+			p=0;
+			continue;
+		}
+		if (c=='}') {		//escape the next char
+			c=gdbRecvChar();
+			chsum+=c;
+			c^=0x20;
+		}
+		cmd[p++]=c;
+		if (p>=PBUFLEN) return ST_ERR;
+	}
+	//A # has been received. Get and check the received chsum.
+	sentchs[0]=gdbRecvChar();
+	sentchs[1]=gdbRecvChar();
+	ptr=&sentchs[0];
+	rchsum=gdbGetHexVal(&ptr, 8);
+	if (rchsum!=chsum) {
+		gdbSendChar('-');
+		return ST_ERR;
+	} else {
+		gdbSendChar('+');
+		return gdbHandleCommand(cmd, p);
+	}
+}
+
+
+
+void esp_gdbstub_panic_handler(XtExcFrame *frame) {
+	dumpHwToRegfile(frame);
+	//Make sure txd/rxd are enabled
+	gpio_pullup_dis(1);
+	PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
+	PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
+
+	sendReason();
+	while(gdbReadCommand()!=ST_CONT);
+	while(1);
+}
+

components/esp32s2beta/hw_random.c

@@ -0,0 +1,70 @@
+// Copyright 2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+#include <sys/param.h>
+#include "esp_attr.h"
+#include "esp32s2beta/clk.h"
+#include "soc/wdev_reg.h"
+#include "freertos/FreeRTOSConfig.h"
+#include "xtensa/core-macros.h"
+
+uint32_t IRAM_ATTR esp_random(void)
+{
+    /* The PRNG which implements WDEV_RANDOM register gets 2 bits
+     * of extra entropy from a hardware randomness source every APB clock cycle
+     * (provided WiFi or BT are enabled). To make sure entropy is not drained
+     * faster than it is added, this function needs to wait for at least 16 APB
+     * clock cycles after reading previous word. This implementation may actually
+     * wait a bit longer due to extra time spent in arithmetic and branch statements.
+     *
+     * As a (probably unncessary) precaution to avoid returning the
+     * RNG state as-is, the result is XORed with additional
+     * WDEV_RND_REG reads while waiting.
+     */
+
+    /* This code does not run in a critical section, so CPU frequency switch may
+     * happens while this code runs (this will not happen in the current
+     * implementation, but possible in the future). However if that happens,
+     * the number of cycles spent on frequency switching will certainly be more
+     * than the number of cycles we need to wait here.
+     */
+    uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
+
+    static uint32_t last_ccount = 0;
+    uint32_t ccount;
+    uint32_t result = 0;
+    do {
+        ccount = XTHAL_GET_CCOUNT();
+        result ^= REG_READ(WDEV_RND_REG);
+    } while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
+    last_ccount = ccount;
+    return result ^ REG_READ(WDEV_RND_REG);
+}
+
+void esp_fill_random(void *buf, size_t len)
+{
+    assert(buf != NULL);
+    uint8_t *buf_bytes = (uint8_t *)buf;
+    while (len > 0) {
+        uint32_t word = esp_random();
+        uint32_t to_copy = MIN(sizeof(word), len);
+        memcpy(buf_bytes, &word, to_copy);
+        buf_bytes += to_copy;
+        len -= to_copy;
+    }
+}

components/esp32s2beta/include/esp32s2beta/brownout.h

@@ -0,0 +1,21 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_BROWNOUT_H
+#define __ESP_BROWNOUT_H
+
+void esp_brownout_init();
+
+#endif

components/esp32s2beta/include/esp32s2beta/cache_err_int.h

@@ -0,0 +1,33 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+/**
+ * @brief initialize cache invalid access interrupt
+ *
+ * This function enables cache invalid access interrupt source and connects it
+ * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
+ * from the startup code.
+ */
+void esp_cache_err_int_init();
+
+
+/**
+ * @brief get the CPU which caused cache invalid access interrupt
+ * @return
+ *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
+ *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
+ *  - (-1) otherwise
+ */
+int esp_cache_err_get_cpuid();

components/esp32s2beta/include/esp32s2beta/clk.h

@@ -0,0 +1,75 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file esp_clk.h
+ *
+ * This file contains declarations of clock related functions.
+ */
+
+/**
+ * @brief Get the calibration value of RTC slow clock
+ *
+ * The value is in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ *
+ * @return the calibration value obtained using rtc_clk_cal, at startup time
+ */
+uint32_t esp_clk_slowclk_cal_get();
+
+/**
+ * @brief Update the calibration value of RTC slow clock
+ *
+ * The value has to be in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ * This value is used by timekeeping functions (such as gettimeofday) to
+ * calculate current time based on RTC counter value.
+ * @param value calibration value obtained using rtc_clk_cal
+ */
+void esp_clk_slowclk_cal_set(uint32_t value);
+
+/**
+ * @brief Return current CPU clock frequency
+ * When frequency switching is performed, this frequency may change.
+ * However it is guaranteed that the frequency never changes with a critical
+ * section.
+ *
+ * @return CPU clock frequency, in Hz
+ */
+int esp_clk_cpu_freq(void);
+
+/**
+ * @brief Return current APB clock frequency
+ *
+ * When frequency switching is performed, this frequency may change.
+ * However it is guaranteed that the frequency never changes with a critical
+ * section.
+ *
+ * @return APB clock frequency, in Hz
+ */
+int esp_clk_apb_freq(void);
+
+
+/**
+ * @brief Read value of RTC counter, converting it to microseconds
+ * @attention The value returned by this function may change abruptly when
+ * calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
+ * function. This should not happen unless application calls esp_clk_slowclk_cal_set.
+ * In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
+ *
+ * @return Value or RTC counter, expressed in microseconds
+ */
+uint64_t esp_clk_rtc_time();

components/esp32s2beta/include/esp32s2beta/dport_access.h

@@ -0,0 +1,52 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+
+#ifndef _ESP_DPORT_ACCESS_H_
+#define _ESP_DPORT_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void esp_dport_access_stall_other_cpu_start(void);
+void esp_dport_access_stall_other_cpu_end(void);
+void esp_dport_access_int_init(void);
+void esp_dport_access_int_pause(void);
+void esp_dport_access_int_resume(void);
+void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
+uint32_t esp_dport_access_reg_read(uint32_t reg);
+uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
+//This routine does not stop the dport routines in any way that is recoverable. Please
+//only call in case of panic().
+void esp_dport_access_int_abort(void);
+
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) || !defined(CONFIG_CHIP_IS_ESP32)
+#define DPORT_STALL_OTHER_CPU_START()
+#define DPORT_STALL_OTHER_CPU_END()
+#define DPORT_INTERRUPT_DISABLE()
+#define DPORT_INTERRUPT_RESTORE()
+#else
+#define DPORT_STALL_OTHER_CPU_START()   esp_dport_access_stall_other_cpu_start()
+#define DPORT_STALL_OTHER_CPU_END()     esp_dport_access_stall_other_cpu_end()
+#define DPORT_INTERRUPT_DISABLE()       unsigned int intLvl = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
+#define DPORT_INTERRUPT_RESTORE()       XTOS_RESTORE_JUST_INTLEVEL(intLvl)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESP_DPORT_ACCESS_H_ */

components/esp32s2beta/include/esp32s2beta/pm.h

@@ -0,0 +1,42 @@
+// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#pragma once
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+
+#include "soc/rtc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief Power management config for ESP32
+ *
+ * Pass a pointer to this structure as an argument to esp_pm_configure function.
+ */
+typedef struct {
+    rtc_cpu_freq_t max_cpu_freq;    /*!< Maximum CPU frequency to use */
+    rtc_cpu_freq_t min_cpu_freq;    /*!< Minimum CPU frequency to use when no frequency locks are taken */
+    bool light_sleep_enable;        /*!< Enter light sleep when no locks are taken */
+} esp_pm_config_esp32_t;
+
+
+#ifdef __cplusplus
+}
+#endif

components/esp32s2beta/include/esp32s2beta/spiram.h

@@ -0,0 +1,90 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_SPIRAM_H
+#define __ESP_SPIRAM_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include "esp_err.h"
+
+/**
+ * @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
+ *
+ * @return ESP_OK on success
+ */
+esp_err_t esp_spiram_init();
+
+/**
+ * @brief Configure Cache/MMU for access to external SPI RAM.
+ *
+ * Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
+ * option is enabled. Applications which need to enable SPI RAM at run time
+ * can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
+ *
+ * @attention this function must be called with flash cache disabled.
+ */
+void esp_spiram_init_cache();
+
+
+/**
+ * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
+ * (in case of a dual-core system) the app CPU is online. This test overwrites the 
+ * memory with crap, so do not call after e.g. the heap allocator has stored important
+ * stuff in SPI RAM.
+ *
+ * @return true on success, false on failed memory test
+ */
+bool esp_spiram_test();
+
+
+/**
+ * @brief Add the initialized SPI RAM to the heap allocator.
+ */
+esp_err_t esp_spiram_add_to_heapalloc();
+
+
+/**
+ * @brief Get the size of the attached SPI RAM chip selected in menuconfig
+ *
+ * @return Size in bytes, or 0 if no external RAM chip support compiled in.
+ */
+size_t esp_spiram_get_size();
+
+
+/**
+ * @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
+ * cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
+ * RAM cache.
+ *
+ * This is meant for use from within the SPI flash code.
+ */
+void esp_spiram_writeback_cache();
+
+
+
+/**
+ * @brief Reserve a pool of internal memory for specific DMA/internal allocations
+ *
+ * @param size Size of reserved pool in bytes
+ *
+ * @return
+ *          - ESP_OK on success
+ *          - ESP_ERR_NO_MEM when no memory available for pool
+ */
+esp_err_t esp_spiram_reserve_dma_pool(size_t size);
+
+
+#endif

components/esp32s2beta/include/esp_attr.h

@@ -0,0 +1,58 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ATTR_H__
+#define __ESP_ATTR_H__
+
+#define ROMFN_ATTR
+
+//Normally, the linker script will put all code and rodata in flash,
+//and all variables in shared RAM. These macros can be used to redirect
+//particular functions/variables to other memory regions.
+
+// Forces code into IRAM instead of flash.
+#define IRAM_ATTR __attribute__((section(".iram1")))
+
+// Forces data into DRAM instead of flash
+#define DRAM_ATTR __attribute__((section(".dram1")))
+
+// Forces data to be 4 bytes aligned
+#define WORD_ALIGNED_ATTR __attribute__((aligned(4)))
+
+// Forces data to be placed to DMA-capable places
+#define DMA_ATTR WORD_ALIGNED_ATTR DRAM_ATTR
+
+// Forces a string into DRAM instead of flash
+// Use as ets_printf(DRAM_STR("Hello world!\n"));
+#define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;}))
+
+// Forces code into RTC fast memory. See "docs/deep-sleep-stub.rst"
+#define RTC_IRAM_ATTR __attribute__((section(".rtc.text")))
+
+// Forces data into RTC slow memory. See "docs/deep-sleep-stub.rst"
+// Any variable marked with this attribute will keep its value
+// during a deep sleep / wake cycle.
+#define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
+
+// Forces read-only data into RTC slow memory. See "docs/deep-sleep-stub.rst"
+#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
+
+// Forces data into noinit section to avoid initialization after restart.
+#define __NOINIT_ATTR __attribute__((section(".noinit")))
+
+// Forces data into RTC slow memory of .noinit section.
+// Any variable marked with this attribute will keep its value
+// after restart or during a deep sleep / wake cycle.
+#define RTC_NOINIT_ATTR  __attribute__((section(".rtc_noinit")))
+
+#endif /* __ESP_ATTR_H__ */

components/esp32s2beta/include/esp_clk.h

@@ -0,0 +1,75 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file esp_clk.h
+ *
+ * This file contains declarations of clock related functions.
+ */
+
+/**
+ * @brief Get the calibration value of RTC slow clock
+ *
+ * The value is in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ *
+ * @return the calibration value obtained using rtc_clk_cal, at startup time
+ */
+uint32_t esp_clk_slowclk_cal_get();
+
+/**
+ * @brief Update the calibration value of RTC slow clock
+ *
+ * The value has to be in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ * This value is used by timekeeping functions (such as gettimeofday) to
+ * calculate current time based on RTC counter value.
+ * @param value calibration value obtained using rtc_clk_cal
+ */
+void esp_clk_slowclk_cal_set(uint32_t value);
+
+/**
+ * @brief Return current CPU clock frequency
+ * When frequency switching is performed, this frequency may change.
+ * However it is guaranteed that the frequency never changes with a critical
+ * section.
+ *
+ * @return CPU clock frequency, in Hz
+ */
+int esp_clk_cpu_freq(void);
+
+/**
+ * @brief Return current APB clock frequency
+ *
+ * When frequency switching is performed, this frequency may change.
+ * However it is guaranteed that the frequency never changes with a critical
+ * section.
+ *
+ * @return APB clock frequency, in Hz
+ */
+int esp_clk_apb_freq(void);
+
+
+/**
+ * @brief Read value of RTC counter, converting it to microseconds
+ * @attention The value returned by this function may change abruptly when
+ * calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
+ * function. This should not happen unless application calls esp_clk_slowclk_cal_set.
+ * In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
+ *
+ * @return Value or RTC counter, expressed in microseconds
+ */
+uint64_t esp_clk_rtc_time();

components/esp32s2beta/include/esp_intr.h

@@ -0,0 +1,89 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_INTR_H__
+#define __ESP_INTR_H__
+
+#include "rom/ets_sys.h"
+#include "freertos/xtensa_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))
+
+#define ESP_EPWM_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))
+
+#define ESP_MPWM_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))
+
+#define ESP_SPI1_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))
+
+#define ESP_SPI2_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))
+
+#define ESP_SPI3_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))
+
+#define ESP_I2S0_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))
+
+#define ESP_PCNT_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))
+
+#define ESP_LEDC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))
+
+#define ESP_WMAC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))
+
+#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
+
+#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
+
+#define ESP_GPIO_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
+
+#define ESP_UART0_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
+
+#define ESP_WDT_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
+
+#define ESP_RTC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))
+
+#define ESP_SLC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))
+
+#define ESP_RMT_CTRL_INTRL(func,arg)\
+    xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))
+
+#define ESP_INTR_ENABLE(inum) \
+    xt_ints_on((1<<inum))
+
+#define ESP_INTR_DISABLE(inum) \
+    xt_ints_off((1<<inum))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_INTR_H__ */

components/esp32s2beta/include/esp_intr_alloc.h

@@ -0,0 +1,295 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_INTR_ALLOC_H__
+#define __ESP_INTR_ALLOC_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Intr_Alloc
+  * @{
+  */
+
+
+/** @brief Interrupt allocation flags
+ *
+ * These flags can be used to specify which interrupt qualities the
+ * code calling esp_intr_alloc* needs.
+ *
+ */
+
+//Keep the LEVELx values as they are here; they match up with (1<<level)
+#define ESP_INTR_FLAG_LEVEL1		(1<<1)	///< Accept a Level 1 interrupt vector (lowest priority)
+#define ESP_INTR_FLAG_LEVEL2		(1<<2)	///< Accept a Level 2 interrupt vector
+#define ESP_INTR_FLAG_LEVEL3		(1<<3)	///< Accept a Level 3 interrupt vector
+#define ESP_INTR_FLAG_LEVEL4		(1<<4)	///< Accept a Level 4 interrupt vector
+#define ESP_INTR_FLAG_LEVEL5		(1<<5)	///< Accept a Level 5 interrupt vector
+#define ESP_INTR_FLAG_LEVEL6		(1<<6)	///< Accept a Level 6 interrupt vector
+#define ESP_INTR_FLAG_NMI			(1<<7)	///< Accept a Level 7 interrupt vector (highest priority)
+#define ESP_INTR_FLAG_SHARED		(1<<8)	///< Interrupt can be shared between ISRs
+#define ESP_INTR_FLAG_EDGE			(1<<9)	///< Edge-triggered interrupt
+#define ESP_INTR_FLAG_IRAM			(1<<10)	///< ISR can be called if cache is disabled
+#define ESP_INTR_FLAG_INTRDISABLED	(1<<11)	///< Return with this interrupt disabled
+
+#define ESP_INTR_FLAG_LOWMED	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
+#define ESP_INTR_FLAG_HIGH		(ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
+
+#define ESP_INTR_FLAG_LEVELMASK	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
+								 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
+								 ESP_INTR_FLAG_NMI) ///< Mask for all level flags
+/**@}*/
+
+
+/** @addtogroup Intr_Alloc_Pseudo_Src
+  * @{
+  */
+
+/**
+ * The esp_intr_alloc* functions can allocate an int for all ETS_*_INTR_SOURCE interrupt sources that
+ * are routed through the interrupt mux. Apart from these sources, each core also has some internal
+ * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
+ * pass these pseudo-sources to the functions.
+ */
+#define ETS_INTERNAL_TIMER0_INTR_SOURCE		-1 ///< Xtensa timer 0 interrupt source
+#define ETS_INTERNAL_TIMER1_INTR_SOURCE		-2 ///< Xtensa timer 1 interrupt source
+#define ETS_INTERNAL_TIMER2_INTR_SOURCE		-3 ///< Xtensa timer 2 interrupt source
+#define ETS_INTERNAL_SW0_INTR_SOURCE		-4 ///< Software int source 1
+#define ETS_INTERNAL_SW1_INTR_SOURCE		-5 ///< Software int source 2
+#define ETS_INTERNAL_PROFILING_INTR_SOURCE	-6 ///< Int source for profiling
+
+/**@}*/
+
+// This is used to provide SystemView with positive IRQ IDs, otherwise sheduler events are not shown properly
+#define ETS_INTERNAL_INTR_SOURCE_OFF		(-ETS_INTERNAL_PROFILING_INTR_SOURCE)
+
+typedef void (*intr_handler_t)(void *arg); 
+
+
+typedef struct intr_handle_data_t intr_handle_data_t;
+typedef intr_handle_data_t* intr_handle_t ;
+
+/**
+ * @brief Mark an interrupt as a shared interrupt
+ * 
+ * This will mark a certain interrupt on the specified CPU as
+ * an interrupt that can be used to hook shared interrupt handlers
+ * to.
+ *
+ * @param intno The number of the interrupt (0-31)
+ * @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
+ * @param is_in_iram Shared interrupt is for handlers that reside in IRAM and
+ *                   the int can be left enabled while the flash cache is disabled.
+ *
+ * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
+
+/**
+ * @brief Reserve an interrupt to be used outside of this framework
+ * 
+ * This will mark a certain interrupt on the specified CPU as
+ * reserved, not to be allocated for any reason.
+ *
+ * @param intno The number of the interrupt (0-31)
+ * @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
+ *
+ * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_reserve(int intno, int cpu);
+
+/**
+ * @brief Allocate an interrupt with the given parameters.
+ *
+ * This finds an interrupt that matches the restrictions as given in the flags
+ * parameter, maps the given interrupt source to it and hooks up the given
+ * interrupt handler (with optional argument) as well. If needed, it can return
+ * a handle for the interrupt as well.
+ *
+ * The interrupt will always be allocated on the core that runs this function.
+ *
+ * If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or
+ * RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned.
+ *
+ * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
+ *               sources, as defined in soc/soc.h, or one of the internal
+ *               ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
+ * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
+ *               choice of interrupts that this routine can choose from. If this value
+ *               is 0, it will default to allocating a non-shared interrupt of level
+ *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
+ *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
+ *               from this function with the interrupt disabled.
+ * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
+ *               is requested, because these types of interrupts aren't C-callable.
+ * @param arg    Optional argument for passed to the interrupt handler
+ * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be
+ *               used to request details or free the interrupt. Can be NULL if no handle
+ *               is required.
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *arg, intr_handle_t *ret_handle);
+
+
+/**
+ * @brief Allocate an interrupt with the given parameters.
+ *
+ *
+ * This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
+ * combo. For shared interrupts, the handler is only called if a read from the specified 
+ * register, ANDed with the mask, returns non-zero. By passing an interrupt status register
+ * address and a fitting mask, this can be used to accelerate interrupt handling in the case
+ * a shared interrupt is triggered; by checking the interrupt statuses first, the code can
+ * decide which ISRs can be skipped
+ *
+ * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
+ *               sources, as defined in soc/soc.h, or one of the internal
+ *               ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
+ * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
+ *               choice of interrupts that this routine can choose from. If this value
+ *               is 0, it will default to allocating a non-shared interrupt of level
+ *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
+ *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
+ *               from this function with the interrupt disabled.
+ * @param intrstatusreg The address of an interrupt status register
+ * @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
+ *               that are 1 in the mask set, the ISR will be called. If not, it will be
+ *               skipped.
+ * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
+ *               is requested, because these types of interrupts aren't C-callable.
+ * @param arg    Optional argument for passed to the interrupt handler
+ * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be
+ *               used to request details or free the interrupt. Can be NULL if no handle
+ *               is required.
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusreg, uint32_t intrstatusmask, intr_handler_t handler, void *arg, intr_handle_t *ret_handle);
+
+
+/**
+ * @brief Disable and free an interrupt.
+ *
+ * Use an interrupt handle to disable the interrupt and release the resources
+ * associated with it.
+ *
+ * @note 
+ * When the handler shares its source with other handlers, the interrupt status 
+ * bits it's responsible for should be managed properly before freeing it. see 
+ * ``esp_intr_disable`` for more details.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return ESP_ERR_INVALID_ARG if handle is invalid, or esp_intr_free runs on another core than
+ *                             where the interrupt is allocated on.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_free(intr_handle_t handle);
+
+
+/**
+ * @brief Get CPU number an interrupt is tied to
+ * 
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return The core number where the interrupt is allocated
+ */
+int esp_intr_get_cpu(intr_handle_t handle);
+
+/**
+ * @brief Get the allocated interrupt for a certain handle
+ * 
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return The interrupt number
+ */
+int esp_intr_get_intno(intr_handle_t handle);
+
+/**
+ * @brief Disable the interrupt associated with the handle
+ * 
+ * @note 
+ * 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
+ * CPU the interrupt is allocated on. Other interrupts have no such restriction.
+ * 2. When several handlers sharing a same interrupt source, interrupt status bits, which are 
+ * handled in the handler to be disabled, should be masked before the disabling, or handled
+ * in other enabled interrupts properly. Miss of interrupt status handling will cause infinite 
+ * interrupt calls and finally system crash.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_disable(intr_handle_t handle);
+
+/**
+ * @brief Enable the interrupt associated with the handle
+ *
+ * @note For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
+ *       CPU the interrupt is allocated on. Other interrupts have no such restriction.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_enable(intr_handle_t handle);
+
+/**
+ * @brief Set the "in IRAM" status of the handler.
+ *
+ * @note Does not work on shared interrupts.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ * @param is_in_iram Whether the handler associated with this handle resides in IRAM.
+ *                   Handlers residing in IRAM can be called when cache is disabled.
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram);
+
+/**
+ * @brief Disable interrupts that aren't specifically marked as running from IRAM
+ */
+void esp_intr_noniram_disable();
+
+
+/**
+ * @brief Re-enable interrupts disabled by esp_intr_noniram_disable
+ */
+void esp_intr_noniram_enable();
+
+/**@}*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/esp32s2beta/include/esp_sleep.h

@@ -0,0 +1,325 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/gpio.h"
+#include "driver/touch_pad.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Logic function used for EXT1 wakeup mode.
+ */
+typedef enum {
+    ESP_EXT1_WAKEUP_ALL_LOW = 0,    //!< Wake the chip when all selected GPIOs go low
+    ESP_EXT1_WAKEUP_ANY_HIGH = 1    //!< Wake the chip when any of the selected GPIOs go high
+} esp_sleep_ext1_wakeup_mode_t;
+
+/**
+ * @brief Power domains which can be powered down in sleep mode
+ */
+typedef enum {
+    ESP_PD_DOMAIN_RTC_PERIPH,      //!< RTC IO, sensors and ULP co-processor
+    ESP_PD_DOMAIN_RTC_SLOW_MEM,    //!< RTC slow memory
+    ESP_PD_DOMAIN_RTC_FAST_MEM,    //!< RTC fast memory
+    ESP_PD_DOMAIN_XTAL,            //!< XTAL oscillator
+    ESP_PD_DOMAIN_MAX              //!< Number of domains
+} esp_sleep_pd_domain_t;
+
+/**
+ * @brief Power down options
+ */
+typedef enum {
+    ESP_PD_OPTION_OFF,      //!< Power down the power domain in sleep mode
+    ESP_PD_OPTION_ON,       //!< Keep power domain enabled during sleep mode
+    ESP_PD_OPTION_AUTO      //!< Keep power domain enabled in sleep mode, if it is needed by one of the wakeup options. Otherwise power it down.
+} esp_sleep_pd_option_t;
+
+/**
+ * @brief Sleep wakeup cause
+ */
+typedef enum {
+    ESP_SLEEP_WAKEUP_UNDEFINED,    //!< In case of deep sleep, reset was not caused by exit from deep sleep
+    ESP_SLEEP_WAKEUP_EXT0,         //!< Wakeup caused by external signal using RTC_IO
+    ESP_SLEEP_WAKEUP_EXT1,         //!< Wakeup caused by external signal using RTC_CNTL
+    ESP_SLEEP_WAKEUP_TIMER,        //!< Wakeup caused by timer
+    ESP_SLEEP_WAKEUP_TOUCHPAD,     //!< Wakeup caused by touchpad
+    ESP_SLEEP_WAKEUP_ULP,          //!< Wakeup caused by ULP program
+} esp_sleep_source_t;
+
+/* Leave this type define for compatibility */
+typedef esp_sleep_source_t esp_sleep_wakeup_cause_t;
+
+/**
+ * @brief Disable wakeup source
+ *
+ * This function is used to deactivate wake up trigger for source
+ * defined as parameter of the function.
+ *
+ * @note This function does not modify wake up configuration in RTC.
+ *       It will be performed in esp_sleep_start function.
+ *
+ * See docs/sleep-modes.rst for details.
+ *
+ * @param source - number of source to disable of type esp_sleep_source_t
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if trigger was not active
+ */
+esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
+
+/**
+ * @brief Enable wakeup by ULP coprocessor
+ * @note In revisions 0 and 1 of the ESP32, ULP wakeup source
+ *       can not be used when RTC_PERIPH power domain is forced
+ *       to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
+ *       source is used.
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
+ */
+esp_err_t esp_sleep_enable_ulp_wakeup();
+
+/**
+ * @brief Enable wakeup by timer
+ * @param time_in_us  time before wakeup, in microseconds
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if value is out of range (TBD)
+ */
+esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
+
+/**
+ * @brief Enable wakeup by touch sensor
+ *
+ * @note In revisions 0 and 1 of the ESP32, touch wakeup source
+ *       can not be used when RTC_PERIPH power domain is forced
+ *       to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
+ *       source is used.
+ *
+ * @note The FSM mode of the touch button should be configured
+ *       as the timer trigger mode.
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
+ */
+esp_err_t esp_sleep_enable_touchpad_wakeup();
+
+/**
+ * @brief Get the touch pad which caused wakeup
+ *
+ * If wakeup was caused by another source, this function will return TOUCH_PAD_MAX;
+ *
+ * @return touch pad which caused wakeup
+ */
+touch_pad_t esp_sleep_get_touchpad_wakeup_status();
+
+/**
+ * @brief Enable wakeup using a pin
+ *
+ * This function uses external wakeup feature of RTC_IO peripheral.
+ * It will work only if RTC peripherals are kept on during sleep.
+ *
+ * This feature can monitor any pin which is an RTC IO. Once the pin transitions
+ * into the state given by level argument, the chip will be woken up.
+ *
+ * @note This function does not modify pin configuration. The pin is
+ *       configured in esp_sleep_start, immediately before entering sleep mode.
+ *
+ * @note In revisions 0 and 1 of the ESP32, ext0 wakeup source
+ *       can not be used together with touch or ULP wakeup sources.
+ *
+ * @param gpio_num  GPIO number used as wakeup source. Only GPIOs which are have RTC
+ *             functionality can be used: 0,2,4,12-15,25-27,32-39.
+ * @param level  input level which will trigger wakeup (0=low, 1=high)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO,
+ *        or the mode is invalid
+ *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
+ */
+esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level);
+
+/**
+ * @brief Enable wakeup using multiple pins
+ *
+ * This function uses external wakeup feature of RTC controller.
+ * It will work even if RTC peripherals are shut down during sleep.
+ *
+ * This feature can monitor any number of pins which are in RTC IOs.
+ * Once any of the selected pins goes into the state given by mode argument,
+ * the chip will be woken up.
+ *
+ * @note This function does not modify pin configuration. The pins are
+ *       configured in esp_sleep_start, immediately before
+ *       entering sleep mode.
+ *
+ * @note internal pullups and pulldowns don't work when RTC peripherals are
+ *       shut down. In this case, external resistors need to be added.
+ *       Alternatively, RTC peripherals (and pullups/pulldowns) may be
+ *       kept enabled using esp_sleep_pd_config function.
+ *
+ * @param mask  bit mask of GPIO numbers which will cause wakeup. Only GPIOs
+ *              which are have RTC functionality can be used in this bit map:
+ *              0,2,4,12-15,25-27,32-39.
+ * @param mode select logic function used to determine wakeup condition:
+ *            - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low
+ *            - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO,
+ *        or mode is invalid
+ */
+esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode);
+
+
+/**
+ * @brief Get the bit mask of GPIOs which caused wakeup (ext1)
+ *
+ * If wakeup was caused by another source, this function will return 0.
+ *
+ * @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
+ */
+uint64_t esp_sleep_get_ext1_wakeup_status();
+
+/**
+ * @brief Set power down mode for an RTC power domain in sleep mode
+ *
+ * If not set set using this API, all power domains default to ESP_PD_OPTION_AUTO.
+ *
+ * @param domain  power domain to configure
+ * @param option  power down option (ESP_PD_OPTION_OFF, ESP_PD_OPTION_ON, or ESP_PD_OPTION_AUTO)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if either of the arguments is out of range
+ */
+esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
+                                   esp_sleep_pd_option_t option);
+
+/**
+ * @brief Enter deep sleep with the configured wakeup options
+ *
+ * This function does not return.
+ */
+void esp_deep_sleep_start() __attribute__((noreturn));
+
+/**
+ * @brief Enter light sleep with the configured wakeup options
+ *
+ * @return
+ *  - ESP_OK on success (returned after wakeup)
+ *  - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped
+ */
+esp_err_t esp_light_sleep_start();
+
+/**
+ * @brief Enter deep-sleep mode
+ *
+ * The device will automatically wake up after the deep-sleep time
+ * Upon waking up, the device calls deep sleep wake stub, and then proceeds
+ * to load application.
+ *
+ * Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup
+ * followed by a call to esp_deep_sleep_start.
+ *
+ * esp_deep_sleep does not shut down WiFi, BT, and higher level protocol
+ * connections gracefully.
+ * Make sure relevant WiFi and BT stack functions are called to close any
+ * connections and deinitialize the peripherals. These include:
+ *     - esp_bluedroid_disable
+ *     - esp_bt_controller_disable
+ *     - esp_wifi_stop
+ *
+ * This function does not return.
+ *
+ * @param time_in_us  deep-sleep time, unit: microsecond
+ */
+void esp_deep_sleep(uint64_t time_in_us) __attribute__((noreturn));
+
+/**
+ * @brief Enter deep-sleep mode
+ *
+ * Function has been renamed to esp_deep_sleep.
+ * This name is deprecated and will be removed in a future version.
+ *
+ * @param time_in_us  deep-sleep time, unit: microsecond
+ */
+void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated));
+
+
+/**
+ * @brief Get the source which caused wakeup from sleep
+ *
+ * @return wakeup cause, or ESP_DEEP_SLEEP_WAKEUP_UNDEFINED if reset happened for reason other than deep sleep wakeup
+ */
+esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause();
+
+
+/**
+ * @brief Default stub to run on wake from deep sleep.
+ *
+ * Allows for executing code immediately on wake from sleep, before
+ * the software bootloader or ESP-IDF app has started up.
+ *
+ * This function is weak-linked, so you can implement your own version
+ * to run code immediately when the chip wakes from
+ * sleep.
+ *
+ * See docs/deep-sleep-stub.rst for details.
+ */
+void esp_wake_deep_sleep(void);
+
+/**
+ * @brief Function type for stub to run on wake from sleep.
+ *
+ */
+typedef void (*esp_deep_sleep_wake_stub_fn_t)(void);
+
+/**
+ * @brief Install a new stub at runtime to run on wake from deep sleep
+ *
+ * If implementing esp_wake_deep_sleep() then it is not necessary to
+ * call this function.
+ *
+ * However, it is possible to call this function to substitute a
+ * different deep sleep stub. Any function used as a deep sleep stub
+ * must be marked RTC_IRAM_ATTR, and must obey the same rules given
+ * for esp_wake_deep_sleep().
+ */
+void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub);
+
+/**
+ * @brief Get current wake from deep sleep stub
+ * @return Return current wake from deep sleep stub, or NULL if
+ *         no stub is installed.
+ */
+esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
+
+/**
+ *  @brief The default esp-idf-provided esp_wake_deep_sleep() stub.
+ *
+ *  See docs/deep-sleep-stub.rst for details.
+ */
+void esp_default_wake_deep_sleep(void);
+
+
+#ifdef __cplusplus
+}
+#endif

components/esp32s2beta/include/esp_spiram.h

@@ -0,0 +1,90 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_SPIRAM_H
+#define __ESP_SPIRAM_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include "esp_err.h"
+
+/**
+ * @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
+ *
+ * @return ESP_OK on success
+ */
+esp_err_t esp_spiram_init();
+
+/**
+ * @brief Configure Cache/MMU for access to external SPI RAM.
+ *
+ * Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
+ * option is enabled. Applications which need to enable SPI RAM at run time
+ * can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
+ *
+ * @attention this function must be called with flash cache disabled.
+ */
+void esp_spiram_init_cache();
+
+
+/**
+ * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
+ * (in case of a dual-core system) the app CPU is online. This test overwrites the 
+ * memory with crap, so do not call after e.g. the heap allocator has stored important
+ * stuff in SPI RAM.
+ *
+ * @return true on success, false on failed memory test
+ */
+bool esp_spiram_test();
+
+
+/**
+ * @brief Add the initialized SPI RAM to the heap allocator.
+ */
+esp_err_t esp_spiram_add_to_heapalloc();
+
+
+/**
+ * @brief Get the size of the attached SPI RAM chip selected in menuconfig
+ *
+ * @return Size in bytes, or 0 if no external RAM chip support compiled in.
+ */
+size_t esp_spiram_get_size();
+
+
+/**
+ * @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
+ * cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
+ * RAM cache.
+ *
+ * This is meant for use from within the SPI flash code.
+ */
+void esp_spiram_writeback_cache();
+
+
+
+/**
+ * @brief Reserve a pool of internal memory for specific DMA/internal allocations
+ *
+ * @param size Size of reserved pool in bytes
+ *
+ * @return
+ *          - ESP_OK on success
+ *          - ESP_ERR_NO_MEM when no memory available for pool
+ */
+esp_err_t esp_spiram_reserve_dma_pool(size_t size);
+
+
+#endif

components/esp32s2beta/include/esp_ssc.h

@@ -0,0 +1,119 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_SSC_H__
+#define __ESP_SSC_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CMD_T_ASYNC   0x01
+#define CMD_T_SYNC    0x02
+
+typedef struct cmd_s {
+    char *cmd_str;
+    uint8_t flag;
+    uint8_t id;
+    void (* cmd_func)(void);
+    void (* cmd_callback)(void *arg);
+} ssc_cmd_t;
+
+#define MAX_LINE_N  127
+
+typedef enum {
+    SSC_BR_9600   = 9600,
+    SSC_BR_19200  = 19200,
+    SSC_BR_38400  = 38400,
+    SSC_BR_57600  = 57600,
+    SSC_BR_74880  = 74880,
+    SSC_BR_115200 = 115200,
+    SSC_BR_230400 = 230400,
+    SSC_BR_460800 = 460800,
+    SSC_BR_921600 = 921600
+} SscBaudRate;
+
+/** \defgroup SSC_APIs SSC APIs
+  * @brief SSC APIs
+  *
+  * SSC means simple serial command.
+  * SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c.
+  *
+  */
+
+/** @addtogroup SSC_APIs
+  * @{
+  */
+
+/**
+  * @brief  Initial the ssc function.
+  *
+  * @attention param is no use, just compatible with ESP8266, default bandrate is 115200
+  *
+  * @param  SscBaudRate bandrate : baud rate
+  *
+  * @return null
+  */
+void ssc_attach(SscBaudRate bandrate);
+
+/**
+  * @brief   Get the length of the simple serial command.
+  *
+  * @param   null
+  *
+  * @return  length of the command.
+  */
+int ssc_param_len(void);
+
+/**
+  * @brief   Get the simple serial command string.
+  *
+  * @param   null
+  *
+  * @return  the command.
+  */
+char *ssc_param_str(void);
+
+/**
+  * @brief   Parse the simple serial command (ssc).
+  *
+  * @param   char *pLine  : [input] the ssc string
+  * @param   char *argv[] : [output] parameters of the ssc
+  *
+  * @return  the number of parameters.
+  */
+int ssc_parse_param(char *pLine, char *argv[]);
+
+/**
+  * @brief  Register the user-defined simple serial command (ssc) set.
+  *
+  * @param  ssc_cmd_t *cmdset   : the ssc set
+  * @param  uint8 cmdnum        : number of commands
+  * @param  void (* help)(void) : callback of user-guide
+  *
+  * @return  null
+  */
+void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void));
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SSC_H__ */

components/esp32s2beta/int_wdt.c

@@ -0,0 +1,106 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+
+#include "sdkconfig.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include <esp_types.h>
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+#include "esp_attr.h"
+#include "esp_freertos_hooks.h"
+#include "soc/timer_group_struct.h"
+#include "soc/timer_group_reg.h"
+#include "driver/timer.h"
+#include "driver/periph_ctrl.h"
+#include "esp_int_wdt.h"
+
+#if CONFIG_INT_WDT
+
+
+#define WDT_INT_NUM 24
+
+
+//Take care: the tick hook can also be called before esp_int_wdt_init() is called.
+#if CONFIG_INT_WDT_CHECK_CPU1
+//Not static; the ISR assembly checks this.
+bool int_wdt_app_cpu_ticked=false;
+
+static void IRAM_ATTR tick_hook(void) {
+    if (xPortGetCoreID()!=0) {
+        int_wdt_app_cpu_ticked=true;
+    } else {
+        //Only feed wdt if app cpu also ticked.
+        if (int_wdt_app_cpu_ticked) {
+            TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+            TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
+            TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
+            TIMERG1.wdt_feed=1;
+            TIMERG1.wdt_wprotect=0;
+            int_wdt_app_cpu_ticked=false;
+        }
+    }
+}
+#else
+static void IRAM_ATTR tick_hook(void) {
+    if (xPortGetCoreID()!=0) return;
+    TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
+    TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
+    TIMERG1.wdt_feed=1;
+    TIMERG1.wdt_wprotect=0;
+}
+#endif
+
+
+void esp_int_wdt_init() {
+    periph_module_enable(PERIPH_TIMG1_MODULE);
+    TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG1.wdt_config0.sys_reset_length=7;                 //3.2uS
+    TIMERG1.wdt_config0.cpu_reset_length=7;                 //3.2uS
+    TIMERG1.wdt_config0.level_int_en=1;
+    TIMERG1.wdt_config0.stg0=TIMG_WDT_STG_SEL_INT;          //1st stage timeout: interrupt
+    TIMERG1.wdt_config0.stg1=TIMG_WDT_STG_SEL_RESET_SYSTEM; //2nd stage timeout: reset system
+    TIMERG1.wdt_config1.clk_prescale=80*500;                //Prescaler: wdt counts in ticks of 0.5mS
+    //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
+    //it to their actual value.
+    TIMERG1.wdt_config2=10000;
+    TIMERG1.wdt_config3=10000;
+    TIMERG1.wdt_config0.en=1;
+    TIMERG1.wdt_feed=1;
+    TIMERG1.wdt_wprotect=0;
+    TIMERG1.int_clr.wdt=1;
+    timer_group_intr_enable(TIMER_GROUP_1, TIMG_WDT_INT_ENA_M);
+}
+
+void esp_int_wdt_cpu_init()
+{
+    esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
+    ESP_INTR_DISABLE(WDT_INT_NUM);
+    intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
+    //We do not register a handler for the interrupt because it is interrupt level 4 which
+    //is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
+    //this interrupt.
+    ESP_INTR_ENABLE(WDT_INT_NUM);
+}
+
+
+
+#endif

components/esp32s2beta/intr_alloc.c

@@ -0,0 +1,900 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+
+#include "sdkconfig.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include <esp_types.h>
+#include "esp_err.h"
+//#define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
+#include "esp_log.h"
+#include "esp_intr_alloc.h"
+#include "esp_attr.h"
+#include "esp_intr_alloc.h"
+#include <limits.h>
+#include <assert.h>
+
+static const char* TAG = "intr_alloc";
+
+#define ETS_INTERNAL_TIMER0_INTR_NO 6
+#define ETS_INTERNAL_TIMER1_INTR_NO 15
+#define ETS_INTERNAL_TIMER2_INTR_NO 16
+#define ETS_INTERNAL_SW0_INTR_NO 7
+#define ETS_INTERNAL_SW1_INTR_NO 29
+#define ETS_INTERNAL_PROFILING_INTR_NO 11
+
+
+/*
+Define this to debug the choices made when allocating the interrupt. This leads to much debugging
+output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
+being triggered, that is why it is separate from the normal LOG* scheme.
+*/
+//define DEBUG_INT_ALLOC_DECISIONS
+#ifdef DEBUG_INT_ALLOC_DECISIONS
+# define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__)
+#else
+# define ALCHLOG(...) do {} while (0)
+#endif
+
+
+typedef enum {
+    INTDESC_NORMAL=0,
+    INTDESC_RESVD,
+    INTDESC_SPECIAL //for xtensa timers / software ints
+} int_desc_flag_t;
+
+typedef enum {
+    INTTP_LEVEL=0,
+    INTTP_EDGE,
+    INTTP_NA
+} int_type_t;
+
+typedef struct {
+    int level;
+    int_type_t type;
+    int_desc_flag_t cpuflags[2];
+} int_desc_t;
+
+
+//We should mark the interrupt for the timer used by FreeRTOS as reserved. The specific timer
+//is selectable using menuconfig; we use these cpp bits to convert that into something we can use in
+//the table below.
+#if CONFIG_FREERTOS_CORETIMER_0
+#define INT6RES INTDESC_RESVD
+#else
+#define INT6RES INTDESC_SPECIAL
+#endif
+
+#if CONFIG_FREERTOS_CORETIMER_1
+#define INT15RES INTDESC_RESVD
+#else
+#define INT15RES INTDESC_SPECIAL
+#endif
+
+//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
+const static int_desc_t int_desc[32]={
+    { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //0
+    { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //1
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //2
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //3
+    { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_NORMAL} }, //4
+    { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //5
+    { 1, INTTP_NA,    {INT6RES,        INT6RES       } }, //6
+    { 1, INTTP_NA,    {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //7
+    { 1, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //8
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //9
+    { 1, INTTP_EDGE , {INTDESC_NORMAL, INTDESC_NORMAL} }, //10
+    { 3, INTTP_NA,    {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //11
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //12
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //13
+    { 7, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //14, NMI
+    { 3, INTTP_NA,    {INT15RES,       INT15RES      } }, //15
+    { 5, INTTP_NA,    {INTDESC_SPECIAL,INTDESC_SPECIAL} }, //16
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //17
+    { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //18
+    { 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //19
+    { 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //20
+    { 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //21
+    { 3, INTTP_EDGE,  {INTDESC_RESVD,  INTDESC_NORMAL} }, //22
+    { 3, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //23
+    { 4, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_NORMAL} }, //24
+    { 4, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //25
+    { 5, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //26
+    { 3, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //27
+    { 4, INTTP_EDGE,  {INTDESC_NORMAL, INTDESC_NORMAL} }, //28
+    { 3, INTTP_NA,    {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //29
+    { 4, INTTP_EDGE,  {INTDESC_RESVD,  INTDESC_RESVD } }, //30
+    { 5, INTTP_LEVEL, {INTDESC_RESVD,  INTDESC_RESVD } }, //31
+};
+
+typedef struct shared_vector_desc_t shared_vector_desc_t;
+typedef struct vector_desc_t vector_desc_t;
+
+struct shared_vector_desc_t {
+    int disabled: 1;
+    int source: 8;
+    volatile uint32_t *statusreg;
+    uint32_t statusmask;
+    intr_handler_t isr;
+    void *arg;
+    shared_vector_desc_t *next;
+};
+
+
+#define VECDESC_FL_RESERVED     (1<<0)
+#define VECDESC_FL_INIRAM       (1<<1)
+#define VECDESC_FL_SHARED       (1<<2)
+#define VECDESC_FL_NONSHARED    (1<<3)
+
+//Pack using bitfields for better memory use
+struct vector_desc_t {
+    int flags: 16;                          //OR of VECDESC_FLAG_* defines
+    unsigned int cpu: 1;
+    unsigned int intno: 5;
+    int source: 8;                          //Interrupt mux flags, used when not shared
+    shared_vector_desc_t *shared_vec_info;  //used when VECDESC_FL_SHARED
+    vector_desc_t *next;
+};
+
+struct intr_handle_data_t {
+    vector_desc_t *vector_desc;
+    shared_vector_desc_t *shared_vector_desc;
+};
+
+typedef struct non_shared_isr_arg_t non_shared_isr_arg_t;
+
+struct non_shared_isr_arg_t {
+    intr_handler_t isr;
+    void *isr_arg;
+    int source;
+};
+
+//Linked list of vector descriptions, sorted by cpu.intno value
+static vector_desc_t *vector_desc_head = NULL;
+
+//This bitmask has an 1 if the int should be disabled when the flash is disabled.
+static uint32_t non_iram_int_mask[portNUM_PROCESSORS];
+//This bitmask has 1 in it if the int was disabled using esp_intr_noniram_disable.
+static uint32_t non_iram_int_disabled[portNUM_PROCESSORS];
+static bool non_iram_int_disabled_flag[portNUM_PROCESSORS];
+
+#if CONFIG_SYSVIEW_ENABLE
+extern uint32_t port_switch_flag[];
+#endif
+
+static portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+//Inserts an item into vector_desc list so that the list is sorted
+//with an incrementing cpu.intno value.
+static void insert_vector_desc(vector_desc_t *to_insert)
+{
+    vector_desc_t *vd=vector_desc_head;
+    vector_desc_t *prev=NULL;
+    while(vd!=NULL) {
+        if (vd->cpu > to_insert->cpu) break;
+        if (vd->cpu == to_insert->cpu && vd->intno >= to_insert->intno) break;
+        prev=vd;
+        vd=vd->next;
+    }
+    if ((vector_desc_head==NULL) || (prev==NULL)) {
+        //First item
+        to_insert->next = vd;
+        vector_desc_head=to_insert;
+    } else {
+        prev->next=to_insert;
+        to_insert->next=vd;
+    }
+}
+
+//Returns a vector_desc entry for an intno/cpu, or NULL if none exists.
+static vector_desc_t *find_desc_for_int(int intno, int cpu)
+{
+    vector_desc_t *vd=vector_desc_head;
+    while(vd!=NULL) {
+        if (vd->cpu==cpu && vd->intno==intno) break;
+        vd=vd->next;
+    }
+    return vd;
+}
+
+//Returns a vector_desc entry for an intno/cpu.
+//Either returns a preexisting one or allocates a new one and inserts
+//it into the list. Returns NULL on malloc fail.
+static vector_desc_t *get_desc_for_int(int intno, int cpu)
+{
+    vector_desc_t *vd=find_desc_for_int(intno, cpu);
+    if (vd==NULL) {
+        vector_desc_t *newvd=heap_caps_malloc(sizeof(vector_desc_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
+        if (newvd==NULL) return NULL;
+        memset(newvd, 0, sizeof(vector_desc_t));
+        newvd->intno=intno;
+        newvd->cpu=cpu;
+        insert_vector_desc(newvd);
+        return newvd;
+    } else {
+        return vd;
+    }
+}
+
+//Returns a vector_desc entry for an source, the cpu parameter is used to tell GPIO_INT and GPIO_NMI from different CPUs
+static vector_desc_t * find_desc_for_source(int source, int cpu)
+{
+    vector_desc_t *vd=vector_desc_head;
+    while(vd!=NULL) {
+        if ( !(vd->flags & VECDESC_FL_SHARED) ) {
+            if ( vd->source == source && cpu == vd->cpu ) break;
+        } else if ( vd->cpu == cpu ) {
+            // check only shared vds for the correct cpu, otherwise skip
+            bool found = false;
+            shared_vector_desc_t *svd = vd->shared_vec_info;
+            assert(svd != NULL );
+            while(svd) {
+                if ( svd->source == source ) {
+                    found = true;
+                    break;
+                }
+                svd = svd->next;
+            }
+            if ( found ) break;
+        }
+        vd=vd->next;
+    }
+    return vd;
+}
+
+esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_int_ram)
+{
+    if (intno>31) return ESP_ERR_INVALID_ARG;
+    if (cpu>=portNUM_PROCESSORS) return ESP_ERR_INVALID_ARG;
+
+    portENTER_CRITICAL(&spinlock);
+    vector_desc_t *vd=get_desc_for_int(intno, cpu);
+    if (vd==NULL) {
+        portEXIT_CRITICAL(&spinlock);
+        return ESP_ERR_NO_MEM;
+    }
+    vd->flags=VECDESC_FL_SHARED;
+    if (is_int_ram) vd->flags|=VECDESC_FL_INIRAM;
+    portEXIT_CRITICAL(&spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t esp_intr_reserve(int intno, int cpu)
+{
+    if (intno>31) return ESP_ERR_INVALID_ARG;
+    if (cpu>=portNUM_PROCESSORS) return ESP_ERR_INVALID_ARG;
+
+    portENTER_CRITICAL(&spinlock);
+    vector_desc_t *vd=get_desc_for_int(intno, cpu);
+    if (vd==NULL) {
+        portEXIT_CRITICAL(&spinlock);
+        return ESP_ERR_NO_MEM;
+    }
+    vd->flags=VECDESC_FL_RESERVED;
+    portEXIT_CRITICAL(&spinlock);
+
+    return ESP_OK;
+}
+
+//Interrupt handler table and unhandled uinterrupt routine. Duplicated
+//from xtensa_intr.c... it's supposed to be private, but we need to look
+//into it in order to see if someone allocated an int using
+//xt_set_interrupt_handler.
+typedef struct xt_handler_table_entry {
+    void * handler;
+    void * arg;
+} xt_handler_table_entry;
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];
+extern void xt_unhandled_interrupt(void * arg);
+
+//Returns true if handler for interrupt is not the default unhandled interrupt handler
+static bool int_has_handler(int intr, int cpu)
+{
+    return (_xt_interrupt_table[intr*portNUM_PROCESSORS+cpu].handler != xt_unhandled_interrupt);
+}
+
+static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force)
+{
+    //Check if interrupt is not reserved by design
+    int x = vd->intno;
+    if (int_desc[x].cpuflags[cpu]==INTDESC_RESVD) {
+        ALCHLOG("....Unusable: reserved");
+        return false;
+    }
+    if (int_desc[x].cpuflags[cpu]==INTDESC_SPECIAL && force==-1) {
+        ALCHLOG("....Unusable: special-purpose int");
+        return false;
+    }
+    //Check if the interrupt level is acceptable
+    if (!(flags&(1<<int_desc[x].level))) {
+        ALCHLOG("....Unusable: incompatible level");
+        return false;
+    }
+    //check if edge/level type matches what we want
+    if (((flags&ESP_INTR_FLAG_EDGE) && (int_desc[x].type==INTTP_LEVEL)) ||
+            (((!(flags&ESP_INTR_FLAG_EDGE)) && (int_desc[x].type==INTTP_EDGE)))) {
+        ALCHLOG("....Unusable: incompatible trigger type");
+        return false;
+    }
+    //check if interrupt is reserved at runtime
+    if (vd->flags&VECDESC_FL_RESERVED)  {
+        ALCHLOG("....Unusable: reserved at runtime.");
+        return false;
+    }
+
+    //Ints can't be both shared and non-shared.
+    assert(!((vd->flags&VECDESC_FL_SHARED)&&(vd->flags&VECDESC_FL_NONSHARED)));
+    //check if interrupt already is in use by a non-shared interrupt
+    if (vd->flags&VECDESC_FL_NONSHARED) {
+        ALCHLOG("....Unusable: already in (non-shared) use.");
+        return false;
+    }
+    // check shared interrupt flags
+    if (vd->flags&VECDESC_FL_SHARED ) {
+        if (flags&ESP_INTR_FLAG_SHARED) {
+            bool in_iram_flag=((flags&ESP_INTR_FLAG_IRAM)!=0);
+            bool desc_in_iram_flag=((vd->flags&VECDESC_FL_INIRAM)!=0);
+            //Bail out if int is shared, but iram property doesn't match what we want.
+            if ((vd->flags&VECDESC_FL_SHARED) && (desc_in_iram_flag!=in_iram_flag))  {
+                ALCHLOG("....Unusable: shared but iram prop doesn't match");
+                return false;
+            }
+        } else {
+            //We need an unshared IRQ; can't use shared ones; bail out if this is shared.
+            ALCHLOG("...Unusable: int is shared, we need non-shared.");
+            return false;
+        }
+    } else if (int_has_handler(x, cpu)) {
+        //Check if interrupt already is allocated by xt_set_interrupt_handler
+        ALCHLOG("....Unusable: already allocated");
+        return false;
+    }
+
+    return true;
+}
+
+//Locate a free interrupt compatible with the flags given.
+//The 'force' argument can be -1, or 0-31 to force checking a certain interrupt.
+//When a CPU is forced, the INTDESC_SPECIAL marked interrupts are also accepted.
+static int get_available_int(int flags, int cpu, int force, int source)
+{
+    int x;
+    int best=-1;
+    int bestLevel=9;
+    int bestSharedCt=INT_MAX;
+    //Default vector desc, for vectors not in the linked list
+    vector_desc_t empty_vect_desc;
+    memset(&empty_vect_desc, 0, sizeof(vector_desc_t));
+
+
+    //Level defaults to any low/med interrupt
+    if (!(flags&ESP_INTR_FLAG_LEVELMASK)) flags|=ESP_INTR_FLAG_LOWMED;
+
+    ALCHLOG("get_available_int: try to find existing. Cpu: %d, Source: %d", cpu, source);
+    vector_desc_t *vd = find_desc_for_source(source, cpu);
+    if ( vd ) {
+        // if existing vd found, don't need to search any more.
+        ALCHLOG("get_avalible_int: existing vd found. intno: %d", vd->intno);
+        if ( force != -1 && force != vd->intno ) {
+            ALCHLOG("get_avalible_int: intr forced but not matach existing. existing intno: %d, force: %d", vd->intno, force);
+        } else if ( !is_vect_desc_usable(vd, flags, cpu, force) ) {
+            ALCHLOG("get_avalible_int: existing vd invalid.");
+        } else {
+            best = vd->intno;
+        }
+        return best;
+    }
+    if (force!=-1) {
+        ALCHLOG("get_available_int: try to find force. Cpu: %d, Source: %d, Force: %d", cpu, source, force);
+        //if force assigned, don't need to search any more.
+        vd = find_desc_for_int(force, cpu);
+        if (vd == NULL ) {
+            //if existing vd not found, just check the default state for the intr.
+            empty_vect_desc.intno = force;
+            vd = &empty_vect_desc;
+        }
+        if ( is_vect_desc_usable(vd, flags, cpu, force) ) {
+            best = vd->intno;
+        } else {
+            ALCHLOG("get_avalible_int: forced vd invalid.");
+        }
+        return best;
+    }
+
+    ALCHLOG("get_free_int: start looking. Current cpu: %d", cpu);
+    //No allocated handlers as well as forced intr, iterate over the 32 possible interrupts
+    for (x=0; x<32; x++) {
+        //Grab the vector_desc for this vector.
+        vd=find_desc_for_int(x, cpu);
+        if (vd==NULL) {
+            empty_vect_desc.intno = x;
+            vd=&empty_vect_desc;
+        }
+
+        ALCHLOG("Int %d reserved %d level %d %s hasIsr %d",
+            x, int_desc[x].cpuflags[cpu]==INTDESC_RESVD, int_desc[x].level,
+            int_desc[x].type==INTTP_LEVEL?"LEVEL":"EDGE", int_has_handler(x, cpu));
+
+        if ( !is_vect_desc_usable(vd, flags, cpu, force) ) continue;
+
+        if (flags&ESP_INTR_FLAG_SHARED) {
+            //We're allocating a shared int.
+
+            //See if int already is used as a shared interrupt.
+            if (vd->flags&VECDESC_FL_SHARED) {
+                //We can use this already-marked-as-shared interrupt. Count the already attached isrs in order to see
+                //how useful it is.
+                int no=0;
+                shared_vector_desc_t *svdesc=vd->shared_vec_info;
+                while (svdesc!=NULL) {
+                    no++;
+                    svdesc=svdesc->next;
+                }
+                if (no<bestSharedCt || bestLevel>int_desc[x].level) {
+                    //Seems like this shared vector is both okay and has the least amount of ISRs already attached to it.
+                    best=x;
+                    bestSharedCt=no;
+                    bestLevel=int_desc[x].level;
+                    ALCHLOG("...int %d more usable as a shared int: has %d existing vectors", x, no);
+                } else {
+                    ALCHLOG("...worse than int %d", best);
+                }
+            } else {
+                if (best==-1) {
+                    //We haven't found a feasible shared interrupt yet. This one is still free and usable, even if
+                    //not marked as shared.
+                    //Remember it in case we don't find any other shared interrupt that qualifies.
+                    if (bestLevel>int_desc[x].level) {
+                        best=x;
+                        bestLevel=int_desc[x].level;
+                        ALCHLOG("...int %d usable as a new shared int", x);
+                    }
+                } else {
+                    ALCHLOG("...already have a shared int");
+                }
+            }
+        } else {
+            //Seems this interrupt is feasible. Select it and break out of the loop; no need to search further.
+            if (bestLevel>int_desc[x].level) {
+                best=x;
+                bestLevel=int_desc[x].level;
+            } else {
+                ALCHLOG("...worse than int %d", best);
+            }
+        }
+    }
+    ALCHLOG("get_available_int: using int %d", best);
+
+    //Okay, by now we have looked at all potential interrupts and hopefully have selected the best one in best.
+    return best;
+}
+
+//Common shared isr handler. Chain-call all ISRs.
+static void IRAM_ATTR shared_intr_isr(void *arg)
+{
+    vector_desc_t *vd=(vector_desc_t*)arg;
+    shared_vector_desc_t *sh_vec=vd->shared_vec_info;
+    portENTER_CRITICAL(&spinlock);
+    while(sh_vec) {
+        if (!sh_vec->disabled) {
+            if ((sh_vec->statusreg == NULL) || (*sh_vec->statusreg & sh_vec->statusmask)) {
+#if CONFIG_SYSVIEW_ENABLE
+                traceISR_ENTER(sh_vec->source+ETS_INTERNAL_INTR_SOURCE_OFF);
+#endif
+                sh_vec->isr(sh_vec->arg);
+#if CONFIG_SYSVIEW_ENABLE
+                // check if we will return to scheduler or to interrupted task after ISR
+                if (!port_switch_flag[xPortGetCoreID()]) {
+                    traceISR_EXIT();
+                }
+#endif
+            }
+        }
+        sh_vec=sh_vec->next;
+    }
+    portEXIT_CRITICAL(&spinlock);
+}
+
+#if CONFIG_SYSVIEW_ENABLE
+//Common non-shared isr handler wrapper.
+static void IRAM_ATTR non_shared_intr_isr(void *arg)
+{
+    non_shared_isr_arg_t *ns_isr_arg=(non_shared_isr_arg_t*)arg;
+    portENTER_CRITICAL(&spinlock);
+    traceISR_ENTER(ns_isr_arg->source+ETS_INTERNAL_INTR_SOURCE_OFF);
+    // FIXME: can we call ISR and check port_switch_flag after releasing spinlock?
+    // when CONFIG_SYSVIEW_ENABLE = 0 ISRs for non-shared IRQs are called without spinlock
+    ns_isr_arg->isr(ns_isr_arg->isr_arg);
+    // check if we will return to scheduler or to interrupted task after ISR
+    if (!port_switch_flag[xPortGetCoreID()]) {
+        traceISR_EXIT();
+    }
+    portEXIT_CRITICAL(&spinlock);
+}
+#endif
+
+//We use ESP_EARLY_LOG* here because this can be called before the scheduler is running.
+esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusreg, uint32_t intrstatusmask, intr_handler_t handler,
+                                        void *arg, intr_handle_t *ret_handle)
+{
+    intr_handle_data_t *ret=NULL;
+    int force=-1;
+    ESP_EARLY_LOGV(TAG, "esp_intr_alloc_intrstatus (cpu %d): checking args", xPortGetCoreID());
+    //Shared interrupts should be level-triggered.
+    if ((flags&ESP_INTR_FLAG_SHARED) && (flags&ESP_INTR_FLAG_EDGE)) return ESP_ERR_INVALID_ARG;
+    //You can't set an handler / arg for a non-C-callable interrupt.
+    if ((flags&ESP_INTR_FLAG_HIGH) && (handler)) return ESP_ERR_INVALID_ARG;
+    //Shared ints should have handler and non-processor-local source
+    if ((flags&ESP_INTR_FLAG_SHARED) && (!handler || source<0)) return ESP_ERR_INVALID_ARG;
+    //Statusreg should have a mask
+    if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG;
+    //If the ISR is marked to be IRAM-resident, the handler must not be in the cached region
+    if ((flags&ESP_INTR_FLAG_IRAM) &&
+            (ptrdiff_t) handler >= SOC_RTC_IRAM_HIGH &&
+            (ptrdiff_t) handler < SOC_RTC_DATA_LOW ) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    //Default to prio 1 for shared interrupts. Default to prio 1, 2 or 3 for non-shared interrupts.
+    if ((flags&ESP_INTR_FLAG_LEVELMASK)==0) {
+        if (flags&ESP_INTR_FLAG_SHARED) {
+            flags|=ESP_INTR_FLAG_LEVEL1;
+        } else {
+            flags|=ESP_INTR_FLAG_LOWMED;
+        }
+    }
+    ESP_EARLY_LOGV(TAG, "esp_intr_alloc_intrstatus (cpu %d): Args okay. Resulting flags 0x%X", xPortGetCoreID(), flags);
+
+    //Check 'special' interrupt sources. These are tied to one specific interrupt, so we
+    //have to force get_free_int to only look at that.
+    if (source==ETS_INTERNAL_TIMER0_INTR_SOURCE) force=ETS_INTERNAL_TIMER0_INTR_NO;
+    if (source==ETS_INTERNAL_TIMER1_INTR_SOURCE) force=ETS_INTERNAL_TIMER1_INTR_NO;
+    if (source==ETS_INTERNAL_TIMER2_INTR_SOURCE) force=ETS_INTERNAL_TIMER2_INTR_NO;
+    if (source==ETS_INTERNAL_SW0_INTR_SOURCE) force=ETS_INTERNAL_SW0_INTR_NO;
+    if (source==ETS_INTERNAL_SW1_INTR_SOURCE) force=ETS_INTERNAL_SW1_INTR_NO;
+    if (source==ETS_INTERNAL_PROFILING_INTR_SOURCE) force=ETS_INTERNAL_PROFILING_INTR_NO;
+
+    //Allocate a return handle. If we end up not needing it, we'll free it later on.
+    ret=heap_caps_malloc(sizeof(intr_handle_data_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
+    if (ret==NULL) return ESP_ERR_NO_MEM;
+
+    portENTER_CRITICAL(&spinlock);
+    int cpu=xPortGetCoreID();
+    //See if we can find an interrupt that matches the flags.
+    int intr=get_available_int(flags, cpu, force, source);
+    if (intr==-1) {
+        //None found. Bail out.
+        portEXIT_CRITICAL(&spinlock);
+        free(ret);
+        return ESP_ERR_NOT_FOUND;
+    }
+    //Get an int vector desc for int.
+    vector_desc_t *vd=get_desc_for_int(intr, cpu);
+    if (vd==NULL) {
+        portEXIT_CRITICAL(&spinlock);
+        free(ret);
+        return ESP_ERR_NO_MEM;
+    }
+
+    //Allocate that int!
+    if (flags&ESP_INTR_FLAG_SHARED) {
+        //Populate vector entry and add to linked list.
+        shared_vector_desc_t *sh_vec=malloc(sizeof(shared_vector_desc_t));
+        if (sh_vec==NULL) {
+            portEXIT_CRITICAL(&spinlock);
+            free(ret);
+            return ESP_ERR_NO_MEM;
+        }
+        memset(sh_vec, 0, sizeof(shared_vector_desc_t));
+        sh_vec->statusreg=(uint32_t*)intrstatusreg;
+        sh_vec->statusmask=intrstatusmask;
+        sh_vec->isr=handler;
+        sh_vec->arg=arg;
+        sh_vec->next=vd->shared_vec_info;
+        sh_vec->source=source;
+        sh_vec->disabled=0;
+        vd->shared_vec_info=sh_vec;
+        vd->flags|=VECDESC_FL_SHARED;
+        //(Re-)set shared isr handler to new value.
+        xt_set_interrupt_handler(intr, shared_intr_isr, vd);
+    } else {
+        //Mark as unusable for other interrupt sources. This is ours now!
+        vd->flags=VECDESC_FL_NONSHARED;
+        if (handler) {
+#if CONFIG_SYSVIEW_ENABLE
+            non_shared_isr_arg_t *ns_isr_arg=malloc(sizeof(non_shared_isr_arg_t));
+            if (!ns_isr_arg) {
+                portEXIT_CRITICAL(&spinlock);
+                free(ret);
+                return ESP_ERR_NO_MEM;
+            }
+            ns_isr_arg->isr=handler;
+            ns_isr_arg->isr_arg=arg;
+            ns_isr_arg->source=source;
+            xt_set_interrupt_handler(intr, non_shared_intr_isr, ns_isr_arg);
+#else
+            xt_set_interrupt_handler(intr, handler, arg);
+#endif
+        }
+        if (flags&ESP_INTR_FLAG_EDGE) xthal_set_intclear(1 << intr);
+        vd->source=source;
+    }
+    if (flags&ESP_INTR_FLAG_IRAM) {
+        vd->flags|=VECDESC_FL_INIRAM;
+        non_iram_int_mask[cpu]&=~(1<<intr);
+    } else {
+        vd->flags&=~VECDESC_FL_INIRAM;
+        non_iram_int_mask[cpu]|=(1<<intr);
+    }
+    if (source>=0) {
+        intr_matrix_set(cpu, source, intr);
+    }
+
+    //Fill return handle data.
+    ret->vector_desc=vd;
+    ret->shared_vector_desc=vd->shared_vec_info;
+
+    //Enable int at CPU-level;
+    ESP_INTR_ENABLE(intr);
+
+    //If interrupt has to be started disabled, do that now; ints won't be enabled for real until the end
+    //of the critical section.
+    if (flags&ESP_INTR_FLAG_INTRDISABLED) {
+        esp_intr_disable(ret);
+    }
+
+    portEXIT_CRITICAL(&spinlock);
+
+    //Fill return handle if needed, otherwise free handle.
+    if (ret_handle!=NULL) {
+        *ret_handle=ret;
+    } else {
+        free(ret);
+    }
+
+    ESP_EARLY_LOGD(TAG, "Connected src %d to int %d (cpu %d)", source, intr, cpu);
+    return ESP_OK;
+}
+
+esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *arg, intr_handle_t *ret_handle)
+{
+    /*
+      As an optimization, we can create a table with the possible interrupt status registers and masks for every single
+      source there is. We can then add code here to look up an applicable value and pass that to the
+      esp_intr_alloc_intrstatus function.
+    */
+    return esp_intr_alloc_intrstatus(source, flags, 0, 0, handler, arg, ret_handle);
+}
+
+esp_err_t IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
+{
+    if (!handle) return ESP_ERR_INVALID_ARG;
+    vector_desc_t *vd = handle->vector_desc;
+    if (vd->flags & VECDESC_FL_SHARED) {
+      return ESP_ERR_INVALID_ARG;
+    }
+    portENTER_CRITICAL(&spinlock);
+    uint32_t mask = (1 << vd->intno);
+    if (is_in_iram) {
+        vd->flags |= VECDESC_FL_INIRAM;
+        non_iram_int_mask[vd->cpu] &= ~mask;
+    } else {
+        vd->flags &= ~VECDESC_FL_INIRAM;
+        non_iram_int_mask[vd->cpu] |= mask;
+    }
+    portEXIT_CRITICAL(&spinlock);
+    return ESP_OK;
+}
+
+esp_err_t esp_intr_free(intr_handle_t handle)
+{
+    bool free_shared_vector=false;
+    if (!handle) return ESP_ERR_INVALID_ARG;
+    //This routine should be called from the interrupt the task is scheduled on.
+    if (handle->vector_desc->cpu!=xPortGetCoreID()) return ESP_ERR_INVALID_ARG;
+
+    portENTER_CRITICAL(&spinlock);
+    esp_intr_disable(handle);
+    if (handle->vector_desc->flags&VECDESC_FL_SHARED) {
+        //Find and kill the shared int
+        shared_vector_desc_t *svd=handle->vector_desc->shared_vec_info;
+        shared_vector_desc_t *prevsvd=NULL;
+        assert(svd); //should be something in there for a shared int
+        while (svd!=NULL) {
+            if (svd==handle->shared_vector_desc) {
+                //Found it. Now kill it.
+                if (prevsvd) {
+                    prevsvd->next=svd->next;
+                } else {
+                    handle->vector_desc->shared_vec_info=svd->next;
+                }
+                free(svd);
+                break;
+            }
+            prevsvd=svd;
+            svd=svd->next;
+        }
+        //If nothing left, disable interrupt.
+        if (handle->vector_desc->shared_vec_info==NULL) free_shared_vector=true;
+        ESP_LOGV(TAG, "esp_intr_free: Deleting shared int: %s. Shared int is %s", svd?"not found or last one":"deleted", free_shared_vector?"empty now.":"still in use");
+    }
+
+    if ((handle->vector_desc->flags&VECDESC_FL_NONSHARED) || free_shared_vector) {
+        ESP_LOGV(TAG, "esp_intr_free: Disabling int, killing handler");
+#if CONFIG_SYSVIEW_ENABLE
+        if (!free_shared_vector) {
+            void *isr_arg = xt_get_interrupt_handler_arg(handle->vector_desc->intno);
+            if (isr_arg) {
+                free(isr_arg);
+            }
+        }
+#endif
+        //Reset to normal handler
+        xt_set_interrupt_handler(handle->vector_desc->intno, xt_unhandled_interrupt, (void*)((int)handle->vector_desc->intno));
+        //Theoretically, we could free the vector_desc... not sure if that's worth the few bytes of memory
+        //we save.(We can also not use the same exit path for empty shared ints anymore if we delete
+        //the desc.) For now, just mark it as free.
+        handle->vector_desc->flags&=!(VECDESC_FL_NONSHARED|VECDESC_FL_RESERVED);
+        //Also kill non_iram mask bit.
+        non_iram_int_mask[handle->vector_desc->cpu]&=~(1<<(handle->vector_desc->intno));
+    }
+    portEXIT_CRITICAL(&spinlock);
+    free(handle);
+    return ESP_OK;
+}
+
+int esp_intr_get_intno(intr_handle_t handle)
+{
+    return handle->vector_desc->intno;
+}
+
+int esp_intr_get_cpu(intr_handle_t handle)
+{
+    return handle->vector_desc->cpu;
+}
+
+/*
+ Interrupt disabling strategy:
+ If the source is >=0 (meaning a muxed interrupt), we disable it by muxing the interrupt to a non-connected
+ interrupt. If the source is <0 (meaning an internal, per-cpu interrupt), we disable it using ESP_INTR_DISABLE.
+ This allows us to, for the muxed CPUs, disable an int from the other core. It also allows disabling shared
+ interrupts.
+ */
+
+//Muxing an interrupt source to interrupt 6, 7, 11, 15, 16 or 29 cause the interrupt to effectively be disabled.
+#define INT_MUX_DISABLED_INTNO 6
+
+esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
+{
+    if (!handle) return ESP_ERR_INVALID_ARG;
+    portENTER_CRITICAL(&spinlock);
+    int source;
+    if (handle->shared_vector_desc) {
+        handle->shared_vector_desc->disabled=0;
+        source=handle->shared_vector_desc->source;
+    } else {
+        source=handle->vector_desc->source;
+    }
+    if (source >= 0) {
+        //Disabled using int matrix; re-connect to enable
+        intr_matrix_set(handle->vector_desc->cpu, source, handle->vector_desc->intno);
+    } else {
+        //Re-enable using cpu int ena reg
+        if (handle->vector_desc->cpu!=xPortGetCoreID()) return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
+        ESP_INTR_ENABLE(handle->vector_desc->intno);
+    }
+    portEXIT_CRITICAL(&spinlock);
+    return ESP_OK;
+}
+
+esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
+{
+    if (!handle) return ESP_ERR_INVALID_ARG;
+    portENTER_CRITICAL(&spinlock);
+    int source;
+    bool disabled = 1;
+    if (handle->shared_vector_desc) {
+        handle->shared_vector_desc->disabled=1;
+        source=handle->shared_vector_desc->source;
+
+        shared_vector_desc_t *svd=handle->vector_desc->shared_vec_info;
+        assert( svd != NULL );
+        while( svd ) {
+            if ( svd->source == source && svd->disabled == 0 ) {
+                disabled = 0;
+                break;
+            }
+            svd = svd->next;
+        }
+    } else {
+        source=handle->vector_desc->source;
+    }
+
+    if (source >= 0) {
+        if ( disabled ) {
+            //Disable using int matrix
+            intr_matrix_set(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
+        }
+    } else {
+        //Disable using per-cpu regs
+        if (handle->vector_desc->cpu!=xPortGetCoreID()) {
+            portEXIT_CRITICAL(&spinlock);
+            return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
+        }
+        ESP_INTR_DISABLE(handle->vector_desc->intno);
+    }
+    portEXIT_CRITICAL(&spinlock);
+    return ESP_OK;
+}
+
+
+void IRAM_ATTR esp_intr_noniram_disable()
+{
+    int oldint;
+    int cpu=xPortGetCoreID();
+    int intmask=~non_iram_int_mask[cpu];
+    if (non_iram_int_disabled_flag[cpu]) abort();
+    non_iram_int_disabled_flag[cpu]=true;
+    asm volatile (
+        "movi %0,0\n"
+        "xsr %0,INTENABLE\n"    //disable all ints first
+        "rsync\n"
+        "and a3,%0,%1\n"        //mask ints that need disabling
+        "wsr a3,INTENABLE\n"    //write back
+        "rsync\n"
+        :"=&r"(oldint):"r"(intmask):"a3");
+    //Save which ints we did disable
+    non_iram_int_disabled[cpu]=oldint&non_iram_int_mask[cpu];
+}
+
+void IRAM_ATTR esp_intr_noniram_enable()
+{
+    int cpu=xPortGetCoreID();
+    int intmask=non_iram_int_disabled[cpu];
+    if (!non_iram_int_disabled_flag[cpu]) abort();
+    non_iram_int_disabled_flag[cpu]=false;
+    asm volatile (
+        "movi a3,0\n"
+        "xsr a3,INTENABLE\n"
+        "rsync\n"
+        "or a3,a3,%0\n"
+        "wsr a3,INTENABLE\n"
+        "rsync\n"
+        ::"r"(intmask):"a3");
+}
+
+//These functions are provided in ROM, but the ROM-based functions use non-multicore-capable
+//virtualized interrupt levels. Thus, we disable them in the ld file and provide working
+//equivalents here.
+
+
+void IRAM_ATTR ets_isr_unmask(unsigned int mask) {
+    xt_ints_on(mask);
+}
+
+void IRAM_ATTR ets_isr_mask(unsigned int mask) {
+    xt_ints_off(mask);
+}
+
+
+
+

components/esp32s2beta/ld/esp32s2beta.common.ld

@@ -0,0 +1,253 @@
+/*  Default entry point:  */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+  /* RTC fast memory holds RTC wake stub code,
+     including from any source file named rtc_wake_stub*.c
+  */
+  .rtc.text :
+  {
+    . = ALIGN(4);
+    *(.rtc.literal .rtc.text)
+    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)
+  } > rtc_iram_seg
+
+  /* RTC slow memory holds RTC wake stub
+     data/rodata, including from any source file
+     named rtc_wake_stub*.c
+  */
+  .rtc.data :
+  {
+    _rtc_data_start = ABSOLUTE(.);
+    *(.rtc.data)
+    *(.rtc.rodata)
+    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
+    _rtc_data_end = ABSOLUTE(.);
+  } > rtc_slow_seg
+
+  /* RTC bss, from any source file named rtc_wake_stub*.c */
+  .rtc.bss (NOLOAD) :
+  {
+    _rtc_bss_start = ABSOLUTE(.);
+    *rtc_wake_stub*.o(.bss .bss.*)
+    *rtc_wake_stub*.o(COMMON)
+    _rtc_bss_end = ABSOLUTE(.);
+  } > rtc_slow_seg
+
+  /* This section holds data that should not be initialized at power up 
+     and will be retained during deep sleep. The section located in 
+     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed
+     into this section. See the file "esp_attr.h" for more information.
+  */
+  .rtc_noinit (NOLOAD):
+  {
+    . = ALIGN(4);
+    _rtc_noinit_start = ABSOLUTE(.);
+    *(.rtc_noinit .rtc_noinit.*)
+    . = ALIGN(4) ;
+    _rtc_noinit_end = ABSOLUTE(.);
+  } > rtc_slow_seg
+
+  /* Send .iram0 code to iram */
+  .iram0.vectors :
+  {
+    /* Vectors go to IRAM */
+    _init_start = ABSOLUTE(.);
+    /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+    . = 0x0;
+    KEEP(*(.WindowVectors.text));
+    . = 0x180;
+    KEEP(*(.Level2InterruptVector.text));
+    . = 0x1c0;
+    KEEP(*(.Level3InterruptVector.text));
+    . = 0x200;
+    KEEP(*(.Level4InterruptVector.text));
+    . = 0x240;
+    KEEP(*(.Level5InterruptVector.text));
+    . = 0x280;
+    KEEP(*(.DebugExceptionVector.text));
+    . = 0x2c0;
+    KEEP(*(.NMIExceptionVector.text));
+    . = 0x300;
+    KEEP(*(.KernelExceptionVector.text));
+    . = 0x340;
+    KEEP(*(.UserExceptionVector.text));
+    . = 0x3C0;
+    KEEP(*(.DoubleExceptionVector.text));
+    . = 0x400;
+    *(.*Vector.literal)
+
+    *(.UserEnter.literal);
+    *(.UserEnter.text);
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+    _init_end = ABSOLUTE(.);
+
+    /* This goes here, not at top of linker script, so addr2line finds it last,
+       and uses it in preference to the first symbol in IRAM */
+    _iram_start = ABSOLUTE(0);
+  } > iram0_0_seg
+
+  .iram0.text :
+  {
+    /* Code marked as runnning out of IRAM */
+    _iram_text_start = ABSOLUTE(.);
+    *(.iram1 .iram1.*)
+    *libfreertos.a:(.literal .text .literal.* .text.*)
+    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)
+    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)
+    *libesp32c.a:panic.o(.literal .text .literal.* .text.*)
+    *libesp32c.a:core_dump.o(.literal .text .literal.* .text.*)
+    *libapp_trace.a:(.literal .text .literal.* .text.*)
+    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)
+    *librtc.a:(.literal .text .literal.* .text.*)
+    *libsoc.a:(.literal .text .literal.* .text.*)
+    *libhal.a:(.literal .text .literal.* .text.*)
+    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)
+    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)
+    *libgcov.a:(.literal .text .literal.* .text.*)
+    INCLUDE esp32.spiram.rom-functions-iram.ld
+    _iram_text_end = ABSOLUTE(.);
+  } > iram0_0_seg
+  
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    *(.dram1 .dram1.*)
+    *libesp32c.a:panic.o(.rodata .rodata.*)
+    *libphy.a:(.rodata .rodata.*)
+    *libsoc.a:rtc_clk.o(.rodata .rodata.*)
+    *libapp_trace.a:(.rodata .rodata.*)
+    *libgcov.a:(.rodata .rodata.*)
+    *libheap.a:multi_heap.o(.rodata .rodata.*)
+    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)
+    INCLUDE esp32.spiram.rom-functions-dram.ld
+    _data_end = ABSOLUTE(.);
+    . = ALIGN(4);
+  } > dram0_0_seg
+
+  /*This section holds data that should not be initialized at power up.
+    The section located in Internal SRAM memory region. The macro _NOINIT
+    can be used as attribute to place data into this section.
+    See the esp_attr.h file for more information.
+  */
+  .noinit (NOLOAD):
+  {
+    . = ALIGN(4);
+    _noinit_start = ABSOLUTE(.);
+    *(.noinit .noinit.*) 
+    . = ALIGN(4) ;
+    _noinit_end = ABSOLUTE(.);
+  } > dram0_0_seg
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.share.mem)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    /* The heap starts right after end of this section */
+    _heap_start = ABSOLUTE(.);
+  } > dram0_0_seg
+
+  .flash.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table .gcc_except_table.*)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    . = (. + 3) & ~ 3;
+    __eh_frame = ABSOLUTE(.);
+    KEEP(*(.eh_frame))
+    . = (. + 7) & ~ 3;
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _thread_local_start = ABSOLUTE(.);
+    *(.tdata)
+    *(.tdata.*)
+    *(.tbss)
+    *(.tbss.*)
+    _thread_local_end = ABSOLUTE(.);
+    . = ALIGN(4);
+  } >drom0_0_seg
+
+  .flash.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+
+    /* Similar to _iram_start, this symbol goes here so it is
+       resolved by addr2line in preference to the first symbol in
+       the flash.text segment.
+    */
+    _flash_cache_start = ABSOLUTE(0);
+  } >iram0_2_seg
+}

components/esp32s2beta/ld/esp32s2beta.ld

@@ -0,0 +1,74 @@
+/* ESP32 Linker Script Memory Layout
+
+   This file describes the memory layout (memory blocks) as virtual
+   memory addresses.
+
+   esp32.common.ld contains output sections to link compiler output
+   into these memory blocks.
+
+   ***
+
+   This linker script is passed through the C preprocessor to include
+   configuration options.
+
+   Please use preprocessor features sparingly! Restrict
+   to simple macros with numeric values, and/or #if/#endif blocks.
+*/
+#include "sdkconfig.h"
+
+/* If BT is not built at all */
+#ifndef CONFIG_BT_RESERVE_DRAM
+#define CONFIG_BT_RESERVE_DRAM 0
+#endif
+
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+
+  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_0_seg (RX) :                 org = 0x40028000, len = 0x18000
+
+  /* Even though the segment name is iram, it is actually mapped to flash
+  */
+  iram0_2_seg (RX) :                 org = 0x40080018, len = 0xb80000-0x18
+
+  /*
+    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
+    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
+    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
+  */
+
+
+  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+
+     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
+     the amount of RAM available.
+
+     Note: Length of this section *should* be 0x50000, and this extra DRAM is available
+     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
+     additional static memory temporarily cannot be used.
+  */
+  dram0_0_seg (RW) :                 org = 0x3FFD0000 + CONFIG_BT_RESERVE_DRAM,
+                                     len = 0x28000 - CONFIG_BT_RESERVE_DRAM
+
+  /* Flash mapped constant data */
+  drom0_0_seg (R) :                  org = 0x3F000018, len = 0x3f0000-0x18
+
+  /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
+
+  /* RTC fast memory (executable). Persists over deep sleep.
+   */
+  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000
+
+  /* RTC slow memory (data accessible). Persists over deep sleep.
+
+     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
+  */
+  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
+                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
+}
+
+/* Heap ends at top of dram0_0_seg */
+_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;

components/esp32s2beta/ld/esp32s2beta.peripherals.ld

@@ -0,0 +1,29 @@
+PROVIDE ( UART0 = 0x3f400000 );
+PROVIDE ( SPIMEM1    = 0x3f402000 );
+PROVIDE ( SPIMEM0    = 0x3f403000 );
+PROVIDE ( GPIO = 0x3f404000 );
+PROVIDE ( SIGMADELTA = 0x3f404f00 );
+PROVIDE ( RTCCNTL = 0x3f408000 );
+PROVIDE ( RTCIO = 0x3f408400 );
+PROVIDE ( SENS = 0x3f408800 );
+PROVIDE ( HINF = 0x3f40B000 );
+PROVIDE ( I2S0 = 0x3f40F000 );
+PROVIDE ( UART1 = 0x3f410000 );
+PROVIDE ( I2C0 = 0x3f413000 );
+PROVIDE ( UHCI0 = 0x3f414000 );
+PROVIDE ( HOST = 0x3f415000 );
+PROVIDE ( RMT = 0x3f416000 );
+PROVIDE ( RMTMEM = 0x3f416800 );
+PROVIDE ( PCNT = 0x3f417000 );
+PROVIDE ( SLC = 0x3f418000 );
+PROVIDE ( LEDC = 0x3f419000 );
+PROVIDE ( TIMERG0 = 0x3f41F000 );
+PROVIDE ( TIMERG1    = 0x3f420000 );
+PROVIDE ( GPSPI2     = 0x3f424000 );
+PROVIDE ( GPSPI3     = 0x3f425000 );
+PROVIDE ( SYSCON = 0x3f426000 );
+PROVIDE ( I2C1 = 0x3f427000 );
+PROVIDE ( GPSPI4     = 0x3f437000 );
+
+PROVIDE ( ToBeCleanedUpBelow = 0x00000000 );
+PROVIDE ( UART2      = 0x3f410000 );

components/esp32s2beta/linker.lf

@@ -0,0 +1,14 @@
+[mapping:esp32s2beta]
+archive: libesp32s2beta.a
+entries:
+    panic (noflash)
+
+[mapping:gcc]
+archive: libgcc.a
+entries:
+    lib2funcs (noflash_text)
+
+[mapping:gcov]
+archive: libgcov.a
+entries:
+    * (noflash)

components/esp32s2beta/panic.c

@@ -0,0 +1,672 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stdlib.h>
+
+#include <xtensa/config/core.h>
+
+#include "esp32s2beta/rom/rtc.h"
+#include "esp32s2beta/rom/uart.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/xtensa_api.h"
+
+#include "soc/uart_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/timer_group_struct.h"
+#include "soc/timer_group_reg.h"
+#include "soc/cpu.h"
+#include "soc/rtc.h"
+#include "soc/rtc_wdt.h"
+
+#include "esp_private/gdbstub.h"
+#include "esp_debug_helpers.h"
+#include "esp_private/panic_reason.h"
+#include "esp_attr.h"
+#include "esp_err.h"
+#include "esp_core_dump.h"
+#include "esp_spi_flash.h"
+#include "esp32s2beta/cache_err_int.h"
+#include "esp_app_trace.h"
+#include "esp_private/system_internal.h"
+#include "sdkconfig.h"
+#if CONFIG_SYSVIEW_ENABLE
+#include "SEGGER_RTT.h"
+#endif
+
+#if CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TMO == -1
+#define APPTRACE_ONPANIC_HOST_FLUSH_TMO   ESP_APPTRACE_TMO_INFINITE
+#else
+#define APPTRACE_ONPANIC_HOST_FLUSH_TMO   (1000*CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TMO)
+#endif
+/*
+  Panic handlers; these get called when an unhandled exception occurs or the assembly-level
+  task switching / interrupt code runs into an unrecoverable error. The default task stack
+  overflow handler and abort handler are also in here.
+*/
+
+/*
+  Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled.
+*/
+
+#if !CONFIG_ESP32_PANIC_SILENT_REBOOT
+//printf may be broken, so we fix our own printing fns...
+static void panicPutChar(char c)
+{
+    while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
+    WRITE_PERI_REG(UART_FIFO_AHB_REG(CONFIG_CONSOLE_UART_NUM), c);
+}
+
+static void panicPutStr(const char *c)
+{
+    int x = 0;
+    while (c[x] != 0) {
+        panicPutChar(c[x]);
+        x++;
+    }
+}
+
+static void panicPutHex(int a)
+{
+    int x;
+    int c;
+    for (x = 0; x < 8; x++) {
+        c = (a >> 28) & 0xf;
+        if (c < 10) {
+            panicPutChar('0' + c);
+        } else {
+            panicPutChar('a' + c - 10);
+        }
+        a <<= 4;
+    }
+}
+
+static void panicPutDec(int a)
+{
+    int n1, n2;
+    n1 = a % 10;
+    n2 = a / 10;
+    if (n2 == 0) {
+        panicPutChar(' ');
+    } else {
+        panicPutChar(n2 + '0');
+    }
+    panicPutChar(n1 + '0');
+}
+#else
+//No printing wanted. Stub out these functions.
+static void panicPutChar(char c) { }
+static void panicPutStr(const char *c) { }
+static void panicPutHex(int a) { }
+static void panicPutDec(int a) { }
+#endif
+
+void  __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )
+{
+    panicPutStr("***ERROR*** A stack overflow in task ");
+    panicPutStr((char *)pcTaskName);
+    panicPutStr(" has been detected.\r\n");
+    abort();
+}
+
+static bool abort_called;
+
+static __attribute__((noreturn)) inline void invoke_abort()
+{
+    abort_called = true;
+#if CONFIG_ESP32_APPTRACE_ENABLE
+#if CONFIG_SYSVIEW_ENABLE
+    SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#else
+    esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
+                              APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#endif
+#endif
+    while (1) {
+        if (esp_cpu_in_ocd_debug_mode()) {
+            __asm__ ("break 0,0");
+        }
+        *((int *) 0) = 0;
+    }
+}
+
+void abort()
+{
+#if !CONFIG_ESP32_PANIC_SILENT_REBOOT
+    ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
+#endif
+    invoke_abort();
+}
+
+
+static const char *edesc[] = {
+    "IllegalInstruction", "Syscall", "InstructionFetchError", "LoadStoreError",
+    "Level1Interrupt", "Alloca", "IntegerDivideByZero", "PCValue",
+    "Privileged", "LoadStoreAlignment", "res", "res",
+    "InstrPDAddrError", "LoadStorePIFDataError", "InstrPIFAddrError", "LoadStorePIFAddrError",
+    "InstTLBMiss", "InstTLBMultiHit", "InstFetchPrivilege", "res",
+    "InstrFetchProhibited", "res", "res", "res",
+    "LoadStoreTLBMiss", "LoadStoreTLBMultihit", "LoadStorePrivilege", "res",
+    "LoadProhibited", "StoreProhibited", "res", "res",
+    "Cp0Dis", "Cp1Dis", "Cp2Dis", "Cp3Dis",
+    "Cp4Dis", "Cp5Dis", "Cp6Dis", "Cp7Dis"
+};
+
+#define NUM_EDESCS (sizeof(edesc) / sizeof(char *))
+
+static void commonErrorHandler(XtExcFrame *frame);
+static inline void disableAllWdts();
+
+//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
+//messing up the serial output, so we stall it here.
+static void haltOtherCore()
+{
+    esp_cpu_stall( xPortGetCoreID() == 0 ? 1 : 0 );
+}
+
+
+static void setFirstBreakpoint(uint32_t pc)
+{
+    asm(
+        "wsr.ibreaka0 %0\n" \
+        "rsr.ibreakenable a3\n" \
+        "movi a4,1\n" \
+        "or a4, a4, a3\n" \
+        "wsr.ibreakenable a4\n" \
+        ::"r"(pc):"a3", "a4");
+}
+
+//When interrupt watchdog happen in one core, both cores will be interrupted.
+//The core which doesn't trigger the interrupt watchdog will save the frame and return.
+//The core which triggers the interrupt watchdog will use the saved frame, and dump frames for both cores.
+#if !CONFIG_FREERTOS_UNICORE
+static volatile XtExcFrame * other_core_frame = NULL;
+#endif //!CONFIG_FREERTOS_UNICORE
+
+void panicHandler(XtExcFrame *frame)
+{
+    int core_id = xPortGetCoreID();
+    //Please keep in sync with PANIC_RSN_* defines
+    const char *reasons[] = {
+        "Unknown reason",
+        "Unhandled debug exception",
+        "Double exception",
+        "Unhandled kernel exception",
+        "Coprocessor exception",
+        "Interrupt wdt timeout on CPU0",
+        "Interrupt wdt timeout on CPU1",
+        "Cache disabled but cached memory region accessed",
+    };
+    const char *reason = reasons[0];
+    //The panic reason is stored in the EXCCAUSE register.
+    if (frame->exccause <= PANIC_RSN_MAX) {
+        reason = reasons[frame->exccause];
+    }
+
+#if !CONFIG_FREERTOS_UNICORE
+    //Save frame for other core.
+    if ((frame->exccause == PANIC_RSN_INTWDT_CPU0 && core_id == 1) || (frame->exccause == PANIC_RSN_INTWDT_CPU1 && core_id == 0)) {
+        other_core_frame = frame;
+        while (1);
+    }
+
+    //The core which triggers the interrupt watchdog will delay 1 us, so the other core can save its frame.
+    if (frame->exccause == PANIC_RSN_INTWDT_CPU0 || frame->exccause == PANIC_RSN_INTWDT_CPU1) {
+        ets_delay_us(1);
+    }
+
+    if (frame->exccause == PANIC_RSN_CACHEERR && esp_cache_err_get_cpuid() != core_id) {
+        // Cache error interrupt will be handled by the panic handler
+        // on the other CPU.
+        while (1);
+    }
+#endif //!CONFIG_FREERTOS_UNICORE
+
+    haltOtherCore();
+    esp_dport_access_int_abort();
+    panicPutStr("Guru Meditation Error: Core ");
+    panicPutDec(core_id);
+    panicPutStr(" panic'ed (");
+    panicPutStr(reason);
+    panicPutStr(")\r\n");
+#ifdef PANIC_COMPLETE_IN_ESP32C
+    if (frame->exccause == PANIC_RSN_DEBUGEXCEPTION) {
+        int debugRsn;
+        asm("rsr.debugcause %0":"=r"(debugRsn));
+        panicPutStr("Debug exception reason: ");
+        if (debugRsn & XCHAL_DEBUGCAUSE_ICOUNT_MASK) {
+            panicPutStr("SingleStep ");
+        }
+        if (debugRsn & XCHAL_DEBUGCAUSE_IBREAK_MASK) {
+            panicPutStr("HwBreakpoint ");
+        }
+        if (debugRsn & XCHAL_DEBUGCAUSE_DBREAK_MASK) {
+            //Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
+            //reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
+            //debugcause if the cause is watchdog 1 and clearing it if it's watchdog 0.
+            if (debugRsn & (1 << 8)) {
+#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
+                const char *name = pcTaskGetTaskName(xTaskGetCurrentTaskHandleForCPU(core_id));
+                panicPutStr("Stack canary watchpoint triggered (");
+                panicPutStr(name);
+                panicPutStr(") ");
+#else
+                panicPutStr("Watchpoint 1 triggered ");
+#endif
+            } else {
+                panicPutStr("Watchpoint 0 triggered ");
+            }
+        }
+        if (debugRsn & XCHAL_DEBUGCAUSE_BREAK_MASK) {
+            panicPutStr("BREAK instr ");
+        }
+        if (debugRsn & XCHAL_DEBUGCAUSE_BREAKN_MASK) {
+            panicPutStr("BREAKN instr ");
+        }
+        if (debugRsn & XCHAL_DEBUGCAUSE_DEBUGINT_MASK) {
+            panicPutStr("DebugIntr ");
+        }
+        panicPutStr("\r\n");
+    }
+
+    if (esp_cpu_in_ocd_debug_mode()) {
+        disableAllWdts();
+        if (frame->exccause == PANIC_RSN_INTWDT_CPU0 ||
+            frame->exccause == PANIC_RSN_INTWDT_CPU1) {
+            TIMERG1.int_clr.wdt = 1;
+        }
+#if CONFIG_ESP32_APPTRACE_ENABLE
+#if CONFIG_SYSVIEW_ENABLE
+        SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#else
+        esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
+                                  APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#endif
+#endif
+        setFirstBreakpoint(frame->pc);
+        return;
+    }
+#endif
+    commonErrorHandler(frame);
+}
+
+void xt_unhandled_exception(XtExcFrame *frame)
+{
+    haltOtherCore();
+    esp_dport_access_int_abort();
+    if (!abort_called) {
+        panicPutStr("Guru Meditation Error: Core ");
+        panicPutDec(xPortGetCoreID());
+        panicPutStr(" panic'ed (");
+        int exccause = frame->exccause;
+        if (exccause < NUM_EDESCS) {
+            panicPutStr(edesc[exccause]);
+        } else {
+            panicPutStr("Unknown");
+        }
+        panicPutStr(")");
+#ifdef PANIC_COMPLETE_IN_ESP32C
+        if (esp_cpu_in_ocd_debug_mode()) {
+            panicPutStr(" at pc=");
+            panicPutHex(frame->pc);
+            panicPutStr(". Setting bp and returning..\r\n");
+#if CONFIG_ESP32_APPTRACE_ENABLE
+#if CONFIG_SYSVIEW_ENABLE
+            SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#else
+            esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
+                                      APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#endif
+#endif
+            //Stick a hardware breakpoint on the address the handler returns to. This way, the OCD debugger
+            //will kick in exactly at the context the error happened.
+            setFirstBreakpoint(frame->pc);
+            return;
+        }
+#endif
+        panicPutStr(". Exception was unhandled.\r\n");
+    }
+    commonErrorHandler(frame);
+}
+
+
+/*
+  If watchdogs are enabled, the panic handler runs the risk of getting aborted pre-emptively because
+  an overzealous watchdog decides to reset it. On the other hand, if we disable all watchdogs, we run
+  the risk of somehow halting in the panic handler and not resetting. That is why this routine kills
+  all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
+  one second.
+*/
+static void reconfigureAllWdts()
+{
+    TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
+    TIMERG0.wdt_feed = 1;
+    TIMERG0.wdt_config0.sys_reset_length = 7;           //3.2uS
+    TIMERG0.wdt_config0.cpu_reset_length = 7;           //3.2uS
+    TIMERG0.wdt_config0.stg0 = TIMG_WDT_STG_SEL_RESET_SYSTEM; //1st stage timeout: reset system
+    TIMERG0.wdt_config1.clk_prescale = 80 * 500;        //Prescaler: wdt counts in ticks of 0.5mS
+    TIMERG0.wdt_config2 = 2000;                         //1 second before reset
+    TIMERG0.wdt_config0.en = 1;
+    TIMERG0.wdt_wprotect = 0;
+    //Disable wdt 1
+    TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
+    TIMERG1.wdt_config0.en = 0;
+    TIMERG1.wdt_wprotect = 0;
+}
+
+/*
+  This disables all the watchdogs for when we call the gdbstub.
+*/
+static inline void disableAllWdts()
+{
+    TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
+    TIMERG0.wdt_config0.en = 0;
+    TIMERG0.wdt_wprotect = 0;
+    TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
+    TIMERG1.wdt_config0.en = 0;
+    TIMERG1.wdt_wprotect = 0;
+}
+
+static void esp_panic_wdt_start()
+{
+    if (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN)) {
+        return;
+    }
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
+    WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_SYS_RESET_LENGTH, 7);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_CPU_RESET_LENGTH, 7);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, RTC_WDT_STG_SEL_RESET_SYSTEM);
+    // 64KB of core dump data (stacks of about 30 tasks) will produce ~85KB base64 data.
+    // @ 115200 UART speed it will take more than 6 sec to print them out.
+    WRITE_PERI_REG(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * 7);
+    REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN);
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
+}
+
+void esp_panic_wdt_stop()
+{
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
+    WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, RTC_WDT_STG_SEL_OFF);
+    REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN);
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
+}
+
+static void esp_panic_dig_reset() __attribute__((noreturn));
+
+static void esp_panic_dig_reset()
+{
+    // make sure all the panic handler output is sent from UART FIFO
+    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    // switch to XTAL (otherwise we will keep running from the PLL)
+    rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
+    // reset the digital part
+    esp_cpu_unstall(PRO_CPU_NUM);
+    SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
+    while (true) {
+        ;
+    }
+}
+
+static void putEntry(uint32_t pc, uint32_t sp)
+{
+    if (pc & 0x80000000) {
+        pc = (pc & 0x3fffffff) | 0x40000000;
+    }
+    panicPutStr(" 0x");
+    panicPutHex(pc);
+    panicPutStr(":0x");
+    panicPutHex(sp);
+}
+
+static void doBacktrace(XtExcFrame *frame)
+{
+    uint32_t i = 0, pc = frame->pc, sp = frame->a1;
+    panicPutStr("\r\nBacktrace:");
+    /* Do not check sanity on first entry, PC could be smashed. */
+    putEntry(pc, sp);
+    pc = frame->a0;
+    while (i++ < 100) {
+        uint32_t psp = sp;
+        if (!esp_stack_ptr_is_sane(sp) || i++ > 100) {
+            break;
+        }
+        sp = *((uint32_t *) (sp - 0x10 + 4));
+        putEntry(pc - 3, sp); // stack frame addresses are return addresses, so subtract 3 to get the CALL address
+        pc = *((uint32_t *) (psp - 0x10));
+        if (pc < 0x40000000) {
+            break;
+        }
+    }
+    panicPutStr("\r\n\r\n");
+}
+
+/*
+ * Dump registers and do backtrace.
+ */
+static void commonErrorHandler_dump(XtExcFrame *frame, int core_id)
+{
+    int *regs = (int *)frame;
+    int x, y;
+    const char *sdesc[] = {
+        "PC      ", "PS      ", "A0      ", "A1      ", "A2      ", "A3      ", "A4      ", "A5      ",
+        "A6      ", "A7      ", "A8      ", "A9      ", "A10     ", "A11     ", "A12     ", "A13     ",
+        "A14     ", "A15     ", "SAR     ", "EXCCAUSE", "EXCVADDR", "LBEG    ", "LEND    ", "LCOUNT  "
+    };
+
+    /* only dump registers for 'real' crashes, if crashing via abort()
+       the register window is no longer useful.
+    */
+    if (!abort_called) {
+        panicPutStr("Core");
+        panicPutDec(core_id);
+        panicPutStr(" register dump:\r\n");
+
+        for (x = 0; x < 24; x += 4) {
+            for (y = 0; y < 4; y++) {
+                if (sdesc[x + y][0] != 0) {
+                    panicPutStr(sdesc[x + y]);
+                    panicPutStr(": 0x");
+                    panicPutHex(regs[x + y + 1]);
+                    panicPutStr("  ");
+                }
+            }
+            panicPutStr("\r\n");
+        }
+
+        if (xPortInterruptedFromISRContext()
+#if !CONFIG_FREERTOS_UNICORE
+            && other_core_frame != frame
+#endif //!CONFIG_FREERTOS_UNICORE
+            ) {
+            //If the core which triggers the interrupt watchdog was in ISR context, dump the epc registers.
+            uint32_t __value;
+            panicPutStr("Core");
+            panicPutDec(core_id);
+            panicPutStr(" was running in ISR context:\r\n");
+
+            __asm__("rsr.epc1 %0" : "=a"(__value));
+            panicPutStr("EPC1    : 0x");
+            panicPutHex(__value);
+
+            __asm__("rsr.epc2 %0" : "=a"(__value));
+            panicPutStr("  EPC2    : 0x");
+            panicPutHex(__value);
+
+            __asm__("rsr.epc3 %0" : "=a"(__value));
+            panicPutStr("  EPC3    : 0x");
+            panicPutHex(__value);
+
+            __asm__("rsr.epc4 %0" : "=a"(__value));
+            panicPutStr("  EPC4    : 0x");
+            panicPutHex(__value);
+
+            panicPutStr("\r\n");
+        }
+
+    }
+
+    /* With windowed ABI backtracing is easy, let's do it. */
+    doBacktrace(frame);
+
+}
+
+/*
+  We arrive here after a panic or unhandled exception, when no OCD is detected. Dump the registers to the
+  serial port and either jump to the gdb stub, halt the CPU or reboot.
+*/
+static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
+{
+
+    int core_id = xPortGetCoreID();
+    // start panic WDT to restart system if we hang in this handler
+    esp_panic_wdt_start();
+
+    //Feed the watchdogs, so they will give us time to print out debug info
+    reconfigureAllWdts();
+
+    commonErrorHandler_dump(frame, core_id);
+#if !CONFIG_FREERTOS_UNICORE
+    if (other_core_frame != NULL) {
+        commonErrorHandler_dump((XtExcFrame *)other_core_frame, (core_id ? 0 : 1));
+    }
+#endif //!CONFIG_FREERTOS_UNICORE
+
+#if CONFIG_ESP32_APPTRACE_ENABLE
+    disableAllWdts();
+#if CONFIG_SYSVIEW_ENABLE
+    SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#else
+    esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH,
+                              APPTRACE_ONPANIC_HOST_FLUSH_TMO);
+#endif
+    reconfigureAllWdts();
+#endif
+
+#if CONFIG_ESP32_PANIC_GDBSTUB
+    disableAllWdts();
+    esp_panic_wdt_stop();
+    panicPutStr("Entering gdb stub now.\r\n");
+    esp_gdbstub_panic_handler(frame);
+#else
+#if CONFIG_ESP32_ENABLE_COREDUMP
+    static bool s_dumping_core;
+    if (s_dumping_core) {
+        panicPutStr("Re-entered core dump! Exception happened during core dump!\r\n");
+    } else {
+        disableAllWdts();
+        s_dumping_core = true;
+#if CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH
+        esp_core_dump_to_flash(frame);
+#endif
+#if CONFIG_ESP32_ENABLE_COREDUMP_TO_UART && !CONFIG_ESP32_PANIC_SILENT_REBOOT
+        esp_core_dump_to_uart(frame);
+#endif
+        s_dumping_core = false;
+        reconfigureAllWdts();
+    }
+#endif /* CONFIG_ESP32_ENABLE_COREDUMP */
+    esp_panic_wdt_stop();
+#if CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT
+    panicPutStr("Rebooting...\r\n");
+    if (frame->exccause != PANIC_RSN_CACHEERR) {
+        esp_restart_noos();
+    } else {
+        // The only way to clear invalid cache access interrupt is to reset the digital part
+        esp_panic_dig_reset();
+    }
+#else
+    disableAllWdts();
+    panicPutStr("CPU halted.\r\n");
+    while (1);
+#endif /* CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT */
+#endif /* CONFIG_ESP32_PANIC_GDBSTUB */
+}
+
+
+void esp_set_breakpoint_if_jtag(void *fn)
+{
+    if (esp_cpu_in_ocd_debug_mode()) {
+        setFirstBreakpoint((uint32_t)fn);
+    }
+}
+
+
+esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags)
+{
+    int x;
+    if (no < 0 || no > 1) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (flags & (~0xC0000000)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    int dbreakc = 0x3F;
+    //We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
+    for (x = 0; x < 7; x++) {
+        if (size == (1 << x)) {
+            break;
+        }
+        dbreakc <<= 1;
+    }
+    if (x == 7) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    //Mask mask and add in flags.
+    dbreakc = (dbreakc & 0x3f) | flags;
+
+    if (no == 0) {
+        asm volatile(
+            "wsr.dbreaka0 %0\n" \
+            "wsr.dbreakc0 %1\n" \
+            ::"r"(adr), "r"(dbreakc));
+    } else {
+        asm volatile(
+            "wsr.dbreaka1 %0\n" \
+            "wsr.dbreakc1 %1\n" \
+            ::"r"(adr), "r"(dbreakc));
+    }
+    return ESP_OK;
+}
+
+void esp_clear_watchpoint(int no)
+{
+    //Setting a dbreakc register to 0 makes it trigger on neither load nor store, effectively disabling it.
+    int dbreakc = 0;
+    if (no == 0) {
+        asm volatile(
+            "wsr.dbreakc0 %0\n" \
+            ::"r"(dbreakc));
+    } else {
+        asm volatile(
+            "wsr.dbreakc1 %0\n" \
+            ::"r"(dbreakc));
+    }
+}
+
+void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression)
+{
+    ets_printf("ESP_ERROR_CHECK failed: esp_err_t 0x%x", rc);
+#ifdef CONFIG_ESP_ERR_TO_NAME_LOOKUP
+    ets_printf(" (%s)", esp_err_to_name(rc));
+#endif //CONFIG_ESP_ERR_TO_NAME_LOOKUP
+    ets_printf(" at 0x%08x\n", (intptr_t)__builtin_return_address(0) - 3);
+    if (spi_flash_cache_enabled()) { // strings may be in flash cache
+        ets_printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression);
+    }
+    invoke_abort();
+}

components/esp32s2beta/pm_esp32s2beta.c

@@ -0,0 +1,573 @@
+// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include <sys/param.h>
+
+#include "esp_attr.h"
+#include "esp_err.h"
+#include "esp_pm.h"
+#include "esp_log.h"
+#include "esp32s2beta/clk.h"
+#include "esp_private/crosscore_int.h"
+
+#include "soc/rtc.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/xtensa_timer.h"
+#include "xtensa/core-macros.h"
+
+#include "esp_private/pm_impl.h"
+#include "esp_private/pm_trace.h"
+#include "esp_private/esp_timer_impl.h"
+#include "esp32/pm.h"
+
+/* CCOMPARE update timeout, in CPU cycles. Any value above ~600 cycles will work
+ * for the purpose of detecting a deadlock.
+ */
+#define CCOMPARE_UPDATE_TIMEOUT 1000000
+
+/* When changing CCOMPARE, don't allow changes if the difference is less
+ * than this. This is to prevent setting CCOMPARE below CCOUNT.
+ */
+#define CCOMPARE_MIN_CYCLES_IN_FUTURE 1000
+
+/* When light sleep is used, wake this number of microseconds earlier than
+ * the next tick.
+ */
+#define LIGHT_SLEEP_EARLY_WAKEUP_US 100
+
+#ifdef CONFIG_PM_PROFILING
+#define WITH_PROFILING
+#endif
+
+
+static portMUX_TYPE s_switch_lock = portMUX_INITIALIZER_UNLOCKED;
+/* The following state variables are protected using s_switch_lock: */
+/* Current sleep mode; When switching, contains old mode until switch is complete */
+static pm_mode_t s_mode = PM_MODE_CPU_MAX;
+/* True when switch is in progress */
+static volatile bool s_is_switching;
+/* When switch is in progress, this is the mode we are switching into */
+static pm_mode_t s_new_mode = PM_MODE_CPU_MAX;
+/* Number of times each mode was locked */
+static size_t s_mode_lock_counts[PM_MODE_COUNT];
+/* Bit mask of locked modes. BIT(i) is set iff s_mode_lock_counts[i] > 0. */
+static uint32_t s_mode_mask;
+
+/* Divider and multiplier used to adjust (ccompare - ccount) duration.
+ * Only set to non-zero values when switch is in progress.
+ */
+static uint32_t s_ccount_div;
+static uint32_t s_ccount_mul;
+
+/* Indicates to the ISR hook that CCOMPARE needs to be updated on the given CPU.
+ * Used in conjunction with cross-core interrupt to update CCOMPARE on the other CPU.
+ */
+static volatile bool s_need_update_ccompare[portNUM_PROCESSORS];
+
+/* When no RTOS tasks are active, these locks are released to allow going into
+ * a lower power mode. Used by ISR hook and idle hook.
+ */
+static esp_pm_lock_handle_t s_rtos_lock_handle[portNUM_PROCESSORS];
+
+/* A flag indicating that Idle hook has run on a given CPU;
+ * Next interrupt on the same CPU will take s_rtos_lock_handle.
+ */
+static bool s_core_idle[portNUM_PROCESSORS];
+
+/* g_ticks_us defined in ROM for PRO CPU */
+extern uint32_t g_ticks_per_us_pro;
+
+/* Lookup table of CPU frequencies to be used in each mode.
+ * Initialized by esp_pm_impl_init and modified by esp_pm_configure.
+ */
+rtc_cpu_freq_t s_cpu_freq_by_mode[PM_MODE_COUNT];
+
+/* Lookup table of CPU ticks per microsecond for each RTC_CPU_FREQ_ value.
+ * Essentially the same as returned by rtc_clk_cpu_freq_value(), but without
+ * the function call. Not const because XTAL frequency is only known at run time.
+ */
+static uint32_t s_cpu_freq_to_ticks[] = {
+       [RTC_CPU_FREQ_XTAL] = 0, /* This is set by esp_pm_impl_init */
+       [RTC_CPU_FREQ_80M]  = 80,
+       [RTC_CPU_FREQ_160M] = 160,
+       [RTC_CPU_FREQ_240M] = 240,
+       [RTC_CPU_FREQ_2M]   = 2
+};
+
+/* Lookup table of names for each RTC_CPU_FREQ_ value. Used for logging only. */
+static const char* s_freq_names[] __attribute__((unused)) = {
+        [RTC_CPU_FREQ_XTAL] = "XTAL",
+        [RTC_CPU_FREQ_80M] = "80",
+        [RTC_CPU_FREQ_160M] = "160",
+        [RTC_CPU_FREQ_240M] = "240",
+        [RTC_CPU_FREQ_2M] = "2"
+};
+
+/* Whether automatic light sleep is enabled */
+static bool s_light_sleep_en = false;
+
+/* When configuration is changed, current frequency may not match the
+ * newly configured frequency for the current mode. This is an indicator
+ * to the mode switch code to get the actual current frequency instead of
+ * relying on the current mode.
+ */
+static bool s_config_changed = false;
+
+#ifdef WITH_PROFILING
+/* Time, in microseconds, spent so far in each mode */
+static pm_time_t s_time_in_mode[PM_MODE_COUNT];
+/* Timestamp, in microseconds, when the mode switch last happened */
+static pm_time_t s_last_mode_change_time;
+/* User-readable mode names, used by esp_pm_impl_dump_stats */
+static const char* s_mode_names[] = {
+        "SLEEP",
+        "APB_MIN",
+        "APB_MAX",
+        "CPU_MAX"
+};
+#endif // WITH_PROFILING
+
+
+static const char* TAG = "pm_esp32";
+
+static void update_ccompare();
+static void do_switch(pm_mode_t new_mode);
+static void leave_idle();
+static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
+
+
+pm_mode_t esp_pm_impl_get_mode(esp_pm_lock_type_t type, int arg)
+{
+    (void) arg;
+    if (type == ESP_PM_CPU_FREQ_MAX) {
+        return PM_MODE_CPU_MAX;
+    } else if (type == ESP_PM_APB_FREQ_MAX) {
+        return PM_MODE_APB_MAX;
+    } else if (type == ESP_PM_NO_LIGHT_SLEEP) {
+        return PM_MODE_APB_MIN;
+    } else {
+        // unsupported mode
+        abort();
+    }
+}
+
+/* rtc_cpu_freq_t enum is not ordered by frequency, so convert to MHz,
+ * figure out the maximum value, then convert back to rtc_cpu_freq_t.
+ */
+static rtc_cpu_freq_t max_freq_of(rtc_cpu_freq_t f1, rtc_cpu_freq_t f2)
+{
+    int f1_hz = rtc_clk_cpu_freq_value(f1);
+    int f2_hz = rtc_clk_cpu_freq_value(f2);
+    int f_max_hz = MAX(f1_hz, f2_hz);
+    rtc_cpu_freq_t result = RTC_CPU_FREQ_XTAL;
+    if (!rtc_clk_cpu_freq_from_mhz(f_max_hz/1000000, &result)) {
+        assert(false && "unsupported frequency");
+    }
+    return result;
+}
+
+esp_err_t esp_pm_configure(const void* vconfig)
+{
+#ifndef CONFIG_PM_ENABLE
+    return ESP_ERR_NOT_SUPPORTED;
+#endif
+
+    const esp_pm_config_esp32_t* config = (const esp_pm_config_esp32_t*) vconfig;
+#ifndef CONFIG_FREERTOS_USE_TICKLESS_IDLE
+    if (config->light_sleep_enable) {
+        return ESP_ERR_NOT_SUPPORTED;
+    }
+#endif
+
+    if (config->min_cpu_freq == RTC_CPU_FREQ_2M) {
+        /* Minimal APB frequency to achieve 1MHz REF_TICK frequency is 5 MHz */
+        return ESP_ERR_NOT_SUPPORTED;
+    }
+
+    rtc_cpu_freq_t min_freq = config->min_cpu_freq;
+    rtc_cpu_freq_t max_freq = config->max_cpu_freq;
+    int min_freq_mhz = rtc_clk_cpu_freq_value(min_freq);
+    int max_freq_mhz = rtc_clk_cpu_freq_value(max_freq);
+    if (min_freq_mhz > max_freq_mhz) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    rtc_cpu_freq_t apb_max_freq = max_freq; /* CPU frequency in APB_MAX mode */
+    if (max_freq == RTC_CPU_FREQ_240M) {
+        /* We can't switch between 240 and 80/160 without disabling PLL,
+         * so use 240MHz CPU frequency when 80MHz APB frequency is requested.
+         */
+        apb_max_freq = RTC_CPU_FREQ_240M;
+    } else if (max_freq == RTC_CPU_FREQ_160M || max_freq == RTC_CPU_FREQ_80M) {
+        /* Otherwise, can use 80MHz
+         * CPU frequency when 80MHz APB frequency is requested.
+         */
+        apb_max_freq = RTC_CPU_FREQ_80M;
+    }
+
+    apb_max_freq = max_freq_of(apb_max_freq, min_freq);
+
+    ESP_LOGI(TAG, "Frequency switching config: "
+                  "CPU_MAX: %s, APB_MAX: %s, APB_MIN: %s, Light sleep: %s",
+                  s_freq_names[max_freq],
+                  s_freq_names[apb_max_freq],
+                  s_freq_names[min_freq],
+                  config->light_sleep_enable ? "ENABLED" : "DISABLED");
+
+    portENTER_CRITICAL(&s_switch_lock);
+    s_cpu_freq_by_mode[PM_MODE_CPU_MAX] = max_freq;
+    s_cpu_freq_by_mode[PM_MODE_APB_MAX] = apb_max_freq;
+    s_cpu_freq_by_mode[PM_MODE_APB_MIN] = min_freq;
+    s_cpu_freq_by_mode[PM_MODE_LIGHT_SLEEP] = min_freq;
+    s_light_sleep_en = config->light_sleep_enable;
+    s_config_changed = true;
+    portEXIT_CRITICAL(&s_switch_lock);
+
+    return ESP_OK;
+}
+
+static pm_mode_t IRAM_ATTR get_lowest_allowed_mode()
+{
+    /* TODO: optimize using ffs/clz */
+    if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
+        return PM_MODE_CPU_MAX;
+    } else if (s_mode_mask >= BIT(PM_MODE_APB_MAX)) {
+        return PM_MODE_APB_MAX;
+    } else if (s_mode_mask >= BIT(PM_MODE_APB_MIN) || !s_light_sleep_en) {
+        return PM_MODE_APB_MIN;
+    } else {
+        return PM_MODE_LIGHT_SLEEP;
+    }
+}
+
+void IRAM_ATTR esp_pm_impl_switch_mode(pm_mode_t mode,
+        pm_mode_switch_t lock_or_unlock, pm_time_t now)
+{
+    bool need_switch = false;
+    uint32_t mode_mask = BIT(mode);
+    portENTER_CRITICAL(&s_switch_lock);
+    uint32_t count;
+    if (lock_or_unlock == MODE_LOCK) {
+        count = ++s_mode_lock_counts[mode];
+    } else {
+        count = s_mode_lock_counts[mode]--;
+    }
+    if (count == 1) {
+        if (lock_or_unlock == MODE_LOCK) {
+            s_mode_mask |= mode_mask;
+        } else {
+            s_mode_mask &= ~mode_mask;
+        }
+        need_switch = true;
+    }
+
+    pm_mode_t new_mode = s_mode;
+    if (need_switch) {
+        new_mode = get_lowest_allowed_mode();
+#ifdef WITH_PROFILING
+        if (s_last_mode_change_time != 0) {
+            pm_time_t diff = now - s_last_mode_change_time;
+            s_time_in_mode[s_mode] += diff;
+        }
+        s_last_mode_change_time = now;
+#endif // WITH_PROFILING
+    }
+    portEXIT_CRITICAL(&s_switch_lock);
+    if (need_switch && new_mode != s_mode) {
+        do_switch(new_mode);
+    }
+}
+
+/**
+ * @brief Update clock dividers in esp_timer and FreeRTOS, and adjust CCOMPARE
+ * values on both CPUs.
+ * @param old_ticks_per_us old CPU frequency
+ * @param ticks_per_us new CPU frequency
+ */
+static void IRAM_ATTR on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us)
+{
+    uint32_t old_apb_ticks_per_us = MIN(old_ticks_per_us, 80);
+    uint32_t apb_ticks_per_us = MIN(ticks_per_us, 80);
+    /* Update APB frequency value used by the timer */
+    if (old_apb_ticks_per_us != apb_ticks_per_us) {
+        esp_timer_impl_update_apb_freq(apb_ticks_per_us);
+    }
+
+    /* Calculate new tick divisor */
+    _xt_tick_divisor = ticks_per_us * 1000000 / XT_TICK_PER_SEC;
+
+    int core_id = xPortGetCoreID();
+    if (s_rtos_lock_handle[core_id] != NULL) {
+        ESP_PM_TRACE_ENTER(CCOMPARE_UPDATE, core_id);
+        /* ccount_div and ccount_mul are used in esp_pm_impl_update_ccompare
+         * to calculate new CCOMPARE value.
+         */
+        s_ccount_div = old_ticks_per_us;
+        s_ccount_mul = ticks_per_us;
+
+        /* Update CCOMPARE value on this CPU */
+        update_ccompare();
+
+#if portNUM_PROCESSORS == 2
+        /* Send interrupt to the other CPU to update CCOMPARE value */
+        int other_core_id = (core_id == 0) ? 1 : 0;
+
+        s_need_update_ccompare[other_core_id] = true;
+        esp_crosscore_int_send_freq_switch(other_core_id);
+
+        int timeout = 0;
+        while (s_need_update_ccompare[other_core_id]) {
+            if (++timeout == CCOMPARE_UPDATE_TIMEOUT) {
+                assert(false && "failed to update CCOMPARE, possible deadlock");
+            }
+        }
+#endif // portNUM_PROCESSORS == 2
+
+        s_ccount_mul = 0;
+        s_ccount_div = 0;
+        ESP_PM_TRACE_EXIT(CCOMPARE_UPDATE, core_id);
+    }
+}
+
+/**
+ * Perform the switch to new power mode.
+ * Currently only changes the CPU frequency and adjusts clock dividers.
+ * No light sleep yet.
+ * @param new_mode mode to switch to
+ */
+static void IRAM_ATTR do_switch(pm_mode_t new_mode)
+{
+    const int core_id = xPortGetCoreID();
+
+    do {
+        portENTER_CRITICAL_ISR(&s_switch_lock);
+        if (!s_is_switching) {
+            break;
+        }
+        if (s_new_mode <= new_mode) {
+            portEXIT_CRITICAL_ISR(&s_switch_lock);
+            return;
+        }
+        if (s_need_update_ccompare[core_id]) {
+            s_need_update_ccompare[core_id] = false;
+        }
+        portEXIT_CRITICAL_ISR(&s_switch_lock);
+    } while (true);
+    s_new_mode = new_mode;
+    s_is_switching = true;
+    bool config_changed = s_config_changed;
+    s_config_changed = false;
+    portEXIT_CRITICAL_ISR(&s_switch_lock);
+
+    rtc_cpu_freq_t new_freq = s_cpu_freq_by_mode[new_mode];
+    rtc_cpu_freq_t old_freq;
+    if (!config_changed) {
+        old_freq = s_cpu_freq_by_mode[s_mode];
+    } else {
+        old_freq = rtc_clk_cpu_freq_get();
+    }
+
+    if (new_freq != old_freq) {
+        uint32_t old_ticks_per_us = g_ticks_per_us_pro;
+        uint32_t new_ticks_per_us = s_cpu_freq_to_ticks[new_freq];
+
+        bool switch_down = new_ticks_per_us < old_ticks_per_us;
+
+        ESP_PM_TRACE_ENTER(FREQ_SWITCH, core_id);
+        if (switch_down) {
+            on_freq_update(old_ticks_per_us, new_ticks_per_us);
+        }
+        rtc_clk_cpu_freq_set_fast(new_freq);
+        if (!switch_down) {
+            on_freq_update(old_ticks_per_us, new_ticks_per_us);
+        }
+        ESP_PM_TRACE_EXIT(FREQ_SWITCH, core_id);
+    }
+
+    portENTER_CRITICAL_ISR(&s_switch_lock);
+    s_mode = new_mode;
+    s_is_switching = false;
+    portEXIT_CRITICAL_ISR(&s_switch_lock);
+}
+
+/**
+ * @brief Calculate new CCOMPARE value based on s_ccount_{mul,div}
+ *
+ * Adjusts CCOMPARE value so that the interrupt happens at the same time as it
+ * would happen without the frequency change.
+ * Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
+ */
+static void IRAM_ATTR update_ccompare()
+{
+    uint32_t ccount = XTHAL_GET_CCOUNT();
+    uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
+    if ((ccompare - CCOMPARE_MIN_CYCLES_IN_FUTURE) - ccount < UINT32_MAX / 2) {
+        uint32_t diff = ccompare - ccount;
+        uint32_t diff_scaled = (diff * s_ccount_mul + s_ccount_div - 1) / s_ccount_div;
+        if (diff_scaled < _xt_tick_divisor) {
+            uint32_t new_ccompare = ccount + diff_scaled;
+            XTHAL_SET_CCOMPARE(XT_TIMER_INDEX, new_ccompare);
+        }
+    }
+}
+
+static void IRAM_ATTR leave_idle()
+{
+    int core_id = xPortGetCoreID();
+    if (s_core_idle[core_id]) {
+        // TODO: possible optimization: raise frequency here first
+        esp_pm_lock_acquire(s_rtos_lock_handle[core_id]);
+        s_core_idle[core_id] = false;
+    }
+}
+
+void esp_pm_impl_idle_hook()
+{
+    int core_id = xPortGetCoreID();
+    uint32_t state = portENTER_CRITICAL_NESTED();
+    if (!s_core_idle[core_id]) {
+        esp_pm_lock_release(s_rtos_lock_handle[core_id]);
+        s_core_idle[core_id] = true;
+    }
+    portEXIT_CRITICAL_NESTED(state);
+    ESP_PM_TRACE_ENTER(IDLE, core_id);
+}
+
+void IRAM_ATTR esp_pm_impl_isr_hook()
+{
+    int core_id = xPortGetCoreID();
+    ESP_PM_TRACE_ENTER(ISR_HOOK, core_id);
+#if portNUM_PROCESSORS == 2
+    if (s_need_update_ccompare[core_id]) {
+        update_ccompare();
+        s_need_update_ccompare[core_id] = false;
+    } else {
+        leave_idle();
+    }
+#else
+    leave_idle();
+#endif // portNUM_PROCESSORS == 2
+    ESP_PM_TRACE_EXIT(ISR_HOOK, core_id);
+}
+
+#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+
+bool IRAM_ATTR vApplicationSleep( TickType_t xExpectedIdleTime )
+{
+    bool result = false;
+    portENTER_CRITICAL(&s_switch_lock);
+    if (s_mode == PM_MODE_LIGHT_SLEEP && !s_is_switching) {
+        /* Calculate how much we can sleep */
+        int64_t next_esp_timer_alarm = esp_timer_get_next_alarm();
+        int64_t now = esp_timer_get_time();
+        int64_t time_until_next_alarm = next_esp_timer_alarm - now;
+        int64_t wakeup_delay_us = portTICK_PERIOD_MS * 1000LL * xExpectedIdleTime;
+        int64_t sleep_time_us = MIN(wakeup_delay_us, time_until_next_alarm);
+        if (sleep_time_us >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP * portTICK_PERIOD_MS * 1000LL) {
+            esp_sleep_enable_timer_wakeup(sleep_time_us - LIGHT_SLEEP_EARLY_WAKEUP_US);
+#ifdef CONFIG_PM_TRACE
+            /* to force tracing GPIOs to keep state */
+            esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+#endif
+            /* Enter sleep */
+            int core_id = xPortGetCoreID();
+            ESP_PM_TRACE_ENTER(SLEEP, core_id);
+            int64_t sleep_start = esp_timer_get_time();
+            esp_light_sleep_start();
+            int64_t slept_us = esp_timer_get_time() - sleep_start;
+            ESP_PM_TRACE_EXIT(SLEEP, core_id);
+
+            uint32_t slept_ticks = slept_us / (portTICK_PERIOD_MS * 1000LL);
+            if (slept_ticks > 0) {
+                /* Adjust RTOS tick count based on the amount of time spent in sleep */
+                vTaskStepTick(slept_ticks);
+
+                /* Trigger tick interrupt, since sleep time was longer
+                 * than portTICK_PERIOD_MS. Note that setting INTSET does not
+                 * work for timer interrupt, and changing CCOMPARE would clear
+                 * the interrupt flag.
+                 */
+                XTHAL_SET_CCOUNT(XTHAL_GET_CCOMPARE(XT_TIMER_INDEX) - 16);
+                while (!(XTHAL_GET_INTERRUPT() & BIT(XT_TIMER_INTNUM))) {
+                    ;
+                }
+            }
+            result = true;
+        }
+    }
+    portEXIT_CRITICAL(&s_switch_lock);
+    return result;
+}
+#endif //CONFIG_FREERTOS_USE_TICKLESS_IDLE
+
+#ifdef WITH_PROFILING
+void esp_pm_impl_dump_stats(FILE* out)
+{
+    pm_time_t time_in_mode[PM_MODE_COUNT];
+
+    portENTER_CRITICAL_ISR(&s_switch_lock);
+    memcpy(time_in_mode, s_time_in_mode, sizeof(time_in_mode));
+    pm_time_t last_mode_change_time = s_last_mode_change_time;
+    pm_mode_t cur_mode = s_mode;
+    pm_time_t now = pm_get_time();
+    portEXIT_CRITICAL_ISR(&s_switch_lock);
+
+    time_in_mode[cur_mode] += now - last_mode_change_time;
+
+    fprintf(out, "Mode stats:\n");
+    for (int i = 0; i < PM_MODE_COUNT; ++i) {
+        if (i == PM_MODE_LIGHT_SLEEP && !s_light_sleep_en) {
+            /* don't display light sleep mode if it's not enabled */
+            continue;
+        }
+        fprintf(out, "%8s %6s %12lld  %2d%%\n",
+                s_mode_names[i],
+                s_freq_names[s_cpu_freq_by_mode[i]],
+                time_in_mode[i],
+                (int) (time_in_mode[i] * 100 / now));
+    }
+}
+#endif // WITH_PROFILING
+
+void esp_pm_impl_init()
+{
+    s_cpu_freq_to_ticks[RTC_CPU_FREQ_XTAL] = rtc_clk_xtal_freq_get();
+#ifdef CONFIG_PM_TRACE
+    esp_pm_trace_init();
+#endif
+    ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos0",
+            &s_rtos_lock_handle[0]));
+    ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[0]));
+#if portNUM_PROCESSORS == 2
+    ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos1",
+            &s_rtos_lock_handle[1]));
+    ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[1]));
+#endif // portNUM_PROCESSORS == 2
+
+    /* Configure all modes to use the default CPU frequency.
+     * This will be modified later by a call to esp_pm_configure.
+     */
+    rtc_cpu_freq_t default_freq;
+    if (!rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, &default_freq)) {
+        assert(false && "unsupported frequency");
+    }
+    for (size_t i = 0; i < PM_MODE_COUNT; ++i) {
+        s_cpu_freq_by_mode[i] = default_freq;
+    }
+}

components/esp32s2beta/pm_trace.c

@@ -0,0 +1,52 @@
+// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include "esp_private/pm_trace.h"
+#include "driver/gpio.h"
+#include "soc/gpio_reg.h"
+
+/* GPIOs to use for tracing of esp_pm events.
+ * Two entries in the array for each type, one for each CPU.
+ * Feel free to change when debugging.
+ */
+static const int DRAM_ATTR s_trace_io[] = {
+        BIT(4),  BIT(5),  // ESP_PM_TRACE_IDLE
+        BIT(16), BIT(17), // ESP_PM_TRACE_TICK
+        BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH
+        BIT(19), BIT(19), // ESP_PM_TRACE_CCOMPARE_UPDATE
+        BIT(25), BIT(26), // ESP_PM_TRACE_ISR_HOOK
+        BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP
+};
+
+void esp_pm_trace_init()
+{
+    for (size_t i = 0; i < sizeof(s_trace_io)/sizeof(s_trace_io[0]); ++i) {
+        int io = __builtin_ffs(s_trace_io[i]);
+        if (io == 0) {
+            continue;
+        }
+        gpio_set_direction(io - 1, GPIO_MODE_OUTPUT);
+    }
+}
+
+void IRAM_ATTR esp_pm_trace_enter(esp_pm_trace_event_t event, int core_id)
+{
+    REG_WRITE(GPIO_OUT_W1TS_REG, s_trace_io[2 * event + core_id]);
+}
+
+void IRAM_ATTR esp_pm_trace_exit(esp_pm_trace_event_t event, int core_id)
+{
+    REG_WRITE(GPIO_OUT_W1TC_REG, s_trace_io[2 * event + core_id]);
+}

components/esp32s2beta/sleep_modes.c

@@ -0,0 +1,650 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stddef.h>
+#include <sys/lock.h>
+#include <sys/param.h>
+#include "esp_attr.h"
+#include "esp_sleep.h"
+#include "esp_private/esp_timer_impl.h"
+#include "esp_log.h"
+#include "esp32s2beta/clk.h"
+#include "esp_newlib.h"
+#include "esp_spi_flash.h"
+#include "esp32s2beta/rom/cache.h"
+#include "esp32s2beta/rom/rtc.h"
+#include "esp32s2beta/rom/uart.h"
+#include "soc/cpu.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/apb_ctrl_reg.h"
+#include "soc/rtc_io_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/sens_reg.h"
+#include "soc/dport_reg.h"
+#include "driver/rtc_io.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "sdkconfig.h"
+
+// If light sleep time is less than that, don't power down flash
+#define FLASH_PD_MIN_SLEEP_TIME_US  2000
+
+// Time from VDD_SDIO power up to first flash read in ROM code
+#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700
+
+// Extra time it takes to enter and exit light sleep and deep sleep
+// For deep sleep, this is until the wake stub runs (not the app).
+#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
+#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
+#else
+#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
+#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
+#endif // CONFIG_ESP32_RTC_CLOCK_SOURCE
+
+// Minimal amount of time we can sleep for
+#define LIGHT_SLEEP_MIN_TIME_US 200
+
+#define CHECK_SOURCE(source, value, mask) ((s_config.wakeup_triggers & mask) && \
+                                            (source == value))
+
+/**
+ * Internal structure which holds all requested deep sleep parameters
+ */
+typedef struct {
+    esp_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX];
+    uint64_t sleep_duration;
+    uint32_t wakeup_triggers : 11;
+    uint32_t ext1_trigger_mode : 1;
+    uint32_t ext1_rtc_gpio_mask : 18;
+    uint32_t ext0_trigger_level : 1;
+    uint32_t ext0_rtc_gpio_num : 5;
+    uint32_t sleep_time_adjustment;
+    uint64_t rtc_ticks_at_sleep_start;
+} sleep_config_t;
+
+static sleep_config_t s_config = {
+    .pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
+    .wakeup_triggers = 0
+};
+
+/* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
+   is not thread-safe. */
+static _lock_t lock_rtc_memory_crc;
+
+static const char* TAG = "sleep";
+
+static uint32_t get_power_down_flags();
+static void ext0_wakeup_prepare();
+static void ext1_wakeup_prepare();
+static void timer_wakeup_prepare();
+
+/* Wake from deep sleep stub
+   See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
+*/
+esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
+{
+    _lock_acquire(&lock_rtc_memory_crc);
+    uint32_t stored_crc = REG_READ(RTC_MEMORY_CRC_REG);
+    set_rtc_memory_crc();
+    uint32_t calc_crc = REG_READ(RTC_MEMORY_CRC_REG);
+    REG_WRITE(RTC_MEMORY_CRC_REG, stored_crc);
+    _lock_release(&lock_rtc_memory_crc);
+
+    if(stored_crc == calc_crc) {
+        return (esp_deep_sleep_wake_stub_fn_t)REG_READ(RTC_ENTRY_ADDR_REG);
+    } else {
+        return NULL;
+    }
+}
+
+void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
+{
+    _lock_acquire(&lock_rtc_memory_crc);
+    REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
+    set_rtc_memory_crc();
+    _lock_release(&lock_rtc_memory_crc);
+}
+
+void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
+    /* Clear MMU for CPU 0 */
+    _DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_INT_CLR);
+    _DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_DBG_EN);
+
+#if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
+    // ROM code has not started yet, so we need to set delay factor
+    // used by ets_delay_us first.
+    ets_update_cpu_frequency(ets_get_xtal_freq() / 1000000);
+    // This delay is configured in menuconfig, it can be used to give
+    // the flash chip some time to become ready.
+    ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
+#endif
+}
+
+void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
+
+void esp_deep_sleep(uint64_t time_in_us)
+{
+    esp_sleep_enable_timer_wakeup(time_in_us);
+    esp_deep_sleep_start();
+}
+
+static void IRAM_ATTR suspend_uarts()
+{
+    for (int i = 0; i < 2; ++i) {
+        REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
+        uart_tx_wait_idle(i);
+    }
+}
+
+static void IRAM_ATTR resume_uarts()
+{
+    for (int i = 0; i < 2; ++i) {
+        REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
+        REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
+        REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
+    }
+}
+
+static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
+{
+    // Stop UART output so that output is not lost due to APB frequency change
+    suspend_uarts();
+
+    // Save current frequency and switch to XTAL
+    rtc_cpu_freq_t cpu_freq = rtc_clk_cpu_freq_get();
+    rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
+
+    // Configure pins for external wakeup
+    if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
+        ext0_wakeup_prepare();
+    }
+    if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) {
+        ext1_wakeup_prepare();
+    }
+    // Enable ULP wakeup
+    if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
+        //TODO, esp32s2 does not have this bit
+        //SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN);
+    }
+
+    // Enter sleep
+    rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags);
+    rtc_sleep_init(config);
+
+    // Configure timer wakeup
+    if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) &&
+        s_config.sleep_duration > 0) {
+        timer_wakeup_prepare();
+    }
+    uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0,0);
+
+    // Restore CPU frequency
+    rtc_clk_cpu_freq_set(cpu_freq);
+
+    // re-enable UART output
+    resume_uarts();
+
+    return result;
+}
+
+void IRAM_ATTR esp_deep_sleep_start()
+{
+    // record current RTC time
+    s_config.rtc_ticks_at_sleep_start = rtc_time_get();
+    esp_sync_counters_rtc_and_frc();
+    // Configure wake stub
+    if (esp_get_deep_sleep_wake_stub() == NULL) {
+        esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
+    }
+
+    // Decide which power domains can be powered down
+    uint32_t pd_flags = get_power_down_flags();
+
+    // Correct the sleep time
+    s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
+
+    // Enter sleep
+    esp_sleep_start(RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | pd_flags);
+
+    // Because RTC is in a slower clock domain than the CPU, it
+    // can take several CPU cycles for the sleep mode to start.
+    while (1) {
+        ;
+    }
+}
+
+static void rtc_wdt_enable(int time_ms)
+{
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
+    WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_SYS_RESET_LENGTH, 7);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_CPU_RESET_LENGTH, 7);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, RTC_WDT_STG_SEL_RESET_RTC);
+    WRITE_PERI_REG(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * time_ms / 1000);
+    SET_PERI_REG_MASK(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN | RTC_CNTL_WDT_PAUSE_IN_SLP);
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
+}
+
+static void rtc_wdt_disable()
+{
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
+    WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
+    REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, RTC_WDT_STG_SEL_OFF);
+    REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN);
+    WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
+}
+
+/**
+ * Helper function which handles entry to and exit from light sleep
+ * Placed into IRAM as flash may need some time to be powered on.
+ */
+static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
+        uint32_t flash_enable_time_us,
+        rtc_vddsdio_config_t vddsdio_config) IRAM_ATTR __attribute__((noinline));
+
+static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
+        uint32_t flash_enable_time_us,
+        rtc_vddsdio_config_t vddsdio_config)
+{
+    // Enter sleep
+    esp_err_t err = esp_sleep_start(pd_flags);
+
+    // If VDDSDIO regulator was controlled by RTC registers before sleep,
+    // restore the configuration.
+    if (vddsdio_config.force) {
+        rtc_vddsdio_set_config(vddsdio_config);
+    }
+
+    // If SPI flash was powered down, wait for it to become ready
+    if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
+        // Wait for the flash chip to start up
+        ets_delay_us(flash_enable_time_us);
+    }
+    return err;
+}
+
+esp_err_t esp_light_sleep_start()
+{
+    static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
+    portENTER_CRITICAL(&light_sleep_lock);
+    /* We will be calling esp_timer_impl_advance inside DPORT access critical
+     * section. Make sure the code on the other CPU is not holding esp_timer
+     * lock, otherwise there will be deadlock.
+     */
+    esp_timer_impl_lock();
+    s_config.rtc_ticks_at_sleep_start = rtc_time_get();
+    uint64_t frc_time_at_start = esp_timer_get_time();
+    DPORT_STALL_OTHER_CPU_START();
+
+    // Decide which power domains can be powered down
+    uint32_t pd_flags = get_power_down_flags();
+
+    // Amount of time to subtract from actual sleep time.
+    // This is spent on entering and leaving light sleep.
+    s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US;
+
+    // Decide if VDD_SDIO needs to be powered down;
+    // If it needs to be powered down, adjust sleep time.
+    const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
+                                          + CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
+
+#ifndef CONFIG_SPIRAM_SUPPORT
+    const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
+            flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US);
+
+    if (s_config.sleep_duration > vddsdio_pd_sleep_duration) {
+        pd_flags |= RTC_SLEEP_PD_VDDSDIO;
+        s_config.sleep_time_adjustment += flash_enable_time_us;
+    }
+#endif //CONFIG_SPIRAM_SUPPORT
+
+    rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
+
+    // Safety net: enable WDT in case exit from light sleep fails
+    rtc_wdt_enable(1000);
+
+    // Enter sleep, then wait for flash to be ready on wakeup
+    esp_err_t err = esp_light_sleep_inner(pd_flags,
+            flash_enable_time_us, vddsdio_config);
+
+    // FRC1 has been clock gated for the duration of the sleep, correct for that.
+    uint64_t rtc_ticks_at_end = rtc_time_get();
+    uint64_t frc_time_at_end = esp_timer_get_time();
+
+    uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start,
+                                    esp_clk_slowclk_cal_get());
+    uint64_t frc_time_diff = frc_time_at_end - frc_time_at_start;
+
+    int64_t time_diff = rtc_time_diff - frc_time_diff;
+    /* Small negative values (up to 1 RTC_SLOW clock period) are possible,
+     * for very small values of sleep_duration. Ignore those to keep esp_timer
+     * monotonic.
+     */
+    if (time_diff > 0) {
+        esp_timer_impl_advance(time_diff);
+    }
+    esp_set_time_from_rtc();
+
+    esp_timer_impl_unlock();
+    DPORT_STALL_OTHER_CPU_END();
+    rtc_wdt_disable();
+    portEXIT_CRITICAL(&light_sleep_lock);
+    return err;
+}
+
+void system_deep_sleep(uint64_t) __attribute__((alias("esp_deep_sleep")));
+
+esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
+{
+    // For most of sources it is enough to set trigger mask in local
+    // configuration structure. The actual RTC wake up options
+    // will be updated by esp_sleep_start().
+    if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TIMER, RTC_TIMER_TRIG_EN)) {
+        s_config.wakeup_triggers &= ~RTC_TIMER_TRIG_EN;
+        s_config.sleep_duration = 0;
+    }
+    else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT0, RTC_EXT0_TRIG_EN)) {
+        s_config.ext0_rtc_gpio_num = 0;
+        s_config.ext0_trigger_level = 0;
+        s_config.wakeup_triggers &= ~RTC_EXT0_TRIG_EN;
+    }
+    else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT1, RTC_EXT1_TRIG_EN)) {
+        s_config.ext1_rtc_gpio_mask = 0;
+        s_config.ext1_trigger_mode = 0;
+        s_config.wakeup_triggers &= ~RTC_EXT1_TRIG_EN;
+    }
+    else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) {
+        s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN;
+    }
+#ifdef CONFIG_ULP_COPROC_ENABLED
+    else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
+        s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
+    }
+#endif
+    else {
+        ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source);
+        return ESP_ERR_INVALID_STATE;
+    }
+    return ESP_OK;
+}
+
+esp_err_t esp_sleep_enable_ulp_wakeup()
+{
+#ifdef CONFIG_ULP_COPROC_ENABLED
+    if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
+        ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
+        return ESP_ERR_INVALID_STATE;
+    }
+    s_config.wakeup_triggers |= RTC_ULP_TRIG_EN;
+    return ESP_OK;
+#else
+    return ESP_ERR_INVALID_STATE;
+#endif
+}
+
+esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
+{
+    s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN;
+    s_config.sleep_duration = time_in_us;
+    return ESP_OK;
+}
+
+static void timer_wakeup_prepare()
+{
+    uint32_t period = esp_clk_slowclk_cal_get();
+    int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
+    if (sleep_duration < 0) {
+        sleep_duration = 0;
+    }
+    int64_t rtc_count_delta = rtc_time_us_to_slowclk(sleep_duration, period);
+
+    rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + rtc_count_delta);
+}
+
+esp_err_t esp_sleep_enable_touchpad_wakeup()
+{
+    if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
+        ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
+        return ESP_ERR_INVALID_STATE;
+    }
+    s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN;
+    return ESP_OK;
+}
+
+touch_pad_t esp_sleep_get_touchpad_wakeup_status()
+{
+    if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
+        return TOUCH_PAD_MAX;
+    }
+    uint32_t touch_mask = REG_GET_FIELD(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN);
+    assert(touch_mask != 0 && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
+    return (touch_pad_t) (__builtin_ffs(touch_mask) - 1);
+}
+
+esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
+{
+    if (level < 0 || level > 1) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
+        ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
+        return ESP_ERR_INVALID_STATE;
+    }
+    s_config.ext0_rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
+    s_config.ext0_trigger_level = level;
+    s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN;
+    return ESP_OK;
+}
+
+static void ext0_wakeup_prepare()
+{
+    int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
+    // Set GPIO to be used for wakeup
+    REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtc_gpio_num);
+    // Set level which will trigger wakeup
+    SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
+            s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S);
+    // Find GPIO descriptor in the rtc_gpio_desc table and configure the pad
+    for (size_t gpio_num = 0; gpio_num < GPIO_PIN_COUNT; ++gpio_num) {
+        const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio_num];
+        if (desc->rtc_num == rtc_gpio_num) {
+            REG_SET_BIT(desc->reg, desc->mux);
+            SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
+            REG_SET_BIT(desc->reg, desc->ie);
+            break;
+        }
+    }
+}
+
+esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode)
+{
+    if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    // Translate bit map of GPIO numbers into the bit map of RTC IO numbers
+    uint32_t rtc_gpio_mask = 0;
+    for (int gpio = 0; mask; ++gpio, mask >>= 1) {
+        if ((mask & 1) == 0) {
+            continue;
+        }
+        if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
+            ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
+            return ESP_ERR_INVALID_ARG;
+        }
+        rtc_gpio_mask |= BIT(rtc_gpio_desc[gpio].rtc_num);
+    }
+    s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
+    s_config.ext1_trigger_mode = mode;
+    s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN;
+    return ESP_OK;
+}
+
+static void ext1_wakeup_prepare()
+{
+    // Configure all RTC IOs selected as ext1 wakeup inputs
+    uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
+    for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
+        int rtc_pin = rtc_gpio_desc[gpio].rtc_num;
+        if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
+            continue;
+        }
+        const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio];
+        // Route pad to RTC
+        REG_SET_BIT(desc->reg, desc->mux);
+        SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
+        // set input enable in sleep mode
+        REG_SET_BIT(desc->reg, desc->ie);
+        // Pad configuration depends on RTC_PERIPH state in sleep mode
+        if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
+            // RTC_PERIPH will be powered down, so RTC_IO_ registers will
+            // loose their state. Lock pad configuration.
+            // Pullups/pulldowns also need to be disabled.
+            REG_CLR_BIT(desc->reg, desc->pulldown);
+            REG_CLR_BIT(desc->reg, desc->pullup);
+        }
+        // Keep track of pins which are processed to bail out early
+        rtc_gpio_mask &= ~BIT(rtc_pin);
+    }
+    // Clear state from previous wakeup
+    REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
+    // Set pins to be used for wakeup
+    REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, s_config.ext1_rtc_gpio_mask);
+    // Set logic function (any low, all high)
+    SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
+            s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
+}
+
+uint64_t esp_sleep_get_ext1_wakeup_status()
+{
+    if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
+        return 0;
+    }
+    uint32_t status = REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
+    // Translate bit map of RTC IO numbers into the bit map of GPIO numbers
+    uint64_t gpio_mask = 0;
+    for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
+        if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
+            continue;
+        }
+        int rtc_pin = rtc_gpio_desc[gpio].rtc_num;
+        if ((status & BIT(rtc_pin)) == 0) {
+            continue;
+        }
+        gpio_mask |= 1ULL << gpio;
+    }
+    return gpio_mask;
+}
+
+esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause()
+{
+    if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
+        return ESP_SLEEP_WAKEUP_UNDEFINED;
+    }
+
+    uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
+    if (wakeup_cause & RTC_EXT0_TRIG_EN) {
+        return ESP_SLEEP_WAKEUP_EXT0;
+    } else if (wakeup_cause & RTC_EXT1_TRIG_EN) {
+        return ESP_SLEEP_WAKEUP_EXT1;
+    } else if (wakeup_cause & RTC_TIMER_TRIG_EN) {
+        return ESP_SLEEP_WAKEUP_TIMER;
+    } else if (wakeup_cause & RTC_TOUCH_TRIG_EN) {
+        return ESP_SLEEP_WAKEUP_TOUCHPAD;
+    } else if (wakeup_cause & RTC_ULP_TRIG_EN) {
+        return ESP_SLEEP_WAKEUP_ULP;
+    } else {
+        return ESP_SLEEP_WAKEUP_UNDEFINED;
+    }
+}
+
+esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
+                                   esp_sleep_pd_option_t option)
+{
+    if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    s_config.pd_options[domain] = option;
+    return ESP_OK;
+}
+
+static uint32_t get_power_down_flags()
+{
+    // Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
+
+    // RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP
+    // is used and RTC_SLOW_MEM is Auto.
+    // If there is any data placed into .rtc.data or .rtc.bss segments, and
+    // RTC_SLOW_MEM is Auto, keep it powered up as well.
+
+    // These labels are defined in the linker script:
+    extern int _rtc_data_start, _rtc_data_end, _rtc_bss_start, _rtc_bss_end;
+
+    if ((s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO) &&
+            (&_rtc_data_end > &_rtc_data_start || &_rtc_bss_end > &_rtc_bss_start ||
+            (s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) {
+        s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
+    }
+
+    // RTC_FAST_MEM is needed for deep sleep stub.
+    // If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub
+    // can run.
+    // In the new chip revision, deep sleep stub will be optional,
+    // and this can be changed.
+    if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) {
+        s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
+    }
+
+    // RTC_PERIPH is needed for EXT0 wakeup.
+    // If RTC_PERIPH is auto, and EXT0 isn't enabled, power down RTC_PERIPH.
+    if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
+        if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
+            s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
+        } else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
+            // In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH
+            // prevents ULP timer and touch FSMs from working correctly.
+            s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
+        }
+    }
+
+    if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) {
+        s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
+    }
+
+    const char* option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
+    ESP_LOGD(TAG, "RTC_PERIPH: %s, RTC_SLOW_MEM: %s, RTC_FAST_MEM: %s",
+            option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]],
+            option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]],
+            option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
+
+    // Prepare flags based on the selected options
+    uint32_t pd_flags = 0;
+    if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
+        pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
+    }
+    if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
+        pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
+    }
+    if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
+        pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
+    }
+//    if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) {
+//        pd_flags |= RTC_SLEEP_PD_XTAL;
+//    }
+    return pd_flags;
+}

components/esp32s2beta/spiram.c

@@ -0,0 +1,367 @@
+/*
+Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if
+we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
+*/
+
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <string.h>
+#include <sys/param.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_err.h"
+#include "esp32s2beta/spiram.h"
+#include "spiram_psram.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/xtensa_api.h"
+#include "soc/soc.h"
+#include "esp_heap_caps_init.h"
+#include "soc/soc_memory_layout.h"
+#include "soc/dport_reg.h"
+#include "esp32s2beta/rom/cache.h"
+
+#if CONFIG_FREERTOS_UNICORE
+#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
+#else
+#if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD
+#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
+#else
+#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
+#endif
+#endif
+
+#if CONFIG_SPIRAM_SUPPORT
+
+static const char* TAG = "spiram";
+
+#if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
+#define PSRAM_SPEED PSRAM_CACHE_F40M_S40M
+#elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
+#define PSRAM_SPEED PSRAM_CACHE_F80M_S40M
+#elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
+#define PSRAM_SPEED PSRAM_CACHE_F80M_S80M
+#else
+#define PSRAM_SPEED PSRAM_CACHE_F20M_S20M
+#endif
+
+
+static bool spiram_inited=false;
+
+
+/*
+ Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
+ true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
+ initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
+*/
+bool esp_spiram_test()
+{
+    volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - CONFIG_SPIRAM_SIZE);
+    size_t p;
+    size_t s=CONFIG_SPIRAM_SIZE;
+    int errct=0;
+    int initial_err=-1;
+
+    if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) < CONFIG_SPIRAM_SIZE) {
+        ESP_EARLY_LOGW(TAG, "Only test spiram from %08x to %08x\n", SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH);
+        spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
+        s = SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW;
+    }
+    for (p=0; p<(s/sizeof(int)); p+=8) {
+        spiram[p]=p^0xAAAAAAAA;
+    }
+    for (p=0; p<(s/sizeof(int)); p+=8) {
+        if (spiram[p]!=(p^0xAAAAAAAA)) {
+            errct++;
+            if (errct==1) initial_err=p*4;
+            if (errct < 4) {
+                ESP_EARLY_LOGE(TAG, "SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p], p^0xAAAAAAAA);
+            }
+        }
+    }
+    if (errct) {
+        ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW);
+        return false;
+    } else {
+        ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
+        return true;
+    }
+}
+
+#define DRAM0_ONLY_CACHE_SIZE                   BUS_IRAM0_CACHE_SIZE
+#define DRAM0_DRAM1_CACHE_SIZE	                (BUS_IRAM0_CACHE_SIZE + BUS_IRAM1_CACHE_SIZE)
+#define DRAM0_DRAM1_DPORT_CACHE_SIZE            (BUS_IRAM0_CACHE_SIZE + BUS_IRAM1_CACHE_SIZE + BUS_DPORT_CACHE_SIZE)
+#define DBUS3_ONLY_CACHE_SIZE                   BUS_AHB_DBUS3_CACHE_SIZE
+#define DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE      (DRAM0_DRAM1_DPORT_CACHE_SIZE + DBUS3_ONLY_CACHE_SIZE)
+
+#define SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT      (CONFIG_SPIRAM_SIZE - DRAM0_DRAM1_DPORT_CACHE_SIZE)
+#define SPIRAM_SIZE_EXC_DATA_CACHE             (CONFIG_SPIRAM_SIZE - DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE)
+
+#define SPIRAM_SMALL_SIZE_MAP_VADDR             (DRAM0_CACHE_ADDRESS_HIGH - CONFIG_SPIRAM_SIZE)
+#define SPIRAM_SMALL_SIZE_MAP_PADDR             0
+#define SPIRAM_SMALL_SIZE_MAP_SIZE              CONFIG_SPIRAM_SIZE
+
+#define SPIRAM_MID_SIZE_MAP_VADDR               (AHB_DBUS3_ADDRESS_HIGH - SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT)
+#define SPIRAM_MID_SIZE_MAP_PADDR               0
+#define SPIRAM_MID_SIZE_MAP_SIZE                (SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT)
+
+#define SPIRAM_BIG_SIZE_MAP_VADDR               AHB_DBUS3_ADDRESS_LOW
+#define SPIRAM_BIG_SIZE_MAP_PADDR               (AHB_DBUS3_ADDRESS_HIGH - DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE)
+#define SPIRAM_BIG_SIZE_MAP_SIZE                DBUS3_ONLY_CACHE_SIZE
+
+#define SPIRAM_MID_BIG_SIZE_MAP_VADDR           DPORT_CACHE_ADDRESS_LOW
+#define SPIRAM_MID_BIG_SIZE_MAP_PADDR           SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT
+#define SPIRAM_MID_BIG_SIZE_MAP_SIZE            DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE
+
+
+void IRAM_ATTR esp_spiram_init_cache()
+{
+    Cache_Suspend_DCache();
+    /* map the address from SPIRAM end to the start, map the address in order: DRAM1, DRAM1, DPORT, DBUS3 */
+#if CONFIG_SPIRAM_SIZE <= DRAM0_ONLY_CACHE_SIZE
+    /* cache size <= 3MB + 576 KB, only map DRAM0 bus */
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0);
+    REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0);
+    REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM0);
+#elif CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_CACHE_SIZE
+    /* cache size <= 7MB + 576KB, only map DRAM0 and DRAM1 bus */
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0);
+    REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0);
+    REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0);
+#elif CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_CACHE_SIZE
+    /* cache size <= 10MB + 576KB, map DRAM0, DRAM1, DPORT bus */
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0);
+    REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0);
+    REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT);
+#else
+#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
+#if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE
+    /* cache size <= 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0);
+#else
+    /* cache size > 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_BIG_SIZE_MAP_VADDR, SPIRAM_BIG_SIZE_MAP_PADDR, 64, SPIRAM_BIG_SIZE_MAP_SIZE >> 16, 0);
+#endif
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0);
+    REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0);
+    REG_CLR_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0);
+    REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT | DPORT_PRO_DCACHE_MASK_BUS3);
+#else
+    /* cache size > 10MB + 576KB, map DRAM0, DRAM1, DPORT bus , only remap 0x3f500000 ~ 0x3ff90000*/
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0);
+    REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0);
+    REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT);
+#endif
+#endif
+}
+
+static uint32_t pages_for_flash = 0;
+static uint32_t page0_mapped = 0;
+static uint32_t page0_page = 0xffff;
+static uint32_t instrcution_in_spiram = 0;
+static uint32_t rodata_in_spiram = 0;
+
+uint32_t esp_spiram_instruction_access_enabled()
+{
+    return instrcution_in_spiram;
+}
+
+uint32_t esp_spiram_rodata_access_enabled()
+{
+    return rodata_in_spiram;
+}
+
+esp_err_t esp_spiram_enable_instruction_access(void)
+{
+    uint32_t pages_in_flash = 0;
+    pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped);
+    pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped);
+    pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped);
+    if ((pages_in_flash + pages_for_flash) > (CONFIG_SPIRAM_SIZE >> 16)) {
+        ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (CONFIG_SPIRAM_SIZE >> 16), (pages_in_flash + pages_for_flash));
+        return ESP_FAIL;
+    }
+    ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
+    pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, pages_for_flash, &page0_page);
+    pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, pages_for_flash, &page0_page);
+    pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, IROM0_ADDRESS_LOW, pages_for_flash, &page0_page);
+    instrcution_in_spiram = 1;
+    return ESP_OK;
+}
+
+esp_err_t esp_spiram_enable_rodata_access(void)
+{
+    uint32_t pages_in_flash = 0;
+    if (Cache_Drom0_Using_ICache()) {
+        pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS3, &page0_mapped);
+    } else {
+        pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS3, &page0_mapped);
+    }
+    pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS0, &page0_mapped);
+    pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped);
+    pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped);
+
+    if ((pages_in_flash + pages_for_flash) > (CONFIG_SPIRAM_SIZE >> 16)) {
+        ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the read only data.");
+        return ESP_FAIL;
+    }
+
+    ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM");
+    if (Cache_Drom0_Using_ICache()) {
+        pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS3, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page);
+    } else {
+        pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS3, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page);
+    }
+    pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, pages_for_flash, &page0_page);
+    pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, pages_for_flash, &page0_page);
+    pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, pages_for_flash, &page0_page);
+    rodata_in_spiram = 1;
+    return ESP_OK;
+}
+
+esp_err_t esp_spiram_init()
+{
+    esp_err_t r;
+    r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
+    if (r != ESP_OK) {
+#if CONFIG_SPIRAM_IGNORE_NOTFOUND
+        ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
+#endif
+        return r;
+    }
+
+    ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \
+                                          PSRAM_SPEED == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \
+                                          PSRAM_SPEED == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : "flash 20m sram 20m");
+    ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
+                                          (PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \
+                                          (PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \
+                                          (PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR");
+    spiram_inited=true;
+    return ESP_OK;
+}
+
+
+esp_err_t esp_spiram_add_to_heapalloc()
+{
+    uint32_t size_for_flash = (pages_for_flash << 16);
+    ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (CONFIG_SPIRAM_SIZE - (pages_for_flash << 16))/1024);
+    //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
+    //no need to explicitly specify them.
+
+#if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_CACHE_SIZE
+    /* cache size <= 10MB + 576KB, map DRAM0, DRAM1, DPORT bus */
+    return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1);
+#else
+#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
+#if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE
+    /* cache size <= 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */
+    if (size_for_flash <= SPIRAM_MID_SIZE_MAP_SIZE) {
+        esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1);
+        if (err) {
+            return err;
+        }
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    } else {
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + size_for_flash - SPIRAM_MID_SIZE_MAP_SIZE, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    }
+#else
+    if (size_for_flash <= SPIRAM_SIZE_EXC_DATA_CACHE) {
+        esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_BIG_SIZE_MAP_VADDR + SPIRAM_BIG_SIZE_MAP_SIZE -1);
+        if (err) {
+            return err;
+        }
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    } else if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) {
+        esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_BIG_SIZE_MAP_VADDR + size_for_flash - SPIRAM_SIZE_EXC_DATA_CACHE, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1);
+        if (err) {
+            return err;
+        }
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    } else {
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + size_for_flash - SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    }
+#endif
+#else
+    Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0);
+    if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) {
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    } else {
+        return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1);
+    }
+#endif
+#endif
+}
+
+
+static uint8_t *dma_heap;
+
+esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
+    if (size==0) return ESP_OK; //no-op
+    ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024);
+    dma_heap=heap_caps_malloc(size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
+    if (!dma_heap) return ESP_ERR_NO_MEM;
+    uint32_t caps[]={MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT};
+    return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+size-1);
+}
+
+size_t esp_spiram_get_size()
+{
+    return CONFIG_SPIRAM_SIZE;
+}
+
+/*
+ Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
+ otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
+*/
+void IRAM_ATTR esp_spiram_writeback_cache()
+{
+    extern void Cache_WriteBack_All(void);
+    int cache_was_disabled=0;
+
+    if (!spiram_inited) return;
+
+    //We need cache enabled for this to work. Re-enable it if needed; make sure we
+    //disable it again on exit as well.
+    if (DPORT_REG_GET_BIT(DPORT_PRO_DCACHE_CTRL_REG, DPORT_PRO_DCACHE_ENABLE)==0) {
+        cache_was_disabled|=(1<<0);
+        DPORT_SET_PERI_REG_BITS(DPORT_PRO_DCACHE_CTRL_REG, 1, 1, DPORT_PRO_DCACHE_ENABLE_S);
+    }
+
+#ifndef CONFIG_FREERTOS_UNICORE
+    if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) {
+        cache_was_disabled|=(1<<1);
+        DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
+    }
+#endif
+
+    Cache_WriteBack_All();
+
+    if (cache_was_disabled&(1<<0)) {
+#ifdef DPORT_CODE_COMPLETE
+        while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG2_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
+#endif
+        DPORT_SET_PERI_REG_BITS(DPORT_PRO_DCACHE_CTRL_REG, 1, 0, DPORT_PRO_DCACHE_ENABLE_S);
+    }
+#ifndef CONFIG_FREERTOS_UNICORE
+    if (cache_was_disabled&(1<<1)) {
+        while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG2_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) ;
+        DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
+    }
+#endif
+}
+
+#endif

components/esp32s2beta/spiram_psram.c

@@ -0,0 +1,903 @@
+/*
+ Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
+*/
+
+// Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include "sdkconfig.h"
+#include "string.h"
+#include "esp_attr.h"
+#include "esp_err.h"
+#include "esp_types.h"
+#include "esp_log.h"
+#include "spiram_psram.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/gpio.h"
+#include "esp32s2beta/rom/cache.h"
+#include "soc/io_mux_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/apb_ctrl_reg.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/efuse_reg.h"
+#include "driver/gpio.h"
+#include "driver/spi_common.h"
+#include "driver/periph_ctrl.h"
+
+#if CONFIG_SPIRAM_SUPPORT
+#include "soc/rtc.h"
+
+//Commands for PSRAM chip
+#define PSRAM_READ                 0x03
+#define PSRAM_FAST_READ            0x0B
+#define PSRAM_FAST_READ_DUMMY      0x3
+#define PSRAM_FAST_READ_QUAD       0xEB
+#define PSRAM_FAST_READ_QUAD_DUMMY 0x5
+#define PSRAM_WRITE                0x02
+#define PSRAM_QUAD_WRITE           0x38
+#define PSRAM_ENTER_QMODE          0x35
+#define PSRAM_EXIT_QMODE           0xF5
+#define PSRAM_RESET_EN             0x66
+#define PSRAM_RESET                0x99
+#define PSRAM_SET_BURST_LEN        0xC0
+#define PSRAM_DEVICE_ID            0x9F
+
+typedef enum {
+    PSRAM_CLK_MODE_NORM = 0,    /*!< Normal SPI mode */
+    PSRAM_CLK_MODE_DCLK = 1,    /*!< Two extra clock cycles after CS is set high level */
+} psram_clk_mode_t;
+
+#define PSRAM_ID_KGD_M          0xff
+#define PSRAM_ID_KGD_S             8
+#define PSRAM_ID_KGD            0x5d
+#define PSRAM_ID_EID_M          0xff
+#define PSRAM_ID_EID_S            16
+
+#define PSRAM_KGD(id)          (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
+#define PSRAM_EID(id)          (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
+#define PSRAM_IS_VALID(id)     (PSRAM_KGD(id) == PSRAM_ID_KGD)
+
+// PSRAM_EID = 0x26 or 0x4x ----> 64MBit psram
+// PSRAM_EID = 0x20 ------------> 32MBit psram
+#define PSRAM_IS_64MBIT(id)       ((PSRAM_EID(id) == 0x26) || ((PSRAM_EID(id) & 0xf0) == 0x40))
+#define PSRAM_IS_32MBIT_VER0(id)  (PSRAM_EID(id) == 0x20)
+
+// IO-pins for PSRAM. These need to be in the VDD_SIO power domain because all chips we
+// currently support are 1.8V parts.
+// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
+// hardcode the flash pins as well, making this code incompatible with either a setup
+// that has the flash on non-standard pins or ESP32s with built-in flash.
+#define FLASH_CLK_IO      SPI_CLK_GPIO_NUM  //Psram clock is a delayed version of this in 40MHz mode
+#define FLASH_CS_IO       SPI_CS0_GPIO_NUM
+#define PSRAM_CS_IO       26
+#define PSRAM_SPIQ_IO     SPI_Q_GPIO_NUM
+#define PSRAM_SPID_IO     SPI_D_GPIO_NUM
+#define PSRAM_SPIWP_IO    SPI_WP_GPIO_NUM
+#define PSRAM_SPIHD_IO    SPI_HD_GPIO_NUM
+#define PSRAM_INTERNAL_IO_28       28
+#define PSRAM_INTERNAL_IO_29       29
+#define PSRAM_IO_MATRIX_DUMMY_20M   0
+#define PSRAM_IO_MATRIX_DUMMY_40M   0
+#define PSRAM_IO_MATRIX_DUMMY_80M   0
+
+#define _SPI_CACHE_PORT   0
+#define _SPI_FLASH_PORT   1
+#define _SPI_80M_CLK_DIV  1
+#define _SPI_40M_CLK_DIV  2
+#define _SPI_20M_CLK_DIV  4
+
+static const char* TAG = "psram";
+typedef enum {
+    PSRAM_SPI_1  = 0x1,
+    PSRAM_SPI_2,
+    PSRAM_SPI_3,
+    PSRAM_SPI_MAX ,
+} psram_spi_num_t;
+
+static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
+static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK;
+static uint32_t s_psram_id = 0;
+
+/* dummy_len_plus values defined in ROM for SPI flash configuration */
+extern uint8_t g_rom_spiflash_dummy_len_plus[];
+static int extra_dummy = 0;
+typedef enum {
+    PSRAM_CMD_QPI,
+    PSRAM_CMD_SPI,
+} psram_cmd_mode_t;
+
+typedef struct {
+    uint16_t cmd;                /*!< Command value */
+    uint16_t cmdBitLen;          /*!< Command byte length*/
+    uint32_t *addr;              /*!< Point to address value*/
+    uint16_t addrBitLen;         /*!< Address byte length*/
+    uint32_t *txData;            /*!< Point to send data buffer*/
+    uint16_t txDataBitLen;       /*!< Send data byte length.*/
+    uint32_t *rxData;            /*!< Point to recevie data buffer*/
+    uint16_t rxDataBitLen;       /*!< Recevie Data byte length.*/
+    uint32_t dummyBitLen;
+} psram_cmd_t;
+
+static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
+
+static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
+{
+    int i;
+    for (i = 0; i < 16; i++) {
+        WRITE_PERI_REG(SPI_MEM_W0_REG(spi_num)+i*4, 0);
+    }
+}
+
+//set basic SPI write mode
+static void psram_set_basic_write_mode(psram_spi_num_t spi_num)
+{
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QIO);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DIO);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QUAD);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DUAL);
+}
+//set QPI write mode
+static void psram_set_qio_write_mode(psram_spi_num_t spi_num)
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QIO);
+    SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DIO);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QUAD);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DUAL);
+}
+//set QPI read mode
+static void psram_set_qio_read_mode(psram_spi_num_t spi_num)
+{
+    SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QIO);
+    SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QUAD);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DUAL);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DIO);
+}
+//set SPI read mode
+static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
+{
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QIO);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QUAD);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DUAL);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DIO);
+}
+
+
+//start sending cmd/addr and optionally, receiving data
+static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen,
+        psram_cmd_mode_t cmd_mode)
+{
+    //get cs1
+    CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS1_DIS_M);
+    SET_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS0_DIS_M);
+
+    uint32_t mode_backup = (READ_PERI_REG(SPI_MEM_USER_REG(spi_num)) >> SPI_MEM_FWRITE_DUAL_S) & 0xf;
+#ifdef FAKE_QPI
+    uint32_t rd_mode_backup = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)) & (SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_QIO_M);
+#else
+    uint32_t rd_mode_backup = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)) & (SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_QIO_M | SPI_MEM_FCMD_QUAD);
+#endif
+    if (cmd_mode == PSRAM_CMD_SPI) {
+        psram_set_basic_write_mode(spi_num);
+        psram_set_basic_read_mode(spi_num);
+    } else if (cmd_mode == PSRAM_CMD_QPI) {
+        psram_set_qio_write_mode(spi_num);
+        psram_set_qio_read_mode(spi_num);
+    }
+
+    // Start send data
+    SET_PERI_REG_MASK(SPI_MEM_CMD_REG(spi_num), SPI_MEM_USR);
+    while ((READ_PERI_REG(SPI_MEM_CMD_REG(spi_num)) & SPI_MEM_USR));
+
+    //recover spi mode
+    SET_PERI_REG_BITS(SPI_MEM_USER_REG(spi_num), (pRxData?SPI_MEM_FWRITE_DUAL_M:0xf), mode_backup, SPI_MEM_FWRITE_DUAL_S);
+#ifdef FAKE_QPI
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), (SPI_MEM_FREAD_DIO_M|SPI_MEM_FREAD_DUAL_M|SPI_MEM_FREAD_QUAD_M|SPI_MEM_FREAD_QIO_M));
+#else
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), (SPI_MEM_FREAD_DIO_M|SPI_MEM_FREAD_DUAL_M|SPI_MEM_FREAD_QUAD_M|SPI_MEM_FREAD_QIO_M|SPI_MEM_FCMD_QUAD));
+#endif
+    SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), rd_mode_backup);
+
+    //return cs to cs0
+    SET_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS1_DIS_M);
+    CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS0_DIS_M);
+
+    if (pRxData) {
+        int idx = 0;
+        // Read data out
+        do {
+            *pRxData++ = READ_PERI_REG(SPI_MEM_W0_REG(spi_num) + (idx << 2));
+        } while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0)));
+    }
+}
+
+static uint32_t backup_usr[3];
+static uint32_t backup_usr1[3];
+static uint32_t backup_usr2[3];
+
+
+
+//setup spi command/addr/data/dummy in user mode
+static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData)
+{
+    while (READ_PERI_REG(SPI_MEM_CMD_REG(spi_num)) & SPI_MEM_USR);
+    backup_usr[spi_num]=READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
+    backup_usr1[spi_num]=READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
+    backup_usr2[spi_num]=READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
+    // Set command by user.
+    if (pInData->cmdBitLen != 0) {
+        // Max command length 16 bits.
+        SET_PERI_REG_BITS(SPI_MEM_USER2_REG(spi_num), SPI_MEM_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1,
+                SPI_MEM_USR_COMMAND_BITLEN_S);
+        // Enable command
+        SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_COMMAND);
+        // Load command,bit15-0 is cmd value.
+        SET_PERI_REG_BITS(SPI_MEM_USER2_REG(spi_num), SPI_MEM_USR_COMMAND_VALUE, pInData->cmd, SPI_MEM_USR_COMMAND_VALUE_S);
+    } else {
+        CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_COMMAND);
+        SET_PERI_REG_BITS(SPI_MEM_USER2_REG(spi_num), SPI_MEM_USR_COMMAND_BITLEN, 0, SPI_MEM_USR_COMMAND_BITLEN_S);
+    }
+    // Set Address by user.
+    if (pInData->addrBitLen != 0) {
+        SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_MEM_USR_ADDR_BITLEN_S);
+        // Enable address
+        SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_ADDR);
+        // Set address
+        WRITE_PERI_REG(SPI_MEM_ADDR_REG(spi_num), *pInData->addr);
+    } else {
+        CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_ADDR);
+        SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_ADDR_BITLEN, 0, SPI_MEM_USR_ADDR_BITLEN_S);
+    }
+    // Set data by user.
+    uint32_t* p_tx_val = pInData->txData;
+    if (pInData->txDataBitLen != 0) {
+        // Enable MOSI
+        SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MOSI);
+        // Load send buffer
+        int len = (pInData->txDataBitLen + 31) / 32;
+        if (p_tx_val != NULL) {
+            memcpy((void*)SPI_MEM_W0_REG(spi_num), p_tx_val, len * 4);
+        }
+        // Set data send buffer length.Max data length 64 bytes.
+        SET_PERI_REG_BITS(SPI_MEM_MOSI_DLEN_REG(spi_num), SPI_MEM_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1),
+                SPI_MEM_USR_MOSI_DBITLEN_S);
+    } else {
+        CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MOSI);
+        SET_PERI_REG_BITS(SPI_MEM_MOSI_DLEN_REG(spi_num), SPI_MEM_USR_MOSI_DBITLEN, 0, SPI_MEM_USR_MOSI_DBITLEN_S);
+    }
+    // Set rx data by user.
+    if (pInData->rxDataBitLen != 0) {
+        // Enable MOSI
+        SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MISO);
+        // Set data send buffer length.Max data length 64 bytes.
+        SET_PERI_REG_BITS(SPI_MEM_MISO_DLEN_REG(spi_num), SPI_MEM_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1),
+                SPI_MEM_USR_MISO_DBITLEN_S);
+    } else {
+        CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MISO);
+        SET_PERI_REG_BITS(SPI_MEM_MISO_DLEN_REG(spi_num), SPI_MEM_USR_MISO_DBITLEN, 0, SPI_MEM_USR_MISO_DBITLEN_S);
+    }
+    if (pInData->dummyBitLen != 0) {
+        SET_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY); // dummy en
+        SET_PERI_REG_BITS(SPI_MEM_USER1_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1,
+                SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+    } else {
+        CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY); // dummy en
+        SET_PERI_REG_BITS(SPI_MEM_USER1_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY_CYCLELEN_V, 0, SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+    }
+    return 0;
+}
+
+void psram_cmd_end(int spi_num) {
+    while (READ_PERI_REG(SPI_MEM_CMD_REG(spi_num)) & SPI_MEM_USR);
+    WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr[spi_num]);
+    WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1[spi_num]);
+    WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2[spi_num]);
+}
+
+#ifdef FAKE_QPI
+//exit QPI mode(set back to SPI mode)
+static void psram_disable_qio_mode(psram_spi_num_t spi_num)
+{
+    psram_cmd_t ps_cmd;
+    uint32_t cmd_exit_qpi;
+    cmd_exit_qpi = PSRAM_EXIT_QMODE;
+    ps_cmd.txDataBitLen = 8;
+    if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
+        switch (s_psram_mode) {
+            case PSRAM_CACHE_F80M_S80M:
+                break;
+            case PSRAM_CACHE_F80M_S40M:
+            case PSRAM_CACHE_F40M_S40M:
+            default:
+                cmd_exit_qpi = PSRAM_EXIT_QMODE << 8;
+                ps_cmd.txDataBitLen = 16;
+                break;
+        }
+    }
+    ps_cmd.txData = &cmd_exit_qpi;
+    ps_cmd.cmd = 0;
+    ps_cmd.cmdBitLen = 0;
+    ps_cmd.addr = 0;
+    ps_cmd.addrBitLen = 0;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI);
+    psram_cmd_end(spi_num);
+}
+
+//read psram id
+static void psram_read_id(uint32_t* dev_id)
+{
+    psram_spi_num_t spi_num = PSRAM_SPI_1;
+    psram_disable_qio_mode(spi_num);
+    uint32_t dummy_bits = 0 + extra_dummy;
+    psram_cmd_t ps_cmd;
+
+    uint32_t addr = 0;
+    ps_cmd.addrBitLen = 3 * 8;
+    ps_cmd.cmd = PSRAM_DEVICE_ID;
+    ps_cmd.cmdBitLen = 8;
+    if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
+        switch (s_psram_mode) {
+            case PSRAM_CACHE_F80M_S80M:
+                break;
+            case PSRAM_CACHE_F80M_S40M:
+            case PSRAM_CACHE_F40M_S40M:
+            default:
+                ps_cmd.cmdBitLen = 2;   //this two bits is used to delay 2 clock cycle
+                ps_cmd.cmd = 0;
+                addr = (PSRAM_DEVICE_ID << 24) | 0;
+                ps_cmd.addrBitLen = 4 * 8;
+                break;
+        }
+    }
+    ps_cmd.addr = &addr;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.txData = NULL;
+    ps_cmd.rxDataBitLen = 4 * 8;
+    ps_cmd.rxData = dev_id;
+    ps_cmd.dummyBitLen = dummy_bits;
+
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_clear_spi_fifo(spi_num);
+    psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
+    psram_cmd_end(spi_num);
+}
+
+//enter QPI mode
+static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
+{
+    psram_cmd_t ps_cmd;
+    uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0;
+
+    ps_cmd.cmdBitLen = 0;
+    if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
+        switch (s_psram_mode) {
+            case PSRAM_CACHE_F80M_S80M:
+                break;
+            case PSRAM_CACHE_F80M_S40M:
+            case PSRAM_CACHE_F40M_S40M:
+            default:
+                ps_cmd.cmdBitLen = 2;
+                break;
+        }
+    }
+    ps_cmd.cmd = 0;
+    ps_cmd.addr = &addr;
+    ps_cmd.addrBitLen = 8;
+    ps_cmd.txData = NULL;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
+    psram_cmd_end(spi_num);
+    return ESP_OK;
+}
+#else /* FAKE_QPI */
+//exit QPI mode(set back to SPI mode)
+static void psram_disable_qio_mode(psram_spi_num_t spi_num)
+{
+    psram_cmd_t ps_cmd;
+    ps_cmd.txData = NULL;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.cmd = PSRAM_EXIT_QMODE;
+    ps_cmd.cmdBitLen = 8;
+    ps_cmd.addr = 0;
+    ps_cmd.addrBitLen = 0;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI);
+    psram_cmd_end(spi_num);
+}
+
+
+//switch psram burst length(32 bytes or 1024 bytes)
+//datasheet says it should be 1024 bytes by default
+static void psram_set_wrap_burst_length(psram_spi_num_t spi_num, psram_cmd_mode_t mode)
+{
+    psram_cmd_t ps_cmd;
+    ps_cmd.cmd = 0xC0;
+    ps_cmd.cmdBitLen = 8;
+    ps_cmd.addr = 0;
+    ps_cmd.addrBitLen = 0;
+    ps_cmd.txData = NULL;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, mode);
+    psram_cmd_end(spi_num);
+}
+
+//send reset command to psram, in spi mode
+static void psram_reset_mode(psram_spi_num_t spi_num)
+{
+    psram_cmd_t ps_cmd;
+    ps_cmd.txData = NULL;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.addr = NULL;
+    ps_cmd.addrBitLen = 0;
+    ps_cmd.cmd = PSRAM_RESET_EN;
+    ps_cmd.cmdBitLen = 8;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
+    psram_cmd_end(spi_num);
+
+    memset(&ps_cmd, 0, sizeof(ps_cmd));
+    ps_cmd.txData = NULL;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.addr = NULL;
+    ps_cmd.addrBitLen = 0;
+    ps_cmd.cmd = PSRAM_RESET;
+    ps_cmd.cmdBitLen = 8;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
+    psram_cmd_end(spi_num);
+}
+
+esp_err_t psram_enable_wrap(uint32_t wrap_size)
+{
+    switch (wrap_size) {
+        case 32:
+            psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI);
+            return ESP_OK;
+        case 16:
+        case 64:
+        default:
+            return ESP_FAIL;
+    }
+}
+
+bool psram_support_wrap_size(uint32_t wrap_size)
+{
+    switch (wrap_size) {
+        case 0:
+        case 32:
+            return true;
+        case 16:
+        case 64:
+        default:
+            return false;
+    }
+
+}
+
+static void psram_read_id(uint32_t* dev_id)
+{
+    psram_spi_num_t spi_num = PSRAM_SPI_1;
+    psram_disable_qio_mode(spi_num);
+    uint32_t dummy_bits = 0;
+    uint32_t addr = 0;
+    psram_cmd_t ps_cmd;
+    switch (s_psram_mode) {
+        case PSRAM_CACHE_F80M_S80M:
+            dummy_bits = 0 + extra_dummy;
+            break;
+        case PSRAM_CACHE_F80M_S40M:
+        case PSRAM_CACHE_F40M_S40M:
+        case PSRAM_CACHE_F26M_S26M:
+        case PSRAM_CACHE_F20M_S20M:
+        default:
+            dummy_bits = 0 + extra_dummy;
+            break;
+    }
+    ps_cmd.cmd = PSRAM_DEVICE_ID;
+    ps_cmd.cmdBitLen = 8;
+    ps_cmd.addr = &addr;
+    ps_cmd.addrBitLen = 24;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.txData = NULL;
+    ps_cmd.rxDataBitLen = 3 * 8;
+    ps_cmd.rxData = dev_id;
+    ps_cmd.dummyBitLen = dummy_bits;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_clear_spi_fifo(spi_num);
+    psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
+    psram_cmd_end(spi_num);
+}
+
+//enter QPI mode
+static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
+{
+    psram_cmd_t ps_cmd;
+    ps_cmd.cmd = PSRAM_ENTER_QMODE;
+    ps_cmd.cmdBitLen = 8;   //this two bits is used to delay 2 clock cycle
+    ps_cmd.addr = NULL;
+    ps_cmd.addrBitLen = 0;
+    ps_cmd.txData = NULL;
+    ps_cmd.txDataBitLen = 0;
+    ps_cmd.rxData = NULL;
+    ps_cmd.rxDataBitLen = 0;
+    ps_cmd.dummyBitLen = 0;
+    psram_cmd_config(spi_num, &ps_cmd);
+    psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
+    psram_cmd_end(spi_num);
+    return ESP_OK;
+}
+#endif /* FAKE_QPI */
+
+//spi param init for psram
+void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
+{
+    uint8_t k;
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP);
+#if 0
+    // SPI_CPOL & SPI_CPHA
+    CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(spi_num), SPI_MEM_CK_IDLE_EDGE);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CK_OUT_EDGE);
+    // SPI bit order
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_WR_BIT_ORDER);
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_RD_BIT_ORDER);
+    // SPI bit order
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_DOUTDIN);
+#endif
+    // May be not must to do.
+    WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), 0);
+#if 0
+    // SPI mode type
+    CLEAR_PERI_REG_MASK(SPI_MEM_SLAVE_REG(spi_num), SPI_MEM_SLAVE_MODE);
+#endif
+    // Set SPI speed for non-80M mode. (80M mode uses APB clock directly.)
+    if (mode!=PSRAM_CACHE_F80M_S80M) {
+        k = 2;      //Main divider. Divide by 2 so we get 40MHz
+         //clear bit 31, set SPI clock div
+        CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
+        WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num),
+                (((k - 1) & SPI_MEM_CLKCNT_N) << SPI_MEM_CLKCNT_N_S) |
+                ((((k + 1) / 2 - 1) & SPI_MEM_CLKCNT_H) << SPI_MEM_CLKCNT_H_S) | //50% duty cycle
+                (((k - 1) & SPI_MEM_CLKCNT_L) << SPI_MEM_CLKCNT_L_S));
+    }
+    // Enable MOSI
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP | SPI_MEM_CS_HOLD | SPI_MEM_USR_MOSI);
+    memset((void*)SPI_MEM_W0_REG(spi_num), 0, 16 * 4);
+}
+
+/*
+ * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
+ * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
+ */
+static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
+{
+    int spi_cache_dummy = 0;
+    uint32_t rd_mode_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
+    if (rd_mode_reg & (SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_DIO_M)) {
+        spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
+    } else if (rd_mode_reg & (SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DUAL_M)) {
+        spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
+    } else {
+        spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
+    }
+    // In bootloader, all the signals are already configured,
+    // We keep the following code in case the bootloader is some older version.
+    gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
+    gpio_matrix_out(PSRAM_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
+    gpio_matrix_in(PSRAM_SPIQ_IO, SPIQ_IN_IDX, 0);
+    gpio_matrix_out(PSRAM_SPID_IO, SPID_OUT_IDX, 0, 0);
+    gpio_matrix_in(PSRAM_SPID_IO, SPID_IN_IDX, 0);
+    gpio_matrix_out(PSRAM_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
+    gpio_matrix_in(PSRAM_SPIWP_IO, SPIWP_IN_IDX, 0);
+    gpio_matrix_out(PSRAM_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
+    gpio_matrix_in(PSRAM_SPIHD_IO, SPIHD_IN_IDX, 0);
+    switch (mode) {
+        case PSRAM_CACHE_F80M_S40M:
+            extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
+            g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
+            g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
+            SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+            esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
+            esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
+            break;
+        case PSRAM_CACHE_F80M_S80M:
+            extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
+#if 0
+            g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
+            g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
+            SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+
+            CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
+            esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
+            CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
+            esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_FLASH_PORT);
+
+#endif
+            break;
+        case PSRAM_CACHE_F40M_S40M:
+            extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
+#if 0
+            g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
+            g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
+            SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_40M, SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+
+            CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
+            esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_CACHE_PORT);
+
+            CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
+            esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
+#endif
+
+            break;
+        case PSRAM_CACHE_F26M_S26M:
+        case PSRAM_CACHE_F20M_S20M:
+            extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
+#if 0
+            g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_20M;
+            g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_20M;
+            SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_20M, SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+
+            CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
+            esp_rom_spiflash_config_clk(_SPI_20M_CLK_DIV, _SPI_CACHE_PORT);
+            CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE);
+            esp_rom_spiflash_config_clk(_SPI_20M_CLK_DIV, _SPI_FLASH_PORT);
+#endif
+
+        default:
+            break;
+    }
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY); // dummy en
+    //select pin function gpio
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIHD_U, PIN_FUNC_GPIO);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIWP_U, PIN_FUNC_GPIO);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, PIN_FUNC_GPIO);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, PIN_FUNC_GPIO);
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, PIN_FUNC_GPIO);
+    // flash clock signal should come from IO MUX.
+    // set drive ability for clock
+    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK);
+}
+
+psram_size_t psram_get_size()
+{
+    if (PSRAM_IS_32MBIT_VER0(s_psram_id)) {
+        return PSRAM_SIZE_32MBITS;
+    } else if (PSRAM_IS_64MBIT(s_psram_id)) {
+        return PSRAM_SIZE_64MBITS;
+    } else {
+        return PSRAM_SIZE_MAX;
+    }
+}
+
+//psram gpio init , different working frequency we have different solutions
+esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)   //psram init
+{
+
+    assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
+    s_psram_mode = mode;
+
+    periph_module_enable(PERIPH_SPI_MODULE);
+#if 0
+    WRITE_PERI_REG(SPI_MEM_EXT3_REG(0), 0x1);
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_PREP_HOLD_M);
+#endif
+
+
+    switch (mode) {
+        case PSRAM_CACHE_F80M_S80M:
+        case PSRAM_CACHE_F80M_S40M:
+        case PSRAM_CACHE_F40M_S40M:
+        case PSRAM_CACHE_F26M_S26M:
+        case PSRAM_CACHE_F20M_S20M:
+        default:
+            psram_spi_init(PSRAM_SPI_1, mode);
+            CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_CS_HOLD);
+            gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
+#ifdef FAKE_QPI
+            /* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
+            We do this by routing it signal to signal 220/221, which are used as a loopback; the extra run through
+            the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
+            silicon) as a temporary pad for this. So the signal path is:
+            SPI CLK --> GPIO28 --> signal220(in then out) --> internal GPIO29 --> signal221(in then out) --> GPIO17(PSRAM CLK)
+            */
+            gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
+            gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC220_IDX, 0);
+            gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC220_IDX, 0, 0);
+            gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC221_IDX, 0);
+            gpio_matrix_out(PSRAM_CLK_IO, SIG_IN_FUNC221_IDX, 0, 0);
+#else
+            REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, 1);
+            REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, 1);
+#endif
+
+            break;
+    }
+
+    #if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
+        // For flash 80Mhz, we must update ldo voltage in case older version of bootloader didn't do this.
+        rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
+        if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {    // VDDSDIO regulator is enabled @ 1.8V
+            cfg.drefh = 3;
+            cfg.drefm = 3;
+            cfg.drefl = 3;
+            cfg.force = 1;
+            rtc_vddsdio_set_config(cfg);
+            ets_delay_us(10);                     // wait for regulator to become stable
+        }
+    #endif
+    CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_CS_SETUP_M);
+    psram_gpio_config(mode);
+    PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], PIN_FUNC_GPIO);
+    psram_read_id(&s_psram_id);
+    if (!PSRAM_IS_VALID(s_psram_id)) {
+        return ESP_FAIL;
+    }
+    uint32_t flash_id = g_rom_flashchip.device_id;
+    if (flash_id == FLASH_ID_GD25LQ32C) {
+        // Set drive ability for 1.8v flash in 80Mhz.
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIHD_U, FUN_DRV, 3, FUN_DRV_S);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIWP_U, FUN_DRV, 3, FUN_DRV_S);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICS0_U, FUN_DRV, 3, FUN_DRV_S);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, 3, FUN_DRV_S);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIQ_U, FUN_DRV, 3, FUN_DRV_S);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPID_U, FUN_DRV, 3, FUN_DRV_S);
+        SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CS_IO], FUN_DRV, 3, FUN_DRV_S);
+    }
+    if (PSRAM_IS_64MBIT(s_psram_id)) {
+        // For this psram, we don't need any extra clock cycles after cs get back to high level
+        s_clk_mode = PSRAM_CLK_MODE_NORM;
+        REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, 0);
+        REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, 0);
+    } else if (PSRAM_IS_32MBIT_VER0(s_psram_id)) {
+        s_clk_mode = PSRAM_CLK_MODE_DCLK;
+        if (mode == PSRAM_CACHE_F80M_S80M) {
+        }
+    }
+    psram_reset_mode(PSRAM_SPI_1);
+    psram_enable_qio_mode(PSRAM_SPI_1);
+    psram_cache_init(mode, vaddrmode);
+    return ESP_OK;
+}
+
+static void IRAM_ATTR psram_clock_set(psram_spi_num_t spi_num, int8_t freqdiv)
+{
+    uint32_t  freqbits;
+    if (1 >= freqdiv) {
+        WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
+    } else {
+        freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
+        WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
+    }
+}
+
+//register initialization for sram cache params and r/w commands
+static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
+{
+    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M);   //enable cache read dummy
+    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
+    SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
+            SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
+    SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
+            SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
+    SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
+            SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
+    SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
+            SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
+    SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
+            SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache :  40m--+1dummy,80m--+2dummy
+
+    switch (psram_cache_mode) {
+        case PSRAM_CACHE_F80M_S80M:
+            psram_clock_set(0, 1);
+            break;
+        case PSRAM_CACHE_F80M_S40M:
+            psram_clock_set(0, 2);
+            break;
+        case PSRAM_CACHE_F26M_S26M:
+            psram_clock_set(0, 3);
+            break;
+        case PSRAM_CACHE_F20M_S20M:
+            psram_clock_set(0, 4);
+            break;
+        case PSRAM_CACHE_F40M_S40M:
+        default:
+            psram_clock_set(0, 2);
+            break;
+    }
+    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M);     // cache write command enable
+    SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S); //write address for cache command.
+    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M);     //enable qio mode for cache command
+    CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M);     //disable dio mode for cache command
+
+    //config sram cache r/w command
+    switch (psram_cache_mode) {
+        case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
+            break;
+        case PSRAM_CACHE_F80M_S40M: //is sram is @40M, need 2 cycles of delay
+        case PSRAM_CACHE_F40M_S40M:
+        case PSRAM_CACHE_F26M_S26M:
+        case PSRAM_CACHE_F20M_S20M:
+        default:
+#ifdef FAKE_QPI
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
+                    SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ_QUAD) << 8),
+                    SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd)
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
+                    SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8),
+                    SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
+#else
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
+                    SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
+                    SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd)
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
+                    SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
+            SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
+                    SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
+#endif
+            break;
+    }
+
+#if !CONFIG_FREERTOS_UNICORE
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
+    if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
+        DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
+        DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
+    } else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
+        DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
+        DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
+    }
+#endif
+
+    Cache_Resume_DCache(0);
+
+    CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
+    if (s_clk_mode == PSRAM_CLK_MODE_NORM) {    //different
+        REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, 0);
+        REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, 0);
+
+        SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD);
+        // Set cs time.
+        SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
+    }
+}
+#endif // CONFIG_SPIRAM_SUPPORT

components/esp32s2beta/spiram_psram.h

@@ -0,0 +1,80 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _PSRAM_H
+#define _PSRAM_H
+#include "soc/spi_mem_reg.h"
+#include "esp_err.h"
+#include "sdkconfig.h"
+
+typedef enum {
+    PSRAM_CACHE_F80M_S40M = 0,
+    PSRAM_CACHE_F80M_S80M,
+    PSRAM_CACHE_F40M_S40M,
+    PSRAM_CACHE_F26M_S26M,
+    PSRAM_CACHE_F20M_S20M,
+    PSRAM_CACHE_MAX,
+} psram_cache_mode_t;
+
+typedef enum {
+    PSRAM_SIZE_32MBITS = 0,
+    PSRAM_SIZE_64MBITS = 1,
+    PSRAM_SIZE_MAX,
+} psram_size_t;
+
+/*
+See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the definitions of these modes.
+
+Important is that NORMAL works with the app CPU cache disabled, but gives huge cache coherency
+issues when both app and pro CPU are enabled. LOWHIGH and EVENODD do not have these coherency
+issues but cannot be used when the app CPU cache is disabled.
+*/
+typedef enum {
+    PSRAM_VADDR_MODE_NORMAL=0, ///< App and pro CPU use their own flash cache for external RAM access
+    PSRAM_VADDR_MODE_LOWHIGH,  ///< App and pro CPU share external RAM caches: pro CPU has low 2M, app CPU has high 2M
+    PSRAM_VADDR_MODE_EVENODD,  ///< App and pro CPU share external RAM caches: pro CPU does even 32yte ranges, app does odd ones.
+} psram_vaddr_mode_t;
+
+/**
+ * @brief get psram size
+ * @return
+ *     - PSRAM_SIZE_MAX if psram not enabled or not valid
+ *     - PSRAM size
+ */
+psram_size_t psram_get_size();
+
+/**
+ * @brief psram cache enable function
+ *
+ * Esp-idf uses this to initialize cache for psram, mapping it into the main memory
+ * address space.
+ *
+ * @param mode       SPI mode to access psram in
+ * @param vaddrmode  Mode the psram cache works in.
+ * @return ESP_OK on success, ESP_ERR_INVALID_STATE when VSPI peripheral is needed but cannot be claimed.
+ */
+esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
+
+typedef enum {
+    SPIRAM_WRAP_MODE_16B,
+    SPIRAM_WRAP_MODE_32B,
+    SPIRAM_WRAP_MODE_64B,
+    SPIRAM_WRAP_MODE_DISABLE
+} spiram_wrap_mode_t;
+
+esp_err_t esp_spiram_wrap_set(spiram_wrap_mode_t mode);
+
+
+#endif

components/esp32s2beta/system_api.c

@@ -0,0 +1,369 @@
+// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <string.h>
+
+#include "esp_system.h"
+#include "esp_attr.h"
+#include "esp_wifi.h"
+#include "esp_private/wifi.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+#include "esp32s2beta/rom/efuse.h"
+#include "esp32s2beta/rom/cache.h"
+#include "esp32s2beta/rom/uart.h"
+#include "soc/dport_reg.h"
+#include "soc/gpio_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/timer_group_reg.h"
+#include "soc/timer_group_struct.h"
+#include "soc/cpu.h"
+#include "soc/rtc.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/xtensa_api.h"
+#include "esp_heap_caps.h"
+#include "soc/syscon_reg.h"
+
+static const char* TAG = "system_api";
+
+static uint8_t base_mac_addr[6] = { 0 };
+
+#define SHUTDOWN_HANDLERS_NO 2
+static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
+
+void system_init()
+{
+}
+
+esp_err_t esp_base_mac_addr_set(uint8_t *mac)
+{
+    if (mac == NULL) {
+        ESP_LOGE(TAG, "Base MAC address is NULL");
+        abort();
+    }
+
+    memcpy(base_mac_addr, mac, 6);
+
+    return ESP_OK;
+}
+
+esp_err_t esp_base_mac_addr_get(uint8_t *mac)
+{
+    uint8_t null_mac[6] = {0};
+
+    if (memcmp(base_mac_addr, null_mac, 6) == 0) {
+        ESP_LOGI(TAG, "Base MAC address is not set, read default base MAC address from BLK0 of EFUSE");
+        return ESP_ERR_INVALID_MAC;
+    }
+
+    memcpy(mac, base_mac_addr, 6);
+
+    return ESP_OK;
+}
+
+esp_err_t esp_efuse_mac_get_custom(uint8_t *mac)
+{
+    return ESP_ERR_NOT_SUPPORTED; // TODO: read from MAC block in efuse
+}
+
+esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
+{
+    uint32_t mac_low;
+    uint32_t mac_high;
+    uint8_t efuse_crc;
+    uint8_t calc_crc;
+
+//   mac_low = REG_READ(EFUSE_BLK0_RDATA1_REG);
+//    mac_high = REG_READ(EFUSE_BLK0_RDATA2_REG);
+   mac_low  = REG_READ(EFUSE_RD_MAC_SPI_8M_0_REG);
+   mac_high = REG_GET_BIT(EFUSE_RD_MAC_SPI_8M_1_REG,EFUSE_MAC_1);
+
+    mac[0] = mac_high >> 8;
+    mac[1] = mac_high;
+    mac[2] = mac_low >> 24;
+    mac[3] = mac_low >> 16;
+    mac[4] = mac_low >> 8;
+    mac[5] = mac_low;
+
+    //efuse_crc = mac_high >> 16;
+
+    //calc_crc = esp_crc8(mac, 6);
+
+    //if (efuse_crc != calc_crc) {
+         // Small range of MAC addresses are accepted even if CRC is invalid.
+         // These addresses are reserved for Espressif internal use.
+    //    if ((mac_high & 0xFFFF) == 0x18fe) {
+    //        if ((mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
+    //            return ESP_OK;
+    //        }
+    //    } else {
+    //        ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
+    //        abort();
+    //    }
+    //}
+    return ESP_OK;
+}
+
+esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default")));
+esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default")));
+
+esp_err_t esp_derive_mac(uint8_t* local_mac, const uint8_t* universal_mac)
+{
+    uint8_t idx;
+
+    if (local_mac == NULL || universal_mac == NULL) {
+        ESP_LOGE(TAG, "mac address param is NULL");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    memcpy(local_mac, universal_mac, 6);
+    for (idx = 0; idx < 64; idx++) {
+        local_mac[0] = universal_mac[0] | 0x02;
+        local_mac[0] ^= idx << 2;
+
+        if (memcmp(local_mac, universal_mac, 6)) {
+            break;
+        }
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type)
+{
+    uint8_t efuse_mac[6];
+
+    if (mac == NULL) {
+        ESP_LOGE(TAG, "mac address param is NULL");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if (type < ESP_MAC_WIFI_STA || type > ESP_MAC_ETH) {
+        ESP_LOGE(TAG, "mac type is incorrect");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    _Static_assert(UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR \
+            || UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR, \
+            "incorrect NUM_MAC_ADDRESS_FROM_EFUSE value");
+
+    if (esp_base_mac_addr_get(efuse_mac) != ESP_OK) {
+        esp_efuse_mac_get_default(efuse_mac);
+    }
+
+    switch (type) {
+    case ESP_MAC_WIFI_STA:
+        memcpy(mac, efuse_mac, 6);
+        break;
+    case ESP_MAC_WIFI_SOFTAP:
+        if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
+            memcpy(mac, efuse_mac, 6);
+            mac[5] += 1;
+        }
+        else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
+            esp_derive_mac(mac, efuse_mac);
+        }
+        break;
+    case ESP_MAC_BT:
+        memcpy(mac, efuse_mac, 6);
+        if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
+            mac[5] += 2;
+        }
+        else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
+            mac[5] += 1;
+        }
+        break;
+    case ESP_MAC_ETH:
+        if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
+            memcpy(mac, efuse_mac, 6);
+            mac[5] += 3;
+        }
+        else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
+            efuse_mac[5] += 1;
+            esp_derive_mac(mac, efuse_mac);
+        }
+        break;
+    default:
+        ESP_LOGW(TAG, "incorrect mac type");
+        break;
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
+{
+     int i;
+     for (i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
+	  if (shutdown_handlers[i] == NULL) {
+	       shutdown_handlers[i] = handler;
+	       return ESP_OK;
+	  }
+     }
+     return ESP_FAIL;
+}
+
+void esp_restart_noos() __attribute__ ((noreturn));
+
+void IRAM_ATTR esp_restart(void)
+{
+     int i;
+     for (i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
+	  if (shutdown_handlers[i]) {
+	       shutdown_handlers[i]();
+	  }
+     }
+
+    // Disable scheduler on this core.
+    vTaskSuspendAll();
+
+    esp_restart_noos();
+}
+
+/* "inner" restart function for after RTOS, interrupts & anything else on this
+ * core are already stopped. Stalls other core, resets hardware,
+ * triggers restart.
+*/
+void IRAM_ATTR esp_restart_noos()
+{
+    // Disable interrupts
+    xt_ints_off(0xFFFFFFFF);
+
+    // Enable RTC watchdog for 1 second
+    REG_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
+    REG_WRITE(RTC_CNTL_WDTCONFIG0_REG,
+            RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M |
+            (RTC_WDT_STG_SEL_RESET_SYSTEM << RTC_CNTL_WDT_STG0_S) |
+            (RTC_WDT_STG_SEL_RESET_RTC << RTC_CNTL_WDT_STG1_S) |
+            (1 << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) |
+            (1 << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) );
+    REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * 1);
+
+    // Reset and stall the other CPU.
+    // CPU must be reset before stalling, in case it was running a s32c1i
+    // instruction. This would cause memory pool to be locked by arbiter
+    // to the stalled CPU, preventing current CPU from accessing this pool.
+    const uint32_t core_id = xPortGetCoreID();
+#if !CONFIG_FREERTOS_UNICORE
+    const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
+    esp_cpu_reset(other_core_id);
+    esp_cpu_stall(other_core_id);
+#endif
+
+    // Other core is now stalled, can access DPORT registers directly
+    esp_dport_access_int_abort();
+
+    // Disable TG0/TG1 watchdogs
+    TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG0.wdt_config0.en = 0;
+    TIMERG0.wdt_wprotect=0;
+    TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG1.wdt_config0.en = 0;
+    TIMERG1.wdt_wprotect=0;
+
+    // Flush any data left in UART FIFOs
+    uart_tx_wait_idle(0);
+    uart_tx_wait_idle(1);
+    // Disable cache
+    Cache_Disable_ICache();
+    Cache_Disable_DCache();
+
+    // 2nd stage bootloader reconfigures SPI flash signals.
+    // Reset them to the defaults expected by ROM.
+    WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
+
+    // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
+    DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
+         DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
+         DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
+         DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
+         DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
+    DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
+
+    // Reset timer/spi/uart
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
+            DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
+    DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
+
+    // Set CPU back to XTAL source, no PLL, same as hard reset
+    rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
+
+#if !CONFIG_FREERTOS_UNICORE
+    // Clear entry point for APP CPU
+    DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
+#endif
+
+    // Reset CPUs
+    if (core_id == 0) {
+        // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
+#if !CONFIG_FREERTOS_UNICORE
+        esp_cpu_reset(1);
+#endif
+        esp_cpu_reset(0);
+    }
+#if !CONFIG_FREERTOS_UNICORE
+      else {
+        // Running on APP CPU: need to reset PRO CPU and unstall it,
+        // then reset APP CPU
+        esp_cpu_reset(0);
+        esp_cpu_unstall(0);
+        esp_cpu_reset(1);
+    }
+#endif
+    while(true) {
+        ;
+    }
+}
+
+void system_restart(void) __attribute__((alias("esp_restart")));
+
+uint32_t esp_get_free_heap_size( void )
+{
+    return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
+}
+
+uint32_t esp_get_minimum_free_heap_size( void )
+{
+    return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
+}
+
+uint32_t system_get_free_heap_size(void) __attribute__((alias("esp_get_free_heap_size")));
+
+const char* system_get_sdk_version(void)
+{
+    return "master";
+}
+
+const char* esp_get_idf_version(void)
+{
+    return IDF_VER;
+}
+
+void esp_chip_info(esp_chip_info_t* out_info)
+{
+    memset(out_info, 0, sizeof(*out_info));
+
+    out_info->model = CHIP_ESP32S2BETA;
+    out_info->cores = 1;
+    out_info->features = CHIP_FEATURE_WIFI_BGN;
+
+    // FIXME: other features?
+}

components/esp32s2beta/task_wdt.c

@@ -0,0 +1,414 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdbool.h>
+#include "sdkconfig.h"
+#include "freertos/FreeRTOSConfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+#include <esp_types.h>
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+#include "esp_attr.h"
+#include "esp_freertos_hooks.h"
+#include "soc/timer_group_struct.h"
+#include "soc/timer_group_reg.h"
+#include "esp_log.h"
+#include "driver/timer.h"
+#include "driver/periph_ctrl.h"
+#include "esp_task_wdt.h"
+
+//Assertion macro where, if 'cond' is false, will exit the critical section and return 'ret'
+#define ASSERT_EXIT_CRIT_RETURN(cond, ret)  ({                              \
+            if(!(cond)){                                                    \
+                portEXIT_CRITICAL(&twdt_spinlock);                          \
+                return ret;                                                 \
+            }                                                               \
+})
+
+//Empty define used in ASSERT_EXIT_CRIT_RETURN macro when returning in void
+#define VOID_RETURN
+
+//Structure used for each subscribed task
+typedef struct twdt_task_t twdt_task_t;
+struct twdt_task_t {
+    TaskHandle_t task_handle;
+    bool has_reset;
+    twdt_task_t *next;
+};
+
+//Structure used to hold run time configuration of the TWDT
+typedef struct twdt_config_t twdt_config_t;
+struct twdt_config_t {
+    twdt_task_t *list;      //Linked list of subscribed tasks
+    uint32_t timeout;       //Timeout period of TWDT
+    bool panic;             //Flag to trigger panic when TWDT times out
+    intr_handle_t intr_handle;
+};
+
+static twdt_config_t *twdt_config = NULL;
+static portMUX_TYPE twdt_spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+/*
+ * Idle hook callback for Idle Tasks to reset the TWDT. This callback will only
+ * be registered to the Idle Hook of a particular core when the corresponding
+ * Idle Task subscribes to the TWDT.
+ */
+static bool idle_hook_cb(void)
+{
+    esp_task_wdt_reset();
+    return true;
+}
+
+/*
+ * Internal function that looks for the target task in the TWDT task list.
+ * Returns the list item if found and returns null if not found. Also checks if
+ * all the other tasks have reset. Should be called within critical.
+ */
+static twdt_task_t *find_task_in_twdt_list(TaskHandle_t handle, bool *all_reset)
+{
+    twdt_task_t *target = NULL;
+    *all_reset = true;
+    for(twdt_task_t *task = twdt_config->list; task != NULL; task = task->next){
+        if(task->task_handle == handle){
+            target = task;   //Get pointer to target task list member
+        }else{
+            if(task->has_reset == false){     //If a task has yet to reset
+                *all_reset = false;
+            }
+        }
+    }
+    return target;
+}
+
+/*
+ * Resets the hardware timer and has_reset flags of each task on the list.
+ * Called within critical
+ */
+static void reset_hw_timer()
+{
+    //All tasks have reset; time to reset the hardware timer.
+    TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG0.wdt_feed=1;
+    TIMERG0.wdt_wprotect=0;
+    //Clear all has_reset flags in list
+    for (twdt_task_t *task = twdt_config->list; task != NULL; task = task->next){
+        task->has_reset=false;
+    }
+}
+
+/*
+ * ISR for when TWDT times out. Checks for which tasks have not reset. Also
+ * triggers panic if configured to do so
+ */
+static void task_wdt_isr(void *arg)
+{
+    portENTER_CRITICAL(&twdt_spinlock);
+    twdt_task_t *twdttask;
+    const char *cpu;
+    //Reset hardware timer so that 2nd stage timeout is not reached (will trigger system reset)
+    TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
+    TIMERG0.wdt_feed=1;
+    TIMERG0.wdt_wprotect=0;
+    //Acknowledge interrupt
+    TIMERG0.int_clr.wdt=1;
+    //We are taking a spinlock while doing I/O (ets_printf) here. Normally, that is a pretty
+    //bad thing, possibly (temporarily) hanging up the 2nd core and stopping FreeRTOS. In this case,
+    //something bad already happened and reporting this is considered more important
+    //than the badness caused by a spinlock here.
+
+    //Return immediately if no tasks have been added to task list
+    ASSERT_EXIT_CRIT_RETURN((twdt_config->list != NULL), VOID_RETURN);
+
+    //Watchdog got triggered because at least one task did not reset in time.
+    ets_printf("Task watchdog got triggered. The following tasks did not reset the watchdog in time:\n");
+    for (twdttask=twdt_config->list; twdttask!=NULL; twdttask=twdttask->next) {
+        if (!twdttask->has_reset) {
+            cpu=xTaskGetAffinity(twdttask->task_handle)==0?DRAM_STR("CPU 0"):DRAM_STR("CPU 1");
+            if (xTaskGetAffinity(twdttask->task_handle)==tskNO_AFFINITY) cpu=DRAM_STR("CPU 0/1");
+            ets_printf(" - %s (%s)\n", pcTaskGetTaskName(twdttask->task_handle), cpu);
+        }
+    }
+    ets_printf(DRAM_STR("Tasks currently running:\n"));
+    for (int x=0; x<portNUM_PROCESSORS; x++) {
+        ets_printf("CPU %d: %s\n", x, pcTaskGetTaskName(xTaskGetCurrentTaskHandleForCPU(x)));
+    }
+
+    if (twdt_config->panic){     //Trigger Panic if configured to do so
+        ets_printf("Aborting.\n");
+        portEXIT_CRITICAL(&twdt_spinlock);
+        abort();
+    }
+
+    portEXIT_CRITICAL(&twdt_spinlock);
+}
+
+/*
+ * Initializes the TWDT by allocating memory for the config data
+ * structure, obtaining the idle task handles/registering idle hooks, and
+ * setting the hardware timer registers. If reconfiguring, it will just modify
+ * wdt_config and reset the hardware timer.
+ */
+esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
+{
+    portENTER_CRITICAL(&twdt_spinlock);
+    if(twdt_config == NULL){        //TWDT not initialized yet
+        //Allocate memory for wdt_config
+        twdt_config = calloc(1, sizeof(twdt_config_t));
+        ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), ESP_ERR_NO_MEM);
+
+        twdt_config->list = NULL;
+        twdt_config->timeout = timeout;
+        twdt_config->panic = panic;
+
+        //Register Interrupt and ISR
+        ESP_ERROR_CHECK(esp_intr_alloc(ETS_TG0_WDT_LEVEL_INTR_SOURCE, 0, task_wdt_isr, NULL, &twdt_config->intr_handle))
+
+        //Configure hardware timer
+        periph_module_enable(PERIPH_TIMG0_MODULE);
+        TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;               //Disable write protection
+        TIMERG0.wdt_config0.sys_reset_length=7;                 //3.2uS
+        TIMERG0.wdt_config0.cpu_reset_length=7;                 //3.2uS
+        TIMERG0.wdt_config0.level_int_en=1;
+        TIMERG0.wdt_config0.stg0=TIMG_WDT_STG_SEL_INT;          //1st stage timeout: interrupt
+        TIMERG0.wdt_config0.stg1=TIMG_WDT_STG_SEL_RESET_SYSTEM; //2nd stage timeout: reset system
+        TIMERG0.wdt_config1.clk_prescale=80*500;                //Prescaler: wdt counts in ticks of 0.5mS
+        TIMERG0.wdt_config2=twdt_config->timeout*2000;      //Set timeout before interrupt
+        TIMERG0.wdt_config3=twdt_config->timeout*4000;      //Set timeout before reset
+        TIMERG0.wdt_config0.en=1;
+        TIMERG0.wdt_feed=1;
+        TIMERG0.wdt_wprotect=0;                         //Enable write protection
+
+    }else{      //twdt_config previously initialized
+        //Reconfigure task wdt
+        twdt_config->panic = panic;
+        twdt_config->timeout = timeout;
+
+        //Reconfigure hardware timer
+        TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;   //Disable write protection
+        TIMERG0.wdt_config0.en=0;                   //Disable timer
+        TIMERG0.wdt_config2=twdt_config->timeout*2000;           //Set timeout before interrupt
+        TIMERG0.wdt_config3=twdt_config->timeout*4000;           //Set timeout before reset
+        TIMERG0.wdt_config0.en=1;                   //Renable timer
+        TIMERG0.wdt_feed=1;                         //Reset timer
+        TIMERG0.wdt_wprotect=0;                     //Enable write protection
+    }
+    portEXIT_CRITICAL(&twdt_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t esp_task_wdt_deinit()
+{
+    portENTER_CRITICAL(&twdt_spinlock);
+    //TWDT must already be initialized
+    ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), ESP_ERR_NOT_FOUND);
+    //Task list must be empty
+    ASSERT_EXIT_CRIT_RETURN((twdt_config->list == NULL), ESP_ERR_INVALID_STATE);
+
+    //Disable hardware timer
+    TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;   //Disable write protection
+    TIMERG0.wdt_config0.en=0;                   //Disable timer
+    TIMERG0.wdt_wprotect=0;                     //Enable write protection
+
+    ESP_ERROR_CHECK(esp_intr_free(twdt_config->intr_handle))  //Unregister interrupt
+    free(twdt_config);                      //Free twdt_config
+    twdt_config = NULL;
+    portEXIT_CRITICAL(&twdt_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t esp_task_wdt_add(TaskHandle_t handle)
+{
+    portENTER_CRITICAL(&twdt_spinlock);
+    //TWDT must already be initialized
+    ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), ESP_ERR_INVALID_STATE);
+
+    twdt_task_t *target_task;
+    bool all_reset;
+    if (handle == NULL){    //Get handle of current task if none is provided
+        handle = xTaskGetCurrentTaskHandle();
+    }
+    //Check if tasks exists in task list, and if all other tasks have reset
+    target_task = find_task_in_twdt_list(handle, &all_reset);
+    //task cannot be already subscribed
+    ASSERT_EXIT_CRIT_RETURN((target_task == NULL), ESP_ERR_INVALID_ARG);
+
+    //Add target task to TWDT task list
+    target_task = calloc(1,sizeof(twdt_task_t));
+    ASSERT_EXIT_CRIT_RETURN((target_task != NULL), ESP_ERR_NO_MEM);
+    target_task->task_handle = handle;
+    target_task->has_reset = true;
+    target_task->next = NULL;
+    if (twdt_config->list == NULL) {    //Adding to empty list
+        twdt_config->list = target_task;
+    } else {    //Adding to tail of list
+        twdt_task_t *task;
+        for (task = twdt_config->list; task->next != NULL; task = task->next){
+            ;   //point task to current tail of TWDT task list
+        }
+        task->next = target_task;
+    }
+
+    //If idle task, register the idle hook callback to appropriate core
+    for(int i = 0; i < portNUM_PROCESSORS; i++){
+        if(handle == xTaskGetIdleTaskHandleForCPU(i)){
+            ESP_ERROR_CHECK(esp_register_freertos_idle_hook_for_cpu(idle_hook_cb, i))
+            break;
+        }
+    }
+
+    if(all_reset){     //Reset hardware timer if all other tasks in list have reset in
+        reset_hw_timer();
+    }
+
+    portEXIT_CRITICAL(&twdt_spinlock);       //Nested critical if Legacy
+    return ESP_OK;
+}
+
+esp_err_t esp_task_wdt_reset()
+{
+    portENTER_CRITICAL(&twdt_spinlock);
+    //TWDT must already be initialized
+    ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), ESP_ERR_INVALID_STATE);
+
+    TaskHandle_t handle = xTaskGetCurrentTaskHandle();
+    twdt_task_t *target_task;
+    bool all_reset;
+
+    //Check if task exists in task list, and if all other tasks have reset
+    target_task = find_task_in_twdt_list(handle, &all_reset);
+    //Return error if trying to reset task that is not on the task list
+    ASSERT_EXIT_CRIT_RETURN((target_task != NULL), ESP_ERR_NOT_FOUND);
+
+    target_task->has_reset = true;    //Reset the task if it's on the task list
+    if(all_reset){     //Reset if all other tasks in list have reset in
+        reset_hw_timer();
+    }
+
+    portEXIT_CRITICAL(&twdt_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t esp_task_wdt_delete(TaskHandle_t handle)
+{
+    if(handle == NULL){
+        handle = xTaskGetCurrentTaskHandle();
+    }
+    portENTER_CRITICAL(&twdt_spinlock);
+    //Return error if twdt has not been initialized
+    ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), ESP_ERR_NOT_FOUND);
+
+    twdt_task_t *target_task;
+    bool all_reset;
+    target_task = find_task_in_twdt_list(handle, &all_reset);
+    //Task doesn't exist on list. Return error
+    ASSERT_EXIT_CRIT_RETURN((target_task != NULL), ESP_ERR_INVALID_ARG);
+
+    if(target_task == twdt_config->list){     //target_task is head of list. Delete
+        twdt_config->list = target_task->next;
+        free(target_task);
+    }else{                                      //target_task not head of list. Delete
+        twdt_task_t *prev;
+        for (prev = twdt_config->list; prev->next != target_task; prev = prev->next){
+            ;   //point prev to task preceding target_task
+        }
+        prev->next = target_task->next;
+        free(target_task);
+    }
+
+    //If idle task, deregister idle hook callback form appropriate core
+    for(int i = 0; i < portNUM_PROCESSORS; i++){
+        if(handle == xTaskGetIdleTaskHandleForCPU(i)){
+            esp_deregister_freertos_idle_hook_for_cpu(idle_hook_cb, i);
+            break;
+        }
+    }
+
+    if(all_reset){     //Reset hardware timer if all remaining tasks have reset
+        reset_hw_timer();
+    }
+
+    portEXIT_CRITICAL(&twdt_spinlock);
+    return ESP_OK;
+}
+
+esp_err_t esp_task_wdt_status(TaskHandle_t handle)
+{
+    if(handle == NULL){
+        handle = xTaskGetCurrentTaskHandle();
+    }
+
+    portENTER_CRITICAL(&twdt_spinlock);
+    //Return if TWDT is not initialized
+    ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), ESP_ERR_INVALID_STATE);
+
+    twdt_task_t *task;
+    for(task = twdt_config->list; task!=NULL; task=task->next){
+        //Return ESP_OK if task is found
+        ASSERT_EXIT_CRIT_RETURN((task->task_handle != handle), ESP_OK);
+    }
+
+    //Task could not be found
+    portEXIT_CRITICAL(&twdt_spinlock);
+    return ESP_ERR_NOT_FOUND;
+}
+
+void esp_task_wdt_feed()
+{
+    portENTER_CRITICAL(&twdt_spinlock);
+    //Return immediately if TWDT has not been initialized
+    ASSERT_EXIT_CRIT_RETURN((twdt_config != NULL), VOID_RETURN);
+
+    //Check if task is on list
+    TaskHandle_t handle = xTaskGetCurrentTaskHandle();
+    bool all_reset;
+    twdt_task_t *target_task = find_task_in_twdt_list(handle, &all_reset);
+
+    //reset the task if it's on the list, then return
+    if(target_task != NULL){
+        target_task->has_reset = true;
+        if(all_reset){
+            reset_hw_timer();       //Reset hardware timer if all other tasks have reset
+        }
+        portEXIT_CRITICAL(&twdt_spinlock);
+        return;
+    }
+
+    //Add task if it's has not on list
+    target_task = calloc(1, sizeof(twdt_task_t));
+    ASSERT_EXIT_CRIT_RETURN((target_task != NULL), VOID_RETURN);   //If calloc failed
+    target_task->task_handle = handle;
+    target_task->has_reset = true;
+    target_task->next = NULL;
+
+    if (twdt_config->list == NULL) {    //Adding to empty list
+        twdt_config->list = target_task;
+    } else {    //Adding to tail of list
+        twdt_task_t *task;
+        for (task = twdt_config->list; task->next != NULL; task = task->next){
+            ;   //point task to current tail of wdt task list
+        }
+        task->next = target_task;
+    }
+
+    portEXIT_CRITICAL(&twdt_spinlock);
+}
+
+

components/esp_wifi/src/phy_init.c

@@ -16,13 +16,10 @@
 #include <stdlib.h>
 #include <string.h>
 #include <stdbool.h>
-
 #include <sys/lock.h>
 
-#include "esp32/rom/ets_sys.h"
-#include "esp32/rom/rtc.h"
 #include "soc/rtc.h"
-
+#include "soc/dport_reg.h"
 #include "esp_err.h"
 #include "esp_phy_init.h"
 #include "esp_system.h"
@@ -30,7 +27,6 @@
 #include "nvs.h"
 #include "nvs_flash.h"
 #include "sdkconfig.h"
-
 #include "freertos/FreeRTOS.h"
 #include "freertos/portmacro.h"
 #include "phy.h"
@@ -39,6 +35,14 @@
 #include "driver/periph_ctrl.h"
 #include "esp_private/wifi.h"
 
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/ets_sys.h"
+#include "esp32/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/rtc.h"
+#endif
+
 extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
 
 static const char* TAG = "phy_init";
@@ -100,7 +104,7 @@ static inline void phy_update_wifi_mac_time(bool en_clock_stopped, int64_t now)
     }
 }
 
-esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, esp_phy_calibration_mode_t mode, 
+esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, esp_phy_calibration_mode_t mode,
                           esp_phy_calibration_data_t* calibration_data, phy_rf_module_t module)
 {
     /* 3 modules may call phy_init: Wi-Fi, BT, Modem Sleep */
@@ -123,9 +127,9 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data, esp_phy_calibrat
     }
     else {
         /* If Wi-Fi, BT all disabled, modem sleep should not take effect;
-         * If either Wi-Fi or BT is enabled, should allow modem sleep requires 
+         * If either Wi-Fi or BT is enabled, should allow modem sleep requires
          * to enter sleep;
-         * If Wi-Fi, BT co-exist, it is disallowed that only one module 
+         * If Wi-Fi, BT co-exist, it is disallowed that only one module
          * support modem sleep, E,g. BT support modem sleep but Wi-Fi not
          * support modem sleep;
          */
@@ -577,7 +581,7 @@ static esp_err_t store_cal_data_to_nvs_handle(nvs_handle_t handle,
     if (err != ESP_OK) {
         ESP_LOGE(TAG, "%s: store calibration nvs commit failed(0x%x)\n", __func__, err);
     }
-    
+
     return err;
 }
 
@@ -585,10 +589,10 @@ static esp_err_t store_cal_data_to_nvs_handle(nvs_handle_t handle,
 static void esp_phy_reduce_tx_power(esp_phy_init_data_t* init_data)
 {
     uint8_t i;
-                                         
+
     for(i = 0; i < PHY_TX_POWER_NUM; i++) {
         // LOWEST_PHY_TX_POWER is the lowest tx power
-        init_data->params[PHY_TX_POWER_OFFSET+i] = PHY_TX_POWER_LOWEST;   
+        init_data->params[PHY_TX_POWER_OFFSET+i] = PHY_TX_POWER_LOWEST;
     }
 }
 #endif

components/mbedtls/port/esp32s2beta/aes.c

@@ -0,0 +1,381 @@
+/**
+ * \brief AES block cipher, ESP32 hardware accelerated version
+ * Based on mbedTLS FIPS-197 compliant version.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  Additions Copyright (C) 2016-2017, Espressif Systems (Shanghai) PTE Ltd
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+/*
+ *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
+ *
+ *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
+ *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
+ */
+#include <string.h>
+#include "mbedtls/aes.h"
+#include "hwcrypto/aes.h"
+#include "soc/dport_reg.h"
+#include "soc/hwcrypto_reg.h"
+#include <sys/lock.h>
+
+#include <freertos/FreeRTOS.h>
+
+#include "soc/cpu.h"
+#include <stdio.h>
+
+#define AES_BLOCK_BYTES 16
+
+/* AES uses a spinlock mux not a lock as the underlying block operation
+   only takes a small number of cycles, much less than using
+   a mutex for this.
+
+   For CBC, CFB, etc. this may mean that interrupts are disabled for a longer
+   period of time for bigger data lengths.
+*/
+static portMUX_TYPE aes_spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+void esp_aes_acquire_hardware( void )
+{
+    /* newlib locks lazy initialize on ESP-IDF */
+    portENTER_CRITICAL(&aes_spinlock);
+
+    /* Enable AES hardware */
+    REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES);
+    /* Clear reset on digital signature unit,
+       otherwise AES unit is held in reset also. */
+    REG_CLR_BIT(DPORT_PERI_RST_EN_REG,
+                DPORT_PERI_EN_AES
+                | DPORT_PERI_EN_DIGITAL_SIGNATURE);
+}
+
+void esp_aes_release_hardware( void )
+{
+    /* Disable AES hardware */
+    REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_AES);
+    /* Don't return other units to reset, as this pulls
+       reset on RSA & SHA units, respectively. */
+    REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES);
+
+    portEXIT_CRITICAL(&aes_spinlock);
+}
+
+void esp_aes_init( esp_aes_context *ctx )
+{
+    bzero( ctx, sizeof( esp_aes_context ) );
+}
+
+void esp_aes_free( esp_aes_context *ctx )
+{
+    if ( ctx == NULL ) {
+        return;
+    }
+
+    bzero( ctx, sizeof( esp_aes_context ) );
+}
+
+/*
+ * AES key schedule (same for encryption or decryption, as hardware handles schedule)
+ *
+ */
+int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits )
+{
+    if (keybits != 128 && keybits != 192 && keybits != 256) {
+        return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
+    }
+    ctx->key_bytes = keybits / 8;
+    memcpy(ctx->key, key, ctx->key_bytes);
+    return 0;
+}
+
+/*
+ * Helper function to copy key from esp_aes_context buffer
+ * to hardware key registers.
+ *
+ * Call only while holding esp_aes_acquire_hardware().
+ */
+static inline void esp_aes_setkey_hardware( esp_aes_context *ctx, int mode)
+{
+    const uint32_t MODE_DECRYPT_BIT = 4;
+    unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT;
+
+    memcpy((uint32_t *)AES_KEY_BASE, ctx->key, ctx->key_bytes);
+    REG_WRITE(AES_MODE_REG, mode_reg_base + ((ctx->key_bytes / 8) - 2));
+}
+
+/* Run a single 16 byte block of AES, using the hardware engine.
+ *
+ * Call only while holding esp_aes_acquire_hardware().
+ */
+static inline void esp_aes_block(const void *input, void *output)
+{
+    memcpy((void *)AES_TEXT_IN_BASE, input, AES_BLOCK_BYTES);
+
+    REG_WRITE(AES_TRIGGER_REG, 1);
+    while (REG_READ(AES_STATE_REG) != 0) { }
+
+    memcpy(output, (void *)AES_TEXT_OUT_BASE, AES_BLOCK_BYTES);
+}
+
+/*
+ * AES-ECB block encryption
+ */
+int esp_internal_aes_encrypt( esp_aes_context *ctx,
+                      const unsigned char input[16],
+                      unsigned char output[16] )
+{
+    esp_aes_acquire_hardware();
+    esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
+    esp_aes_block(input, output);
+    esp_aes_release_hardware();
+    return 0;
+}
+
+void esp_aes_encrypt( esp_aes_context *ctx,
+        const unsigned char input[16],
+        unsigned char output[16] )
+{
+    esp_internal_aes_encrypt(ctx, input, output);
+}
+
+/*
+ * AES-ECB block decryption
+ */
+
+int esp_internal_aes_decrypt( esp_aes_context *ctx,
+                      const unsigned char input[16],
+                      unsigned char output[16] )
+{
+    esp_aes_acquire_hardware();
+    esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT);
+    esp_aes_block(input, output);
+    esp_aes_release_hardware();
+    return 0;
+}
+
+void esp_aes_decrypt( esp_aes_context *ctx,
+                      const unsigned char input[16],
+                      unsigned char output[16] )
+{
+    esp_internal_aes_decrypt(ctx, input, output);
+}
+
+
+/*
+ * AES-ECB block encryption/decryption
+ */
+int esp_aes_crypt_ecb( esp_aes_context *ctx,
+                       int mode,
+                       const unsigned char input[16],
+                       unsigned char output[16] )
+{
+    esp_aes_acquire_hardware();
+    esp_aes_setkey_hardware(ctx, mode);
+    esp_aes_block(input, output);
+    esp_aes_release_hardware();
+
+    return 0;
+}
+
+
+/*
+ * AES-CBC buffer encryption/decryption
+ */
+int esp_aes_crypt_cbc( esp_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    int i;
+    uint32_t *output_words = (uint32_t *)output;
+    const uint32_t *input_words = (const uint32_t *)input;
+    uint32_t *iv_words = (uint32_t *)iv;
+    unsigned char temp[16];
+
+    if ( length % 16 ) {
+        return ( ERR_ESP_AES_INVALID_INPUT_LENGTH );
+    }
+
+    esp_aes_acquire_hardware();
+
+    esp_aes_setkey_hardware(ctx, mode);
+
+    if ( mode == ESP_AES_DECRYPT ) {
+        while ( length > 0 ) {
+            memcpy(temp, input_words, 16);
+            esp_aes_block(input_words, output_words);
+
+            for ( i = 0; i < 4; i++ ) {
+                output_words[i] = output_words[i] ^ iv_words[i];
+            }
+
+            memcpy( iv_words, temp, 16 );
+
+            input_words += 4;
+            output_words += 4;
+            length -= 16;
+        }
+    } else { // ESP_AES_ENCRYPT
+        while ( length > 0 ) {
+
+            for ( i = 0; i < 4; i++ ) {
+                output_words[i] = input_words[i] ^ iv_words[i];
+            }
+
+            esp_aes_block(output_words, output_words);
+            memcpy( iv_words, output_words, 16 );
+
+            input_words  += 4;
+            output_words += 4;
+            length -= 16;
+        }
+    }
+
+    esp_aes_release_hardware();
+
+    return 0;
+}
+
+/*
+ * AES-CFB128 buffer encryption/decryption
+ */
+int esp_aes_crypt_cfb128( esp_aes_context *ctx,
+                          int mode,
+                          size_t length,
+                          size_t *iv_off,
+                          unsigned char iv[16],
+                          const unsigned char *input,
+                          unsigned char *output )
+{
+    int c;
+    size_t n = *iv_off;
+
+    esp_aes_acquire_hardware();
+
+    esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
+
+    if ( mode == ESP_AES_DECRYPT ) {
+        while ( length-- ) {
+            if ( n == 0 ) {
+                esp_aes_block(iv, iv );
+            }
+
+            c = *input++;
+            *output++ = (unsigned char)( c ^ iv[n] );
+            iv[n] = (unsigned char) c;
+
+            n = ( n + 1 ) & 0x0F;
+        }
+    } else {
+        while ( length-- ) {
+            if ( n == 0 ) {
+                esp_aes_block(iv, iv );
+            }
+
+            iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
+
+            n = ( n + 1 ) & 0x0F;
+        }
+    }
+
+    *iv_off = n;
+
+    esp_aes_release_hardware();
+
+    return 0;
+}
+
+/*
+ * AES-CFB8 buffer encryption/decryption
+ */
+int esp_aes_crypt_cfb8( esp_aes_context *ctx,
+                        int mode,
+                        size_t length,
+                        unsigned char iv[16],
+                        const unsigned char *input,
+                        unsigned char *output )
+{
+    unsigned char c;
+    unsigned char ov[17];
+
+    esp_aes_acquire_hardware();
+
+    esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
+
+    while ( length-- ) {
+        memcpy( ov, iv, 16 );
+        esp_aes_block(iv, iv);
+
+        if ( mode == ESP_AES_DECRYPT ) {
+            ov[16] = *input;
+        }
+
+        c = *output++ = (unsigned char)( iv[0] ^ *input++ );
+
+        if ( mode == ESP_AES_ENCRYPT ) {
+            ov[16] = c;
+        }
+
+        memcpy( iv, ov + 1, 16 );
+    }
+
+    esp_aes_release_hardware();
+
+    return 0;
+}
+
+/*
+ * AES-CTR buffer encryption/decryption
+ */
+int esp_aes_crypt_ctr( esp_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    int c, i;
+    size_t n = *nc_off;
+
+    esp_aes_acquire_hardware();
+
+    esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT);
+
+    while ( length-- ) {
+        if ( n == 0 ) {
+            esp_aes_block(nonce_counter, stream_block);
+
+            for ( i = 16; i > 0; i-- )
+                if ( ++nonce_counter[i - 1] != 0 ) {
+                    break;
+                }
+        }
+        c = *input++;
+        *output++ = (unsigned char)( c ^ stream_block[n] );
+
+        n = ( n + 1 ) & 0x0F;
+    }
+
+    *nc_off = n;
+
+    esp_aes_release_hardware();
+
+    return 0;
+}

components/mbedtls/port/esp32s2beta/sha.c

@@ -0,0 +1,184 @@
+/*
+ *  ESP32 hardware accelerated SHA1/256/512 implementation
+ *  based on mbedTLS FIPS-197 compliant version.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+/*
+ *  The SHA-1 standard was published by NIST in 1993.
+ *
+ *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <sys/lock.h>
+#include <byteswap.h>
+#include <assert.h>
+
+#include "hwcrypto/sha.h"
+#include "rom/ets_sys.h"
+#include "soc/dport_reg.h"
+#include "soc/hwcrypto_reg.h"
+
+/* Single lock for SHA engine
+*/
+static _lock_t s_sha_lock;
+
+/* This API was designed for ESP32, which has seperate
+   engines for SHA1,256,512. ESP32C has a single engine.
+*/
+
+/* Return block size (in bytes) for a given SHA type */
+inline static size_t block_length(esp_sha_type type) {
+    switch(type) {
+    case SHA1:
+    case SHA2_224:
+    case SHA2_256:
+        return 64;
+    case SHA2_384:
+    case SHA2_512:
+        return 128;
+    default:
+        return 0;
+    }
+}
+
+/* Return state size (in bytes) for a given SHA type */
+inline static size_t state_length(esp_sha_type type) {
+    switch(type) {
+    case SHA1:
+        return 160/8;
+    case SHA2_224:
+    case SHA2_256:
+        return 256/8;
+    case SHA2_384:
+    case SHA2_512:
+        return 512/8;
+    default:
+        return 0;
+    }
+}
+
+/* Copy words in memory (to/from a memory block), byte swapping as we go. */
+static void memcpy_endianswap(void *to, const void *from, size_t num_bytes)
+{
+    uint32_t *to_words = (uint32_t *)to;
+    const uint32_t *from_words = (const uint32_t *)from;
+    assert(num_bytes % 4 == 0);
+    for (int i = 0; i < num_bytes / 4; i++) {
+        to_words[i] = __bswap_32(from_words[i]);
+    }
+    asm volatile ("memw");
+}
+
+static void memcpy_swapwords(void *to, const void *from, size_t num_bytes)
+{
+    uint32_t *to_words = (uint32_t *)to;
+    const uint32_t *from_words = (const uint32_t *)from;
+    assert(num_bytes % 8 == 0);
+    for (int i = 0; i < num_bytes / 4; i += 2) {
+        to_words[i] = from_words[i+1];
+        to_words[i+1] = from_words[i];
+    }
+    asm volatile ("memw");
+}
+
+static void esp_sha_lock_engine_inner(void);
+
+bool esp_sha_try_lock_engine(esp_sha_type sha_type)
+{
+  if(_lock_try_acquire(&s_sha_lock) != 0) {
+        /* SHA engine is already in use */
+        return false;
+    } else {
+        esp_sha_lock_engine_inner();
+        return true;
+    }
+}
+
+void esp_sha_lock_engine(esp_sha_type sha_type)
+{
+    _lock_acquire(&s_sha_lock);
+    esp_sha_lock_engine_inner();
+}
+
+static void esp_sha_lock_engine_inner(void)
+{
+    ets_sha_enable();
+}
+
+void esp_sha_unlock_engine(esp_sha_type sha_type)
+{
+    ets_sha_disable();
+    _lock_release(&s_sha_lock);
+}
+
+void esp_sha_wait_idle(void)
+{
+    while(DPORT_REG_READ(SHA_BUSY_REG) != 0) { }
+}
+
+void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state)
+{
+    /* engine should be locked */
+    esp_sha_wait_idle();
+    if (sha_type != SHA2_512 && sha_type != SHA2_384) {
+        /* <SHA-512, read out directly */
+        memcpy(digest_state, (void *)SHA_H_BASE, state_length(sha_type));
+    } else {
+        /* SHA-512, read out with each pair of words swapped */
+        memcpy_swapwords(digest_state, (void *)SHA_H_BASE, state_length(sha_type));
+    }
+}
+
+void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block)
+{
+    /* engine should be locked */
+
+    REG_WRITE(SHA_MODE_REG, sha_type);
+
+    /* ESP32C SHA unit can be loaded while previous block is processing */
+    memcpy_endianswap((void *)SHA_M_BASE, data_block, block_length(sha_type));
+
+    esp_sha_wait_idle();
+    if (is_first_block) {
+        REG_WRITE(SHA_START_REG, 1);
+    } else {
+        REG_WRITE(SHA_CONTINUE_REG, 1);
+    }
+
+    /* Note: deliberately not waiting for this operation to complete,
+       as a performance tweak - delay waiting until the next time we need the SHA
+       unit, instead.
+    */
+}
+
+void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output)
+{
+    SHA_CTX ctx;
+
+    esp_sha_lock_engine(sha_type);
+
+    ets_sha_init(&ctx, sha_type);
+    ets_sha_starts(&ctx, 0);
+    ets_sha_update(&ctx, input, ilen, false);
+    ets_sha_finish(&ctx, output);
+
+    esp_sha_unlock_engine(sha_type);
+}

components/mbedtls/port/include/esp32s2beta/aes.h

@@ -0,0 +1,269 @@
+/**
+ * \brief AES block cipher, ESP32 hardware accelerated version
+ * Based on mbedTLS FIPS-197 compliant version.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *
+ */
+
+#ifndef ESP_AES_H
+#define ESP_AES_H
+
+#include "esp_types.h"
+#include "rom/aes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* padlock.c and aesni.c rely on these values! */
+#define ESP_AES_ENCRYPT     1
+#define ESP_AES_DECRYPT     0
+
+#define ERR_ESP_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
+#define ERR_ESP_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
+
+/**
+ * \brief          AES context structure
+ *
+ * \note           buf is able to hold 32 extra bytes, which can be used:
+ *                 - for alignment purposes if VIA padlock is used, and/or
+ *                 - to simplify key expansion in the 256-bit case by
+ *                 generating an extra round key
+ */
+typedef struct {
+    uint8_t key_bytes;
+    uint8_t key[32];
+} esp_aes_context;
+
+/**
+ * \brief Lock access to AES hardware unit
+ *
+ * AES hardware unit can only be used by one
+ * consumer at a time.
+ *
+ * esp_aes_xxx API calls automatically manage locking & unlocking of
+ * hardware, this function is only needed if you want to call
+ * ets_aes_xxx functions directly.
+ */
+void esp_aes_acquire_hardware( void );
+
+/**
+ * \brief Unlock access to AES hardware unit
+ *
+ * esp_aes_xxx API calls automatically manage locking & unlocking of
+ * hardware, this function is only needed if you want to call
+ * ets_aes_xxx functions directly.
+ */
+void esp_aes_release_hardware( void );
+
+/**
+ * \brief          Initialize AES context
+ *
+ * \param ctx      AES context to be initialized
+ */
+void esp_aes_init( esp_aes_context *ctx );
+
+/**
+ * \brief          Clear AES context
+ *
+ * \param ctx      AES context to be cleared
+ */
+void esp_aes_free( esp_aes_context *ctx );
+
+/**
+ * \brief          AES set key schedule (encryption or decryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or ERR_AES_INVALID_KEY_LENGTH
+ */
+int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits );
+
+/**
+ * \brief          AES-ECB block encryption/decryption
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] );
+
+/**
+ * \brief          AES-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or ERR_AES_INVALID_INPUT_LENGTH
+ */
+int esp_aes_crypt_cbc( esp_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+
+/**
+ * \brief          AES-CFB128 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_cfb128( esp_aes_context *ctx,
+                          int mode,
+                          size_t length,
+                          size_t *iv_off,
+                          unsigned char iv[16],
+                          const unsigned char *input,
+                          unsigned char *output );
+
+/**
+ * \brief          AES-CFB8 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_cfb8( esp_aes_context *ctx,
+                        int mode,
+                        size_t length,
+                        unsigned char iv[16],
+                        const unsigned char *input,
+                        unsigned char *output );
+
+/**
+ * \brief               AES-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \param ctx           AES context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_ctr( esp_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+
+/**
+ * \brief           Internal AES block encryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see AES_ENCRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ */
+int esp_internal_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
+
+/** Deprecated, see esp_aes_internal_encrypt */
+void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated));
+
+/**
+ * \brief           Internal AES block decryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see AES_DECRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ */
+int esp_internal_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
+
+/** Deprecated, see esp_aes_internal_decrypt */
+void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes.h */

components/mbedtls/port/include/esp32s2beta/sha.h

@@ -0,0 +1,207 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ESP_SHA_H_
+#define _ESP_SHA_H_
+
+#include "rom/sha.h"
+#include "esp_types.h"
+
+/** @brief Low-level support functions for the hardware SHA engine
+ *
+ * @note If you're looking for a SHA API to use, try mbedtls component
+ * mbedtls/shaXX.h. That API supports hardware acceleration.
+ *
+ * The API in this header provides some building blocks for implementing a
+ * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha().
+ *
+ * Some technical details about the hardware SHA engine:
+ *
+ * - SHA accelerator engine calculates one digest at a time, per SHA
+ *   algorithm type. It initialises and maintains the digest state
+ *   internally. It is possible to read out an in-progress SHA digest
+ *   state, but it is not possible to restore a SHA digest state
+ *   into the engine.
+ *
+ * - The memory block SHA_TEXT_BASE is shared between all SHA digest
+ *   engines, so all engines must be idle before this memory block is
+ *   modified.
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Defined in rom/sha.h */
+typedef SHA_TYPE esp_sha_type;
+
+/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine
+ *
+ * @note For more versatile SHA calculations, where data doesn't need
+ * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The
+ * hardware-accelerated mbedTLS implementation is also faster when
+ * hashing large amounts of data.
+ *
+ * @note It is not necessary to lock any SHA hardware before calling
+ * this function, thread safety is managed internally.
+ *
+ * @note If a TLS connection is open then this function may block
+ * indefinitely waiting for a SHA engine to become available. Use the
+ * mbedTLS SHA API to avoid this problem.
+ *
+ * @param sha_type SHA algorithm to use.
+ *
+ * @param input Input data buffer.
+ *
+ * @param ilen Length of input data in bytes.
+ *
+ * @param output Buffer for output SHA digest. Output is 20 bytes for
+ * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for
+ * sha_type SHA2_384, 64 bytes for sha_type SHA2_512.
+ */
+void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output);
+
+/* @brief Begin to execute a single SHA block operation
+ *
+ * @note This is a piece of a SHA algorithm, rather than an entire SHA
+ * algorithm.
+ *
+ * @note Call esp_sha_try_lock_engine() before calling this
+ * function. Do not call esp_sha_lock_memory_block() beforehand, this
+ * is done inside the function.
+ *
+ * @param sha_type SHA algorithm to use.
+ *
+ * @param data_block Pointer to block of data. Block size is
+ * determined by algorithm (SHA1/SHA2_256 = 64 bytes,
+ * SHA2_384/SHA2_512 = 128 bytes)
+ *
+ * @param is_first_block If this parameter is true, the SHA state will
+ * be initialised (with the initial state of the given SHA algorithm)
+ * before the block is calculated. If false, the existing state of the
+ * SHA engine will be used.
+ *
+ * @return As a performance optimisation, this function returns before
+ * the SHA block operation is complete. Both this function and
+ * esp_sha_read_state() will automatically wait for any previous
+ * operation to complete before they begin. If using the SHA registers
+ * directly in another way, call esp_sha_wait_idle() after calling this
+ * function but before accessing the SHA registers.
+ */
+void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block);
+
+/** @brief Read out the current state of the SHA digest loaded in the engine.
+ *
+ * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm.
+ *
+ * @note Call esp_sha_try_lock_engine() before calling this
+ * function. Do not call esp_sha_lock_memory_block() beforehand, this
+ * is done inside the function.
+ *
+ * If the SHA suffix padding block has been executed already, the
+ * value that is read is the SHA digest (in big endian
+ * format). Otherwise, the value that is read is an interim SHA state.
+ *
+ * @note If sha_type is SHA2_384, only 48 bytes of state will be read.
+ * This is enough for the final SHA2_384 digest, but if you want the
+ * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead.
+ *
+ * @param sha_type SHA algorithm in use.
+ *
+ * @param state Pointer to a memory buffer to hold the SHA state. Size
+ * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512).
+ *
+ */
+void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state);
+
+/**
+ * @brief Obtain exclusive access to a particular SHA engine
+ *
+ * @param sha_type Type of SHA engine to use.
+ *
+ * Blocks until engine is available. Note: Can block indefinitely
+ * while a TLS connection is open, suggest using
+ * esp_sha_try_lock_engine() and failing over to software SHA.
+ */
+void esp_sha_lock_engine(esp_sha_type sha_type);
+
+/**
+ * @brief Try and obtain exclusive access to a particular SHA engine
+ *
+ * @param sha_type Type of SHA engine to use.
+ *
+ * @return Returns true if the SHA engine is locked for exclusive
+ * use. Call esp_sha_unlock_sha_engine() when done.  Returns false if
+ * the SHA engine is already in use, caller should use software SHA
+ * algorithm for this digest.
+ */
+bool esp_sha_try_lock_engine(esp_sha_type sha_type);
+
+/**
+ * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine()
+ *
+ * @param sha_type Type of engine to release.
+ */
+void esp_sha_unlock_engine(esp_sha_type sha_type);
+
+/**
+ * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE
+ *
+ * This memory block is shared across all the SHA algorithm types.
+ *
+ * Caller should have already locked a SHA engine before calling this function.
+ *
+ * Note that it is possible to obtain exclusive access to the memory block even
+ * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle()
+ * to ensure the SHA engine is not reading from the memory block in hardware.
+ *
+ * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally.
+ *
+ * Call esp_sha_unlock_memory_block() when done.
+ */
+void esp_sha_lock_memory_block(void);
+
+/**
+ * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE
+ *
+ * Caller should have already locked a SHA engine before calling this function.
+ *
+ * Call following esp_sha_lock_memory_block().
+ */
+void esp_sha_unlock_memory_block(void);
+
+/** @brief Wait for the SHA engine to finish any current operation
+ *
+ * @note This function does not ensure exclusive access to any SHA
+ * engine. Caller should use esp_sha_try_lock_engine() and
+ * esp_sha_lock_memory_block() as required.
+ *
+ * @note Functions declared in this header file wait for SHA engine
+ * completion automatically, so you don't need to use this API for
+ * these. However if accessing SHA registers directly, you will need
+ * to call this before accessing SHA registers if using the
+ * esp_sha_block() function.
+ *
+ * @note This function busy-waits, so wastes CPU resources.
+ * Best to delay calling until you are about to need it.
+ *
+ */
+void esp_sha_wait_idle(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

components/xtensa/esp32s2beta/include/xtensa/config/core-isa.h

@@ -0,0 +1,712 @@
+/* 
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ *				processor CORE configuration
+ *
+ *  See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+   Copyright (c) 1999-2018 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		0	/* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE		0	/* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE            0	/* L32EX/S32EX instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
+#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
+#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
+
+#define XCHAL_HAVE_FUSION		0	/* Fusion*/
+#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI		0	
+
+
+
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU		0       /* user SP floating-point pkg */
+#define XCHAL_HAVE_FP			0	/* single prec floating point */
+#define XCHAL_HAVE_FP_DIV		0	/* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP		0	/* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT		0	/* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT		0	/* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+
+#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
+#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
+#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
+#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
+#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
+#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
+
+#define XCHAL_HAVE_PDX			0    /* PDX */
+#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
+#define XCHAL_HAVE_PDX4			0    /* PDX4 */
+#define XCHAL_HAVE_PDX8			0    /* PDX8 */
+#define XCHAL_HAVE_PDX16		0    /* PDX16 */
+
+#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BBENEP_SP_VFPU	0      /* sp_vfpu option on BBE-EP */
+#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
+
+#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
+#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
+#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, or P3 */
+#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
+#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6 */
+
+#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
+						   (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL	0	/* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT	0	/* funct. unit clock gating */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	0	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	0	/* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW		1	/* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW	1	/* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION		1200008	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"test_0731_1_TIE_GPIO_f"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID		0x00075F76	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC2ECFAFE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x22075F76	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX7.0.8"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2700	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		8	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		270008	/* major*100+minor */
+#define XCHAL_HW_REL_LX7		1
+#define XCHAL_HW_REL_LX7_0		1
+#define XCHAL_HW_REL_LX7_0_8		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2700	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	8	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		270008	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2700	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	8	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		270008	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST		0	/* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST		0	/* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
+
+#define XCHAL_HAVE_AXI			0	/* AXI bus */
+#define XCHAL_HAVE_AXI_ECC		0	/* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
+
+#define XCHAL_HAVE_PIF_WR_RESP			0	/* pif write response */
+#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		0
+#define XCHAL_DCACHE_SETWIDTH		0
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		1
+#define XCHAL_DCACHE_WAYS		1
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	0
+#define XCHAL_DCACHE_LINE_LOCKABLE	0
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Cache access size in bytes (affects operation of SICW instruction):  */
+#define XCHAL_ICACHE_ACCESS_SIZE	1
+#define XCHAL_DCACHE_ACCESS_SIZE	1
+
+#define XCHAL_DCACHE_BANKS		0	/* number of banks */
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
+
+/*  Instruction ROM 0:  */
+#define XCHAL_INSTROM0_VADDR		0x40800000	/* virtual address */
+#define XCHAL_INSTROM0_PADDR		0x40800000	/* physical address */
+#define XCHAL_INSTROM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Instruction RAM 0:  */
+#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
+#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
+#define XCHAL_INSTRAM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0		1
+#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
+
+/*  Instruction RAM 1:  */
+#define XCHAL_INSTRAM1_VADDR		0x40400000	/* virtual address */
+#define XCHAL_INSTRAM1_PADDR		0x40400000	/* physical address */
+#define XCHAL_INSTRAM1_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM1		1
+#define XCHAL_INSTRAM1_HAVE_IDMA	0	/* idma supported by this local memory */
+
+/*  Data ROM 0:  */
+#define XCHAL_DATAROM0_VADDR		0x3F400000	/* virtual address */
+#define XCHAL_DATAROM0_PADDR		0x3F400000	/* physical address */
+#define XCHAL_DATAROM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_DATAROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATAROM0_BANKS		1	/* number of banks */
+
+/*  Data RAM 0:  */
+#define XCHAL_DATARAM0_VADDR		0x3FF80000	/* virtual address */
+#define XCHAL_DATARAM0_PADDR		0x3FF80000	/* physical address */
+#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
+#define XCHAL_HAVE_DATARAM0		1
+#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
+
+/*  Data RAM 1:  */
+#define XCHAL_DATARAM1_VADDR		0x3F800000	/* virtual address */
+#define XCHAL_DATARAM1_PADDR		0x3F800000	/* physical address */
+#define XCHAL_DATARAM1_SIZE		4194304	/* size in bytes */
+#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM1_BANKS		1	/* number of banks */
+#define XCHAL_HAVE_DATARAM1		1
+#define XCHAL_DATARAM1_HAVE_IDMA	0	/* idma supported by this local memory */
+
+/*  XLMI Port 0:  */
+#define XCHAL_XLMI0_VADDR		0x3FE00000	/* virtual address */
+#define XCHAL_XLMI0_PADDR		0x3FE00000	/* physical address */
+#define XCHAL_XLMI0_SIZE		1048576	/* size in bytes */
+#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+#define XCHAL_HAVE_IDMA			0
+#define XCHAL_HAVE_IDMA_TRANSPOSE	0
+
+#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x000637FF
+#define XCHAL_INTLEVEL2_MASK		0x00380000
+#define XCHAL_INTLEVEL3_MASK		0x28C08800
+#define XCHAL_INTLEVEL4_MASK		0x53000000
+#define XCHAL_INTLEVEL5_MASK		0x84010000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000637FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x003E37FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x28FEBFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x7BFEBFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFFFFBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		1
+#define XCHAL_INT9_LEVEL		1
+#define XCHAL_INT10_LEVEL		1
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		1
+#define XCHAL_INT13_LEVEL		1
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		3
+#define XCHAL_INT16_LEVEL		5
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		2
+#define XCHAL_INT20_LEVEL		2
+#define XCHAL_INT21_LEVEL		2
+#define XCHAL_INT22_LEVEL		3
+#define XCHAL_INT23_LEVEL		3
+#define XCHAL_INT24_LEVEL		4
+#define XCHAL_INT25_LEVEL		4
+#define XCHAL_INT26_LEVEL		5
+#define XCHAL_INT27_LEVEL		3
+#define XCHAL_INT28_LEVEL		4
+#define XCHAL_INT29_LEVEL		3
+#define XCHAL_INT30_LEVEL		4
+#define XCHAL_INT31_LEVEL		5
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_PROFILING
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x20000080
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x50400400
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x8FBE333F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00018040
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING	0x00000800
+#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
+#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		15	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		16	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+#define XCHAL_PROFILING_INTERRUPT	11
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 2, 3, 4, 5.)  */
+
+
+/*
+ *  External interrupt mapping.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
+#define XCHAL_EXTINT9_NUM		12	/* (intlevel 1) */
+#define XCHAL_EXTINT10_NUM		13	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 2) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 2) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 2) */
+#define XCHAL_EXTINT17_NUM		22	/* (intlevel 3) */
+#define XCHAL_EXTINT18_NUM		23	/* (intlevel 3) */
+#define XCHAL_EXTINT19_NUM		24	/* (intlevel 4) */
+#define XCHAL_EXTINT20_NUM		25	/* (intlevel 4) */
+#define XCHAL_EXTINT21_NUM		26	/* (intlevel 5) */
+#define XCHAL_EXTINT22_NUM		27	/* (intlevel 3) */
+#define XCHAL_EXTINT23_NUM		28	/* (intlevel 4) */
+#define XCHAL_EXTINT24_NUM		30	/* (intlevel 4) */
+#define XCHAL_EXTINT25_NUM		31	/* (intlevel 5) */
+/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
+#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM		6	/* (intlevel 1) */
+#define XCHAL_INT9_EXTNUM		7	/* (intlevel 1) */
+#define XCHAL_INT10_EXTNUM		8	/* (intlevel 1) */
+#define XCHAL_INT12_EXTNUM		9	/* (intlevel 1) */
+#define XCHAL_INT13_EXTNUM		10	/* (intlevel 1) */
+#define XCHAL_INT14_EXTNUM		11	/* (intlevel 7) */
+#define XCHAL_INT17_EXTNUM		12	/* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM		13	/* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM		14	/* (intlevel 2) */
+#define XCHAL_INT20_EXTNUM		15	/* (intlevel 2) */
+#define XCHAL_INT21_EXTNUM		16	/* (intlevel 2) */
+#define XCHAL_INT22_EXTNUM		17	/* (intlevel 3) */
+#define XCHAL_INT23_EXTNUM		18	/* (intlevel 3) */
+#define XCHAL_INT24_EXTNUM		19	/* (intlevel 4) */
+#define XCHAL_INT25_EXTNUM		20	/* (intlevel 4) */
+#define XCHAL_INT26_EXTNUM		21	/* (intlevel 5) */
+#define XCHAL_INT27_EXTNUM		22	/* (intlevel 3) */
+#define XCHAL_INT28_EXTNUM		23	/* (intlevel 4) */
+#define XCHAL_INT30_EXTNUM		24	/* (intlevel 4) */
+#define XCHAL_INT31_EXTNUM		25	/* (intlevel 5) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_HALT			0	/* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR	0x40000400
+#define XCHAL_RESET_VECTOR_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR_PADDR	0x40000400
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0x40000340
+#define XCHAL_USER_VECTOR_PADDR		0x40000340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0x40000300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x40000300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x400003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x400003C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0x40000000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x40000000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x400001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x400001C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x40000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x40000200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x40000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x40000240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x40000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x40000280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0x400002C0
+#define XCHAL_NMI_VECTOR_PADDR		0x400002C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG MODULE
+  ----------------------------------------------------------------------*/
+
+/*  Misc  */
+#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
+
+/*  On-Chip Debug (OCD)  */
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
+
+/*  TRAX (in core)  */
+#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE		16384	/* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
+
+/*  Perf counters  */
+#define XCHAL_NUM_PERF_COUNTERS		2	/* performance counters */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+
+/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
+
+#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
+
+/*----------------------------------------------------------------------
+				MPU
+  ----------------------------------------------------------------------*/
+#define XCHAL_HAVE_MPU			0 
+#define XCHAL_MPU_ENTRIES		0
+
+#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES	0	/* number of entries in bg map*/
+#define XCHAL_MPU_BG_CACHEADRDIS	0	/* default CACHEADRDIS for bg */
+ 
+#define XCHAL_MPU_ALIGN_BITS		0
+#define XCHAL_MPU_ALIGN			0
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+

components/xtensa/esp32s2beta/include/xtensa/config/core-matmap.h

@@ -0,0 +1,322 @@
+/* 
+ * xtensa/config/core-matmap.h -- Memory access and translation mapping
+ *	parameters (CHAL) of the Xtensa processor core configuration.
+ *
+ *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
+ *  this file) for more details.
+ *
+ *  In the Xtensa processor products released to date, all parameters
+ *  defined in this file are derivable (at least in theory) from
+ *  information contained in the core-isa.h header file.
+ *  In particular, the following core configuration parameters are relevant:
+ *	XCHAL_HAVE_CACHEATTR
+ *	XCHAL_HAVE_MIMIC_CACHEATTR
+ *	XCHAL_HAVE_XLT_CACHEATTR
+ *	XCHAL_HAVE_PTP_MMU
+ *	XCHAL_ITLB_ARF_ENTRIES_LOG2
+ *	XCHAL_DTLB_ARF_ENTRIES_LOG2
+ *	XCHAL_DCACHE_IS_WRITEBACK
+ *	XCHAL_ICACHE_SIZE		(presence of I-cache)
+ *	XCHAL_DCACHE_SIZE		(presence of D-cache)
+ *	XCHAL_HW_VERSION_MAJOR
+ *	XCHAL_HW_VERSION_MINOR
+ */
+
+/* Copyright (c) 1999-2018 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+
+#ifndef XTENSA_CONFIG_CORE_MATMAP_H
+#define XTENSA_CONFIG_CORE_MATMAP_H
+
+
+/*----------------------------------------------------------------------
+			CACHE (MEMORY ACCESS) ATTRIBUTES
+  ----------------------------------------------------------------------*/
+
+
+
+/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
+#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION
+#define XCHAL_LCA_LIST		XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION
+#define XCHAL_SCA_LIST		XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION
+
+#define XCHAL_CA_R   (0xC0 | 0x40000000)
+#define XCHAL_CA_RX  (0xD0 | 0x40000000)
+#define XCHAL_CA_RW  (0xE0 | 0x40000000)
+#define XCHAL_CA_RWX (0xF0 | 0x40000000)
+
+/*
+ *  Specific encoded cache attribute values of general interest.
+ *  If a specific cache mode is not available, the closest available
+ *  one is returned instead (eg. writethru instead of writeback,
+ *  bypass instead of writethru).
+ */
+#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
+#define XCHAL_CA_BYPASSBUF  		6	/* cache disabled (bypassed) bufferable mode */
+#define XCHAL_CA_WRITETHRU		1	/* cache enabled (write-through) mode */
+#define XCHAL_CA_WRITEBACK		2	/* cache enabled (write-back) mode */
+#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC	0	/* write-back no-allocate availability */
+#define XCHAL_CA_WRITEBACK_NOALLOC	2	/* cache enabled (write-back no-allocate) mode */
+#define XCHAL_CA_BYPASS_RW  		0	/* cache disabled (bypassed) mode (no exec) */
+#define XCHAL_CA_WRITETHRU_RW		0	/* cache enabled (write-through) mode (no exec) (FALLBACK) */
+#define XCHAL_CA_WRITEBACK_RW		0	/* cache enabled (write-back) mode (no exec) */
+#define XCHAL_CA_WRITEBACK_NOALLOC_RW	0	/* cache enabled (write-back no-allocate) mode (no exec) */
+#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
+#define XCHAL_CA_ISOLATE		0	/* cache isolate (accesses go to cache not memory) mode */
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*
+ *  General notes on MMU parameters.
+ *
+ *  Terminology:
+ *	ASID = address-space ID (acts as an "extension" of virtual addresses)
+ *	VPN  = virtual page number
+ *	PPN  = physical page number
+ *	CA   = encoded cache attribute (access modes)
+ *	TLB  = translation look-aside buffer (term is stretched somewhat here)
+ *	I    = instruction (fetch accesses)
+ *	D    = data (load and store accesses)
+ *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
+ *		that simultaneously match the virtual address of an access;
+ *		a TLB successfully translates a virtual address if exactly
+ *		one way matches the vaddr; if none match, it is a miss;
+ *		if multiple match, one gets a "multihit" exception;
+ *		each way can be independently configured in terms of number of
+ *		entries, page sizes, which fields are writable or constant, etc.
+ *	set  = group of contiguous ways with exactly identical parameters
+ *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
+ *		from the page table and storing it in one of the auto-refill ways;
+ *		if this PTE load also misses, a miss exception is posted for s/w.
+ *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ * 		page arbitrarily under program control; it has a single entry,
+ *		is non-auto-refill (some other way(s) must be auto-refill),
+ *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ *		restriction is that this be the only page size it supports).
+ *
+ *  TLB way entries are virtually indexed.
+ *  TLB ways that support multiple page sizes:
+ *	- must have all writable VPN and PPN fields;
+ *	- can only use one page size at any given time (eg. setup at startup),
+ *	  selected by the respective ITLBCFG or DTLBCFG special register,
+ *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ *	  this list may be sparse for auto-refill ways because auto-refill
+ *	  ways have independent lists of supported page sizes sharing a
+ *	  common encoding with PTE entries; the encoding is the index into
+ *	  this list; unsupported sizes for a given way are zero in the list;
+ *	  selecting unsupported sizes results in undefine hardware behaviour;
+ *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
+#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
+#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
+#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
+#define XCHAL_MMU_CA_BITS		4	 /* number of bits needed to hold cache attribute encoding */
+#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
+#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
+
+
+/***  Instruction TLB:  ***/
+
+#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
+#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
+#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
+#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_ITLB_WAY0_SET		0
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
+
+
+/*  ITLB way set 0 (group of ways 0 thru 0):  */
+#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
+#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
+							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
+#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
+#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
+#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
+#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
+#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
+#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
+#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
+/*  Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_PPN_CONST		0x00000000
+#define XCHAL_ITLB_SET0_E1_PPN_CONST		0x20000000
+#define XCHAL_ITLB_SET0_E2_PPN_CONST		0x40000000
+#define XCHAL_ITLB_SET0_E3_PPN_CONST		0x60000000
+#define XCHAL_ITLB_SET0_E4_PPN_CONST		0x80000000
+#define XCHAL_ITLB_SET0_E5_PPN_CONST		0xA0000000
+#define XCHAL_ITLB_SET0_E6_PPN_CONST		0xC0000000
+#define XCHAL_ITLB_SET0_E7_PPN_CONST		0xE0000000
+/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
+
+
+/***  Data TLB:  ***/
+
+#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
+#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
+#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
+#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_DTLB_WAY0_SET		0
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
+
+
+/*  DTLB way set 0 (group of ways 0 thru 0):  */
+#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
+#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
+							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
+#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
+#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
+#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
+#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
+#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
+#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
+#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
+/*  Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_PPN_CONST		0x00000000
+#define XCHAL_DTLB_SET0_E1_PPN_CONST		0x20000000
+#define XCHAL_DTLB_SET0_E2_PPN_CONST		0x40000000
+#define XCHAL_DTLB_SET0_E3_PPN_CONST		0x60000000
+#define XCHAL_DTLB_SET0_E4_PPN_CONST		0x80000000
+#define XCHAL_DTLB_SET0_E5_PPN_CONST		0xA0000000
+#define XCHAL_DTLB_SET0_E6_PPN_CONST		0xC0000000
+#define XCHAL_DTLB_SET0_E7_PPN_CONST		0xE0000000
+/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
+
+
+
+
+#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
+

components/xtensa/esp32s2beta/include/xtensa/config/defs.h

@@ -0,0 +1,37 @@
+/* Definitions for Xtensa instructions, types, and protos. */
+
+/* Copyright (c) 2003-2004 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+/* NOTE: This file exists only for backward compatibility with T1050
+   and earlier Xtensa releases.  It includes only a subset of the
+   available header files.  */
+
+#ifndef _XTENSA_BASE_HEADER
+#define _XTENSA_BASE_HEADER
+
+#ifdef __XTENSA__
+
+#include <xtensa/tie/xt_core.h>
+#include <xtensa/tie/xt_misc.h>
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_BASE_HEADER */

components/xtensa/esp32s2beta/include/xtensa/config/specreg.h

@@ -0,0 +1,103 @@
+/*
+ * Xtensa Special Register symbolic names
+ */
+
+/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
+
+/* Copyright (c) 1998-2002 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef XTENSA_SPECREG_H
+#define XTENSA_SPECREG_H
+
+/*  Include these special register bitfield definitions, for historical reasons:  */
+#include <xtensa/corebits.h>
+
+
+/*  Special registers:  */
+#define SAR		3
+#define WINDOWBASE	72
+#define WINDOWSTART	73
+#define IBREAKENABLE	96
+#define DDR		104
+#define IBREAKA_0	128
+#define IBREAKA_1	129
+#define DBREAKA_0	144
+#define DBREAKA_1	145
+#define DBREAKC_0	160
+#define DBREAKC_1	161
+#define EPC_1		177
+#define EPC_2		178
+#define EPC_3		179
+#define EPC_4		180
+#define EPC_5		181
+#define EPC_6		182
+#define EPC_7		183
+#define DEPC		192
+#define EPS_2		194
+#define EPS_3		195
+#define EPS_4		196
+#define EPS_5		197
+#define EPS_6		198
+#define EPS_7		199
+#define EXCSAVE_1	209
+#define EXCSAVE_2	210
+#define EXCSAVE_3	211
+#define EXCSAVE_4	212
+#define EXCSAVE_5	213
+#define EXCSAVE_6	214
+#define EXCSAVE_7	215
+#define CPENABLE	224
+#define INTERRUPT	226
+#define INTENABLE	228
+#define PS		230
+#define VECBASE		231
+#define EXCCAUSE	232
+#define DEBUGCAUSE	233
+#define CCOUNT		234
+#define PRID		235
+#define ICOUNT		236
+#define ICOUNTLEVEL	237
+#define EXCVADDR	238
+#define CCOMPARE_0	240
+#define CCOMPARE_1	241
+#define CCOMPARE_2	242
+#define MISC_REG_0	244
+#define MISC_REG_1	245
+#define MISC_REG_2	246
+#define MISC_REG_3	247
+
+/*  Special cases (bases of special register series):  */
+#define IBREAKA		128
+#define DBREAKA		144
+#define DBREAKC		160
+#define EPC		176
+#define EPS		192
+#define EXCSAVE		208
+#define CCOMPARE	240
+
+/*  Special names for read-only and write-only interrupt registers:  */
+#define INTREAD		226
+#define INTSET		226
+#define INTCLEAR	227
+
+#endif /* XTENSA_SPECREG_H */
+

components/xtensa/esp32s2beta/include/xtensa/config/system.h

@@ -0,0 +1,277 @@
+/* 
+ * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
+ *
+ *  NOTE: The location and contents of this file are highly subject to change.
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  The HAL itself has historically included this file in some instances,
+ *  but this is not appropriate either, because the HAL is meant to be
+ *  core-specific but system independent.
+ */
+
+/* Copyright (c) 2000-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+
+#ifndef XTENSA_CONFIG_SYSTEM_H
+#define XTENSA_CONFIG_SYSTEM_H
+
+/*#include <xtensa/hal.h>*/
+
+
+
+/*----------------------------------------------------------------------
+				CONFIGURED SOFTWARE OPTIONS
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
+#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
+
+#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
+/*  The above maps to one of the following constants:  */
+#define XTHAL_ABI_WINDOWED		0
+#define XTHAL_ABI_CALL0			1
+/*  Alternatives:  */
+/*#define XSHAL_WINDOWED_ABI		1*/	/* set if windowed ABI selected */
+/*#define XSHAL_CALL0_ABI		0*/	/* set if call0 ABI selected */
+
+#define XSHAL_CLIB			XTHAL_CLIB_NEWLIB	/* (sw-only option, selected C library) */
+/*  The above maps to one of the following constants:  */
+#define XTHAL_CLIB_NEWLIB		0
+#define XTHAL_CLIB_UCLIBC		1
+#define XTHAL_CLIB_XCLIB		2
+/*  Alternatives:  */
+/*#define XSHAL_NEWLIB			1*/	/* set if newlib C library selected */
+/*#define XSHAL_UCLIBC			0*/	/* set if uCLibC C library selected */
+/*#define XSHAL_XCLIB			0*/	/* set if Xtensa C library selected */
+
+#define XSHAL_USE_FLOATING_POINT	1
+
+#define XSHAL_FLOATING_POINT_ABI	0
+
+/*  SW workarounds enabled for HW errata:  */
+
+/*  SW options for functional safety:  */
+#define XSHAL_FUNC_SAFETY_ENABLED	0
+
+/*----------------------------------------------------------------------
+				DEVICE ADDRESSES
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Strange place to find these, but the configuration GUI
+ *  allows moving these around to account for various core
+ *  configurations.  Specific boards (and their BSP software)
+ *  will have specific meanings for these components.
+ */
+
+/*  I/O Block areas:  */
+#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
+#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
+#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
+
+#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
+#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
+#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
+
+/*  System ROM:  */
+#define XSHAL_ROM_VADDR		0x50000000
+#define XSHAL_ROM_PADDR		0x50000000
+#define XSHAL_ROM_SIZE		0x01000000
+/*  Largest available area (free of vectors):  */
+#define XSHAL_ROM_AVAIL_VADDR	0x50000000
+#define XSHAL_ROM_AVAIL_VSIZE	0x01000000
+
+/*  System RAM:  */
+#define XSHAL_RAM_VADDR		0x60000000
+#define XSHAL_RAM_PADDR		0x60000000
+#define XSHAL_RAM_VSIZE		0x20000000
+#define XSHAL_RAM_PSIZE		0x20000000
+#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
+/*  Largest available area (free of vectors):  */
+#define XSHAL_RAM_AVAIL_VADDR	0x60000000
+#define XSHAL_RAM_AVAIL_VSIZE	0x20000000
+
+/*
+ *  Shadow system RAM (same device as system RAM, at different address).
+ *  (Emulation boards need this for the SONIC Ethernet driver
+ *   when data caches are configured for writeback mode.)
+ *  NOTE: on full MMU configs, this points to the BYPASS virtual address
+ *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
+ *  addresses are viewed through the BYPASS static map rather than
+ *  the CACHED static map.
+ */
+#define XSHAL_RAM_BYPASS_VADDR		0xA0000000
+#define XSHAL_RAM_BYPASS_PADDR		0xA0000000
+#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
+
+/*  Alternate system RAM (different device than system RAM):  */
+/*#define XSHAL_ALTRAM_[VP]ADDR		...not configured...*/
+/*#define XSHAL_ALTRAM_SIZE		...not configured...*/
+
+/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
+#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
+#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
+#define XSHAL_SIMIO_PADDR		0xC0000000
+#define XSHAL_SIMIO_SIZE		0x20000000
+
+
+/*----------------------------------------------------------------------
+ *  For use by reference testbench exit and diagnostic routines.
+ */
+#define XSHAL_MAGIC_EXIT		0x0
+
+/*----------------------------------------------------------------------
+ *			DEVICE-ADDRESS DEPENDENT...
+ *
+ *  Values written to CACHEATTR special register (or its equivalent)
+ *  to enable and disable caches in various modes.
+ *----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------
+			BACKWARD COMPATIBILITY ...
+  ----------------------------------------------------------------------*/
+
+/*
+ *  NOTE:  the following two macros are DEPRECATED.  Use the latter
+ *  board-specific macros instead, which are specially tuned for the
+ *  particular target environments' memory maps.
+ */
+#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
+#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
+
+/*----------------------------------------------------------------------
+				GENERIC
+  ----------------------------------------------------------------------*/
+
+/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
+ *  system (PIF) ROM, local memory, or XLMI.  */
+
+/*  These set any unused 512MB region to cache-BYPASS attribute:  */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22221112	/* enable caches in write-back mode */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22221112	/* enable caches in write-allocate mode */
+#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22221112	/* enable caches in write-through mode */
+#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
+#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*  These set any unused 512MB region to ILLEGAL attribute:  */
+#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFFFF111F	/* enable caches in write-back mode */
+#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFFFF111F	/* enable caches in write-allocate mode */
+#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFFFF111F	/* enable caches in write-through mode */
+#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFFFF222F	/* disable caches in bypass mode */
+#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
+ *  NULL-pointer dereference bugs; all other unused 512MB regions are set
+ *  to cache-BYPASS attribute:  */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2222111F	/* enable caches in write-back mode */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2222111F	/* enable caches in write-allocate mode */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2222111F	/* enable caches in write-through mode */
+#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
+#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*----------------------------------------------------------------------
+			ISS (Instruction Set Simulator) SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+/*  For now, ISS defaults to the TRAPNULL settings:  */
+#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
+#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
+#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
+#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
+#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
+
+#define XSHAL_ISS_PIPE_REGIONS	0
+#define XSHAL_ISS_SDRAM_REGIONS	0
+
+
+/*----------------------------------------------------------------------
+			XT2000 BOARD SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+/*  For the following, a 512MB region is used if it contains any system RAM,
+ *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
+ *  Regions containing devices are forced to cache-BYPASS mode regardless
+ *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
+
+/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
+#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xFF22111F	/* enable caches in write-back mode */
+#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xFF22111F	/* enable caches in write-allocate mode */
+#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xFF22111F	/* enable caches in write-through mode */
+#define XSHAL_XT2000_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
+#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
+#define XSHAL_XT2000_SDRAM_REGIONS	0x00000440	/* BusInt SDRAM regions */
+
+
+/*----------------------------------------------------------------------
+				VECTOR INFO AND SIZES
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_VECTORS_PACKED		0
+#define XSHAL_STATIC_VECTOR_SELECT	1
+#define XSHAL_RESET_VECTOR_VADDR	0x40000400
+#define XSHAL_RESET_VECTOR_PADDR	0x40000400
+
+/*
+ *  Sizes allocated to vectors by the system (memory map) configuration.
+ *  These sizes are constrained by core configuration (eg. one vector's
+ *  code cannot overflow into another vector) but are dependent on the
+ *  system or board (or LSP) memory map configuration.
+ *
+ *  Whether or not each vector happens to be in a system ROM is also
+ *  a system configuration matter, sometimes useful, included here also:
+ */
+#define XSHAL_RESET_VECTOR_SIZE	0x00000300
+#define XSHAL_RESET_VECTOR_ISROM	0
+#define XSHAL_USER_VECTOR_SIZE	0x00000038
+#define XSHAL_USER_VECTOR_ISROM	0
+#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_KERNEL_VECTOR_SIZE	0x00000038
+#define XSHAL_KERNEL_VECTOR_ISROM	0
+#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000040
+#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
+#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
+#define XSHAL_WINDOW_VECTORS_ISROM	0
+#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL6_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL6_VECTOR_ISROM	0
+#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL6_VECTOR_SIZE
+#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL6_VECTOR_ISROM
+#define XSHAL_NMI_VECTOR_SIZE	0x00000038
+#define XSHAL_NMI_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL7_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
+
+
+#endif /*XTENSA_CONFIG_SYSTEM_H*/
+

components/xtensa/esp32s2beta/include/xtensa/config/tie-asm.h

@@ -0,0 +1,130 @@
+/* 
+ * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
+ *
+ *  NOTE:  This header file is not meant to be included directly.
+ */
+
+/* This header file contains assembly-language definitions (assembly
+   macros, etc.) for this specific Xtensa processor's TIE extensions
+   and options.  It is customized to this Xtensa processor configuration.
+
+   Copyright (c) 1999-2018 Cadence Design Systems Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
+					| ((ccuse) & XTHAL_SAS_ANYCC)  \
+					| ((abi)   & XTHAL_SAS_ANYABI) )
+
+
+    /*
+      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
+      *  (not including zero-overhead loop registers).
+      *  Required parameters:
+      *      ptr         Save area pointer address register (clobbered)
+      *                  (register must contain a 4 byte aligned address).
+      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+      *                  registers are clobbered, the remaining are unused).
+      *  Optional parameters:
+      *      continue    If macro invoked as part of a larger store sequence, set to 1
+      *                  if this is not the first in the sequence.  Defaults to 0.
+      *      ofs         Offset from start of larger sequence (from value of first ptr
+      *                  in sequence) at which to store.  Defaults to next available space
+      *                  (or 0 if <continue> is 0).
+      *      select      Select what category(ies) of registers to store, as a bitmask
+      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
+      *      alloc       Select what category(ies) of registers to allocate; if any
+      *                  category is selected here that is not in <select>, space for
+      *                  the corresponding registers is skipped without doing any store.
+      */
+    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional global registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	rur.THREADPTR	\at1		// threadptr option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+    .endm	// xchal_ncp_store
+
+    /*
+      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
+      *  (not including zero-overhead loop registers).
+      *  Required parameters:
+      *      ptr         Save area pointer address register (clobbered)
+      *                  (register must contain a 4 byte aligned address).
+      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+      *                  registers are clobbered, the remaining are unused).
+      *  Optional parameters:
+      *      continue    If macro invoked as part of a larger load sequence, set to 1
+      *                  if this is not the first in the sequence.  Defaults to 0.
+      *      ofs         Offset from start of larger sequence (from value of first ptr
+      *                  in sequence) at which to load.  Defaults to next available space
+      *                  (or 0 if <continue> is 0).
+      *      select      Select what category(ies) of registers to load, as a bitmask
+      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
+      *      alloc       Select what category(ies) of registers to allocate; if any
+      *                  category is selected here that is not in <select>, space for
+      *                  the corresponding registers is skipped without doing any load.
+      */
+    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional global registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wur.THREADPTR	\at1		// threadptr option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+    .endm	// xchal_ncp_load
+
+
+#define XCHAL_NCP_NUM_ATMPS	1
+
+#define XCHAL_SA_NUM_ATMPS	1
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+

components/xtensa/esp32s2beta/include/xtensa/config/tie.h

@@ -0,0 +1,130 @@
+/* 
+ * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ *  NOTE:  This header file is not meant to be included directly.
+ */
+
+/* This header file describes this specific Xtensa processor's TIE extensions
+   that extend basic Xtensa core functionality.  It is customized to this
+   Xtensa processor configuration.
+
+   Copyright (c) 1999-2018 Cadence Design Systems Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			0	/* number of coprocessors */
+#define XCHAL_CP_MAX			0	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x00	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		4
+#define XCHAL_NCP_SA_ALIGN		4
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		16	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	1
+#define XCHAL_NCP_SA_LIST(s)	\
+ XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM	0
+#define XCHAL_CP0_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+/* Byte length of instruction from its first byte, per FLIX.  */
+#define XCHAL_BYTE0_FORMAT_LENGTHS	\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+