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fix(uart): correct C2 UART_BITRATE_MAX value

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This commit is contained in:
Song Ruo Jing 2024-03-22 11:24:07 +08:00
parent 2fd087b246
commit b00844ca57
3 changed files with 4 additions and 5 deletions
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2
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@ -565,7 +565,7 @@ config SOC_UART_FIFO_LEN
config SOC_UART_BITRATE_MAX config SOC_UART_BITRATE_MAX
int int
default 5000000 default 2500000
config SOC_UART_SUPPORT_WAKEUP_INT config SOC_UART_SUPPORT_WAKEUP_INT
bool bool

5
components/soc/esp32c2/include/soc/clk_tree_defs.h
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@ -185,9 +185,6 @@ typedef enum {
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock default choice is PLL_F40M */ UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock default choice is PLL_F40M */
} soc_periph_uart_clk_src_legacy_t; } soc_periph_uart_clk_src_legacy_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/** /**
@ -204,6 +201,8 @@ typedef enum {
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
} soc_periph_spi_clk_src_t; } soc_periph_spi_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/** /**
* @brief Array initializer for all supported clock sources of I2C * @brief Array initializer for all supported clock sources of I2C
*/ */

2
components/soc/esp32c2/include/soc/soc_caps.h
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@ -269,7 +269,7 @@
// ESP32-C2 has 2 UARTs // ESP32-C2 has 2 UARTs
#define SOC_UART_NUM (2) #define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ #define SOC_UART_BITRATE_MAX (2500000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */ #define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */