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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
fix(cache): no longer use freeze in esp_cache_msync
Writeback and invalidation don't need cache to be frozen first
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parent
38d54b4b62
commit
aff298be18
@ -15,35 +15,10 @@
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#include "esp_cache.h"
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#include "esp_private/critical_section.h"
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static const char *TAG = "cache";
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#if SOC_CACHE_WRITEBACK_SUPPORTED
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DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock);
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void s_cache_freeze(void)
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{
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#if SOC_CACHE_FREEZE_SUPPORTED
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cache_hal_freeze(CACHE_TYPE_DATA | CACHE_TYPE_INSTRUCTION);
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#endif
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/**
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* For writeback supported, but the freeze not supported chip (Now only S2),
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* as it's single core, the critical section is enough to prevent preemption from an non-IRAM ISR
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*/
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}
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void s_cache_unfreeze(void)
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{
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#if SOC_CACHE_FREEZE_SUPPORTED
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cache_hal_unfreeze(CACHE_TYPE_DATA | CACHE_TYPE_INSTRUCTION);
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#endif
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/**
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* Similarly, for writeback supported, but the freeze not supported chip (Now only S2),
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* we don't need to do more
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*/
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}
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#endif //#if SOC_CACHE_WRITEBACK_SUPPORTED
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@ -54,9 +29,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
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#if SOC_CACHE_WRITEBACK_SUPPORTED
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if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) {
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esp_os_enter_critical_safe(&s_spinlock);
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
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esp_os_exit_critical_safe(&s_spinlock);
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ESP_RETURN_ON_FALSE_ISR(((uint32_t)addr % data_cache_line_size) == 0, ESP_ERR_INVALID_ARG, TAG, "start address isn't aligned with the data cache line size (%d)B", data_cache_line_size);
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ESP_RETURN_ON_FALSE_ISR((size % data_cache_line_size) == 0, ESP_ERR_INVALID_ARG, TAG, "size isn't aligned with the data cache line size (%d)B", data_cache_line_size);
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@ -66,15 +39,14 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
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uint32_t vaddr = (uint32_t)addr;
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esp_os_enter_critical_safe(&s_spinlock);
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s_cache_freeze();
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cache_hal_writeback_addr(vaddr, size);
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if (flags & ESP_CACHE_MSYNC_FLAG_INVALIDATE) {
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cache_hal_invalidate_addr(vaddr, size);
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}
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s_cache_unfreeze();
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esp_os_exit_critical_safe(&s_spinlock);
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if (flags & ESP_CACHE_MSYNC_FLAG_INVALIDATE) {
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esp_os_enter_critical_safe(&s_spinlock);
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cache_hal_invalidate_addr(vaddr, size);
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esp_os_exit_critical_safe(&s_spinlock);
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}
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#endif
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return ESP_OK;
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