diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c
index a9c246ba84..3203ef6e36 100644
--- a/components/esp_hw_support/port/esp32/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32/rtc_clk.c
@@ -251,8 +251,7 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
-        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
+        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         if (d256_en) {
             CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
         } else {
diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c
index fa931f5e1d..66bc0003e7 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c
@@ -96,7 +96,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {
diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk.c b/components/esp_hw_support/port/esp32s2/rtc_clk.c
index e0e0146a59..8a11266efb 100644
--- a/components/esp_hw_support/port/esp32s2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_clk.c
@@ -99,7 +99,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {
diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c
index 4645393b91..d506c66fcc 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c
@@ -99,7 +99,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {
diff --git a/components/esp_system/test_apps/rtc_8md256/CMakeLists.txt b/components/esp_system/test_apps/rtc_8md256/CMakeLists.txt
new file mode 100644
index 0000000000..46c2c5b8ac
--- /dev/null
+++ b/components/esp_system/test_apps/rtc_8md256/CMakeLists.txt
@@ -0,0 +1,7 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.5)
+
+set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(rtc_8md256)
diff --git a/components/esp_system/test_apps/rtc_8md256/component_ut_test.py b/components/esp_system/test_apps/rtc_8md256/component_ut_test.py
new file mode 100644
index 0000000000..f0d88e7573
--- /dev/null
+++ b/components/esp_system/test_apps/rtc_8md256/component_ut_test.py
@@ -0,0 +1,66 @@
+# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import re
+
+import ttfw_idf
+
+
+def deepsleep_test(dut, case_name):
+    dut.expect('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    reset_reason = 'DEEPSLEEP_RESET' if dut.TARGET == 'esp32' else 'DSLEEP'
+    if dut.TARGET == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(re.compile(r'rst:.*\(%s\)' % reset_reason), timeout=40)
+    else:
+        dut.expect(re.compile(r'rst:.*\(%s\)' % reset_reason), timeout=10)
+
+
+@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32c3'])
+def test_component_ut_rtc_8md256_deepsleep_force_rtcperiph(env, _):
+    dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256')
+    dut.start_app()
+
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)"')
+
+
+@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32c3'])
+def test_component_ut_rtc_8md256_deepsleep(env, _):
+    dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256')
+    dut.start_app()
+
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep"')
+
+
+def lightsleep_test(dut, case_name):
+    dut.expect('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    if dut.TARGET == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=40)
+    else:
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=10)
+
+
+@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32c3'])
+def test_component_ut_rtc_8md256_lightsleep(env, _):
+    dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256')
+    dut.start_app()
+
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep"')
+
+
+@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32c3'])
+def test_component_ut_rtc_8md256_lightsleep_force_rtcperiph(env, _):
+    dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256')
+    dut.start_app()
+
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)"')
+
+
+if __name__ == '__main__':
+    test_component_ut_rtc_8md256_deepsleep()
+    test_component_ut_rtc_8md256_deepsleep_force_rtcperiph()
+    test_component_ut_rtc_8md256_lightsleep()
+    test_component_ut_rtc_8md256_lightsleep_force_rtcperiph()
diff --git a/components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt b/components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt
new file mode 100644
index 0000000000..de06a799d0
--- /dev/null
+++ b/components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "test_rtc_8md256.c"
+                       PRIV_REQUIRES unity)
diff --git a/components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c b/components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c
new file mode 100644
index 0000000000..73c46a38c7
--- /dev/null
+++ b/components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "esp_sleep.h"
+#include "unity.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "driver/uart.h"
+#include "soc/soc_caps.h"
+
+static const char TAG[] = "rtc_8m";
+
+static void test_deepsleep(bool force_rtc_periph)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+    if (force_rtc_periph) {
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+    }
+#else
+    (void)force_rtc_periph;
+#endif
+
+    ESP_LOGI(TAG, "Entering deep sleep");
+    esp_deep_sleep_start();
+}
+
+TEST_CASE("Can use 8MD256 as RTC clock source in deepsleep", "[pm]")
+{
+    test_deepsleep(false);
+}
+
+static void test_lightsleep(bool force_rtc_periph)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+    if (force_rtc_periph) {
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+    }
+#else
+    (void)force_rtc_periph;
+#endif
+
+    while (true) {
+        printf("Entering light sleep\n");
+        /* To make sure the complete line is printed before entering sleep mode,
+         * need to wait until UART TX FIFO is empty:
+         */
+        uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM);
+
+        /* Enter sleep mode */
+        esp_light_sleep_start();
+
+        /* Determine wake up reason */
+        const char* wakeup_reason;
+        switch (esp_sleep_get_wakeup_cause()) {
+            case ESP_SLEEP_WAKEUP_TIMER:
+                wakeup_reason = "timer";
+                break;
+            default:
+                wakeup_reason = "other";
+                break;
+        }
+        printf("Returned from light sleep, reason: %s\n", wakeup_reason);
+        vTaskDelay(1000/portTICK_PERIOD_MS);
+    }
+}
+
+TEST_CASE("Can use 8MD256 as RTC clock source in lightsleep", "[pm]")
+{
+    test_lightsleep(false);
+}
+
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+TEST_CASE("Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)", "[pm]")
+{
+    test_deepsleep(true);
+}
+
+TEST_CASE("Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)", "[pm]")
+{
+    test_lightsleep(true);
+}
+#endif
+
+void app_main(void)
+{
+    unity_run_menu();
+}
diff --git a/components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults b/components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults
new file mode 100644
index 0000000000..3660129c9f
--- /dev/null
+++ b/components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults
@@ -0,0 +1,3 @@
+CONFIG_FREERTOS_HZ=1000
+CONFIG_ESP_TASK_WDT=n
+CONFIG_RTC_CLK_SRC_INT_8MD256=y
diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h
index ebdc0b6185..d9b9f1ce79 100644
--- a/components/soc/esp32/include/soc/rtc.h
+++ b/components/soc/esp32/include/soc/rtc.h
@@ -568,6 +568,9 @@ typedef struct rtc_sleep_config_s {
 #define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES       (1)
 #define RTC_CNTL_MIN_SLP_VAL_MIN            (128)
 
+#define RTC_CNTL_CK8M_WAIT_DEFAULT          20
+#define RTC_CK8M_ENABLE_WAIT_DEFAULT        5
+
 /**
  * @brief Prepare the chip to enter sleep mode
  *
diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h
index 0917ee606f..74b77f469b 100644
--- a/components/soc/esp32/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h
@@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
@@ -341,7 +333,6 @@
 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
 #define RTC_CNTL_CK8M_WAIT_V  0xFF
 #define RTC_CNTL_CK8M_WAIT_S  6
-#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
 /*description: CPU stall wait cycles in fast_clk_rtc*/
 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
index 6f976af722..1255f3994c 100644
--- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
@@ -308,7 +308,6 @@ extern "C" {
 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
 #define RTC_CNTL_CK8M_WAIT_V  0xFF
 #define RTC_CNTL_CK8M_WAIT_S  6
-#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
 /*description: CPU stall wait cycles in fast_clk_rtc*/
 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
diff --git a/tools/ci/config/target-test.yml b/tools/ci/config/target-test.yml
index d4e3932d46..b0615212cf 100644
--- a/tools/ci/config/target-test.yml
+++ b/tools/ci/config/target-test.yml
@@ -82,11 +82,16 @@
     - .component_ut_template
     - .rules:tests:unit_test_32
 
-.component_ut_s2_template: # unused yet
+.component_ut_s2_template:
   extends:
     - .component_ut_template
     - .rules:tests:unit_test_s2
 
+.component_ut_c3_template:
+  extends:
+    - .component_ut_template
+    - .rules:tests:unit_test_c3
+
 .unit_test_template:
   extends:
     - .target_test_job_template
@@ -365,6 +370,18 @@ component_ut_test_001:
     - ESP32
     - COMPONENT_UT_GENERIC
 
+component_ut_test_s2_generic:
+  extends: .component_ut_s2_template
+  tags:
+    - ESP32S2
+    - COMPONENT_UT_GENERIC
+
+component_ut_test_c3_generic:
+  extends: .component_ut_c3_template
+  tags:
+    - ESP32C3
+    - COMPONENT_UT_GENERIC
+
 UT_001:
   extends: .unit_test_32_template
   parallel: 50