Merge branch 'feature/efuse_settings_v5.1' into 'release/v5.1'

hal: Explicit setting of efuse time settings (v5.1)

See merge request espressif/esp-idf!23725

components/hal/esp32c2/efuse_hal.c

@@ -30,6 +30,9 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
     (void) apb_freq_hz;
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
     efuse_ll_set_pwr_off_num(0x190);
     int xtal = clk_ll_xtal_load_freq_mhz();
     HAL_ASSERT(xtal == 40 || xtal == 26);

components/hal/esp32c2/include/hal/efuse_ll.h

@@ -181,6 +181,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;

components/hal/esp32c3/efuse_hal.c

@@ -30,6 +30,9 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
     (void) apb_freq_hz;
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
     efuse_ll_set_pwr_off_num(0x190);
 }
 

components/hal/esp32c3/include/hal/efuse_ll.h

@@ -156,6 +156,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;

components/hal/esp32c6/efuse_hal.c

@@ -29,7 +29,10 @@ uint32_t efuse_hal_get_minor_chip_version(void)
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
     (void) apb_freq_hz;
-    // keep the default values, no need to change it
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
+    efuse_ll_set_pwr_off_num(0x190);
 }
 
 void efuse_hal_read(void)

components/hal/esp32c6/include/hal/efuse_ll.h

@@ -115,6 +115,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;

components/hal/esp32h2/efuse_hal.c

@@ -29,7 +29,10 @@ uint32_t efuse_hal_get_minor_chip_version(void)
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
     (void) apb_freq_hz;
-    // keep the default values, no need to change
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
+    efuse_ll_set_pwr_off_num(0x190);
 }
 
 void efuse_hal_read(void)

components/hal/esp32h2/include/hal/efuse_ll.h

@@ -125,6 +125,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;

components/hal/esp32s2/efuse_hal.c

@@ -29,7 +29,60 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
-    ets_efuse_set_timing(apb_freq_hz);
+    uint32_t tsup_a;
+    uint32_t tpgm;
+    uint32_t thp_a;
+    uint32_t tpgm_inact;
+    uint32_t clk_div;
+    uint32_t power_on;
+    uint32_t power_off;
+    uint32_t tsur_a;
+    uint32_t trd;
+    uint32_t thr_a;
+    if (apb_freq_hz == 80000000) {
+        tsup_a = 0x2;
+        tpgm = 0x320;
+        thp_a = 0x2;
+        tpgm_inact = 0x4;
+        clk_div = 0xA0;
+        power_on = 0xA200;
+	    power_off = 0x100;
+        tsur_a = 0x2;
+        trd = 0x4;
+        thr_a = 0x2;
+    } else if (apb_freq_hz == 40000000) {
+        tsup_a = 0x1;
+        tpgm = 0x190;
+        thp_a = 0x1;
+        tpgm_inact = 0x2;
+        clk_div = 0x50;
+        power_on = 0x5100;
+        power_off = 0x80;
+        tsur_a = 0x1;
+        trd = 0x2;
+        thr_a = 0x1;
+    } else { // 20000000 or 5000000 or 10000000
+        tsup_a = 0x1;
+        tpgm = 0xC8;
+        thp_a = 0x1;
+        tpgm_inact = 0x1;
+        clk_div = 0x28;
+        power_on = 0x2880;
+        power_off = 0x40;
+        tsur_a = 0x1;
+        trd = 0x1;
+        thr_a = 0x1;
+    }
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact);
+    REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off);
+    REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a);
+    REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd);
+    REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a);
 }
 
 void efuse_hal_read(void)

components/hal/esp32s3/efuse_hal.c

@@ -50,6 +50,9 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
     (void) apb_freq_hz;
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
     efuse_ll_set_pwr_off_num(0x190);
 }
 

components/hal/esp32s3/include/hal/efuse_ll.h

@@ -156,6 +156,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;