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feat(pm): support PMU trigger regdma when PU TOP

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This commit is contained in:
Lou Tianhao 2023-12-21 11:28:11 +08:00
parent d7b9a3b3da
commit aed3127d19
5 changed files with 25 additions and 16 deletions
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3
components/esp_hw_support/port/esp32c6/pmu_sleep.c
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@ -289,5 +289,6 @@ void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
uint32_t pmu_sleep_get_wakup_retention_cost(void) uint32_t pmu_sleep_get_wakup_retention_cost(void)
{ {
return PMU_REGDMA_S2A_WORK_TIME_US; const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
return mc->hp.regdma_s2a_work_time_us;
} }

22
components/esp_hw_support/port/esp32h2/pmu_sleep.c
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@ -24,20 +24,22 @@
void pmu_sleep_enable_regdma_backup(void) void pmu_sleep_enable_regdma_backup(void)
{ {
/* ESP32H2 does not have PMU HP_AON power domain. because the registers assert(PMU_instance()->hal);
* of PAU REGDMA is included to PMU TOP power domain, cause the contents /* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
* of PAU REGDMA registers will be lost when the TOP domain is powered down * and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
* during light sleep, so we does not need to enable REGDMA backup here. * respectively. entry 3 is reserved, not used yet! */
* We will use the software to trigger REGDMA to backup or restore. */ pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
} }
void pmu_sleep_disable_regdma_backup(void) void pmu_sleep_disable_regdma_backup(void)
{ {
assert(PMU_instance()->hal);
pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
} }
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period) uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
{ {
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc; pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
/* LP core hardware wait time, microsecond */ /* LP core hardware wait time, microsecond */
const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period); const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
@ -49,6 +51,11 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
/* HP core hardware wait time, microsecond */ /* HP core hardware wait time, microsecond */
const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us; const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
if (pd_flags & PMU_SLEEP_PD_TOP) {
mc->hp.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US;
} else {
mc->hp.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US;
}
const int hp_regdma_wait_time_us = mc->hp.regdma_s2a_work_time_us; const int hp_regdma_wait_time_us = mc->hp.regdma_s2a_work_time_us;
const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us; const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us;
@ -231,5 +238,6 @@ bool pmu_sleep_finish(void)
uint32_t pmu_sleep_get_wakup_retention_cost(void) uint32_t pmu_sleep_get_wakup_retention_cost(void)
{ {
return PMU_REGDMA_S2A_WORK_TIME_US; const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
return mc->hp.regdma_s2a_work_time_us;
} }

6
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
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@ -41,7 +41,9 @@ extern "C" {
#define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1
#define PMU_LP_DBIAS_LIGHTSLEEP_0V7 6 #define PMU_LP_DBIAS_LIGHTSLEEP_0V7 6
#define PMU_REGDMA_S2A_WORK_TIME_US 0 #define PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US 0
// The current value of this depends on the restoration time overhead of the longest chain in regdma
#define PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US 390
// FOR DEEPSLEEP // FOR DEEPSLEEP
#define PMU_HP_XPD_DEEPSLEEP 0 #define PMU_HP_XPD_DEEPSLEEP 0
@ -440,7 +442,7 @@ typedef struct pmu_sleep_machine_constant {
.analog_wait_time_us = 154, \ .analog_wait_time_us = 154, \
.power_supply_wait_time_us = 2, \ .power_supply_wait_time_us = 2, \
.power_up_wait_time_us = 2, \ .power_up_wait_time_us = 2, \
.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \ .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US, \
.regdma_a2s_work_time_us = 0, \ .regdma_a2s_work_time_us = 0, \
.xtal_wait_stable_time_us = 250, \ .xtal_wait_stable_time_us = 250, \
.pll_wait_stable_time_us = 1 \ .pll_wait_stable_time_us = 1 \

4
components/esp_hw_support/sleep_retention.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -523,6 +523,8 @@ void IRAM_ATTR sleep_retention_do_system_retention(bool backup_or_restore)
s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) { s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
// Set extra linked list head pointer to hardware // Set extra linked list head pointer to hardware
pau_regdma_set_system_link_addr(s_retention.lists[s_retention.highpri].entries[SYSTEM_LINK_NUM]); pau_regdma_set_system_link_addr(s_retention.lists[s_retention.highpri].entries[SYSTEM_LINK_NUM]);
// When PD TOP, we need to prevent the PMU from triggering the REGDMA backup, because REGDMA will power off
pmu_sleep_disable_regdma_backup();
if (backup_or_restore) { if (backup_or_restore) {
pau_regdma_trigger_system_link_backup(); pau_regdma_trigger_system_link_backup();
} else { } else {

6
components/hal/esp32h2/pau_hal.c
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@ -15,11 +15,7 @@
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
{ {
/* ESP32H2 does not have PMU HP_AON power domain. because the registers pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]);
* of PAU REGDMA is included to PMU TOP power domain, cause the contents
* of PAU REGDMA registers will be lost when the TOP domain is powered down
* during light sleep, so we does not need to enable REGDMA backup here.
* We will use the software to trigger REGDMA to backup or restore. */
} }
void IRAM_ATTR pau_hal_start_regdma_system_link(pau_hal_context_t *hal, bool backup_or_restore) void IRAM_ATTR pau_hal_start_regdma_system_link(pau_hal_context_t *hal, bool backup_or_restore)