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Merge branch 'bugfix/c6_h2_decrease_rng_frequency' into 'master'

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esp_hw_support: decrease RNG read frequency for C6 and H2

See merge request espressif/esp-idf!23977
This commit is contained in:
Mahavir Jain 2023-05-31 16:30:37 +08:00
commit aed0e3604b
2 changed files with 8 additions and 7 deletions
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3
components/bootloader_support/src/bootloader_random.c
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@ -25,7 +25,8 @@
#if !defined CONFIG_IDF_TARGET_ESP32S3 #if !defined CONFIG_IDF_TARGET_ESP32S3
#if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2) #if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 12) // higher frequency because we are reading bytes instead of words #define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
// tested.
#else #else
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */ #define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
#endif #endif

12
components/esp_hw_support/hw_random.c
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@ -19,16 +19,16 @@
#endif #endif
#if defined CONFIG_IDF_TARGET_ESP32S3 #if defined CONFIG_IDF_TARGET_ESP32S3
#define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, maximum sampling frequency is around 45 KHz*/ #define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz*/
/* 45 KHz reading frequency is the maximum we have tested so far on S3 */ /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
#elif defined CONFIG_IDF_TARGET_ESP32C6 #elif defined CONFIG_IDF_TARGET_ESP32C6
#define APB_CYCLE_WAIT_NUM (160 * 5) /* We want to have a maximum sampling frequency below 50KHz for #define APB_CYCLE_WAIT_NUM (160 * 16) /* On ESP32C6, we only read one byte at a time, then XOR the value with
* 32-bit samples. But on ESP32C6, we only read one byte at a time, * an asynchronous timer (see code below).
* hence, the wait time is 4 times lower. The current value translates * The current value translates to a sampling frequency of around 62.5 KHz
* to a sampling frequency of 50 KHz for reading 32 bit samples, * for reading 8 bit samples, which is the rate at which the RNG was tested,
* plus additional overhead for the calculation, making it slower. */ * plus additional overhead for the calculation, making it slower. */
#elif defined CONFIG_IDF_TARGET_ESP32H2 #elif defined CONFIG_IDF_TARGET_ESP32H2
#define APB_CYCLE_WAIT_NUM (160 * 3) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is #define APB_CYCLE_WAIT_NUM (96 * 16) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is
* 96MHz instead of 160 MHz */ * 96MHz instead of 160 MHz */
#else #else
#define APB_CYCLE_WAIT_NUM (16) #define APB_CYCLE_WAIT_NUM (16)