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efuse_table: update esp32c6 efuse block1 fields definition

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This commit is contained in:
wuzhenghui 2022-12-15 15:12:40 +08:00 committed by xiaqilin
parent be94097eab
commit adc259cc79
3 changed files with 14 additions and 138 deletions
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111
components/efuse/esp32c6/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c
// md5_digest_table 19131923372be226ce98d85f5a13f16a
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -340,48 +340,9 @@ static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
{EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
{EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
{EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
{EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
{EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
{EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
{EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
{EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
{EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
{EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
static const esp_efuse_desc_t MAC_EXT[] = {
{EFUSE_BLK1, 48, 8}, // Extend MAC addr [0],
{EFUSE_BLK1, 56, 8}, // Extend MAC addr [1],
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
@ -397,10 +358,6 @@ static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
@ -918,58 +875,9 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
&SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
&SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
&SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
&SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
&SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
&SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
&SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
&SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
&SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
&SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
&SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
&MAC_EXT[0], // Extend MAC addr [0]
&MAC_EXT[1], // Extend MAC addr [1]
NULL
};
@ -989,11 +897,6 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
&OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
NULL

26
components/efuse/esp32c6/esp_efuse_table.csv
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@ -104,39 +104,23 @@
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_SYS BLOCK#
# MAC_SYS_VERSION BLOCK #
#######################
# RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
# RD_MAC_SPI_SYS_3
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
MAC_EXT, EFUSE_BLK1, 48, 8, Extend MAC addr [0]
, EFUSE_BLK1, 56, 8, Extend MAC addr [1]
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# RD_MAC_SPI_SYS_5
# WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
# SYS_DATA_PART1 BLOCK# - System configuration
# SYS_DATA_PART1 BLOCK# - System configuration (TODO: IDF-6483) #
#######################
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
@ -169,7 +153,7 @@ KEY4, EFUSE_BLK8, 0, 256, Key4 or us
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
# AUTO CONFIG DIG&RTC DBIAS#
# AUTO CONFIG DIG&RTC DBIAS (TODO: IDF-6483)#
################
K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO

Can't render this file because it contains an unexpected character in line 7 and column 87.

15
components/efuse/esp32c6/include/esp_efuse_table.h
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@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c
// md5_digest_table 19131923372be226ce98d85f5a13f16a
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -97,21 +97,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];