diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index ee9ad49de5..040228ca72 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -732,6 +732,48 @@ static void load_image(const esp_image_metadata_t *image_data)
     unpack_load_app(image_data);
 }
 
+#if SOC_MMU_DI_VADDR_SHARED
+static void unpack_load_app(const esp_image_metadata_t *data)
+{
+    /**
+     * note:
+     * On chips with shared D/I external vaddr, we don't divide them into either D or I,
+     * as essentially they are the same.
+     * We integrate all the hardware difference into this `unpack_load_app` function.
+     */
+    uint32_t rom_addr[2] = {};
+    uint32_t rom_load_addr[2] = {};
+    uint32_t rom_size[2] = {};
+    int rom_index = 0;  //shall not exceed 2
+
+    // Find DROM & IROM addresses, to configure MMU mappings
+    for (int i = 0; i < data->image.segment_count; i++) {
+        const esp_image_segment_header_t *header = &data->segments[i];
+        //`SOC_DROM_LOW` and `SOC_DROM_HIGH` are the same as `SOC_IROM_LOW` and `SOC_IROM_HIGH`, reasons are in above `note`
+        if (header->load_addr >= SOC_DROM_LOW && header->load_addr < SOC_DROM_HIGH) {
+            /**
+             * D/I are shared, but there should not be a third segment on flash
+             */
+            assert(rom_index < 2);
+            rom_addr[rom_index] = data->segment_data[i];
+            rom_load_addr[rom_index] = header->load_addr;
+            rom_size[rom_index] = header->data_len;
+            rom_index++;
+        }
+    }
+    assert(rom_index == 2);
+
+    ESP_EARLY_LOGD(TAG, "calling set_cache_and_start_app");
+    set_cache_and_start_app(rom_addr[0],
+                            rom_load_addr[0],
+                            rom_size[0],
+                            rom_addr[1],
+                            rom_load_addr[1],
+                            rom_size[1],
+                            data->image.entry_addr);
+}
+
+#else  //!SOC_MMU_DI_VADDR_SHARED
 static void unpack_load_app(const esp_image_metadata_t *data)
 {
     uint32_t drom_addr = 0;
@@ -741,14 +783,14 @@ static void unpack_load_app(const esp_image_metadata_t *data)
     uint32_t irom_load_addr = 0;
     uint32_t irom_size = 0;
 
-    // Find DROM & IROM addresses, to configure cache mappings
+    // Find DROM & IROM addresses, to configure MMU mappings
     for (int i = 0; i < data->image.segment_count; i++) {
         const esp_image_segment_header_t *header = &data->segments[i];
         if (header->load_addr >= SOC_DROM_LOW && header->load_addr < SOC_DROM_HIGH) {
             if (drom_addr != 0) {
-                ESP_LOGE(TAG, MAP_ERR_MSG, "DROM");
+                ESP_EARLY_LOGE(TAG, MAP_ERR_MSG, "DROM");
             } else {
-                ESP_LOGD(TAG, "Mapping segment %d as %s", i, "DROM");
+                ESP_EARLY_LOGD(TAG, "Mapping segment %d as %s", i, "DROM");
             }
             drom_addr = data->segment_data[i];
             drom_load_addr = header->load_addr;
@@ -756,9 +798,9 @@ static void unpack_load_app(const esp_image_metadata_t *data)
         }
         if (header->load_addr >= SOC_IROM_LOW && header->load_addr < SOC_IROM_HIGH) {
             if (irom_addr != 0) {
-                ESP_LOGE(TAG, MAP_ERR_MSG, "IROM");
+                ESP_EARLY_LOGE(TAG, MAP_ERR_MSG, "IROM");
             } else {
-                ESP_LOGD(TAG, "Mapping segment %d as %s", i, "IROM");
+                ESP_EARLY_LOGD(TAG, "Mapping segment %d as %s", i, "IROM");
             }
             irom_addr = data->segment_data[i];
             irom_load_addr = header->load_addr;
@@ -766,7 +808,7 @@ static void unpack_load_app(const esp_image_metadata_t *data)
         }
     }
 
-    ESP_LOGD(TAG, "calling set_cache_and_start_app");
+    ESP_EARLY_LOGD(TAG, "calling set_cache_and_start_app");
     set_cache_and_start_app(drom_addr,
                             drom_load_addr,
                             drom_size,
@@ -775,6 +817,7 @@ static void unpack_load_app(const esp_image_metadata_t *data)
                             irom_size,
                             data->image.entry_addr);
 }
+#endif  //#if SOC_MMU_DI_VADDR_SHARED
 
 static void set_cache_and_start_app(
     uint32_t drom_addr,
diff --git a/components/esp_system/ld/esp32c6/memory.ld.in b/components/esp_system/ld/esp32c6/memory.ld.in
index 95178e726b..686a964df0 100644
--- a/components/esp_system/ld/esp32c6/memory.ld.in
+++ b/components/esp_system/ld/esp32c6/memory.ld.in
@@ -64,7 +64,7 @@ MEMORY
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped instruction data */
-  iram0_2_seg (RX) :                 org = 0x42000020, len = (IDRAM0_2_SEG_SIZE >> 1) -0x20
+  irom_seg (RX) :                    org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
 
   /**
    * (0x20 offset above is a convenience for the app binary image generation.
@@ -83,9 +83,9 @@ MEMORY
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped constant data */
-  drom0_0_seg (R) :                  org = 0x42000020 + (IDRAM0_2_SEG_SIZE >> 1), len = (IDRAM0_2_SEG_SIZE >> 1)-0x20
+  drom_seg (R) :                     org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
 
-  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+  /* (See irom_seg for meaning of 0x20 offset in the above.) */
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
   /**
@@ -123,19 +123,19 @@ REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
 REGION_ALIAS("rtc_data_location", rtc_iram_seg );
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
-  REGION_ALIAS("default_code_seg", iram0_2_seg);
+  REGION_ALIAS("default_code_seg", irom_seg);
 #else
   REGION_ALIAS("default_code_seg", iram0_0_seg);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
-  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+  REGION_ALIAS("default_rodata_seg", drom_seg);
 #else
   REGION_ALIAS("default_rodata_seg", dram0_0_seg);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 /**
- *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
+ *  If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
  *  also be first in the segment.
  */
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 8cb88aa4f7..6f3d40a989 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -355,6 +355,10 @@ config SOC_LEDC_SUPPORT_FADE_STOP
     bool
     default y
 
+config SOC_MMU_DI_VADDR_SHARED
+    bool
+    default y
+
 config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
     bool
     default n
diff --git a/components/soc/esp32c6/include/soc/ext_mem_defs.h b/components/soc/esp32c6/include/soc/ext_mem_defs.h
index 9768e6cd9c..848801888c 100644
--- a/components/soc/esp32c6/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32c6/include/soc/ext_mem_defs.h
@@ -15,17 +15,17 @@ extern "C" {
 
 /*IRAM0 is connected with Cache IBUS0*/
 #define IRAM0_CACHE_ADDRESS_LOW             0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 128)) // MMU has 256 pages, first 128 for instruction
+#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 256))
 #define IRAM0_ADDRESS_LOW                   0x40000000
 #define IRAM0_ADDRESS_HIGH(page_size)       IRAM0_CACHE_ADDRESS_HIGH(page_size)
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x42000000
-#define DRAM0_ADDRESS_HIGH              0x43000000
-#define DRAM0_CACHE_ADDRESS_LOW         IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE) // ESP32C6-TODO after fixed, also need to remove the sdkconfig.h inclusion
-#define DRAM0_CACHE_ADDRESS_HIGH(page_size)        (IRAM0_CACHE_ADDRESS_HIGH(page_size) + ((page_size) * 128)) // MMU has 256 pages, second 128 for data
-#define DRAM0_CACHE_OPERATION_HIGH(page_size)      DRAM0_CACHE_ADDRESS_HIGH(page_size)
-#define ESP_CACHE_TEMP_ADDR             0x42000000
+#define DRAM0_ADDRESS_LOW                        0x42000000
+#define DRAM0_ADDRESS_HIGH                       0x43000000
+#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW     //I/D share the same vaddr range
+#define DRAM0_CACHE_ADDRESS_HIGH(page_size)      IRAM0_CACHE_ADDRESS_HIGH(page_size)    //I/D share the same vaddr range
+#define DRAM0_CACHE_OPERATION_HIGH(page_size)    DRAM0_CACHE_ADDRESS_HIGH(page_size)
+#define ESP_CACHE_TEMP_ADDR                      0x42000000
 
 #define BUS_SIZE(bus_name, page_size)                 (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW)
 #define ADDRESS_IN_BUS(bus_name, vaddr, page_size)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size))
diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h
index 03aea5fb27..6ef720bfae 100644
--- a/components/soc/esp32c6/include/soc/soc.h
+++ b/components/soc/esp32c6/include/soc/soc.h
@@ -163,9 +163,9 @@
  */
 
 #define SOC_IROM_LOW    0x42000000
-#define SOC_IROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7))
-#define SOC_DROM_LOW    SOC_IROM_HIGH
-#define SOC_DROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
+#define SOC_IROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
+#define SOC_DROM_LOW    SOC_IROM_LOW
+#define SOC_DROM_HIGH   SOC_IROM_HIGH
 #define SOC_IROM_MASK_LOW  0x40000000
 #define SOC_IROM_MASK_HIGH 0x4004AC00
 #define SOC_DROM_MASK_LOW  0x4004AC00
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index bcf983f6b1..8e7023d212 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -205,6 +205,9 @@
 #define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP   (1)
 
+/*-------------------------- MMU CAPS ----------------------------------------*/
+#define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
+
 // TODO: IDF-5684 (Copy from esp32c3, need check)
 /*-------------------------- MPU CAPS ----------------------------------------*/
 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0