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Merge branch 'bugfix/riscv_fix_vector_mcause_v4.4' into 'release/v4.4'

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RISC-V: fix usage of special register when interrupts are enabled (backport v4.4)

See merge request espressif/esp-idf!16187
This commit is contained in:
Zim Kalinowski 2021-12-01 04:20:54 +00:00
commit aa96a98c0c
1 changed files with 3 additions and 3 deletions
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6
components/riscv/vectors.S
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@ -267,8 +267,8 @@ _interrupt_handler:
#endif
/* call the C dispatcher */
mv a0, sp /* argument 1, stack pointer */
csrr a1, mcause /* argument 2, interrupt number */
mv a0, sp /* argument 1, stack pointer */
mv a1, s1 /* argument 2, interrupt number (mcause) */
/* mask off the interrupt flag of mcause */
li t0, 0x7fffffff
and a1, a1, t0
@ -276,7 +276,7 @@ _interrupt_handler:
/* After dispatch c handler, disable interrupt to make freertos make context switch */
la t0, 0x8
li t0, 0x8
csrrc t0, mstatus, t0
/* restore the interrupt threshold level */