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docs: remove mention of DIS_BOOT_REMAP for chips other than ESP32-S2
Relevant: https://esp32.com/viewtopic.php?f=13&t=31188
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@ -33,8 +33,7 @@
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DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0)
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DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0)
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DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0)
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DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0)
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ace
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DIS_APP_CPU (BLOCK0) Disables APP CPU = False R/W (0b0)
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FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0)
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unit is (ms/2). When the value is 15, delay is 7.
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5 ms
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@ -164,7 +164,15 @@ Assuming that the eFuse values are in their default states and the firmware boot
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5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
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6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the firmware bootloader by default sets the eFuse bits ``DIS_BOOT_REMAP``, ``DIS_DOWNLOAD_ICACHE``, ``DIS_DOWNLOAD_DCACHE``, ``HARD_DIS_JTAG`` and ``DIS_LEGACY_SPI_BOOT``.
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6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the firmware bootloader by default sets the following eFuse bits:
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.. list::
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:esp32s2: - ``DIS_BOOT_REMAP``
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- ``DIS_DOWNLOAD_ICACHE``
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- ``DIS_DOWNLOAD_DCACHE``
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- ``HARD_DIS_JTAG``
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- ``DIS_LEGACY_SPI_BOOT``
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7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
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