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synced 2024-10-05 20:47:46 -04:00
fix(esp_hw_support): move deepsleep phy callback before PLL disable
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,6 +7,7 @@
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#pragma once
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "esp_sleep.h"
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#ifdef __cplusplus
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extern "C" {
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@ -47,6 +48,29 @@ void esp_sleep_enable_adc_tsens_monitor(bool enable);
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void esp_sleep_isolate_digital_gpio(void);
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#endif
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/**
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* Register a callback to be called from the deep sleep prepare for maintain the PHY state
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* CPU is equal to min_freq_mhz (if DFS is enabled) when running this callback,
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* and PLL clock is exists)
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*
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* @warning deepsleep PHY callbacks should without parameters, and MUST NOT,
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* UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK.
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*
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* @param new_dslp_cb Callback to be called to close PHY related modules
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*
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* @return
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* - ESP_OK: PHY callback registered to the phy modules deepsleep prepare
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* - ESP_ERR_NO_MEM: No more hook space for register the callback
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*/
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esp_err_t esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb);
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/**
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* @brief Unregister an PHY deepsleep callback
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*
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* @param old_dslp_cb Callback to be unregistered
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*/
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void esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb);
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#ifdef __cplusplus
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}
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#endif
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@ -170,7 +170,8 @@
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#define MAX_DSLP_HOOKS 3
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static esp_deep_sleep_cb_t s_dslp_cb[MAX_DSLP_HOOKS]={0};
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static esp_deep_sleep_cb_t s_dslp_cb[MAX_DSLP_HOOKS] = {0};
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static esp_deep_sleep_cb_t s_dslp_phy_cb[MAX_DSLP_HOOKS] = {0};
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/**
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* Internal structure which holds all requested sleep parameters
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@ -387,12 +388,12 @@ esp_err_t esp_deep_sleep_try(uint64_t time_in_us)
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return esp_deep_sleep_try_to_start();
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}
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esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
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static esp_err_t s_sleep_hook_register(esp_deep_sleep_cb_t new_cb, esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])
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{
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portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
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for(int n = 0; n < MAX_DSLP_HOOKS; n++){
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if (s_dslp_cb[n]==NULL || s_dslp_cb[n]==new_dslp_cb) {
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s_dslp_cb[n]=new_dslp_cb;
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for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
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if (s_cb_array[n]==NULL || s_cb_array[n]==new_cb) {
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s_cb_array[n]=new_cb;
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portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
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return ESP_OK;
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}
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@ -402,17 +403,46 @@ esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
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return ESP_ERR_NO_MEM;
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}
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void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
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static void s_sleep_hook_deregister(esp_deep_sleep_cb_t old_cb, esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])
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{
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portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
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for(int n = 0; n < MAX_DSLP_HOOKS; n++){
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if(s_dslp_cb[n] == old_dslp_cb) {
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s_dslp_cb[n] = NULL;
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for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
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if(s_cb_array[n] == old_cb) {
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s_cb_array[n] = NULL;
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}
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}
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portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
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}
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esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
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{
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return s_sleep_hook_register(new_dslp_cb, s_dslp_cb);
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}
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void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
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{
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s_sleep_hook_deregister(old_dslp_cb, s_dslp_cb);
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}
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esp_err_t esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb)
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{
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return s_sleep_hook_register(new_dslp_cb, s_dslp_phy_cb);
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}
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void esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb)
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{
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s_sleep_hook_deregister(old_dslp_cb, s_dslp_phy_cb);
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}
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static void s_do_deep_sleep_phy_callback(void)
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{
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for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
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if (s_dslp_phy_cb[n] != NULL) {
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s_dslp_phy_cb[n]();
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}
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}
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}
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static int s_cache_suspend_cnt = 0;
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// Must be called from critical sections.
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@ -659,6 +689,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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should_skip_sleep = light_sleep_uart_prepare(pd_flags, sleep_duration);
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}
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// Do deep-sleep PHY related callback, which need to be executed when the PLL clock is exists.
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// For light-sleep, PHY state is managed by the upper layer of the wifi/bt protocol stack.
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if (deep_sleep) {
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s_do_deep_sleep_phy_callback();
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}
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// Will switch to XTAL turn down MSPI speed
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mspi_timing_change_speed_mode_cache_safe(true);
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -20,7 +20,7 @@
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#include "nvs_flash.h"
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#include "esp_efuse.h"
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#include "esp_timer.h"
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#include "esp_sleep.h"
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#include "esp_private/esp_sleep_internal.h"
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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@ -865,9 +865,9 @@ void esp_phy_load_cal_and_init(void)
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esp_phy_release_init_data(init_data);
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#endif
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ESP_ERROR_CHECK(esp_deep_sleep_register_hook(&phy_close_rf));
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ESP_ERROR_CHECK(esp_deep_sleep_register_phy_hook(&phy_close_rf));
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#if !CONFIG_IDF_TARGET_ESP32
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ESP_ERROR_CHECK(esp_deep_sleep_register_hook(&phy_xpd_tsens));
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ESP_ERROR_CHECK(esp_deep_sleep_register_phy_hook(&phy_xpd_tsens));
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#endif
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free(cal_data); // PHY maintains a copy of calibration data, so we can free this
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