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fix(lcd): workaround register check failure

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morris 2024-06-19 19:00:11 +08:00
parent 0cfefb8a42
commit a8f2a94fe8
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GPG Key ID: FFB9C5DC0B9DF7A6
3 changed files with 16 additions and 11 deletions
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5
components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt
View File

@ -22,3 +22,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
DEPENDS ${elf}
)
endif()
message(STATUS "Checking rgb_lcd registers are not read-write by half-word")
include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
check_register_rw_half_word(SOC_MODULES "*lcd*" "hp_sys_clkrst"
HAL_MODULES "*lcd*")

10
components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h
View File

@ -114,11 +114,11 @@ static inline void mipi_dsi_host_ll_set_timeout_count(dsi_host_dev_t *dev, uint3
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, hstx_to_cnt, hs_tx);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, lprx_to_cnt, lp_rx);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_rd_to_cnt, hs_rd_to_cnt, hs_rd);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_rd_to_cnt, lp_rd_to_cnt, lp_rd);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_wr_to_cnt, hs_wr_to_cnt, hs_wr);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_wr_to_cnt, lp_wr_to_cnt, lp_wr);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->bta_to_cnt, bta_to_cnt, bta);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_rd_timeout_cnt, hs_rd_to_cnt, hs_rd);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_rd_timeout_cnt, lp_rd_to_cnt, lp_rd);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_wr_timeout_cnt, hs_wr_to_cnt, hs_wr);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_wr_timeout_cnt, lp_wr_to_cnt, lp_wr);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->bta_timeout_cnt, bta_to_cnt, bta);
}
/**

12
components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -1943,11 +1943,11 @@ typedef struct dsi_host_dev_t {
volatile dsi_host_gen_pld_data_reg_t gen_pld_data;
volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status;
volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg;
volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_to_cnt;
volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_to_cnt;
volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_to_cnt;
volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_to_cnt;
volatile dsi_host_bta_to_cnt_reg_t bta_to_cnt;
volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_timeout_cnt;
volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_timeout_cnt;
volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_timeout_cnt;
volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_timeout_cnt;
volatile dsi_host_bta_to_cnt_reg_t bta_timeout_cnt;
volatile dsi_host_sdf_3d_reg_t sdf_3d;
volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl;
volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg;